1351 files changed, 189547 insertions, 0 deletions

diff --git a/DE0_User_manual.pdf b/DE0_User_manual.pdf
new file mode 100644
index 0000000..f151262
--- /dev/null
+++ b/DE0_User_manual.pdf
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..b83b64d
--- /dev/null
+++ b/README.md
@@ -0,0 +1,6 @@
+# dot_product
+
+calculates dot_product in fpga
+
+Used catapult c to program it
+# Dot Product
diff --git a/catapult_lb_useref_uv.pdf b/catapult_lb_useref_uv.pdf
new file mode 100644
index 0000000..9537dad
--- /dev/null
+++ b/catapult_lb_useref_uv.pdf
diff --git a/dot_product/catapult.log b/dot_product/catapult.log
new file mode 100644
index 0000000..1a6b0b3
--- /dev/null
+++ b/dot_product/catapult.log
@@ -0,0 +1,677 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+//  Start time Tue Mar 01 14:25:21 2016
+# -------------------------------------------------
+# Logging session transcript to file "C:\Users\mg3115\AppData\Local\Temp\log682424fa020.0"
+# Loading options from registry.
+project load {C:/Catapult C/dot_product/dot_product.ccs}
+# Moving session transcript to file "C:\Catapult C\dot_product\catapult.log"
+# Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+# Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+flow run /SCVerify/launch_make ././scverify/Verify_orig_cxx_osci.mk {} SIMTOOL=osci sim
+# Making '././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim'
+#     C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+# "============================================"
+# "Creating simulation directory 'scverify\orig_cxx_osci'"
+# mkdir scverify\orig_cxx_osci
+# "============================================"
+# "Compiling C++ file: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp"
+# "c:\PROGRA~2\MICROS~4.0\VC\bin\cl.exe" -DCCS_DUT_SYSC -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=dot_product /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION /D"WIN32" /D"_DEBUG" /D"_CONSOLE" /D"NOGDI" /D"_MBCS" /D"_CRT_SECURE_NO_DEPRECATE" /EHsc /RTCs /MTd /FD /W3 /Z7 /vmg /I"C:/Program Files/Microsoft Platform SDK/Include"   /I. /I../.. /I. /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/src /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/siflibs /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DSC_USE_STD_STRING  /c /Tp ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp /Foscverify/orig_cxx_osci/dot_product.cpp.cxxts.obj
+# Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 15.00.30729.01 for 80x86
+# Copyright (C) Microsoft Corporation.  All rights reserved.
+# 
+# dot_product.cpp
+# ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(26) : warning C4068: unknown pragma
+# ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31) : warning C4102: 'MAC' : unreferenced label
+# "============================================"
+# "Compiling C++ file: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp"
+# "c:\PROGRA~2\MICROS~4.0\VC\bin\cl.exe" -DCCS_DUT_SYSC -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=dot_product /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION /D"WIN32" /D"_DEBUG" /D"_CONSOLE" /D"NOGDI" /D"_MBCS" /D"_CRT_SECURE_NO_DEPRECATE" /EHsc /RTCs /MTd /FD /W3 /Z7 /vmg /I"C:/Program Files/Microsoft Platform SDK/Include"   /I. /I../.. /I. /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/src /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/siflibs /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DSC_USE_STD_STRING  /c /Tp ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp /Foscverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj
+# Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 15.00.30729.01 for 80x86
+# Copyright (C) Microsoft Corporation.  All rights reserved.
+# 
+# tb_dot_product.cpp
+# ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp(39) : warning C4244: '+=' : conversion from 'Slong' to 'int', possible loss of data
+# "============================================"
+# "Linking executable"
+# "c:\PROGRA~2\MICROS~4.0\VC\bin\link.exe" /SUBSYSTEM:CONSOLE /DEBUG /DYNAMICBASE:NO /LIBPATH:C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/Windows_NT/msvc /LIBPATH:C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib /LIBPATH:C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/Windows_NT/msvc scverify/orig_cxx_osci/dot_product.cpp.cxxts.obj scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj libsystemc.lib /out:scverify/orig_cxx_osci/scverify_top.exe
+# Microsoft (R) Incremental Linker Version 9.00.30729.01
+# Copyright (C) Microsoft Corporation.  All rights reserved.
+# 
+#     C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+# chdir ..\..&                    dot_product\dot_product.v1\scverify\orig_cxx_osci\scverify_top.exe 
+# Inputs: A = 1, B = 5 
+# Inputs: A = 2, B = 4 
+# Inputs: A = 3, B = 3 
+# Inputs: A = 4, B = 2 
+# Inputs: A = 5, B = 1 
+# Design output  : 35 
+# Expected output: 35 
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v1' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 33, Real ops = 6, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 4) (SOL-10)
+# Design 'dot_product' contains '8' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v1': elapsed time 0.38 seconds, memory usage 153804kB, peak memory usage 166132kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v1' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Prescheduled LOOP 'MAC' (1 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 7 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 426.23, 0.00, 426.23 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 426.23, 0.00, 426.23 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v1': elapsed time 0.06 seconds, memory usage 153804kB, peak memory usage 166132kB (SOL-9)
+flow run /Schedule/view ./schedule.gnt
+flow run /Schedule/view ./schedule.gnt
+go compile
+directive set /dot_product/core/main/MAC -UNROLL yes
+# Info: Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/core/main/MAC/UNROLL yes
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v2' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v2': elapsed time 0.69 seconds, memory usage 162000kB, peak memory usage 170216kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v2' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1358.03, 0.00, 1358.03 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1027.78, 0.00, 1027.78 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 3, Area (Datapath, Register, Total) = 697.53, 0.00, 697.53 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v2': elapsed time 0.05 seconds, memory usage 162000kB, peak memory usage 170216kB (SOL-9)
+go compile
+directive set /dot_product/core/main/MAC -UNROLL no
+# Info: Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/core/main/MAC/UNROLL no
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+# /dot_product/core/main/PIPELINE_INIT_INTERVAL 1
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v3' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 6, Vars = 3) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 3) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 49, Real ops = 11, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 27, Real ops = 10, Vars = 7) (SOL-10)
+# Design 'dot_product' contains '12' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v3': elapsed time 1.08 seconds, memory usage 166268kB, peak memory usage 178592kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v3' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v3': elapsed time 0.06 seconds, memory usage 166268kB, peak memory usage 178592kB (SOL-9)
+go compile
+directive set /dot_product/core/main/MAC -UNROLL yes
+# Info: Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/core/main/MAC/UNROLL yes
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0
+# /dot_product/core/main/PIPELINE_INIT_INTERVAL 0
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v4' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v4': elapsed time 1.47 seconds, memory usage 169372kB, peak memory usage 178592kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v4' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1358.03, 0.00, 1358.03 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1027.78, 0.00, 1027.78 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 3, Area (Datapath, Register, Total) = 697.53, 0.00, 697.53 (CRAAS-10)
+# Info: Optimized LOOP 'main': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-10)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v4': elapsed time 0.06 seconds, memory usage 169372kB, peak memory usage 178592kB (SOL-9)
+go compile
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+# Info: Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/core/main/PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/main/MAC -UNROLL no
+# /dot_product/core/main/MAC/UNROLL no
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v5' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 6, Vars = 3) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 3) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 49, Real ops = 11, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 27, Real ops = 10, Vars = 7) (SOL-10)
+# Design 'dot_product' contains '12' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v5': elapsed time 1.79 seconds, memory usage 172008kB, peak memory usage 184332kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v5' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v5': elapsed time 0.06 seconds, memory usage 172008kB, peak memory usage 184332kB (SOL-9)
+go compile
+directive set /dot_product/input_b -STREAM 8
+# Info: Branching solution 'dot_product.v6' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/input_b/STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+# /dot_product/input_b/WORD_WIDTH 8
+directive set /dot_product/core/main/MAC -UNROLL yes
+# /dot_product/core/main/MAC/UNROLL yes
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v6' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 23, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 23, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 24, Real ops = 7, Vars = 4) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v6': elapsed time 2.09 seconds, memory usage 174832kB, peak memory usage 184332kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v6' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Error:  insufficient resources 'mgc_ioport.mgc_in_wire(2,8)' to schedule 'core'. 5 are needed, but only 1 instances are available (SCHD-4)
+# Error: Design 'dot_product' could not schedule partition '/dot_product/core' - resource competition
+go compile
+directive set /dot_product/input_b -WORD_WIDTH 40
+# Info: Branching solution 'dot_product.v7' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/input_b/WORD_WIDTH 40
+directive set /dot_product/input_b -STREAM 0
+# /dot_product/input_b/STREAM 0
+go allocate
+# Info: Starting transformation 'architect' on solution 'dot_product.v7' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v7': elapsed time 2.60 seconds, memory usage 176692kB, peak memory usage 184908kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v7' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v7': elapsed time 0.06 seconds, memory usage 176692kB, peak memory usage 184908kB (SOL-9)
+go compile
+directive set /dot_product/input_a -WORD_WIDTH 8
+# Info: Branching solution 'dot_product.v8' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/input_a/WORD_WIDTH 8
+directive set /dot_product/input_a -STREAM 8
+# /dot_product/input_a/STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+# /dot_product/input_b/WORD_WIDTH 8
+directive set /dot_product/input_b -STREAM 8
+# /dot_product/input_b/STREAM 8
+options set Output OutputVHDL false
+# false
+options set Output OutputVerilog true
+# true
+go extract
+# Info: Starting transformation 'architect' on solution 'dot_product.v8' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v8': elapsed time 2.79 seconds, memory usage 179500kB, peak memory usage 187716kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v8' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Error:  insufficient resources 'mgc_ioport.mgc_in_wire(1,8)' to schedule 'core'. 5 are needed, but only 1 instances are available (SCHD-4)
+# Error: Design 'dot_product' could not schedule partition '/dot_product/core' - resource competition
+go compile
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0
+# Info: Branching solution 'dot_product.v9' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/core/main/PIPELINE_INIT_INTERVAL 0
+directive set /dot_product/core/main/MAC -UNROLL no
+# /dot_product/core/main/MAC/UNROLL no
+directive set /dot_product/core/main/MAC -UNROLL yes
+# /dot_product/core/main/MAC/UNROLL yes
+go extract
+# Info: Starting transformation 'architect' on solution 'dot_product.v9' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v9': elapsed time 3.24 seconds, memory usage 182072kB, peak memory usage 190288kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v9' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v9': elapsed time 0.08 seconds, memory usage 182072kB, peak memory usage 190288kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'dot_product.v9' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Global signal 'input_a:rsc.z' added to design 'dot_product' for component 'input_a:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'input_b:rsc.z' added to design 'dot_product' for component 'input_b:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'output:rsc.z' added to design 'dot_product' for component 'output:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/dot_product': (Total ops = 40, Real ops = 11, Vars = 20) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 27, Real ops = 10, Vars = 10) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 21, Real ops = 10, Vars = 4) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 10, Real ops = 10, Vars = 4) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 10, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 16, Real ops = 10, Vars = 10) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Error: Streamed resource 'input_a:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en).
+# Error: Streamed resource 'input_b:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en).
+# Info: Wrote wave database file to C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/ccs_wave_signals.dat
+# Makefile for Cycle Verilog output 'cycle.v' vs Untimed C++ written to file 'scverify/Verify_cycle_v_msim.mk'
+# Info: Completed transformation 'schedule' on solution 'dot_product.v9': elapsed time 1.08 seconds, memory usage 183844kB, peak memory usage 190288kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'dot_product.v9' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/dot_product': (Total ops = 56, Real ops = 16, Vars = 50) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 44, Real ops = 16, Vars = 41) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 46, Real ops = 13, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 34, Real ops = 13, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'dot_product.v9': elapsed time 0.09 seconds, memory usage 184104kB, peak memory usage 190368kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'dot_product.v9' (SOL-8)
+# Shared Operations MAC:acc#5,MAC:acc#6,MAC:acc on resource MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8):mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) (ASG-3)
+# Info: Optimizing partition '/dot_product': (Total ops = 46, Real ops = 11, Vars = 36) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 34, Real ops = 11, Vars = 27) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 11, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 11, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 11, Vars = 33) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 11, Vars = 24) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 29, Real ops = 11, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 28, Real ops = 11, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 40, Real ops = 11, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 28, Real ops = 11, Vars = 17) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: C:/Catapult C/dot_product/dot_product/dot_product.v9/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Makefile for RTL Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_rtl_v_msim.mk'
+# Synthesis timing script written to file './scverify/mapped.psrv_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'mapped.psrv'
+# Makefile for Mapped Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_mapped_v_msim.mk'
+# Synthesis timing script written to file './scverify/gate.psrv_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'gate.psrv'
+# Makefile for Gate Verilog output 'gate.v' vs Untimed C++ written to file 'scverify/Verify_gate_v_msim.mk'
+# Info: Completed transformation 'extract' on solution 'dot_product.v9': elapsed time 2.70 seconds, memory usage 188780kB, peak memory usage 192380kB (SOL-9)
+go instance
+flow run /Schematic/view ./schematic.nlv -state rtl
+flow run /Schematic/view ./schematic.nlv -state rtl
+flow run /Schematic/view ./schematic.nlv -state rtl
+flow run /Schematic/view ./schematic.nlv -state datapath
+flow run /Schematic/view ./schematic.nlv -state criticalpath
+flow run /Schematic/view ./schematic.nlv -state datapath
+flow run /Schematic/view ./schematic.nlv -state rtl
+go extract
+go compile
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+# Info: Branching solution 'dot_product.v10' at state 'compile' (PRJ-2)
+# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk'
+# /dot_product/core/main/PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/main/MAC -UNROLL no
+# /dot_product/core/main/MAC/UNROLL no
+go extract
+# Info: Starting transformation 'architect' on solution 'dot_product.v10' (SOL-8)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+# Info: Optimizing partition '/dot_product': (Total ops = 15, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 15, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 13, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 6, Vars = 2) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 13, Real ops = 6, Vars = 8) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 6, Vars = 3) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 3) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 45, Real ops = 11, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/dot_product/core': (Total ops = 23, Real ops = 10, Vars = 6) (SOL-10)
+# Design 'dot_product' contains '10' real operations. (SOL-11)
+# Info: Completed transformation 'architect' on solution 'dot_product.v10': elapsed time 3.62 seconds, memory usage 192028kB, peak memory usage 204352kB (SOL-9)
+# Info: Starting transformation 'allocate' on solution 'dot_product.v10' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Info: Select qualified components for data operations ... (CRAAS-3)
+# Info: Apply resource constraints on data operations ... (CRAAS-4)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 356.83, 0.00, 356.83 (CRAAS-11)
+# At least one feasible schedule exists. (CRAAS-9)
+# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 356.83, 0.00, 356.83 (CRAAS-12)
+# Resource allocation and scheduling done. (CRAAS-2)
+# Netlist written to file 'schedule.gnt' (NET-4)
+# Info: Completed transformation 'allocate' on solution 'dot_product.v10': elapsed time 0.06 seconds, memory usage 192028kB, peak memory usage 204352kB (SOL-9)
+# Info: Starting transformation 'schedule' on solution 'dot_product.v10' (SOL-8)
+# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+# Global signal 'input_a:rsc.z' added to design 'dot_product' for component 'input_a:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'input_b:rsc.z' added to design 'dot_product' for component 'input_b:rsc:mgc_in_wire' (LIB-3)
+# Global signal 'output:rsc.z' added to design 'dot_product' for component 'output:rsc:mgc_out_stdreg' (LIB-3)
+# Info: Optimizing partition '/dot_product': (Total ops = 49, Real ops = 11, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 36, Real ops = 10, Vars = 16) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 30, Real ops = 10, Vars = 10) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 17, Real ops = 10, Vars = 4) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 10, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 10, Vars = 10) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 17, Real ops = 10, Vars = 4) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 10, Vars = 19) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 10, Vars = 10) (SOL-10)
+# Report written to file 'cycle.rpt'
+# Netlist written to file 'cycle.v' (NET-4)
+# Error: Streamed resource 'input_a:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en).
+# Error: Streamed resource 'input_b:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en).
+# Info: Wrote wave database file to C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/ccs_wave_signals.dat
+# Makefile for Cycle Verilog output 'cycle.v' vs Untimed C++ written to file 'scverify/Verify_cycle_v_msim.mk'
+# Info: Completed transformation 'schedule' on solution 'dot_product.v10': elapsed time 1.12 seconds, memory usage 193784kB, peak memory usage 204352kB (SOL-9)
+# Info: Starting transformation 'dpfsm' on solution 'dot_product.v10' (SOL-8)
+# Performing FSM extraction... (FSM-1)
+# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 13, Vars = 35) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 13, Vars = 26) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Completed transformation 'dpfsm' on solution 'dot_product.v10': elapsed time 0.08 seconds, memory usage 193784kB, peak memory usage 204352kB (SOL-9)
+# Info: Starting transformation 'extract' on solution 'dot_product.v10' (SOL-8)
+# Warning: Reassigned operation MAC:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,3) (ASG-1)
+# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 31) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 22) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 23) (SOL-10)
+# Netlist written to file 'schematic.nlv' (NET-4)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 32) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 23) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+# Report written to file 'rtl.rpt'
+# Netlist written to file 'rtl.v' (NET-4)
+# generate concat
+# order file name is: rtl.v_order.txt
+# Add dependent file: ./rtl_mgc_ioport.v
+# Add dependent file: ./rtl_mgc_ioport_v2001.v
+# Add dependent file: ./rtl.v
+# Finished writing concatenated file: C:/Catapult C/dot_product/dot_product/dot_product.v10/concat_rtl.v
+# Synthesis timing script written to file './rtl.v.psr_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'rtl.v.psr'
+# Makefile for RTL Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_rtl_v_msim.mk'
+# Synthesis timing script written to file './scverify/mapped.psrv_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'mapped.psrv'
+# Makefile for Mapped Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_mapped_v_msim.mk'
+# Synthesis timing script written to file './scverify/gate.psrv_timing'
+# IO timing constraints written to synthesis script file
+# Synthesis script written to file 'gate.psrv'
+# Makefile for Gate Verilog output 'gate.v' vs Untimed C++ written to file 'scverify/Verify_gate_v_msim.mk'
+# Info: Completed transformation 'extract' on solution 'dot_product.v10': elapsed time 2.64 seconds, memory usage 194292kB, peak memory usage 204352kB (SOL-9)
+go instance
+flow run /Schematic/view ./schematic.nlv -state rtl
+go extract
+go instance
+flow run /Schematic/view ./schematic.nlv -state rtl
diff --git a/dot_product/dot_product.ccs b/dot_product/dot_product.ccs
new file mode 100644
index 0000000..0037d69
--- /dev/null
+++ b/dot_product/dot_product.ccs
@@ -0,0 +1,23 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+if {[info script] != {} && [file isdirectory [file rootname [info script]]]} {
+  project load [file rootname [info script]] 2011a
+} elseif { [file isdirectory {//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Catapult C/dot_product/dot_product}] } {
+  project load {//icnas3.cc.ic.ac.uk/mg3115/EIE1 FPGA/Catapult C/dot_product/dot_product} 2011a
+} else {
+  error {unable to locate project directory 'dot_product'}
+}
+
diff --git a/dot_product/dot_product/SIF/project.sif b/dot_product/dot_product/SIF/project.sif
new file mode 100644
index 0000000..cb86bf6
--- /dev/null
+++ b/dot_product/dot_product/SIF/project.sif
diff --git a/dot_product/dot_product/SIF/sid10__allocate.sif b/dot_product/dot_product/SIF/sid10__allocate.sif
new file mode 100644
index 0000000..42a4182
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid10__architect.sif b/dot_product/dot_product/SIF/sid10__architect.sif
new file mode 100644
index 0000000..ed9e390
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__architect.sif
diff --git a/dot_product/dot_product/SIF/sid10__assembly.sif b/dot_product/dot_product/SIF/sid10__assembly.sif
new file mode 100644
index 0000000..571c1cf
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid10__compile.sif b/dot_product/dot_product/SIF/sid10__compile.sif
new file mode 100644
index 0000000..571c1cf
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__compile.sif
diff --git a/dot_product/dot_product/SIF/sid10__dpfsm.sif b/dot_product/dot_product/SIF/sid10__dpfsm.sif
new file mode 100644
index 0000000..7706e89
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__dpfsm.sif
diff --git a/dot_product/dot_product/SIF/sid10__extract.sif b/dot_product/dot_product/SIF/sid10__extract.sif
new file mode 100644
index 0000000..593054e
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__extract.sif
diff --git a/dot_product/dot_product/SIF/sid10__instance.sif b/dot_product/dot_product/SIF/sid10__instance.sif
new file mode 100644
index 0000000..0c8def0
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__instance.sif
diff --git a/dot_product/dot_product/SIF/sid10__loops.sif b/dot_product/dot_product/SIF/sid10__loops.sif
new file mode 100644
index 0000000..571c1cf
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__loops.sif
diff --git a/dot_product/dot_product/SIF/sid10__memories.sif b/dot_product/dot_product/SIF/sid10__memories.sif
new file mode 100644
index 0000000..ec91824
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__memories.sif
diff --git a/dot_product/dot_product/SIF/sid10__schedule.sif b/dot_product/dot_product/SIF/sid10__schedule.sif
new file mode 100644
index 0000000..04cd4eb
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid10__schedule.sif
diff --git a/dot_product/dot_product/SIF/sid1__allocate.sif b/dot_product/dot_product/SIF/sid1__allocate.sif
new file mode 100644
index 0000000..0874057
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid1__analyze.il b/dot_product/dot_product/SIF/sid1__analyze.il
new file mode 100644
index 0000000..72c3433
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__analyze.il
diff --git a/dot_product/dot_product/SIF/sid1__architect.sif b/dot_product/dot_product/SIF/sid1__architect.sif
new file mode 100644
index 0000000..e9272a5
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__architect.sif
diff --git a/dot_product/dot_product/SIF/sid1__assembly.sif b/dot_product/dot_product/SIF/sid1__assembly.sif
new file mode 100644
index 0000000..d90a12a
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid1__compile.sif b/dot_product/dot_product/SIF/sid1__compile.sif
new file mode 100644
index 0000000..d90a12a
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__compile.sif
diff --git a/dot_product/dot_product/SIF/sid1__loops.sif b/dot_product/dot_product/SIF/sid1__loops.sif
new file mode 100644
index 0000000..d90a12a
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__loops.sif
diff --git a/dot_product/dot_product/SIF/sid1__memories.sif b/dot_product/dot_product/SIF/sid1__memories.sif
new file mode 100644
index 0000000..615cd53
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid1__memories.sif
diff --git a/dot_product/dot_product/SIF/sid2__allocate.sif b/dot_product/dot_product/SIF/sid2__allocate.sif
new file mode 100644
index 0000000..840baf7
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid2__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid2__architect.sif b/dot_product/dot_product/SIF/sid2__architect.sif
new file mode 100644
index 0000000..bf48a7b
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid2__architect.sif
diff --git a/dot_product/dot_product/SIF/sid2__assembly.sif b/dot_product/dot_product/SIF/sid2__assembly.sif
new file mode 100644
index 0000000..11a3f87
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid2__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid2__compile.sif b/dot_product/dot_product/SIF/sid2__compile.sif
new file mode 100644
index 0000000..11a3f87
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid2__compile.sif
diff --git a/dot_product/dot_product/SIF/sid2__loops.sif b/dot_product/dot_product/SIF/sid2__loops.sif
new file mode 100644
index 0000000..5ba8f96
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid2__loops.sif
diff --git a/dot_product/dot_product/SIF/sid2__memories.sif b/dot_product/dot_product/SIF/sid2__memories.sif
new file mode 100644
index 0000000..033cff2
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid2__memories.sif
diff --git a/dot_product/dot_product/SIF/sid3__allocate.sif b/dot_product/dot_product/SIF/sid3__allocate.sif
new file mode 100644
index 0000000..e1281ca
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid3__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid3__architect.sif b/dot_product/dot_product/SIF/sid3__architect.sif
new file mode 100644
index 0000000..308ce72
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid3__architect.sif
diff --git a/dot_product/dot_product/SIF/sid3__assembly.sif b/dot_product/dot_product/SIF/sid3__assembly.sif
new file mode 100644
index 0000000..62d8492
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid3__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid3__compile.sif b/dot_product/dot_product/SIF/sid3__compile.sif
new file mode 100644
index 0000000..62d8492
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid3__compile.sif
diff --git a/dot_product/dot_product/SIF/sid3__loops.sif b/dot_product/dot_product/SIF/sid3__loops.sif
new file mode 100644
index 0000000..62d8492
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid3__loops.sif
diff --git a/dot_product/dot_product/SIF/sid3__memories.sif b/dot_product/dot_product/SIF/sid3__memories.sif
new file mode 100644
index 0000000..7b887e9
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid3__memories.sif
diff --git a/dot_product/dot_product/SIF/sid4__allocate.sif b/dot_product/dot_product/SIF/sid4__allocate.sif
new file mode 100644
index 0000000..80e8fb6
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid4__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid4__architect.sif b/dot_product/dot_product/SIF/sid4__architect.sif
new file mode 100644
index 0000000..3c34acb
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid4__architect.sif
diff --git a/dot_product/dot_product/SIF/sid4__assembly.sif b/dot_product/dot_product/SIF/sid4__assembly.sif
new file mode 100644
index 0000000..d45388a
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid4__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid4__compile.sif b/dot_product/dot_product/SIF/sid4__compile.sif
new file mode 100644
index 0000000..d45388a
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid4__compile.sif
diff --git a/dot_product/dot_product/SIF/sid4__loops.sif b/dot_product/dot_product/SIF/sid4__loops.sif
new file mode 100644
index 0000000..41ab5bd
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid4__loops.sif
diff --git a/dot_product/dot_product/SIF/sid4__memories.sif b/dot_product/dot_product/SIF/sid4__memories.sif
new file mode 100644
index 0000000..393bfa2
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid4__memories.sif
diff --git a/dot_product/dot_product/SIF/sid5__allocate.sif b/dot_product/dot_product/SIF/sid5__allocate.sif
new file mode 100644
index 0000000..731b55a
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid5__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid5__architect.sif b/dot_product/dot_product/SIF/sid5__architect.sif
new file mode 100644
index 0000000..fb8dad3
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid5__architect.sif
diff --git a/dot_product/dot_product/SIF/sid5__assembly.sif b/dot_product/dot_product/SIF/sid5__assembly.sif
new file mode 100644
index 0000000..adf8dc4
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid5__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid5__compile.sif b/dot_product/dot_product/SIF/sid5__compile.sif
new file mode 100644
index 0000000..adf8dc4
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid5__compile.sif
diff --git a/dot_product/dot_product/SIF/sid5__loops.sif b/dot_product/dot_product/SIF/sid5__loops.sif
new file mode 100644
index 0000000..adf8dc4
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid5__loops.sif
diff --git a/dot_product/dot_product/SIF/sid5__memories.sif b/dot_product/dot_product/SIF/sid5__memories.sif
new file mode 100644
index 0000000..c9be99d
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid5__memories.sif
diff --git a/dot_product/dot_product/SIF/sid6__architect.sif b/dot_product/dot_product/SIF/sid6__architect.sif
new file mode 100644
index 0000000..72e4928
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid6__architect.sif
diff --git a/dot_product/dot_product/SIF/sid6__assembly.sif b/dot_product/dot_product/SIF/sid6__assembly.sif
new file mode 100644
index 0000000..57d3506
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid6__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid6__compile.sif b/dot_product/dot_product/SIF/sid6__compile.sif
new file mode 100644
index 0000000..57d3506
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid6__compile.sif
diff --git a/dot_product/dot_product/SIF/sid6__loops.sif b/dot_product/dot_product/SIF/sid6__loops.sif
new file mode 100644
index 0000000..94f3a19
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid6__loops.sif
diff --git a/dot_product/dot_product/SIF/sid6__memories.sif b/dot_product/dot_product/SIF/sid6__memories.sif
new file mode 100644
index 0000000..8d9f9a0
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid6__memories.sif
diff --git a/dot_product/dot_product/SIF/sid7__allocate.sif b/dot_product/dot_product/SIF/sid7__allocate.sif
new file mode 100644
index 0000000..58933d7
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid7__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid7__architect.sif b/dot_product/dot_product/SIF/sid7__architect.sif
new file mode 100644
index 0000000..b63a272
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid7__architect.sif
diff --git a/dot_product/dot_product/SIF/sid7__assembly.sif b/dot_product/dot_product/SIF/sid7__assembly.sif
new file mode 100644
index 0000000..5fc0c43
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid7__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid7__compile.sif b/dot_product/dot_product/SIF/sid7__compile.sif
new file mode 100644
index 0000000..5fc0c43
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid7__compile.sif
diff --git a/dot_product/dot_product/SIF/sid7__loops.sif b/dot_product/dot_product/SIF/sid7__loops.sif
new file mode 100644
index 0000000..be0ac49
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid7__loops.sif
diff --git a/dot_product/dot_product/SIF/sid7__memories.sif b/dot_product/dot_product/SIF/sid7__memories.sif
new file mode 100644
index 0000000..20c2b3c
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid7__memories.sif
diff --git a/dot_product/dot_product/SIF/sid8__architect.sif b/dot_product/dot_product/SIF/sid8__architect.sif
new file mode 100644
index 0000000..9dcef05
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid8__architect.sif
diff --git a/dot_product/dot_product/SIF/sid8__assembly.sif b/dot_product/dot_product/SIF/sid8__assembly.sif
new file mode 100644
index 0000000..ba69512
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid8__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid8__compile.sif b/dot_product/dot_product/SIF/sid8__compile.sif
new file mode 100644
index 0000000..ba69512
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid8__compile.sif
diff --git a/dot_product/dot_product/SIF/sid8__loops.sif b/dot_product/dot_product/SIF/sid8__loops.sif
new file mode 100644
index 0000000..4587761
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid8__loops.sif
diff --git a/dot_product/dot_product/SIF/sid8__memories.sif b/dot_product/dot_product/SIF/sid8__memories.sif
new file mode 100644
index 0000000..c2377ab
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid8__memories.sif
diff --git a/dot_product/dot_product/SIF/sid9__allocate.sif b/dot_product/dot_product/SIF/sid9__allocate.sif
new file mode 100644
index 0000000..cc6e3db
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__allocate.sif
diff --git a/dot_product/dot_product/SIF/sid9__architect.sif b/dot_product/dot_product/SIF/sid9__architect.sif
new file mode 100644
index 0000000..fc18a14
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__architect.sif
diff --git a/dot_product/dot_product/SIF/sid9__assembly.sif b/dot_product/dot_product/SIF/sid9__assembly.sif
new file mode 100644
index 0000000..1ad439d
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__assembly.sif
diff --git a/dot_product/dot_product/SIF/sid9__compile.sif b/dot_product/dot_product/SIF/sid9__compile.sif
new file mode 100644
index 0000000..1ad439d
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__compile.sif
diff --git a/dot_product/dot_product/SIF/sid9__dpfsm.sif b/dot_product/dot_product/SIF/sid9__dpfsm.sif
new file mode 100644
index 0000000..08b53bd
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__dpfsm.sif
diff --git a/dot_product/dot_product/SIF/sid9__extract.sif b/dot_product/dot_product/SIF/sid9__extract.sif
new file mode 100644
index 0000000..0ea34ed
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__extract.sif
diff --git a/dot_product/dot_product/SIF/sid9__instance.sif b/dot_product/dot_product/SIF/sid9__instance.sif
new file mode 100644
index 0000000..ff981a3
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__instance.sif
diff --git a/dot_product/dot_product/SIF/sid9__loops.sif b/dot_product/dot_product/SIF/sid9__loops.sif
new file mode 100644
index 0000000..8a75fb4
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__loops.sif
diff --git a/dot_product/dot_product/SIF/sid9__memories.sif b/dot_product/dot_product/SIF/sid9__memories.sif
new file mode 100644
index 0000000..a21e3a1
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__memories.sif
diff --git a/dot_product/dot_product/SIF/sid9__schedule.sif b/dot_product/dot_product/SIF/sid9__schedule.sif
new file mode 100644
index 0000000..b45abbc
--- /dev/null
+++ b/dot_product/dot_product/SIF/sid9__schedule.sif
diff --git a/dot_product/dot_product/dot_product.v1/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v1/ccs_env.mk b/dot_product/dot_product/dot_product.v1/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v1/directives.tcl b/dot_product/dot_product/dot_product.v1/directives.tcl
new file mode 100644
index 0000000..3dc2e6c
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/directives.tcl
@@ -0,0 +1,58 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+go architect
+go allocate
diff --git a/dot_product/dot_product/dot_product.v1/messages.txt b/dot_product/dot_product/dot_product.v1/messages.txt
new file mode 100644
index 0000000..26ea225
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/messages.txt
@@ -0,0 +1,99 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v1' (SOL-8)
+Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+Design 'dot_product' contains '8' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 33, Real ops = 6, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 4) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v1': elapsed time 0.38 seconds, memory usage 153804kB, peak memory usage 166132kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'MAC' (1 c-steps) (SCHD-7)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 7 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v1' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 426.23, 0.00, 426.23 (CRAAS-11)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 426.23, 0.00, 426.23 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v1': elapsed time 0.06 seconds, memory usage 153804kB, peak memory usage 166132kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v1/new_ccs_env.mk b/dot_product/dot_product/dot_product.v1/new_ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/new_ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v1/schedule.gnt b/dot_product/dot_product/dot_product.v1/schedule.gnt
new file mode 100644
index 0000000..922430b
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/schedule.gnt
@@ -0,0 +1,39 @@
+set a(0-11) {NAME acc:asn(acc) TYPE ASSIGN PAR 0-10 XREFS 362 LOC {0 1.0 0 1.0 0 1.0 1 1.0} PREDS {{772 0 0-13 {}}} SUCCS {{258 0 0-13 {}}} CYCLES {}}
+set a(0-12) {NAME MAC:asn(i) TYPE ASSIGN PAR 0-10 XREFS 363 LOC {0 1.0 0 1.0 0 1.0 1 1.0} PREDS {{772 0 0-13 {}}} SUCCS {{259 0 0-13 {}}} CYCLES {}}
+set a(0-14) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-13 XREFS 364 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {} SUCCS {{258 0 0-17 {}} {258 0 0-18 {}} {258 0 0-19 {}} {258 0 0-20 {}} {258 0 0-21 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-15) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-13 XREFS 365 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {} SUCCS {{258 0 0-24 {}} {258 0 0-25 {}} {258 0 0-26 {}} {258 0 0-27 {}} {258 0 0-28 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-16) {NAME MAC:asn TYPE ASSIGN PAR 0-13 XREFS 366 LOC {0 1.0 1 0.92730525 1 0.92730525 1 0.92730525} PREDS {{774 0 0-40 {}}} SUCCS {{258 0 0-32 {}} {130 0 0-39 {}} {256 0 0-40 {}}} CYCLES {}}
+set a(0-17) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt) TYPE READSLICE PAR 0-13 XREFS 367 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-18) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#1 TYPE READSLICE PAR 0-13 XREFS 368 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-19) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#2 TYPE READSLICE PAR 0-13 XREFS 369 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-20) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#3 TYPE READSLICE PAR 0-13 XREFS 370 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-21) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#4 TYPE READSLICE PAR 0-13 XREFS 371 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-22) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-13 XREFS 372 LOC {0 1.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{774 0 0-41 {}}} SUCCS {{259 0 0-23 {}} {130 0 0-39 {}} {256 0 0-41 {}}} CYCLES {}}
+set a(0-23) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-13 XREFS 373 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-21 {}} {258 0 0-20 {}} {258 0 0-19 {}} {258 0 0-18 {}} {258 0 0-17 {}} {259 0 0-22 {}}} SUCCS {{258 0 0-31 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-24) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt) TYPE READSLICE PAR 0-13 XREFS 374 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-25) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#1 TYPE READSLICE PAR 0-13 XREFS 375 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-26) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#2 TYPE READSLICE PAR 0-13 XREFS 376 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-27) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#3 TYPE READSLICE PAR 0-13 XREFS 377 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-28) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#4 TYPE READSLICE PAR 0-13 XREFS 378 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-29) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-13 XREFS 379 LOC {0 1.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{774 0 0-41 {}}} SUCCS {{259 0 0-30 {}} {130 0 0-39 {}} {256 0 0-41 {}}} CYCLES {}}
+set a(0-30) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux#1 TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-13 XREFS 380 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-28 {}} {258 0 0-27 {}} {258 0 0-26 {}} {258 0 0-25 {}} {258 0 0-24 {}} {259 0 0-29 {}}} SUCCS {{259 0 0-31 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-31) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-13 XREFS 381 LOC {1 0.093995 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-23 {}} {259 0 0-30 {}}} SUCCS {{259 0 0-32 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-32) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-13 XREFS 382 LOC {1 0.260196225 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-16 {}} {259 0 0-31 {}}} SUCCS {{130 0 0-39 {}} {258 0 0-40 {}}} CYCLES {}}
+set a(0-33) {NAME MAC:asn#6 TYPE ASSIGN PAR 0-13 XREFS 383 LOC {0 1.0 1 0.898700525 1 0.898700525 1 0.898700525} PREDS {{774 0 0-41 {}}} SUCCS {{259 0 0-34 {}} {130 0 0-39 {}} {256 0 0-41 {}}} CYCLES {}}
+set a(0-34) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-13 XREFS 384 LOC {1 0.0 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{259 0 0-33 {}}} SUCCS {{259 0 0-35 {}} {130 0 0-39 {}} {258 0 0-41 {}}} CYCLES {}}
+set a(0-35) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-13 XREFS 385 LOC {1 0.04777575 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-34 {}}} SUCCS {{259 0 0-36 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-36) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-13 XREFS 386 LOC {1 0.04777575 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-35 {}}} SUCCS {{259 0 0-37 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-37) {NAME MAC:slc TYPE READSLICE PAR 0-13 XREFS 387 LOC {1 0.101299475 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-36 {}}} SUCCS {{259 0 0-38 {}} {130 0 0-39 {}}} CYCLES {}}
+set a(0-38) {NAME MAC:not TYPE NOT PAR 0-13 XREFS 388 LOC {1 0.101299475 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-37 {}}} SUCCS {{259 0 0-39 {}}} CYCLES {}}
+set a(0-39) {NAME break(MAC) TYPE TERMINATE PAR 0-13 XREFS 389 LOC {1 0.332890975 1 1.0 1 1.0 1 1.0} PREDS {{130 0 0-14 {}} {130 0 0-15 {}} {130 0 0-16 {}} {130 0 0-17 {}} {130 0 0-18 {}} {130 0 0-19 {}} {130 0 0-20 {}} {130 0 0-21 {}} {130 0 0-22 {}} {130 0 0-23 {}} {130 0 0-24 {}} {130 0 0-25 {}} {130 0 0-26 {}} {130 0 0-27 {}} {130 0 0-28 {}} {130 0 0-29 {}} {130 0 0-30 {}} {130 0 0-31 {}} {130 0 0-32 {}} {130 0 0-33 {}} {130 0 0-34 {}} {130 0 0-35 {}} {130 0 0-36 {}} {130 0 0-37 {}} {259 0 0-38 {}}} SUCCS {{129 0 0-40 {}} {128 0 0-41 {}}} CYCLES {}}
+set a(0-40) {NAME MAC:asn(acc.sva) TYPE ASSIGN PAR 0-13 XREFS 390 LOC {1 0.332890975 1 1.0 1 1.0 1 1.0} PREDS {{772 0 0-40 {}} {256 0 0-16 {}} {258 0 0-32 {}} {129 0 0-39 {}}} SUCCS {{774 0 0-16 {}} {772 0 0-40 {}}} CYCLES {}}
+set a(0-41) {NAME MAC:asn(i#1.sva) TYPE ASSIGN PAR 0-13 XREFS 391 LOC {1 0.04777575 1 0.946476275 1 0.946476275 1 1.0} PREDS {{128 0 0-39 {}} {772 0 0-41 {}} {256 0 0-22 {}} {256 0 0-29 {}} {256 0 0-33 {}} {258 0 0-34 {}}} SUCCS {{774 0 0-22 {}} {774 0 0-29 {}} {774 0 0-33 {}} {772 0 0-41 {}}} CYCLES {}}
+set a(0-13) {CHI {0-14 0-15 0-16 0-17 0-18 0-19 0-20 0-21 0-22 0-23 0-24 0-25 0-26 0-27 0-28 0-29 0-30 0-31 0-32 0-33 0-34 0-35 0-36 0-37 0-38 0-39 0-40 0-41} ITERATIONS 5 RESET_LATENCY 0 CSTEPS 1 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME MAC TYPE LOOP DELAY {120.00 ns} PAR 0-10 XREFS 392 LOC {1 1.0 1 1.0 1 1.0 1 1.0} PREDS {{258 0 0-11 {}} {259 0 0-12 {}}} SUCCS {{772 0 0-11 {}} {772 0 0-12 {}} {259 0 0-42 {}}} CYCLES {}}
+set a(0-42) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-10 XREFS 393 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{772 0 0-42 {}} {259 0 0-13 {}}} SUCCS {{772 0 0-42 {}}} CYCLES {}}
+set a(0-10) {CHI {0-11 0-12 0-13 0-42} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 7 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 2 TOTAL_CYCLES_IN 2 TOTAL_CYCLES_UNDER 5 TOTAL_CYCLES 7 NAME main TYPE LOOP DELAY {160.00 ns} PAR {} XREFS 394 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-10-TOTALCYCLES) {7}
+set a(0-10-QMOD) {mgc_ioport.mgc_in_wire(1,40) 0-14 mgc_ioport.mgc_in_wire(2,40) 0-15 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,3,8) {0-23 0-30} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-31 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-32 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-34 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-36 mgc_ioport.mgc_out_stdreg(3,8) 0-42}
+set a(0-10-PROC_NAME) {core}
+set a(0-10-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-10}
+
diff --git a/dot_product/dot_product/dot_product.v1/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v1/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..38812af
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:15:46 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v1)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = //icnas3.cc.ic.ac.uk/mg3115/EIE1FP~1/CATAPU~1/dot_product/dot_product/dot_product.v1/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/dot_product.cpp.cxxts b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/dot_product.cpp.cxxts
new file mode 100644
index 0000000..ee5da72
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/dot_product.cpp.cxxts
@@ -0,0 +1 @@
+01/03/2016 14:25:48.16 
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/dot_product.cpp.cxxts.obj b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/dot_product.cpp.cxxts.obj
new file mode 100644
index 0000000..24c0032
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/dot_product.cpp.cxxts.obj
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/make_dir b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/make_dir
new file mode 100644
index 0000000..32a6ae9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/make_dir
@@ -0,0 +1 @@
+01/03/2016 14:25:47.49 
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.exe b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.exe
new file mode 100644
index 0000000..ce2e6c8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.exe
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.ilk b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.ilk
new file mode 100644
index 0000000..f92393d
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.ilk
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.pdb b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.pdb
new file mode 100644
index 0000000..50d583c
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/scverify_top.pdb
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts
new file mode 100644
index 0000000..a461ebe
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts
@@ -0,0 +1 @@
+01/03/2016 14:25:48.43 
diff --git a/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj
new file mode 100644
index 0000000..9902ae5
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj
diff --git a/dot_product/dot_product/dot_product.v1/vc90.idb b/dot_product/dot_product/dot_product.v1/vc90.idb
new file mode 100644
index 0000000..8b3dca3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v1/vc90.idb
diff --git a/dot_product/dot_product/dot_product.v10/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v10/ccs_env.mk b/dot_product/dot_product/dot_product.v10/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v10/concat_rtl.v b/dot_product/dot_product/dot_product.v10/concat_rtl.v
new file mode 100644
index 0000000..f2b2560
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/concat_rtl.v
@@ -0,0 +1,1411 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 15:39:39 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg exit_MAC_lpi;
+  reg [7:0] acc_sva_1;
+  reg [2:0] i_1_sva_1;
+  wire [2:0] MAC_acc_itm;
+  wire [3:0] nl_MAC_acc_itm;
+  wire [7:0] acc_sva_2;
+  wire [8:0] nl_acc_sva_2;
+  wire [2:0] i_1_sva_2;
+  wire [3:0] nl_i_1_sva_2;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_acc_sva_2 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
+      * input_b_rsc_mgc_in_wire_d);
+  assign acc_sva_2 = nl_acc_sva_2[7:0];
+  assign nl_i_1_sva_2 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
+  assign i_1_sva_2 = nl_i_1_sva_2[2:0];
+  assign nl_MAC_acc_itm = i_1_sva_2 + 3'b11;
+  assign MAC_acc_itm = nl_MAC_acc_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      output_rsc_mgc_out_stdreg_d <= 8'b0;
+      acc_sva_1 <= 8'b0;
+      i_1_sva_1 <= 3'b0;
+      exit_MAC_lpi <= 1'b1;
+    end
+    else begin
+      if ( en ) begin
+        output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({acc_sva_2 , output_rsc_mgc_out_stdreg_d},
+            MAC_acc_itm[2]);
+        acc_sva_1 <= acc_sva_2;
+        i_1_sva_1 <= i_1_sva_2;
+        exit_MAC_lpi <= ~ (MAC_acc_itm[2]);
+      end
+    end
+  end
+
+  function [7:0] signext_8_1;
+    input [0:0] vector;
+  begin
+    signext_8_1= {{7{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [7:0] MUX_v_8_2_2;
+    input [15:0] inputs;
+    input [0:0] sel;
+    reg [7:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[15:8];
+      end
+      1'b1 : begin
+        result = inputs[7:0];
+      end
+      default : begin
+        result = inputs[15:8];
+      end
+    endcase
+    MUX_v_8_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_16_8 ;
+    input signed [15:0]  vector ;
+  begin
+    conv_s2s_16_8 = vector[7:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/dot_product.v10/cycle.rpt b/dot_product/dot_product/dot_product.v10/cycle.rpt
new file mode 100644
index 0000000..e3c7b96
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/cycle.rpt
@@ -0,0 +1,84 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-015                                 
+-- Generated date:              Tue Mar 01 15:39:34 +0000 2016                      
+
+Solution Settings: dot_product.v10
+  Current state: schedule
+  Project: dot_product
+  
+  Design Input Files Specified
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+      $MGC_HOME/shared/include/mc_scverify.h
+  
+  Processes/Blocks in Design
+    Process           Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ----------------- ----------------------- ------- ---------- ------------ -- --------
+    /dot_product/core                      12       5          5            0  1          
+    Design Total:                          12       5          5            0  1          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /dot_product/core        
+    
+  I/O Data Ranges
+    Port          Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ------------- ---- -------- --------- --------- ------- -------- --------
+    input_a:rsc.z IN   Unsigned         8                                     
+    input_b:rsc.z IN   Unsigned         8                                     
+    clk           IN   Unsigned         1                                     
+    en            IN   Unsigned         1                                     
+    arst_n        IN   Unsigned         1                                     
+    output:rsc.z  OUT  Unsigned         8                                     
+    
+  Memory Resources
+    Resource Name: /dot_product/input_a:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 8
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable             Indices Phys Memory Address     
+      -------------------- ------- -----------------------
+      /dot_product/input_a     0:7 00000000-00000000 (0-0) 
+      
+    Resource Name: /dot_product/input_b:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 8
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable             Indices Phys Memory Address     
+      -------------------- ------- -----------------------
+      /dot_product/input_b     0:7 00000000-00000000 (0-0) 
+      
+    Resource Name: /dot_product/output:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 8
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable            Indices Phys Memory Address     
+      ------------------- ------- -----------------------
+      /dot_product/output     0:7 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process           Loop             Iterations C-Steps Total Cycles   Duration  Unroll Init Comments 
+    ----------------- ---------------- ---------- ------- ------------- ---------- ------ ---- --------
+    /dot_product/core main               Infinite       2            5  100.00 ns            1          
+    
+  Loop Execution Profile
+    Process           Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------------- ---------------- ------------ -------------------------- ----------------- --------
+    /dot_product/core main                       5                      100.00                5           
+    
+  End of Report
diff --git a/dot_product/dot_product/dot_product.v10/cycle.v b/dot_product/dot_product/dot_product.v10/cycle.v
new file mode 100644
index 0000000..d3d682f
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/cycle.v
@@ -0,0 +1,164 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 15:39:34 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg exit_MAC_lpi;
+    reg [7:0] acc_sva_1;
+    reg [2:0] i_1_sva_1;
+    reg exit_MAC_sva;
+
+    begin : mainExit
+      forever begin : main
+        // C-Step 0 of Loop 'main'
+        begin : waitLoop0Exit
+          forever begin : waitLoop0
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop0Exit;
+          end
+        end
+        // C-Step 1 of Loop 'main'
+        acc_sva_1 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
+            * input_b_rsc_mgc_in_wire_d);
+        i_1_sva_1 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
+        exit_MAC_sva = ~ (readslicef_4_1_3((conv_u2s_3_4(i_1_sva_1) + 4'b1011)));
+        if ( exit_MAC_sva ) begin
+          output_rsc_mgc_out_stdreg_d <= acc_sva_1;
+        end
+        exit_MAC_lpi = exit_MAC_sva;
+      end
+    end
+    exit_MAC_sva = 1'b0;
+    i_1_sva_1 = 3'b0;
+    acc_sva_1 = 8'b0;
+    exit_MAC_lpi = 1'b0;
+    output_rsc_mgc_out_stdreg_d <= 8'b0;
+    exit_MAC_lpi = 1'b1;
+  end
+
+
+  function [7:0] signext_8_1;
+    input [0:0] vector;
+  begin
+    signext_8_1= {{7{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [0:0] readslicef_4_1_3;
+    input [3:0] vector;
+    reg [3:0] tmp;
+  begin
+    tmp = vector >> 3;
+    readslicef_4_1_3 = tmp[0:0];
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_16_8 ;
+    input signed [15:0]  vector ;
+  begin
+    conv_s2s_16_8 = vector[7:0];
+  end
+  endfunction
+
+
+  function signed [3:0] conv_u2s_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2s_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/dot_product.v10/cycle_mgc_ioport.v b/dot_product/dot_product/dot_product.v10/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/dot_product/dot_product/dot_product.v10/cycle_mgc_ioport_v2001.v b/dot_product/dot_product/dot_product.v10/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/dot_product/dot_product/dot_product.v10/cycle_set.tcl b/dot_product/dot_product/dot_product.v10/cycle_set.tcl
new file mode 100644
index 0000000..11460ff
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/cycle_set.tcl
@@ -0,0 +1,16 @@
+
+# Loop constraints
+directive set /dot_product/core/main CSTEPS_FROM {{. == 2}}
+
+# IO operation constraints
+directive set /dot_product/core/main/MAC:io_read(input_a:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:io_read(input_b:rsc.d) CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/io_write(output:rsc.d) CSTEPS_FROM {{.. == 1}}
+
+# Real operation constraints
+directive set /dot_product/core/main/MAC:and CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:mul CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:acc#3 CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:and#1 CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:acc#4 CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:acc CSTEPS_FROM {{.. == 1}}
diff --git a/dot_product/dot_product/dot_product.v10/directives.tcl b/dot_product/dot_product/dot_product.v10/directives.tcl
new file mode 100644
index 0000000..0a1d9a9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/MAC -UNROLL no
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+go architect
+go extract
diff --git a/dot_product/dot_product/dot_product.v10/dut_v_ports.map b/dot_product/dot_product/dot_product.v10/dut_v_ports.map
new file mode 100644
index 0000000..6890ebd
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/dut_v_ports.map
@@ -0,0 +1,6 @@
+clk 1 bit bool
+en 1 bit sc_logic
+arst_n 1 bit sc_logic
+input_a_rsc_z 8 bit_vector sc_lv
+input_b_rsc_z 8 bit_vector sc_lv
+output_rsc_z 8 bit_vector sc_lv
diff --git a/dot_product/dot_product/dot_product.v10/dut_vhdl_ports.map b/dot_product/dot_product/dot_product.v10/dut_vhdl_ports.map
new file mode 100644
index 0000000..23977c8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/dut_vhdl_ports.map
@@ -0,0 +1,6 @@
+clk 1 std_logic bool
+en 1 std_logic sc_logic
+arst_n 1 std_logic sc_logic
+input_a_rsc_z 8 std_logic_vector sc_lv
+input_b_rsc_z 8 std_logic_vector sc_lv
+output_rsc_z 8 std_logic_vector sc_lv
diff --git a/dot_product/dot_product/dot_product.v10/gate.v b/dot_product/dot_product/dot_product.v10/gate.v
new file mode 100644
index 0000000..42dcd48
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/gate.v
@@ -0,0 +1 @@
+Placeholder for gate netlist generated by Precision RTL Synthesis
diff --git a/dot_product/dot_product/dot_product.v10/mapped.v b/dot_product/dot_product/dot_product.v10/mapped.v
new file mode 100644
index 0000000..4345e81
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/mapped.v
@@ -0,0 +1 @@
+Placeholder for mapped netlist generated by Precision RTL Synthesis
diff --git a/dot_product/dot_product/dot_product.v10/messages.txt b/dot_product/dot_product/dot_product.v10/messages.txt
new file mode 100644
index 0000000..1b7ec2f
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/messages.txt
@@ -0,0 +1,177 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v6' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v7' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v8' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v9' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v10' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v10' (SOL-8)
+Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 15, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 15, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 6, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 6, Vars = 8) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 6, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 45, Real ops = 11, Vars = 22) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 23, Real ops = 10, Vars = 6) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v10': elapsed time 3.62 seconds, memory usage 192028kB, peak memory usage 204352kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v10' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 356.83, 0.00, 356.83 (CRAAS-11)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 356.83, 0.00, 356.83 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v10': elapsed time 0.06 seconds, memory usage 192028kB, peak memory usage 204352kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Global signal 'input_a:rsc.z' added to design 'dot_product' for component 'input_a:rsc:mgc_in_wire' (LIB-3)
+Global signal 'input_b:rsc.z' added to design 'dot_product' for component 'input_b:rsc:mgc_in_wire' (LIB-3)
+Global signal 'output:rsc.z' added to design 'dot_product' for component 'output:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'dot_product.v10' (SOL-8)
+Optimizing partition '/dot_product': (Total ops = 49, Real ops = 11, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 36, Real ops = 10, Vars = 16) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 30, Real ops = 10, Vars = 10) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 17, Real ops = 10, Vars = 4) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 10, Vars = 19) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 10, Vars = 10) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 17, Real ops = 10, Vars = 4) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 10, Vars = 19) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 10, Vars = 10) (SOL-10)
+Completed transformation 'schedule' on solution 'dot_product.v10': elapsed time 1.12 seconds, memory usage 193784kB, peak memory usage 204352kB (SOL-9)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'dot_product.v10' (SOL-8)
+Optimizing partition '/dot_product': (Total ops = 43, Real ops = 13, Vars = 35) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 13, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 43, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10)
+Completed transformation 'dpfsm' on solution 'dot_product.v10': elapsed time 0.08 seconds, memory usage 193784kB, peak memory usage 204352kB (SOL-9)
+
+# Messages from "go extract"
+
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'dot_product.v10' (SOL-8)
+Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 31) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 22) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 32) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 23) (SOL-10)
+Reassigned operation MAC:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,3) (ASG-1)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 32) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 23) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10)
+Completed transformation 'extract' on solution 'dot_product.v10': elapsed time 2.64 seconds, memory usage 194292kB, peak memory usage 204352kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v10/new_ccs_env.mk b/dot_product/dot_product/dot_product.v10/new_ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/new_ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v10/reg_sharing.tcl b/dot_product/dot_product/dot_product.v10/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/reg_sharing.tcl
diff --git a/dot_product/dot_product/dot_product.v10/res_sharing.tcl b/dot_product/dot_product/dot_product.v10/res_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/res_sharing.tcl
diff --git a/dot_product/dot_product/dot_product.v10/rtl.rpt b/dot_product/dot_product/dot_product.v10/rtl.rpt
new file mode 100644
index 0000000..d3305da
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl.rpt
@@ -0,0 +1,291 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-015                                 
+-- Generated date:              Tue Mar 01 15:39:39 +0000 2016                      
+
+Solution Settings: dot_product.v10
+  Current state: extract
+  Project: dot_product
+  
+  Design Input Files Specified
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+      $MGC_HOME/shared/include/mc_scverify.h
+  
+  Processes/Blocks in Design
+    Process           Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ----------------- ----------------------- ------- ---------- ------------ -- --------
+    /dot_product/core                      12       5          5            0  1          
+    Design Total:                          12       5          5            0  1          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(3,0,2,0,3)                           4.306                       0.000      4.306 0.764          0           1 
+    mgc_add(3,0,2,1,3)                           4.000                       0.000      4.000 0.764          1           1 
+    mgc_add(4,0,3,0,4)                           5.297                       0.000      5.297 0.856          1           0 
+    mgc_add(8,0,8,0,8)                           9.259                       0.000      9.259 1.163          1           1 
+    mgc_and(3,2)                                 2.189                       0.000      2.189 0.263          1           1 
+    mgc_and(8,2)                                 5.839                       0.000      5.839 0.263          1           1 
+    mgc_mul(8,0,8,0,8)                         330.250                       2.000     10.250 2.659          1           1 
+    mgc_mux(8,1,2)                               7.355                       0.000      7.355 0.369          0           1 
+    mgc_not(1)                                   0.000                       0.000      0.000 0.000          0           3 
+    mgc_reg_pos(1,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(3,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           1 
+    mgc_reg_pos(8,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           2 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,8)                             0.000                       0.000      0.000 0.000          1           1 
+    mgc_in_wire(2,8)                             0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(3,8)                          0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):             363.198                       2.000     43.000                              
+    
+  Area Scores
+                      Post-Scheduling  Post-DP & FSM Post-Assignment 
+    ----------------- --------------- -------------- ---------------
+    Total Area Score:    356.8          364.2           363.2        
+    Total Reg:             0.0            0.0             0.0        
+                                                                     
+    DataPath:            356.8 (100%)   364.2 (100%)    363.2 (100%) 
+      MUX:                 0.0            7.4   (2%)      7.4   (2%) 
+      FUNC:              348.8  (98%)   348.8  (96%)    347.8  (96%) 
+      LOGIC:               8.0   (2%)     8.0   (2%)      8.0   (2%) 
+      BUFFER:              0.0            0.0             0.0        
+      MEM:                 0.0            0.0             0.0        
+      ROM:                 0.0            0.0             0.0        
+      REG:                 0.0            0.0             0.0        
+                                                                     
+    
+    FSM:                   0.0            0.0             0.0        
+      FSM-REG:             0.0            0.0             0.0        
+      FSM-COMB:            0.0            0.0             0.0        
+                                                                     
+    
+  Register-to-Variable Mappings
+    Register                    Size(bits) Gated Register CG Opt Done Variables                                             
+    --------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    acc.sva#1                            8         Y                  acc.sva#1                                             
+    output:rsc:mgc_out_stdreg.d          8         Y                  output:rsc:mgc_out_stdreg.d                           
+    i#1.sva#1                            3         Y                  i#1.sva#1                                             
+    exit:MAC.lpi                         1         Y                  exit:MAC.lpi                                          
+                                                                                                                            
+    Total:                              20             20           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  4.191306
+      Slack:      15.808694
+      
+      Path                                                Startpoint                                 Endpoint                                          Delay  Slack   
+      --------------------------------------------------- ------------------------------------------ ------------------------------------------------- ------ -------
+      1                                                   dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 4.1913 15.8087 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/input_a:rsc:mgc_in_wire.d                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:mul                          mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC:mul.itm                                                                                                                   0.0000 2.6592  
+        dot_product:core/MAC:acc#3                        mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/acc.sva#2                                                                                                                     0.0000 3.8223  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 4.1913  
+        dot_product:core/mux.itm                                                                                                                       0.0000 4.1913  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 4.1913  
+                                                                                                                                                                      
+      2                                                   dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 4.1913 15.8087 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/input_b:rsc:mgc_in_wire.d                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:mul                          mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC:mul.itm                                                                                                                   0.0000 2.6592  
+        dot_product:core/MAC:acc#3                        mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/acc.sva#2                                                                                                                     0.0000 3.8223  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 4.1913  
+        dot_product:core/mux.itm                                                                                                                       0.0000 4.1913  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 4.1913  
+                                                                                                                                                                      
+      3                                                   dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 3.8223 16.1777 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/input_a:rsc:mgc_in_wire.d                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:mul                          mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC:mul.itm                                                                                                                   0.0000 2.6592  
+        dot_product:core/MAC:acc#3                        mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/acc.sva#2                                                                                                                     0.0000 3.8223  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 4.1913  
+        dot_product:core/mux.itm                                                                                                                       0.0000 4.1913  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 4.1913  
+                                                                                                                                                                      
+      4                                                   dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 3.8223 16.1777 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/input_b:rsc:mgc_in_wire.d                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:mul                          mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC:mul.itm                                                                                                                   0.0000 2.6592  
+        dot_product:core/MAC:acc#3                        mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/acc.sva#2                                                                                                                     0.0000 3.8223  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 4.1913  
+        dot_product:core/mux.itm                                                                                                                       0.0000 4.1913  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 4.1913  
+                                                                                                                                                                      
+      5                                                   dot_product:core/reg(i#1.sva#1)            dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 2.1603 17.8397 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/reg(i#1.sva#1)                   mgc_reg_pos_3_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/i#1.sva#1                                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:and#1                        mgc_and_3_2                                                                                  0.2625 0.2625  
+        dot_product:core/MAC:and#1.itm                                                                                                                 0.0000 0.2625  
+        dot_product:core/MAC:acc#4                        mgc_add_3_0_2_1_3                                                                            0.7644 1.0269  
+        dot_product:core/i#1.sva#2                                                                                                                     0.0000 1.0269  
+        dot_product:core/MAC:acc                          mgc_add_3_0_2_0_3                                                                            0.7644 1.7913  
+        dot_product:core/MAC:acc.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/MAC:slc                                                                                                                       0.0000 1.7913  
+        dot_product:core/MAC:slc.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 2.1603  
+        dot_product:core/mux.itm                                                                                                                       0.0000 2.1603  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 2.1603  
+                                                                                                                                                                      
+      6                                                   dot_product:core/reg(exit:MAC.lpi)         dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 2.1603 17.8397 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/reg(exit:MAC.lpi)                mgc_reg_pos_1_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/exit:MAC.lpi                                                                                                                  0.0000 0.0000  
+        dot_product:core/MAC:not#5                        mgc_not_1                                                                                    0.0000 0.0000  
+        dot_product:core/MAC:not#5.itm                                                                                                                 0.0000 0.0000  
+        dot_product:core/MAC:exs#1                                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:exs#1.itm                                                                                                                 0.0000 0.0000  
+        dot_product:core/MAC:and#1                        mgc_and_3_2                                                                                  0.2625 0.2625  
+        dot_product:core/MAC:and#1.itm                                                                                                                 0.0000 0.2625  
+        dot_product:core/MAC:acc#4                        mgc_add_3_0_2_1_3                                                                            0.7644 1.0269  
+        dot_product:core/i#1.sva#2                                                                                                                     0.0000 1.0269  
+        dot_product:core/MAC:acc                          mgc_add_3_0_2_0_3                                                                            0.7644 1.7913  
+        dot_product:core/MAC:acc.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/MAC:slc                                                                                                                       0.0000 1.7913  
+        dot_product:core/MAC:slc.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 2.1603  
+        dot_product:core/mux.itm                                                                                                                       0.0000 2.1603  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 2.1603  
+                                                                                                                                                                      
+      7                                                   dot_product:core/reg(i#1.sva#1)            dot_product:core/reg(exit:MAC.lpi)                1.7913 18.2087 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/reg(i#1.sva#1)                   mgc_reg_pos_3_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/i#1.sva#1                                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:and#1                        mgc_and_3_2                                                                                  0.2625 0.2625  
+        dot_product:core/MAC:and#1.itm                                                                                                                 0.0000 0.2625  
+        dot_product:core/MAC:acc#4                        mgc_add_3_0_2_1_3                                                                            0.7644 1.0269  
+        dot_product:core/i#1.sva#2                                                                                                                     0.0000 1.0269  
+        dot_product:core/MAC:acc                          mgc_add_3_0_2_0_3                                                                            0.7644 1.7913  
+        dot_product:core/MAC:acc.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/MAC:slc#1                                                                                                                     0.0000 1.7913  
+        dot_product:core/MAC:slc#1.itm                                                                                                                 0.0000 1.7913  
+        dot_product:core/MAC:not                          mgc_not_1                                                                                    0.0000 1.7913  
+        dot_product:core/MAC:not.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/reg(exit:MAC.lpi)                mgc_reg_pos_1_1_0_0_0_1_1                                                                    0.0000 1.7913  
+                                                                                                                                                                      
+      8                                                   dot_product:core/reg(exit:MAC.lpi)         dot_product:core/reg(exit:MAC.lpi)                1.7913 18.2087 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/reg(exit:MAC.lpi)                mgc_reg_pos_1_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/exit:MAC.lpi                                                                                                                  0.0000 0.0000  
+        dot_product:core/MAC:not#5                        mgc_not_1                                                                                    0.0000 0.0000  
+        dot_product:core/MAC:not#5.itm                                                                                                                 0.0000 0.0000  
+        dot_product:core/MAC:exs#1                                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:exs#1.itm                                                                                                                 0.0000 0.0000  
+        dot_product:core/MAC:and#1                        mgc_and_3_2                                                                                  0.2625 0.2625  
+        dot_product:core/MAC:and#1.itm                                                                                                                 0.0000 0.2625  
+        dot_product:core/MAC:acc#4                        mgc_add_3_0_2_1_3                                                                            0.7644 1.0269  
+        dot_product:core/i#1.sva#2                                                                                                                     0.0000 1.0269  
+        dot_product:core/MAC:acc                          mgc_add_3_0_2_0_3                                                                            0.7644 1.7913  
+        dot_product:core/MAC:acc.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/MAC:slc#1                                                                                                                     0.0000 1.7913  
+        dot_product:core/MAC:slc#1.itm                                                                                                                 0.0000 1.7913  
+        dot_product:core/MAC:not                          mgc_not_1                                                                                    0.0000 1.7913  
+        dot_product:core/MAC:not.itm                                                                                                                   0.0000 1.7913  
+        dot_product:core/reg(exit:MAC.lpi)                mgc_reg_pos_1_1_0_0_0_1_1                                                                    0.0000 1.7913  
+                                                                                                                                                                      
+      9                                                   dot_product:core/reg(acc.sva#1)            dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 1.4256 18.5744 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/reg(acc.sva#1)                   mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/acc.sva#1                                                                                                                     0.0000 0.0000  
+        dot_product:core/MAC:and                          mgc_and_8_2                                                                                  0.2625 0.2625  
+        dot_product:core/MAC:and.itm                                                                                                                   0.0000 0.2625  
+        dot_product:core/MAC:acc#3                        mgc_add_8_0_8_0_8                                                                            1.1631 1.4256  
+        dot_product:core/acc.sva#2                                                                                                                     0.0000 1.4256  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 1.7946  
+        dot_product:core/mux.itm                                                                                                                       0.0000 1.7946  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 1.7946  
+                                                                                                                                                                      
+      10                                                  dot_product:core/reg(exit:MAC.lpi)         dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 1.4256 18.5744 
+                                                                                                                                                                      
+        Instance                                          Component                                                                                    Delta  Delay   
+        --------                                          ---------                                                                                    -----  -----   
+        dot_product:core/reg(exit:MAC.lpi)                mgc_reg_pos_1_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/exit:MAC.lpi                                                                                                                  0.0000 0.0000  
+        dot_product:core/MAC:not#3                        mgc_not_1                                                                                    0.0000 0.0000  
+        dot_product:core/MAC:not#3.itm                                                                                                                 0.0000 0.0000  
+        dot_product:core/MAC:exs                                                                                                                       0.0000 0.0000  
+        dot_product:core/MAC:exs.itm                                                                                                                   0.0000 0.0000  
+        dot_product:core/MAC:and                          mgc_and_8_2                                                                                  0.2625 0.2625  
+        dot_product:core/MAC:and.itm                                                                                                                   0.0000 0.2625  
+        dot_product:core/MAC:acc#3                        mgc_add_8_0_8_0_8                                                                            1.1631 1.4256  
+        dot_product:core/acc.sva#2                                                                                                                     0.0000 1.4256  
+        dot_product:core/mux                              mgc_mux_8_1_2                                                                                0.3690 1.7946  
+        dot_product:core/mux.itm                                                                                                                       0.0000 1.7946  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 1.7946  
+                                                                                                                                                                      
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                          Port           Slack (Delay) Messages 
+      ------------------------------------------------- ------------ ------- ------- --------
+      dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mux.itm      15.8087  4.1913          
+      dot_product:core/reg(acc.sva#1)                   acc.sva#2    15.8087  4.1913          
+      dot_product:core/reg(i#1.sva#1)                   i#1.sva#2    17.8397  2.1603          
+      dot_product:core/reg(exit:MAC.lpi)                MAC:not.itm  18.2087  1.7913          
+      dot_product                                       output:rsc.z 20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                    8     1 
+    -                    3     2 
+    and                          
+    -                    2     2 
+    mul                          
+    -                    8     1 
+    mux                          
+    -                    1     1 
+    not                          
+    -                    1     3 
+    read_port                    
+    -                    8     2 
+    reg                          
+    -                    8     2 
+    -                    3     1 
+    -                    1     1 
+    write_port                   
+    -                    8     1 
+    
+  End of Report
diff --git a/dot_product/dot_product/dot_product.v10/rtl.v b/dot_product/dot_product/dot_product.v10/rtl.v
new file mode 100644
index 0000000..fb3b8d5
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl.v
@@ -0,0 +1,163 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 15:39:39 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg exit_MAC_lpi;
+  reg [7:0] acc_sva_1;
+  reg [2:0] i_1_sva_1;
+  wire [2:0] MAC_acc_itm;
+  wire [3:0] nl_MAC_acc_itm;
+  wire [7:0] acc_sva_2;
+  wire [8:0] nl_acc_sva_2;
+  wire [2:0] i_1_sva_2;
+  wire [3:0] nl_i_1_sva_2;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_acc_sva_2 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
+      * input_b_rsc_mgc_in_wire_d);
+  assign acc_sva_2 = nl_acc_sva_2[7:0];
+  assign nl_i_1_sva_2 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
+  assign i_1_sva_2 = nl_i_1_sva_2[2:0];
+  assign nl_MAC_acc_itm = i_1_sva_2 + 3'b11;
+  assign MAC_acc_itm = nl_MAC_acc_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      output_rsc_mgc_out_stdreg_d <= 8'b0;
+      acc_sva_1 <= 8'b0;
+      i_1_sva_1 <= 3'b0;
+      exit_MAC_lpi <= 1'b1;
+    end
+    else begin
+      if ( en ) begin
+        output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({acc_sva_2 , output_rsc_mgc_out_stdreg_d},
+            MAC_acc_itm[2]);
+        acc_sva_1 <= acc_sva_2;
+        i_1_sva_1 <= i_1_sva_2;
+        exit_MAC_lpi <= ~ (MAC_acc_itm[2]);
+      end
+    end
+  end
+
+  function [7:0] signext_8_1;
+    input [0:0] vector;
+  begin
+    signext_8_1= {{7{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [7:0] MUX_v_8_2_2;
+    input [15:0] inputs;
+    input [0:0] sel;
+    reg [7:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[15:8];
+      end
+      1'b1 : begin
+        result = inputs[7:0];
+      end
+      default : begin
+        result = inputs[15:8];
+      end
+    endcase
+    MUX_v_8_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_16_8 ;
+    input signed [15:0]  vector ;
+  begin
+    conv_s2s_16_8 = vector[7:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/dot_product.v10/rtl.v.psr b/dot_product/dot_product/dot_product.v10/rtl.v.psr
new file mode 100644
index 0000000..34051fd
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl.v.psr
@@ -0,0 +1,304 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl.v}} -format verilog
+   setup_design -design=dot_product
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'dot_product': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'dot_product': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'dot_product'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'dot_product'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to output_rsc_z(7:0)
+   report_timing -from en -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_a_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_a_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_b_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_b_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock clk] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock en] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'dot_product'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'dot_product'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 mapped.v]
+          puts "-- Writing mapped netlist for 'dot_product' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 gate.v]
+          set gate_sdf [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/dot_product/dot_product/dot_product.v10/rtl.v.psr_timing b/dot_product/dot_product/dot_product.v10/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/dot_product/dot_product/dot_product.v10/rtl.v_order.txt b/dot_product/dot_product/dot_product.v10/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport.v b/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport_v2001.v b/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/dot_product/dot_product/dot_product.v10/schedule.gnt b/dot_product/dot_product/dot_product.v10/schedule.gnt
new file mode 100644
index 0000000..ad658c3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/schedule.gnt
@@ -0,0 +1,31 @@
+set a(0-312) {NAME MAC:asn TYPE ASSIGN PAR 0-311 XREFS 1207 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-335 {}}} SUCCS {{259 0 0-313 {}} {256 0 0-335 {}}} CYCLES {}}
+set a(0-313) {NAME MAC:select TYPE SELECT PAR 0-311 XREFS 1208 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-312 {}}} SUCCS {} CYCLES {}}
+set a(0-314) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-311 XREFS 1209 LOC {0 1.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{262 0 0-335 {}}} SUCCS {{259 0 0-315 {}} {256 0 0-335 {}}} CYCLES {}}
+set a(0-315) {NAME MAC:not#1 TYPE NOT PAR 0-311 XREFS 1210 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-314 {}}} SUCCS {{259 0 0-316 {}}} CYCLES {}}
+set a(0-316) {NAME MAC:exs TYPE SIGNEXTEND PAR 0-311 XREFS 1211 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-315 {}}} SUCCS {{259 0 0-317 {}}} CYCLES {}}
+set a(0-317) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(8,2) AREA_SCORE 5.84 QUANTITY 1 NAME MAC:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-311 XREFS 1212 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.9273052062638539 1 0.9273052062638539} PREDS {{262 0 0-333 {}} {259 0 0-316 {}}} SUCCS {{258 0 0-321 {}} {256 0 0-333 {}}} CYCLES {}}
+set a(0-318) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-311 XREFS 1213 LOC {1 0.0 1 0.761104025 1 0.761104025 1 0.761104025 1 0.761104025} PREDS {{80 0 0-319 {}}} SUCCS {{80 0 0-319 {}} {258 0 0-320 {}}} CYCLES {}}
+set a(0-319) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-311 XREFS 1214 LOC {1 0.0 1 0.761104025 1 0.761104025 1 0.761104025 1 0.761104025} PREDS {{80 0 0-318 {}}} SUCCS {{80 0 0-318 {}} {259 0 0-320 {}}} CYCLES {}}
+set a(0-320) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-311 XREFS 1215 LOC {1 0.0 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-318 {}} {259 0 0-319 {}}} SUCCS {{259 0 0-321 {}}} CYCLES {}}
+set a(0-321) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-311 XREFS 1216 LOC {1 0.16620122499999998 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-317 {}} {259 0 0-320 {}}} SUCCS {{258 0 0-332 {}} {258 0 0-333 {}}} CYCLES {}}
+set a(0-322) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-311 XREFS 1217 LOC {0 1.0 1 0.88229375 1 0.88229375 1 0.88229375} PREDS {{262 0 0-335 {}}} SUCCS {{259 0 0-323 {}} {256 0 0-335 {}}} CYCLES {}}
+set a(0-323) {NAME MAC:not#2 TYPE NOT PAR 0-311 XREFS 1218 LOC {1 0.0 1 0.88229375 1 0.88229375 1 0.88229375} PREDS {{259 0 0-322 {}}} SUCCS {{259 0 0-324 {}}} CYCLES {}}
+set a(0-324) {NAME MAC:exs#1 TYPE SIGNEXTEND PAR 0-311 XREFS 1219 LOC {1 0.0 1 0.88229375 1 0.88229375 1 0.88229375} PREDS {{259 0 0-323 {}}} SUCCS {{259 0 0-325 {}}} CYCLES {}}
+set a(0-325) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(3,2) AREA_SCORE 2.19 QUANTITY 1 NAME MAC:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-311 XREFS 1220 LOC {1 0.0 1 0.88229375 1 0.88229375 1 0.8987004812638539 1 0.8987004812638539} PREDS {{262 0 0-334 {}} {259 0 0-324 {}}} SUCCS {{259 0 0-326 {}} {256 0 0-334 {}}} CYCLES {}}
+set a(0-326) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-311 XREFS 1221 LOC {1 0.016406775 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{259 0 0-325 {}}} SUCCS {{259 0 0-327 {}} {258 0 0-334 {}}} CYCLES {}}
+set a(0-327) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-311 XREFS 1222 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-326 {}}} SUCCS {{259 0 0-328 {}}} CYCLES {}}
+set a(0-328) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-311 XREFS 1223 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-327 {}}} SUCCS {{259 0 0-329 {}}} CYCLES {}}
+set a(0-329) {NAME MAC:slc TYPE READSLICE PAR 0-311 XREFS 1224 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-328 {}}} SUCCS {{259 0 0-330 {}}} CYCLES {}}
+set a(0-330) {NAME MAC:not TYPE NOT PAR 0-311 XREFS 1225 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-329 {}}} SUCCS {{259 0 0-331 {}} {258 0 0-335 {}}} CYCLES {}}
+set a(0-331) {NAME MAC:select#1 TYPE SELECT PAR 0-311 XREFS 1226 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-330 {}}} SUCCS {{131 0 0-332 {}}} CYCLES {}}
+set a(0-332) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-311 XREFS 1227 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-332 {}} {258 0 0-321 {}} {131 0 0-331 {}}} SUCCS {{260 0 0-332 {}}} CYCLES {}}
+set a(0-333) {NAME MAC:asn(acc.lpi) TYPE ASSIGN PAR 0-311 XREFS 1228 LOC {1 0.23889597499999998 1 1.0 1 1.0 2 0.910898475} PREDS {{260 0 0-333 {}} {256 0 0-317 {}} {258 0 0-321 {}}} SUCCS {{262 0 0-317 {}} {260 0 0-333 {}}} CYCLES {}}
+set a(0-334) {NAME MAC:asn(i#1.lpi) TYPE ASSIGN PAR 0-311 XREFS 1229 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 2 0.88229375} PREDS {{260 0 0-334 {}} {256 0 0-325 {}} {258 0 0-326 {}}} SUCCS {{262 0 0-325 {}} {260 0 0-334 {}}} CYCLES {}}
+set a(0-335) {NAME MAC:asn(exit:MAC.lpi) TYPE ASSIGN PAR 0-311 XREFS 1230 LOC {1 0.11770625 1 1.0 1 1.0 2 0.88229375} PREDS {{260 0 0-335 {}} {256 0 0-312 {}} {256 0 0-314 {}} {256 0 0-322 {}} {258 0 0-330 {}}} SUCCS {{262 0 0-312 {}} {262 0 0-314 {}} {262 0 0-322 {}} {260 0 0-335 {}}} CYCLES {}}
+set a(0-311) {CHI {0-312 0-313 0-314 0-315 0-316 0-317 0-318 0-319 0-320 0-321 0-322 0-323 0-324 0-325 0-326 0-327 0-328 0-329 0-330 0-331 0-332 0-333 0-334 0-335} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME main TYPE LOOP DELAY {120.00 ns} PAR {} XREFS 1231 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-311-TOTALCYCLES) {5}
+set a(0-311-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2) 0-317 mgc_ioport.mgc_in_wire(1,8) 0-318 mgc_ioport.mgc_in_wire(2,8) 0-319 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-320 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-321 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2) 0-325 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-326 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-328 mgc_ioport.mgc_out_stdreg(3,8) 0-332}
+set a(0-311-PROC_NAME) {core}
+set a(0-311-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-311}
+
diff --git a/dot_product/dot_product/dot_product.v10/schematic.nlv b/dot_product/dot_product/dot_product.v10/schematic.nlv
new file mode 100644
index 0000000..fb586c0
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/schematic.nlv
@@ -0,0 +1,614 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "dot_product:core" "orig"
+load port {clk} input -attr xrf 1376 -attr oid 1 -attr vt d -attr @path {/dot_product/dot_product:core/clk}
+load port {en} input -attr xrf 1377 -attr oid 2 -attr vt d -attr @path {/dot_product/dot_product:core/en}
+load port {arst_n} input -attr xrf 1378 -attr oid 3 -attr vt d -attr @path {/dot_product/dot_product:core/arst_n}
+load portBus {input_a:rsc:mgc_in_wire.d(7:0)} input 8 {input_a:rsc:mgc_in_wire.d(7)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(0)} -attr xrf 1379 -attr oid 4 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load portBus {input_b:rsc:mgc_in_wire.d(7:0)} input 8 {input_b:rsc:mgc_in_wire.d(7)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(0)} -attr xrf 1380 -attr oid 5 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load portBus {output:rsc:mgc_out_stdreg.d(7:0)} output 8 {output:rsc:mgc_out_stdreg.d(7)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(0)} -attr xrf 1381 -attr oid 6 -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load symbol "mux(2,8)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(7:0)} input 8 {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(7:0)} input 8 {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(8,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(7:0)} input 8 {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(7:0)} input 8 {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(3,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(2:0)} input 3 {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(2:0)} input 3 {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "not(1)" "INTERFACE" INV boxcolor 0 \
+     portBus {A(0:0)} input 1 {A(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "reg(1,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(0:0)} input 1 {D(0)} \
+     portBus {DRa(0:0)} input 1 {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(0:0)} output 1 {Z(0)} \
+
+load symbol "and(2,8)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(7:0)} input 8 {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(7:0)} input 8 {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(8,-1,8,-1,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(8,-1,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "and(2,3)" "INTERFACE" AND boxcolor 0 \
+     portBus {A0(2:0)} input 3 {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(2:0)} input 3 {A1(2)} {A1(1)} {A1(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,1,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(0:0)} input 1 {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "add(3,-1,2,0,3)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(2:0)} input 3 {A(2)} {A(1)} {A(0)} \
+     portBus {B(1:0)} input 2 {B(1)} {B(0)} \
+     portBus {Z(2:0)} output 3 {Z(2)} {Z(1)} {Z(0)} \
+
+load net {acc.sva#1(0)} -attr vt d
+load net {acc.sva#1(1)} -attr vt d
+load net {acc.sva#1(2)} -attr vt d
+load net {acc.sva#1(3)} -attr vt d
+load net {acc.sva#1(4)} -attr vt d
+load net {acc.sva#1(5)} -attr vt d
+load net {acc.sva#1(6)} -attr vt d
+load net {acc.sva#1(7)} -attr vt d
+load netBundle {acc.sva#1} 8 {acc.sva#1(0)} {acc.sva#1(1)} {acc.sva#1(2)} {acc.sva#1(3)} {acc.sva#1(4)} {acc.sva#1(5)} {acc.sva#1(6)} {acc.sva#1(7)} -attr xrf 1382 -attr oid 7 -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {i#1.sva#1(0)} -attr vt d
+load net {i#1.sva#1(1)} -attr vt d
+load net {i#1.sva#1(2)} -attr vt d
+load netBundle {i#1.sva#1} 3 {i#1.sva#1(0)} {i#1.sva#1(1)} {i#1.sva#1(2)} -attr xrf 1383 -attr oid 8 -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load net {acc.sva#2(0)} -attr vt d
+load net {acc.sva#2(1)} -attr vt d
+load net {acc.sva#2(2)} -attr vt d
+load net {acc.sva#2(3)} -attr vt d
+load net {acc.sva#2(4)} -attr vt d
+load net {acc.sva#2(5)} -attr vt d
+load net {acc.sva#2(6)} -attr vt d
+load net {acc.sva#2(7)} -attr vt d
+load netBundle {acc.sva#2} 8 {acc.sva#2(0)} {acc.sva#2(1)} {acc.sva#2(2)} {acc.sva#2(3)} {acc.sva#2(4)} {acc.sva#2(5)} {acc.sva#2(6)} {acc.sva#2(7)} -attr xrf 1384 -attr oid 9 -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {i#1.sva#2(0)} -attr vt d
+load net {i#1.sva#2(1)} -attr vt d
+load net {i#1.sva#2(2)} -attr vt d
+load netBundle {i#1.sva#2} 3 {i#1.sva#2(0)} {i#1.sva#2(1)} {i#1.sva#2(2)} -attr xrf 1385 -attr oid 10 -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
+load net {mux.itm(2)} -attr vt d
+load net {mux.itm(3)} -attr vt d
+load net {mux.itm(4)} -attr vt d
+load net {mux.itm(5)} -attr vt d
+load net {mux.itm(6)} -attr vt d
+load net {mux.itm(7)} -attr vt d
+load netBundle {mux.itm} 8 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} -attr xrf 1386 -attr oid 11 -attr vt d -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {MAC:and.itm(0)} -attr vt d
+load net {MAC:and.itm(1)} -attr vt d
+load net {MAC:and.itm(2)} -attr vt d
+load net {MAC:and.itm(3)} -attr vt d
+load net {MAC:and.itm(4)} -attr vt d
+load net {MAC:and.itm(5)} -attr vt d
+load net {MAC:and.itm(6)} -attr vt d
+load net {MAC:and.itm(7)} -attr vt d
+load netBundle {MAC:and.itm} 8 {MAC:and.itm(0)} {MAC:and.itm(1)} {MAC:and.itm(2)} {MAC:and.itm(3)} {MAC:and.itm(4)} {MAC:and.itm(5)} {MAC:and.itm(6)} {MAC:and.itm(7)} -attr xrf 1387 -attr oid 12 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:exs.itm(0)} -attr vt d
+load net {MAC:exs.itm(1)} -attr vt d
+load net {MAC:exs.itm(2)} -attr vt d
+load net {MAC:exs.itm(3)} -attr vt d
+load net {MAC:exs.itm(4)} -attr vt d
+load net {MAC:exs.itm(5)} -attr vt d
+load net {MAC:exs.itm(6)} -attr vt d
+load net {MAC:exs.itm(7)} -attr vt d
+load netBundle {MAC:exs.itm} 8 {MAC:exs.itm(0)} {MAC:exs.itm(1)} {MAC:exs.itm(2)} {MAC:exs.itm(3)} {MAC:exs.itm(4)} {MAC:exs.itm(5)} {MAC:exs.itm(6)} {MAC:exs.itm(7)} -attr xrf 1388 -attr oid 13 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:mul.itm(0)} -attr vt d
+load net {MAC:mul.itm(1)} -attr vt d
+load net {MAC:mul.itm(2)} -attr vt d
+load net {MAC:mul.itm(3)} -attr vt d
+load net {MAC:mul.itm(4)} -attr vt d
+load net {MAC:mul.itm(5)} -attr vt d
+load net {MAC:mul.itm(6)} -attr vt d
+load net {MAC:mul.itm(7)} -attr vt d
+load netBundle {MAC:mul.itm} 8 {MAC:mul.itm(0)} {MAC:mul.itm(1)} {MAC:mul.itm(2)} {MAC:mul.itm(3)} {MAC:mul.itm(4)} {MAC:mul.itm(5)} {MAC:mul.itm(6)} {MAC:mul.itm(7)} -attr xrf 1389 -attr oid 14 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:and#1.itm(0)} -attr vt d
+load net {MAC:and#1.itm(1)} -attr vt d
+load net {MAC:and#1.itm(2)} -attr vt d
+load netBundle {MAC:and#1.itm} 3 {MAC:and#1.itm(0)} {MAC:and#1.itm(1)} {MAC:and#1.itm(2)} -attr xrf 1390 -attr oid 15 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load net {MAC:exs#1.itm(0)} -attr vt d
+load net {MAC:exs#1.itm(1)} -attr vt d
+load net {MAC:exs#1.itm(2)} -attr vt d
+load netBundle {MAC:exs#1.itm} 3 {MAC:exs#1.itm(0)} {MAC:exs#1.itm(1)} {MAC:exs#1.itm(2)} -attr xrf 1391 -attr oid 16 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
+load net {clk} -attr xrf 1392 -attr oid 17
+load net {clk} -port {clk} -attr xrf 1393 -attr oid 18
+load net {en} -attr xrf 1394 -attr oid 19
+load net {en} -port {en} -attr xrf 1395 -attr oid 20
+load net {arst_n} -attr xrf 1396 -attr oid 21
+load net {arst_n} -port {arst_n} -attr xrf 1397 -attr oid 22
+load net {input_a:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_a:rsc:mgc_in_wire.d} 8 {input_a:rsc:mgc_in_wire.d(0)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(7)} -attr xrf 1398 -attr oid 23 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(0)} -port {input_a:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(1)} -port {input_a:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(2)} -port {input_a:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(3)} -port {input_a:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(4)} -port {input_a:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(5)} -port {input_a:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(6)} -port {input_a:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(7)} -port {input_a:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_a:rsc:mgc_in_wire.d} 8 {input_a:rsc:mgc_in_wire.d(0)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(7)} -attr xrf 1399 -attr oid 24 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_b:rsc:mgc_in_wire.d} 8 {input_b:rsc:mgc_in_wire.d(0)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(7)} -attr xrf 1400 -attr oid 25 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(0)} -port {input_b:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(1)} -port {input_b:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(2)} -port {input_b:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(3)} -port {input_b:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(4)} -port {input_b:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(5)} -port {input_b:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(6)} -port {input_b:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(7)} -port {input_b:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_b:rsc:mgc_in_wire.d} 8 {input_b:rsc:mgc_in_wire.d(0)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(7)} -attr xrf 1401 -attr oid 26 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {output:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load netBundle {output:rsc:mgc_out_stdreg.d} 8 {output:rsc:mgc_out_stdreg.d(0)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(7)} -attr xrf 1402 -attr oid 27 -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(0)} -port {output:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(1)} -port {output:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(2)} -port {output:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(3)} -port {output:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(4)} -port {output:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(5)} -port {output:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(6)} -port {output:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(7)} -port {output:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load inst "mux" "mux(2,8)" "INTERFACE" -attr xrf 1403 -attr oid 28 -attr vt dc -attr @path {/dot_product/dot_product:core/mux} -attr area 7.356384 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,1,2)"
+load net {output:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A0(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A0(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A0(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A0(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A0(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {acc.sva#2(0)} -pin  "mux" {A1(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(1)} -pin  "mux" {A1(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(2)} -pin  "mux" {A1(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(3)} -pin  "mux" {A1(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(4)} -pin  "mux" {A1(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(5)} -pin  "mux" {A1(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(6)} -pin  "mux" {A1(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(7)} -pin  "mux" {A1(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {MAC:acc.itm(2)} -pin  "mux" {S(0)} -attr @path {/dot_product/dot_product:core/MAC:slc.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load inst "reg(output:rsc:mgc_out_stdreg.d)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 1404 -attr oid 29 -attr vt dc -attr @path {/dot_product/dot_product:core/reg(output:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {clk} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 1405 -attr oid 30 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {output:rsc:mgc_out_stdreg.d(0)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(1)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(2)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(3)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(4)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(5)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(6)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(7)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load inst "reg(acc.sva#1)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 1406 -attr oid 31 -attr vt d -attr @path {/dot_product/dot_product:core/reg(acc.sva#1)}
+load net {acc.sva#2(0)} -pin  "reg(acc.sva#1)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(1)} -pin  "reg(acc.sva#1)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(2)} -pin  "reg(acc.sva#1)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(3)} -pin  "reg(acc.sva#1)" {D(3)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(4)} -pin  "reg(acc.sva#1)" {D(4)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(5)} -pin  "reg(acc.sva#1)" {D(5)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(6)} -pin  "reg(acc.sva#1)" {D(6)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(7)} -pin  "reg(acc.sva#1)" {D(7)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(acc.sva#1)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {clk} -pin  "reg(acc.sva#1)" {clk} -attr xrf 1407 -attr oid 32 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(acc.sva#1)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(acc.sva#1)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {acc.sva#1(0)} -pin  "reg(acc.sva#1)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(1)} -pin  "reg(acc.sva#1)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(2)} -pin  "reg(acc.sva#1)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(3)} -pin  "reg(acc.sva#1)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(4)} -pin  "reg(acc.sva#1)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(5)} -pin  "reg(acc.sva#1)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(6)} -pin  "reg(acc.sva#1)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(7)} -pin  "reg(acc.sva#1)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load inst "reg(i#1.sva#1)" "reg(3,1,1,-1,0)" "INTERFACE" -attr xrf 1408 -attr oid 33 -attr vt d -attr @path {/dot_product/dot_product:core/reg(i#1.sva#1)}
+load net {i#1.sva#2(0)} -pin  "reg(i#1.sva#1)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {i#1.sva#2(1)} -pin  "reg(i#1.sva#1)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {i#1.sva#2(2)} -pin  "reg(i#1.sva#1)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {GND} -pin  "reg(i#1.sva#1)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_3}
+load net {GND} -pin  "reg(i#1.sva#1)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_3}
+load net {GND} -pin  "reg(i#1.sva#1)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_3}
+load net {clk} -pin  "reg(i#1.sva#1)" {clk} -attr xrf 1409 -attr oid 34 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(i#1.sva#1)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(i#1.sva#1)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {i#1.sva#1(0)} -pin  "reg(i#1.sva#1)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load net {i#1.sva#1(1)} -pin  "reg(i#1.sva#1)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load net {i#1.sva#1(2)} -pin  "reg(i#1.sva#1)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load inst "MAC:not" "not(1)" "INTERFACE" -attr xrf 1410 -attr oid 35 -attr @path {/dot_product/dot_product:core/MAC:not} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {MAC:acc.itm(2)} -pin  "MAC:not" {A(0)} -attr @path {/dot_product/dot_product:core/MAC:slc#1.itm}
+load net {MAC:not.itm} -pin  "MAC:not" {Z(0)} -attr @path {/dot_product/dot_product:core/MAC:not.itm}
+load inst "reg(exit:MAC.lpi)" "reg(1,1,1,-1,0)" "INTERFACE" -attr xrf 1411 -attr oid 36 -attr @path {/dot_product/dot_product:core/reg(exit:MAC.lpi)}
+load net {MAC:not.itm} -pin  "reg(exit:MAC.lpi)" {D(0)} -attr @path {/dot_product/dot_product:core/MAC:not.itm}
+load net {PWR} -pin  "reg(exit:MAC.lpi)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C1_1}
+load net {clk} -pin  "reg(exit:MAC.lpi)" {clk} -attr xrf 1412 -attr oid 37 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(exit:MAC.lpi)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(exit:MAC.lpi)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {exit:MAC.lpi} -pin  "reg(exit:MAC.lpi)" {Z(0)} -attr @path {/dot_product/dot_product:core/exit:MAC.lpi}
+load inst "MAC:not#3" "not(1)" "INTERFACE" -attr xrf 1413 -attr oid 38 -attr @path {/dot_product/dot_product:core/MAC:not#3} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:MAC.lpi} -pin  "MAC:not#3" {A(0)} -attr @path {/dot_product/dot_product:core/exit:MAC.lpi}
+load net {MAC:not#3.itm} -pin  "MAC:not#3" {Z(0)} -attr @path {/dot_product/dot_product:core/MAC:not#3.itm}
+load inst "MAC:and" "and(2,8)" "INTERFACE" -attr xrf 1414 -attr oid 39 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and} -attr area 5.838659 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2)"
+load net {acc.sva#1(0)} -pin  "MAC:and" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(1)} -pin  "MAC:and" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(2)} -pin  "MAC:and" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(3)} -pin  "MAC:and" {A0(3)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(4)} -pin  "MAC:and" {A0(4)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(5)} -pin  "MAC:and" {A0(5)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(6)} -pin  "MAC:and" {A0(6)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {acc.sva#1(7)} -pin  "MAC:and" {A0(7)} -attr vt d -attr @path {/dot_product/dot_product:core/acc.sva#1}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:not#3.itm} -pin  "MAC:and" {A1(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs.itm}
+load net {MAC:and.itm(0)} -pin  "MAC:and" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(1)} -pin  "MAC:and" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(2)} -pin  "MAC:and" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(3)} -pin  "MAC:and" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(4)} -pin  "MAC:and" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(5)} -pin  "MAC:and" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(6)} -pin  "MAC:and" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(7)} -pin  "MAC:and" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load inst "MAC:mul" "mul(8,-1,8,-1,8)" "INTERFACE" -attr xrf 1415 -attr oid 40 -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8)"
+load net {input_a:rsc:mgc_in_wire.d(0)} -pin  "MAC:mul" {A(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(1)} -pin  "MAC:mul" {A(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(2)} -pin  "MAC:mul" {A(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(3)} -pin  "MAC:mul" {A(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(4)} -pin  "MAC:mul" {A(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(5)} -pin  "MAC:mul" {A(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(6)} -pin  "MAC:mul" {A(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(7)} -pin  "MAC:mul" {A(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(0)} -pin  "MAC:mul" {B(0)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(1)} -pin  "MAC:mul" {B(1)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(2)} -pin  "MAC:mul" {B(2)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(3)} -pin  "MAC:mul" {B(3)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(4)} -pin  "MAC:mul" {B(4)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(5)} -pin  "MAC:mul" {B(5)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(6)} -pin  "MAC:mul" {B(6)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(7)} -pin  "MAC:mul" {B(7)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {MAC:mul.itm(0)} -pin  "MAC:mul" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(1)} -pin  "MAC:mul" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(2)} -pin  "MAC:mul" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(3)} -pin  "MAC:mul" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(4)} -pin  "MAC:mul" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(5)} -pin  "MAC:mul" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(6)} -pin  "MAC:mul" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(7)} -pin  "MAC:mul" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load inst "MAC:acc#3" "add(8,-1,8,-1,8)" "INTERFACE" -attr xrf 1416 -attr oid 41 -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:acc#3} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)"
+load net {MAC:and.itm(0)} -pin  "MAC:acc#3" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(1)} -pin  "MAC:acc#3" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(2)} -pin  "MAC:acc#3" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(3)} -pin  "MAC:acc#3" {A(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(4)} -pin  "MAC:acc#3" {A(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(5)} -pin  "MAC:acc#3" {A(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(6)} -pin  "MAC:acc#3" {A(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:and.itm(7)} -pin  "MAC:acc#3" {A(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and.itm}
+load net {MAC:mul.itm(0)} -pin  "MAC:acc#3" {B(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(1)} -pin  "MAC:acc#3" {B(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(2)} -pin  "MAC:acc#3" {B(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(3)} -pin  "MAC:acc#3" {B(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(4)} -pin  "MAC:acc#3" {B(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(5)} -pin  "MAC:acc#3" {B(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(6)} -pin  "MAC:acc#3" {B(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {MAC:mul.itm(7)} -pin  "MAC:acc#3" {B(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC:mul.itm}
+load net {acc.sva#2(0)} -pin  "MAC:acc#3" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(1)} -pin  "MAC:acc#3" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(2)} -pin  "MAC:acc#3" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(3)} -pin  "MAC:acc#3" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(4)} -pin  "MAC:acc#3" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(5)} -pin  "MAC:acc#3" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(6)} -pin  "MAC:acc#3" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load net {acc.sva#2(7)} -pin  "MAC:acc#3" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/acc.sva#2}
+load inst "MAC:not#5" "not(1)" "INTERFACE" -attr xrf 1417 -attr oid 42 -attr @path {/dot_product/dot_product:core/MAC:not#5} -attr area 0.001000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_not(1)"
+load net {exit:MAC.lpi} -pin  "MAC:not#5" {A(0)} -attr @path {/dot_product/dot_product:core/exit:MAC.lpi}
+load net {MAC:not#5.itm} -pin  "MAC:not#5" {Z(0)} -attr @path {/dot_product/dot_product:core/MAC:not#5.itm}
+load inst "MAC:and#1" "and(2,3)" "INTERFACE" -attr xrf 1418 -attr oid 43 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1} -attr area 2.189497 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2)"
+load net {i#1.sva#1(0)} -pin  "MAC:and#1" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load net {i#1.sva#1(1)} -pin  "MAC:and#1" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load net {i#1.sva#1(2)} -pin  "MAC:and#1" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#1}
+load net {MAC:not#5.itm} -pin  "MAC:and#1" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
+load net {MAC:not#5.itm} -pin  "MAC:and#1" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
+load net {MAC:not#5.itm} -pin  "MAC:and#1" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:exs#1.itm}
+load net {MAC:and#1.itm(0)} -pin  "MAC:and#1" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load net {MAC:and#1.itm(1)} -pin  "MAC:and#1" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load net {MAC:and#1.itm(2)} -pin  "MAC:and#1" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load inst "MAC:acc#4" "add(3,-1,1,0,3)" "INTERFACE" -attr xrf 1419 -attr oid 44 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#4} -attr area 4.000000 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3)"
+load net {MAC:and#1.itm(0)} -pin  "MAC:acc#4" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load net {MAC:and#1.itm(1)} -pin  "MAC:acc#4" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load net {MAC:and#1.itm(2)} -pin  "MAC:acc#4" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:and#1.itm}
+load net {PWR} -pin  "MAC:acc#4" {B(0)} -attr @path {/dot_product/dot_product:core/C1_1#1}
+load net {i#1.sva#2(0)} -pin  "MAC:acc#4" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {i#1.sva#2(1)} -pin  "MAC:acc#4" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {i#1.sva#2(2)} -pin  "MAC:acc#4" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load inst "MAC:acc" "add(3,-1,2,0,3)" "INTERFACE" -attr xrf 1420 -attr oid 45 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc} -attr area 4.306828 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,3)"
+load net {i#1.sva#2(0)} -pin  "MAC:acc" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {i#1.sva#2(1)} -pin  "MAC:acc" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {i#1.sva#2(2)} -pin  "MAC:acc" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/i#1.sva#2}
+load net {PWR} -pin  "MAC:acc" {B(0)} -attr @path {/dot_product/dot_product:core/C3_2}
+load net {PWR} -pin  "MAC:acc" {B(1)} -attr @path {/dot_product/dot_product:core/C3_2}
+load net {MAC:acc.itm(0)} -pin  "MAC:acc" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(1)} -pin  "MAC:acc" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(2)} -pin  "MAC:acc" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+### END MODULE 
+
+module new "dot_product" "orig"
+load portBus {input_a:rsc.z(7:0)} input 8 {input_a:rsc.z(7)} {input_a:rsc.z(6)} {input_a:rsc.z(5)} {input_a:rsc.z(4)} {input_a:rsc.z(3)} {input_a:rsc.z(2)} {input_a:rsc.z(1)} {input_a:rsc.z(0)} -attr xrf 1421 -attr oid 46 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load portBus {input_b:rsc.z(7:0)} input 8 {input_b:rsc.z(7)} {input_b:rsc.z(6)} {input_b:rsc.z(5)} {input_b:rsc.z(4)} {input_b:rsc.z(3)} {input_b:rsc.z(2)} {input_b:rsc.z(1)} {input_b:rsc.z(0)} -attr xrf 1422 -attr oid 47 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load portBus {output:rsc.z(7:0)} output 8 {output:rsc.z(7)} {output:rsc.z(6)} {output:rsc.z(5)} {output:rsc.z(4)} {output:rsc.z(3)} {output:rsc.z(2)} {output:rsc.z(1)} {output:rsc.z(0)} -attr xrf 1423 -attr oid 48 -attr vt d -attr @path {/dot_product/output:rsc.z}
+load port {clk} input -attr xrf 1424 -attr oid 49 -attr vt d -attr @path {/dot_product/clk}
+load port {en} input -attr xrf 1425 -attr oid 50 -attr vt d -attr @path {/dot_product/en}
+load port {arst_n} input -attr xrf 1426 -attr oid 51 -attr vt d -attr @path {/dot_product/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,8)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(7:0)} output 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(7:0)} input 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_in_wire(2,8)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(7:0)} output 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(7:0)} input 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(3,8)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(7:0)} input 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(7:0)} output 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "dot_product:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {input_a:rsc:mgc_in_wire.d(7:0)} input 8 {input_a:rsc:mgc_in_wire.d(7)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(0)} \
+     portBus {input_b:rsc:mgc_in_wire.d(7:0)} input 8 {input_b:rsc:mgc_in_wire.d(7)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(0)} \
+     portBus {output:rsc:mgc_out_stdreg.d(7:0)} output 8 {output:rsc:mgc_out_stdreg.d(7)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(0)} \
+
+load net {input_a:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load netBundle {input_a:rsc:mgc_in_wire.d#1} 8 {input_a:rsc:mgc_in_wire.d#1(0)} {input_a:rsc:mgc_in_wire.d#1(1)} {input_a:rsc:mgc_in_wire.d#1(2)} {input_a:rsc:mgc_in_wire.d#1(3)} {input_a:rsc:mgc_in_wire.d#1(4)} {input_a:rsc:mgc_in_wire.d#1(5)} {input_a:rsc:mgc_in_wire.d#1(6)} {input_a:rsc:mgc_in_wire.d#1(7)} -attr xrf 1427 -attr oid 52 -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load netBundle {input_b:rsc:mgc_in_wire.d#1} 8 {input_b:rsc:mgc_in_wire.d#1(0)} {input_b:rsc:mgc_in_wire.d#1(1)} {input_b:rsc:mgc_in_wire.d#1(2)} {input_b:rsc:mgc_in_wire.d#1(3)} {input_b:rsc:mgc_in_wire.d#1(4)} {input_b:rsc:mgc_in_wire.d#1(5)} {input_b:rsc:mgc_in_wire.d#1(6)} {input_b:rsc:mgc_in_wire.d#1(7)} -attr xrf 1428 -attr oid 53 -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {output:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load netBundle {output:rsc:mgc_out_stdreg.d#1} 8 {output:rsc:mgc_out_stdreg.d#1(0)} {output:rsc:mgc_out_stdreg.d#1(1)} {output:rsc:mgc_out_stdreg.d#1(2)} {output:rsc:mgc_out_stdreg.d#1(3)} {output:rsc:mgc_out_stdreg.d#1(4)} {output:rsc:mgc_out_stdreg.d#1(5)} {output:rsc:mgc_out_stdreg.d#1(6)} {output:rsc:mgc_out_stdreg.d#1(7)} -attr xrf 1429 -attr oid 54 -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {input_a:rsc.z(0)} -attr vt d
+load net {input_a:rsc.z(1)} -attr vt d
+load net {input_a:rsc.z(2)} -attr vt d
+load net {input_a:rsc.z(3)} -attr vt d
+load net {input_a:rsc.z(4)} -attr vt d
+load net {input_a:rsc.z(5)} -attr vt d
+load net {input_a:rsc.z(6)} -attr vt d
+load net {input_a:rsc.z(7)} -attr vt d
+load netBundle {input_a:rsc.z} 8 {input_a:rsc.z(0)} {input_a:rsc.z(1)} {input_a:rsc.z(2)} {input_a:rsc.z(3)} {input_a:rsc.z(4)} {input_a:rsc.z(5)} {input_a:rsc.z(6)} {input_a:rsc.z(7)} -attr xrf 1430 -attr oid 55 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(0)} -port {input_a:rsc.z(0)} -attr vt d
+load net {input_a:rsc.z(1)} -port {input_a:rsc.z(1)} -attr vt d
+load net {input_a:rsc.z(2)} -port {input_a:rsc.z(2)} -attr vt d
+load net {input_a:rsc.z(3)} -port {input_a:rsc.z(3)} -attr vt d
+load net {input_a:rsc.z(4)} -port {input_a:rsc.z(4)} -attr vt d
+load net {input_a:rsc.z(5)} -port {input_a:rsc.z(5)} -attr vt d
+load net {input_a:rsc.z(6)} -port {input_a:rsc.z(6)} -attr vt d
+load net {input_a:rsc.z(7)} -port {input_a:rsc.z(7)} -attr vt d
+load netBundle {input_a:rsc.z} 8 {input_a:rsc.z(0)} {input_a:rsc.z(1)} {input_a:rsc.z(2)} {input_a:rsc.z(3)} {input_a:rsc.z(4)} {input_a:rsc.z(5)} {input_a:rsc.z(6)} {input_a:rsc.z(7)} -attr xrf 1431 -attr oid 56 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_b:rsc.z(0)} -attr vt d
+load net {input_b:rsc.z(1)} -attr vt d
+load net {input_b:rsc.z(2)} -attr vt d
+load net {input_b:rsc.z(3)} -attr vt d
+load net {input_b:rsc.z(4)} -attr vt d
+load net {input_b:rsc.z(5)} -attr vt d
+load net {input_b:rsc.z(6)} -attr vt d
+load net {input_b:rsc.z(7)} -attr vt d
+load netBundle {input_b:rsc.z} 8 {input_b:rsc.z(0)} {input_b:rsc.z(1)} {input_b:rsc.z(2)} {input_b:rsc.z(3)} {input_b:rsc.z(4)} {input_b:rsc.z(5)} {input_b:rsc.z(6)} {input_b:rsc.z(7)} -attr xrf 1432 -attr oid 57 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(0)} -port {input_b:rsc.z(0)} -attr vt d
+load net {input_b:rsc.z(1)} -port {input_b:rsc.z(1)} -attr vt d
+load net {input_b:rsc.z(2)} -port {input_b:rsc.z(2)} -attr vt d
+load net {input_b:rsc.z(3)} -port {input_b:rsc.z(3)} -attr vt d
+load net {input_b:rsc.z(4)} -port {input_b:rsc.z(4)} -attr vt d
+load net {input_b:rsc.z(5)} -port {input_b:rsc.z(5)} -attr vt d
+load net {input_b:rsc.z(6)} -port {input_b:rsc.z(6)} -attr vt d
+load net {input_b:rsc.z(7)} -port {input_b:rsc.z(7)} -attr vt d
+load netBundle {input_b:rsc.z} 8 {input_b:rsc.z(0)} {input_b:rsc.z(1)} {input_b:rsc.z(2)} {input_b:rsc.z(3)} {input_b:rsc.z(4)} {input_b:rsc.z(5)} {input_b:rsc.z(6)} {input_b:rsc.z(7)} -attr xrf 1433 -attr oid 58 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {output:rsc.z(0)} -attr vt d
+load net {output:rsc.z(1)} -attr vt d
+load net {output:rsc.z(2)} -attr vt d
+load net {output:rsc.z(3)} -attr vt d
+load net {output:rsc.z(4)} -attr vt d
+load net {output:rsc.z(5)} -attr vt d
+load net {output:rsc.z(6)} -attr vt d
+load net {output:rsc.z(7)} -attr vt d
+load netBundle {output:rsc.z} 8 {output:rsc.z(0)} {output:rsc.z(1)} {output:rsc.z(2)} {output:rsc.z(3)} {output:rsc.z(4)} {output:rsc.z(5)} {output:rsc.z(6)} {output:rsc.z(7)} -attr xrf 1434 -attr oid 59 -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(0)} -port {output:rsc.z(0)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(1)} -port {output:rsc.z(1)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(2)} -port {output:rsc.z(2)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(3)} -port {output:rsc.z(3)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(4)} -port {output:rsc.z(4)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(5)} -port {output:rsc.z(5)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(6)} -port {output:rsc.z(6)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(7)} -port {output:rsc.z(7)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {clk} -attr xrf 1435 -attr oid 60
+load net {clk} -port {clk} -attr xrf 1436 -attr oid 61
+load net {en} -attr xrf 1437 -attr oid 62
+load net {en} -port {en} -attr xrf 1438 -attr oid 63
+load net {arst_n} -attr xrf 1439 -attr oid 64
+load net {arst_n} -port {arst_n} -attr xrf 1440 -attr oid 65
+load inst "dot_product:core:inst" "dot_product:core" "orig" -attr xrf 1441 -attr oid 66 -attr vt dc -attr @path {/dot_product/dot_product:core:inst} -attr area 363.202905 -attr delay 2.160303 -attr hier "/dot_product/dot_product:core" -pg 1 -lvl 3
+load net {clk} -pin  "dot_product:core:inst" {clk#1} -attr xrf 1442 -attr oid 67 -attr @path {/dot_product/clk}
+load net {en} -pin  "dot_product:core:inst" {en#1} -attr xrf 1443 -attr oid 68 -attr @path {/dot_product/en}
+load net {arst_n} -pin  "dot_product:core:inst" {arst_n#1} -attr xrf 1444 -attr oid 69 -attr @path {/dot_product/arst_n}
+load net {input_a:rsc:mgc_in_wire.d#1(0)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(1)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(2)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(3)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(4)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(5)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(6)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(7)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(0)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(1)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(2)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(3)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(4)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(5)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(6)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(7)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {output:rsc:mgc_out_stdreg.d#1(0)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(1)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(2)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(3)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(4)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(5)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(6)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(7)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load inst "input_a:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,8)" "INTERFACE" -attr xrf 1445 -attr oid 70 -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,8)" -pg 1 -lvl 1
+load net {input_a:rsc:mgc_in_wire.d#1(0)} -pin  "input_a:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(1)} -pin  "input_a:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(2)} -pin  "input_a:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(3)} -pin  "input_a:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(4)} -pin  "input_a:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(5)} -pin  "input_a:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(6)} -pin  "input_a:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(7)} -pin  "input_a:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc.z(0)} -pin  "input_a:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(1)} -pin  "input_a:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(2)} -pin  "input_a:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(3)} -pin  "input_a:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(4)} -pin  "input_a:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(5)} -pin  "input_a:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(6)} -pin  "input_a:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(7)} -pin  "input_a:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load inst "input_b:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(2,8)" "INTERFACE" -attr xrf 1446 -attr oid 71 -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(2,8)" -pg 1 -lvl 1
+load net {input_b:rsc:mgc_in_wire.d#1(0)} -pin  "input_b:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(1)} -pin  "input_b:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(2)} -pin  "input_b:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(3)} -pin  "input_b:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(4)} -pin  "input_b:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(5)} -pin  "input_b:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(6)} -pin  "input_b:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(7)} -pin  "input_b:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc.z(0)} -pin  "input_b:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(1)} -pin  "input_b:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(2)} -pin  "input_b:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(3)} -pin  "input_b:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(4)} -pin  "input_b:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(5)} -pin  "input_b:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(6)} -pin  "input_b:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(7)} -pin  "input_b:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load inst "output:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(3,8)" "INTERFACE" -attr xrf 1447 -attr oid 72 -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(3,8)" -pg 1 -lvl 1002
+load net {output:rsc:mgc_out_stdreg.d#1(0)} -pin  "output:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(1)} -pin  "output:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(2)} -pin  "output:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(3)} -pin  "output:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(4)} -pin  "output:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(5)} -pin  "output:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(6)} -pin  "output:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(7)} -pin  "output:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc.z(0)} -pin  "output:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(1)} -pin  "output:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(2)} -pin  "output:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(3)} -pin  "output:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(4)} -pin  "output:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(5)} -pin  "output:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(6)} -pin  "output:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(7)} -pin  "output:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+### END MODULE 
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/Verify_cycle_v_msim.mk b/dot_product/dot_product/dot_product.v10/scverify/Verify_cycle_v_msim.mk
new file mode 100644
index 0000000..a847da3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/Verify_cycle_v_msim.mk
@@ -0,0 +1,186 @@
+# ----------------------------------------------------------------------------
+# Cycle Verilog output 'cycle.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 15:39:35 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v10)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = cycle
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/cycle.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v10/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = mgc_hls work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = ./cycle.v/cycle.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC = ./cycle_mgc_ioport.v/cycle_mgc_ioport.v.vts ./cycle_mgc_ioport_v2001.v/cycle_mgc_ioport_v2001.v.vts $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = ./cycle_mgc_ioport.v/cycle_mgc_ioport.v.vts ./cycle_mgc_ioport_v2001.v/cycle_mgc_ioport_v2001.v.vts ./cycle.v/cycle.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp/scverify_top.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/cycle_mgc_ioport.v.vts: ./cycle_mgc_ioport.v
+$(TARGET)/cycle_mgc_ioport_v2001.v.vts: ./cycle_mgc_ioport_v2001.v
+$(TARGET)/cycle.v.vts: ./cycle.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/cycle.v.vts: HDL_LIB=work
+$(TARGET)/cycle_mgc_ioport_v2001.v.vts: HDL_LIB=mgc_hls
+$(TARGET)/cycle_mgc_ioport.v.vts: HDL_LIB=mgc_hls
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+$(TARGET)/cycle.v.vts: DUT_E=dot_product
+
+# Specify top design unit
+$(TARGET)/cycle.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/Verify_gate_v_msim.mk b/dot_product/dot_product/dot_product.v10/scverify/Verify_gate_v_msim.mk
new file mode 100644
index 0000000..46a1a53
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/Verify_gate_v_msim.mk
@@ -0,0 +1,192 @@
+# ----------------------------------------------------------------------------
+# Gate Verilog output 'gate.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 15:39:40 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v10)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = gate
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/rtl.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(RTLTOOL)" ""
+RTLTOOL                     = psr
+endif
+export RTLTOOL
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v10/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# Include auxillary makefiles based on simulation flows
+include $(MGC_HOME)/shared/include/mkfiles/ccs_Altera.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/gate.v/gate.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/gate.v/gate.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp/scverify_top.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/top_gate_constraints.cpp/top_gate_constraints.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/gate.psrv
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/gate.v.vts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/gate.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp
+$(TARGET)/top_gate_constraints.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/top_gate_constraints.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/top_gate_constraints.cpp.cxxts: CXX_OPTS=
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+$(TARGET)/top_gate_constraints.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/gate.v.vts: HDL_LIB=work
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+$(TARGET)/gate.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/Verify_mapped_v_msim.mk b/dot_product/dot_product/dot_product.v10/scverify/Verify_mapped_v_msim.mk
new file mode 100644
index 0000000..437eaeb
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/Verify_mapped_v_msim.mk
@@ -0,0 +1,189 @@
+# ----------------------------------------------------------------------------
+# Mapped Verilog output 'rtl.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 15:39:40 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v10)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = mapped
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/rtl.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(RTLTOOL)" ""
+RTLTOOL                     = psr
+endif
+export RTLTOOL
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v10/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# Include auxillary makefiles based on simulation flows
+include $(MGC_HOME)/shared/include/mkfiles/ccs_Altera.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/mapped.v/mapped.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/mapped.v/mapped.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp/scverify_top.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/mapped.v.vts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/mapped.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/mapped.v.vts: HDL_LIB=work
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+$(TARGET)/mapped.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v10/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..9c881a9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 15:39:17 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v10)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/Verify_rtl_v_msim.mk b/dot_product/dot_product/dot_product.v10/scverify/Verify_rtl_v_msim.mk
new file mode 100644
index 0000000..a049ad7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/Verify_rtl_v_msim.mk
@@ -0,0 +1,186 @@
+# ----------------------------------------------------------------------------
+# RTL Verilog output 'rtl.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 15:39:39 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v10)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = rtl
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v10/rtl.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v10/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = mgc_hls work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = ./rtl.v/rtl.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC = ./rtl_mgc_ioport.v/rtl_mgc_ioport.v.vts ./rtl_mgc_ioport_v2001.v/rtl_mgc_ioport_v2001.v.vts $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = ./rtl_mgc_ioport.v/rtl_mgc_ioport.v.vts ./rtl_mgc_ioport_v2001.v/rtl_mgc_ioport_v2001.v.vts ./rtl.v/rtl.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp/scverify_top.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/rtl_mgc_ioport.v.vts: ./rtl_mgc_ioport.v
+$(TARGET)/rtl_mgc_ioport_v2001.v.vts: ./rtl_mgc_ioport_v2001.v
+$(TARGET)/rtl.v.vts: ./rtl.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/rtl.v.vts: HDL_LIB=work
+$(TARGET)/rtl_mgc_ioport_v2001.v.vts: HDL_LIB=mgc_hls
+$(TARGET)/rtl_mgc_ioport.v.vts: HDL_LIB=mgc_hls
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+$(TARGET)/rtl.v.vts: DUT_E=dot_product
+
+# Specify top design unit
+$(TARGET)/rtl.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/ccs_wave_signals.dat b/dot_product/dot_product/dot_product.v10/scverify/ccs_wave_signals.dat
new file mode 100644
index 0000000..50436ee
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/ccs_wave_signals.dat
@@ -0,0 +1,4 @@
+RADIX hex
+CDEBUG 0
+DEBUGVARS {input_a IN input_a:326:input_a input_b IN input_b:328:input_b output OUT output:329:output}
+WAVELIST {{DUT input_a:rsc input_a_rsc_z {scverify_top rtl input_a_rsc_z} {}} {DUT input_b:rsc input_b_rsc_z {scverify_top rtl input_b_rsc_z} {}} {DUT output:rsc output_rsc_z {scverify_top rtl output_rsc_z} {}} {OutputCompare output output-TRANS# {scverify_top user_tb output_comp _compare_cnt_sig} blue} {OutputCompare output output-GOLDEN {scverify_top user_tb output_comp _golden_sig} {}} {OutputCompare output output-DUT {scverify_top user_tb output_comp _dut_sig} {}} {OutputCompare output output-ERR# {scverify_top user_tb output_comp _error_cnt_sig} red} {Sync_Signals testbench clk {scverify_top rtl clk} {}} {Sync_Signals testbench Master_rst {scverify_top rst} {}} {Sync_Signals testbench cpp_testbench_active {scverify_top user_tb cpp_testbench_active} {}} {Sync_Signals testbench arst_n {scverify_top rtl arst_n} {}} {Sync_Signals testbench in_sync {scverify_top in_sync} {}} {Sync_Signals testbench out_sync {scverify_top out_sync} {}} {Sync_Signals testbench inout_sync {scverify_top inout_sync} {}} {DUT enable en {scverify_top rtl en} {}} {Active_Processes {} deadlock {scverify_top deadlocked} {}}}
diff --git a/dot_product/dot_product/dot_product.v10/scverify/gate.psrv b/dot_product/dot_product/dot_product.v10/scverify/gate.psrv
new file mode 100644
index 0000000..5900d5d
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/gate.psrv
@@ -0,0 +1,304 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl.v}} -format verilog
+   setup_design -design=dot_product
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./scverify/gate.psrv_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'dot_product': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'dot_product': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'dot_product'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'dot_product'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to output_rsc_z(7:0)
+   report_timing -from en -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_a_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_a_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_b_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_b_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock clk] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock en] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'dot_product'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'dot_product'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 mapped.v]
+          puts "-- Writing mapped netlist for 'dot_product' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 gate.v]
+          set gate_sdf [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/dot_product/dot_product/dot_product.v10/scverify/gate.psrv_timing b/dot_product/dot_product/dot_product.v10/scverify/gate.psrv_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/gate.psrv_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv b/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv
new file mode 100644
index 0000000..c5b0e96
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv
@@ -0,0 +1,277 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v10/rtl.v}} -format verilog
+   setup_design -design=dot_product
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./scverify/mapped.psrv_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'dot_product': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'dot_product': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'dot_product'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'dot_product'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to output_rsc_z(7:0)
+   report_timing -from en -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_a_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_a_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_b_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_b_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock clk] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock en] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=0"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'dot_product'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'dot_product'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v10 mapped.v]
+          puts "-- Writing mapped netlist for 'dot_product' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv_timing b/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/mapped.psrv_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/dot_product/dot_product/dot_product.v10/scverify/mc_dut_wrapper.h b/dot_product/dot_product/dot_product.v10/scverify/mc_dut_wrapper.h
new file mode 100644
index 0000000..ee708fc
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/mc_dut_wrapper.h
@@ -0,0 +1,75 @@
+// ----------------------------------------------------------------------------
+// SystemC Wrapper for Catapult Design HDL Netlist
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 15:39:35 +0000 2016
+//
+// ----------------------------------------------------------------------------
+#ifndef INCLUDED_CCS_DUT_WRAPPER_H
+#define INCLUDED_CCS_DUT_WRAPPER_H
+
+#ifndef SC_USE_STD_STRING
+#define SC_USE_STD_STRING
+#endif
+
+#include <systemc.h>
+#include <mc_simulator_extensions.h>
+
+#if defined(CCS_DUT_SYSC)
+
+// alias ccs_DUT_wrapper to namespace enclosure of either cycle or RTL SystemC netlist
+namespace ccs_design {
+#if defined(CCS_DUT_CYCLE)
+//#include "cycle.cxx"
+#include "cycle.cxx"
+#else
+#if defined(CCS_DUT_RTL)
+//#include "rtl.cxx"
+#include "rtl.cxx"
+#endif
+#endif
+}
+typedef ccs_design::HDL::dot_product ccs_DUT_wrapper;
+
+#else
+
+// Create a foreign module wrapper around the HDL
+class ccs_DUT_wrapper : public mc_foreign_module
+{
+public:
+   #ifndef VCS_SYSTEMC
+   // Interface Ports
+   sc_in<bool> clk;
+   sc_in< sc_logic > en;
+   sc_in< sc_logic > arst_n;
+   sc_in< sc_lv<8> > input_a_rsc_z;
+   sc_in< sc_lv<8> > input_b_rsc_z;
+   sc_out< sc_lv<8> > output_rsc_z;
+   #endif
+   
+public:
+   ccs_DUT_wrapper(const sc_module_name& nm, const char *hdl_name)
+      : mc_foreign_module(nm,hdl_name)
+      #ifndef VCS_SYSTEMC
+      ,clk("clk")
+      ,en("en")
+      ,arst_n("arst_n")
+      ,input_a_rsc_z("input_a_rsc_z")
+      ,input_b_rsc_z("input_b_rsc_z")
+      ,output_rsc_z("output_rsc_z")
+      #endif
+      {
+          // elaborate_foreign_module(hdl_name);
+      }
+      
+      ~ccs_DUT_wrapper() {}
+   };
+   
+   #endif
+
+#endif
+
diff --git a/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp b/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp
new file mode 100644
index 0000000..a81fcaf
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.cpp
@@ -0,0 +1,337 @@
+// ----------------------------------------------------------------------------
+// SystemC Testbench Body
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 15:39:35 +0000 2016
+//
+// ----------------------------------------------------------------------------
+// 
+// -------------------------------------
+// testbench
+// User supplied testbench
+// -------------------------------------
+// 
+#include "mc_testbench.h"
+#include <mc_simulator_extensions.h>
+
+testbench* testbench::that;
+std::vector<mc_end_of_testbench*> testbench::_end_of_tb_objs;
+bool testbench::input_a_ignore;
+bool testbench::input_a_skip;
+void mc_testbench_input_a_skip(bool v) { testbench::input_a_skip = v; }
+int testbench::input_a_array_comp_first;
+int testbench::input_a_array_comp_last;
+int testbench::input_a_wait_cycles;
+mc_wait_ctrl testbench::input_a_wait_ctrl;
+bool testbench::input_b_ignore;
+bool testbench::input_b_skip;
+void mc_testbench_input_b_skip(bool v) { testbench::input_b_skip = v; }
+int testbench::input_b_array_comp_first;
+int testbench::input_b_array_comp_last;
+int testbench::input_b_wait_cycles;
+mc_wait_ctrl testbench::input_b_wait_ctrl;
+bool testbench::output_ignore;
+bool testbench::output_skip;
+void mc_testbench_output_skip(bool v) { testbench::output_skip = v; }
+int testbench::output_array_comp_first;
+int testbench::output_array_comp_last;
+bool testbench::output_use_mask;
+ac_int<8, true > testbench::output_output_mask;
+int testbench::output_wait_cycles;
+mc_wait_ctrl testbench::output_wait_ctrl;
+extern "C++" void dot_product( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output);
+
+// ============================================
+// Function: mc_testbench_process_wait_ctrl
+// --------------------------------------------
+
+void testbench::mc_testbench_process_wait_ctrl(const sc_string &var,int &var_wait_cycles,mc_wait_ctrl &var_wait_ctrl,tlm::tlm_fifo_put_if< mc_wait_ctrl > *ccs_wait_ctrl_fifo_if,const int var_capture_count,const int var_stopat)
+{
+   if (var_wait_cycles) {
+      // backward compatibility mode
+      var_wait_ctrl.cycles = var_wait_cycles;
+      var_wait_cycles = 0;
+      std::ostringstream msg; msg.str("");
+      msg << "Depricated use of '" << var << "_wait_cycles' variable. Use '" << var << "_wait_ctrl.cycles' instead.";
+      SC_REPORT_WARNING("User testbench", msg.str().c_str());
+   }
+   if (var_wait_ctrl.cycles != 0) {
+      var_wait_ctrl.iteration = var_capture_count;
+      var_wait_ctrl.stopat = var_stopat;
+      if (var_wait_ctrl.cycles < 0) {
+         std::ostringstream msg; msg.str("");
+         msg << "Ignoring negative value (" << var_wait_ctrl.cycles << ") for testbench control testbench::" << var << "_wait_ctrl.cycles.";
+         SC_REPORT_WARNING("User testbench", msg.str().c_str());
+         var_wait_ctrl.cycles = 0;
+      }
+      if (var_wait_ctrl.interval < 0) {
+         std::ostringstream msg; msg.str("");
+         msg << "Ignoring negative value (" << var_wait_ctrl.interval << ") for testbench control testbench::" << var << "_wait_ctrl.interval.";
+         SC_REPORT_WARNING("User testbench", msg.str().c_str());
+         var_wait_ctrl.interval = 0;
+      }
+      if (var_wait_ctrl.is_set()) {
+         std::ostringstream msg; msg.str("");
+         msg << "Captured wait_ctrl request " << var_wait_ctrl;
+         SC_REPORT_INFO("User testbench", msg.str().c_str());
+         ccs_wait_ctrl_fifo_if->put(var_wait_ctrl);
+      }
+   }
+   var_wait_ctrl.clear(); // reset wait_ctrl
+}
+// ============================================
+// Function: register_end_of_testbench_obj
+// --------------------------------------------
+
+void testbench::register_end_of_testbench_obj(mc_end_of_testbench* obj)
+{
+   _end_of_tb_objs.push_back(obj);
+}
+// ============================================
+// Function: capture_input_a
+// --------------------------------------------
+
+void testbench::capture_input_a( ac_int<8, true > *input_a)
+{
+   if (input_a_capture_count == wait_cnt)
+      wait_on_input_required();
+   if (_capture_input_a && !input_a_ignore)
+   {
+      int cur_iter=input_a_iteration_count;
+      ++input_a_iteration_count;
+      ccs_input_a->put((*input_a));
+      ++input_a_capture_count;
+      mc_testbench_process_wait_ctrl("input_a",input_a_wait_cycles,input_a_wait_ctrl,ccs_wait_ctrl_input_a.operator->(),cur_iter,input_a_capture_count);
+      input_a_ignore = false;
+   }
+}
+// ============================================
+// Function: capture_input_b
+// --------------------------------------------
+
+void testbench::capture_input_b( ac_int<8, true > *input_b)
+{
+   if (input_b_capture_count == wait_cnt)
+      wait_on_input_required();
+   if (_capture_input_b && !input_b_ignore)
+   {
+      int cur_iter=input_b_iteration_count;
+      ++input_b_iteration_count;
+      ccs_input_b->put((*input_b));
+      ++input_b_capture_count;
+      mc_testbench_process_wait_ctrl("input_b",input_b_wait_cycles,input_b_wait_ctrl,ccs_wait_ctrl_input_b.operator->(),cur_iter,input_b_capture_count);
+      input_b_ignore = false;
+   }
+}
+// ============================================
+// Function: capture_output
+// --------------------------------------------
+
+void testbench::capture_output( ac_int<8, true > *output)
+{
+   if (_capture_output)
+   {
+      int cur_iter=output_iteration_count;
+      ++output_iteration_count;
+      mc_golden_info< ac_int<8, true >, ac_int<8, true > > output_tmp((*output), output_ignore, ~0, false, output_iteration_count);
+      // BEGIN: testbench output_mask control for field_name output
+      if ( output_use_mask ) {
+         output_tmp._use_mask = true;
+         output_tmp._mask = output_output_mask ;
+      }
+      // END: testbench output_mask control for field_name output
+      if (!output_skip) {
+         output_golden.put(output_tmp);
+         ++output_capture_count;
+      } else {
+         std::ostringstream msg; msg.str("");
+         msg << "output_skip=true for iteration=" << output_iteration_count << " @ " << sc_time_stamp();
+         SC_REPORT_WARNING("User testbench", msg.str().c_str());
+      }
+      mc_testbench_process_wait_ctrl("output",output_wait_cycles,output_wait_ctrl,ccs_wait_ctrl_output.operator->(),cur_iter,output_capture_count);
+      output_ignore = false;
+      output_use_mask = false;
+   }
+   output_skip = false;
+}
+// ============================================
+// Function: wait_on_input_required
+// --------------------------------------------
+
+void testbench::wait_on_input_required()
+{
+   ++wait_cnt;
+   wait(SC_ZERO_TIME); // get fifos a chance to update
+   while (atleast_one_active_input) {
+      if (_capture_input_a && ccs_input_a->used() == 0) return;
+      if (_capture_input_b && ccs_input_b->used() == 0) return;
+      that->cpp_testbench_active.write(false);
+      wait(ccs_input_a->ok_to_put() | ccs_input_b->ok_to_put());
+      that->cpp_testbench_active.write(true);
+   }
+}
+// ============================================
+// Function: capture_IN
+// --------------------------------------------
+
+void testbench::capture_IN( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output)
+{
+   that->capture_input_a(input_a);
+   that->capture_input_b(input_b);
+}
+// ============================================
+// Function: capture_OUT
+// --------------------------------------------
+
+void testbench::capture_OUT( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output)
+{
+   that->capture_output(output);
+}
+// ============================================
+// Function: exec_dot_product
+// --------------------------------------------
+
+void testbench::exec_dot_product( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output)
+{
+   that->cpp_testbench_active.write(true);
+   capture_IN(input_a, input_b, output);
+   dot_product(input_a, input_b, output);
+   // throttle ac_channel based on number of calls to chan::size() or chan::empty() or chan::nb_read() (but not chan::available()) 
+   if (1) {
+      int cnt=0;
+      if (cnt) std::cout << "mc_testbench.cpp: CONTINUES @ " << sc_time_stamp() << std::endl;
+      if (cnt) that->cpp_testbench_active.write(true);
+   }
+   capture_OUT(input_a, input_b, output);
+}
+// ============================================
+// Function: end_of_simulation
+// --------------------------------------------
+
+void testbench::end_of_simulation()
+{
+   if (!_checked_results) {
+      SC_REPORT_INFO(name(), "Simulation ran into deadlock");
+      check_results();
+   }
+}
+// ============================================
+// Function: check_results
+// --------------------------------------------
+
+void testbench::check_results()
+{
+   for (std::vector<mc_end_of_testbench*>::iterator i = _end_of_tb_objs.begin(); i != _end_of_tb_objs.end(); ++i)
+      (*i)->end_of_testbench();
+   
+   _checked_results = true;
+   cout<<endl;
+   cout<<"Checking results"<<endl;
+   _failed = false;
+   if (main_exit_code) _failed = true;
+   int _num_outputs_checked = 0;
+   
+   if (!_capture_output) {
+      cout<<"'output' - warning, output was optimized away"<<endl;
+   } else {
+      _num_outputs_checked++;
+      cout<<"'output'"<<endl;
+      cout<<"   capture count        = "<<output_capture_count<<endl;
+      cout<<"   comparison count     = "<<output_comp->get_compare_count();
+      if (output_comp->get_partial_compare_count()) 
+         cout <<" ("<<output_comp->get_partial_compare_count()<<" partial)";
+      if (output_comp->get_mask_compare_count()) 
+         cout <<" ("<<output_comp->get_mask_compare_count()<<" masked)";
+      cout << endl;
+      cout<<"   ignore count         = "<<output_comp->get_ignore_count()<<endl;
+      cout<<"   error count          = "<<output_comp->get_error_count()<<endl;
+      cout<<"   stuck in dut fifo    = "<<ccs_output->used()<<endl;
+      cout<<"   stuck in golden fifo = "<<output_golden.used()<<endl;
+      if (output_comp->get_error_count() > 0) cout << "   Error: output 'output' had comparison errors"<<endl;
+      if (output_comp->get_compare_count() < output_capture_count) cout << "   Error: output 'output' has incomplete comparisons"<<endl;
+      if (output_capture_count == 0) cout << "   Error: output 'output' has no golden values to compare against"<<endl;
+      _failed = _failed || output_comp->get_error_count() > 0;
+      _failed = _failed || output_comp->get_compare_count() < output_capture_count;
+      _failed = _failed || output_capture_count == 0;
+      cout<<endl;
+   }
+   cout<<endl;
+   if (_num_outputs_checked == 0) {
+      cout<<"Error: All outputs were optimized away. No output values were compared."<<endl;
+      _failed = _failed || (_num_outputs_checked == 0);
+   }
+   if (main_exit_code) cout << "Error: C++ Testbench 'main()' returned a non-zero exit code ("<<main_exit_code<<"). Check your testbench." <<endl;
+   cout<<(_failed ? "Error: ":"Info: ")<<"Simulation "<<(_failed ? "FAILED":"PASSED")<<" @ "<<sc_time_stamp()<<endl;
+   
+   if (_failed) {
+      cout << endl;
+      cout << "Error: Simulation may have failed due to incorrect testbench stimulus synchronization. Try turning on the TRANSACTION_DONE_SIGNAL directive." << endl;
+   }
+}
+// ============================================
+// Function: failed
+// --------------------------------------------
+
+bool testbench::failed()
+{
+   return _failed;
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD wait_for_end
+// Static sensitivity: sensitive << clk.pos() << testbench_end_event;
+
+void testbench::wait_for_end() {
+   // If run() has not finished, we do nothing here
+   if (!testbench_ended) return;
+   // check for completed outputs
+   if (output_comp->get_compare_count() < output_capture_count) {testbench_end_event.notify(1,SC_NS); return;}
+   // If we made it here, all outputs have flushed. Check the results
+   SC_REPORT_INFO(name(), "Simulation completed");
+   check_results();
+   sc_stop();
+}
+// ---------------------------------------------------------------
+// Process: SC_THREAD run
+// Static sensitivity: 
+
+void testbench::run() {
+   input_a_ignore = false;
+   input_a_skip = false;
+   input_a_array_comp_first = -1;
+   input_a_array_comp_last = -1;
+   input_a_wait_cycles = 0;
+   input_a_wait_ctrl.clear();
+   input_a_capture_count = 0;
+   input_a_iteration_count = 0;
+   input_b_ignore = false;
+   input_b_skip = false;
+   input_b_array_comp_first = -1;
+   input_b_array_comp_last = -1;
+   input_b_wait_cycles = 0;
+   input_b_wait_ctrl.clear();
+   input_b_capture_count = 0;
+   input_b_iteration_count = 0;
+   output_ignore = false;
+   output_skip = false;
+   output_array_comp_first = -1;
+   output_array_comp_last = -1;
+   output_use_mask = false;
+   output_output_mask = ~0;
+   output_wait_cycles = 0;
+   output_wait_ctrl.clear();
+   output_capture_count = 0;
+   output_iteration_count = 0;
+   main_exit_code = main();
+   cout<<"Info: Execution of user-supplied C++ testbench 'main()' has completed with exit code = " << main_exit_code << endl;
+   cout<<endl;
+   cout<<"Info: Collecting data completed"<<endl;
+   cout<<"   captured "<<input_a_capture_count<<" values of input_a"<<endl;
+   cout<<"   captured "<<input_b_capture_count<<" values of input_b"<<endl;
+   cout<<"   captured "<<output_capture_count<<" values of output"<<endl;
+   testbench_ended = true;
+   testbench_end_event.notify(SC_ZERO_TIME);
+}
diff --git a/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.h b/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.h
new file mode 100644
index 0000000..4a5c6ee
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/mc_testbench.h
@@ -0,0 +1,188 @@
+// ----------------------------------------------------------------------------
+// SystemC Testbench Header
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 15:39:35 +0000 2016
+//
+// ----------------------------------------------------------------------------
+#ifdef CCS_SCVERIFY
+
+// 
+// -------------------------------------
+// testbench
+// User supplied testbench
+// -------------------------------------
+// 
+#ifndef INCLUDED_TESTBENCH_H
+#define INCLUDED_TESTBENCH_H
+
+extern void mc_testbench_input_a_skip(bool v);
+extern void mc_testbench_input_b_skip(bool v);
+extern void mc_testbench_output_skip(bool v);
+
+#ifndef SC_USE_STD_STRING
+#define SC_USE_STD_STRING
+#endif
+
+#include "../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h"
+#include <systemc.h>
+#include <tlm.h>
+#include <ac_int.h>
+#include <mc_container_types.h>
+#include <mc_typeconv.h>
+#include <mc_transactors.h>
+#include <mc_comparator.h>
+#include <mc_end_of_testbench.h>
+#include <vector>
+
+
+class testbench : public sc_module
+{
+public:
+   // Interface Ports
+   sc_in< bool > clk;
+   sc_port< tlm::tlm_fifo_put_if< ac_int<8, true > > > ccs_input_a;
+   sc_port< tlm::tlm_fifo_put_if< mc_wait_ctrl > > ccs_wait_ctrl_input_a;
+   sc_port< tlm::tlm_fifo_put_if< ac_int<8, true > > > ccs_input_b;
+   sc_port< tlm::tlm_fifo_put_if< mc_wait_ctrl > > ccs_wait_ctrl_input_b;
+   sc_port< tlm::tlm_fifo_get_if< ac_int<8, true > > > ccs_output;
+   sc_port< tlm::tlm_fifo_put_if< mc_wait_ctrl > > ccs_wait_ctrl_output;
+   
+   // Data objects
+   bool testbench_ended;
+   int main_exit_code;
+   bool atleast_one_active_input;
+   sc_time last_event_time;
+   sc_time last_event_time2;
+   sc_signal< bool >                          cpp_testbench_active;
+   sc_event testbench_end_event;
+   int argc;
+   const char* const *argv;
+   bool _checked_results;
+   bool _failed;
+   static testbench* that;
+   static std::vector<mc_end_of_testbench*> _end_of_tb_objs;
+   int main();
+   static bool input_a_ignore;
+   static bool input_a_skip;
+   static int input_a_array_comp_first;
+   static int input_a_array_comp_last;
+   bool _capture_input_a;
+   static int input_a_wait_cycles;
+   static mc_wait_ctrl input_a_wait_ctrl;
+   int input_a_capture_count;
+   int input_a_iteration_count;
+   static bool input_b_ignore;
+   static bool input_b_skip;
+   static int input_b_array_comp_first;
+   static int input_b_array_comp_last;
+   bool _capture_input_b;
+   static int input_b_wait_cycles;
+   static mc_wait_ctrl input_b_wait_ctrl;
+   int input_b_capture_count;
+   int input_b_iteration_count;
+   static bool output_ignore;
+   static bool output_skip;
+   static int output_array_comp_first;
+   static int output_array_comp_last;
+   static bool output_use_mask;
+   static ac_int<8, true > output_output_mask;
+   tlm::tlm_fifo< mc_golden_info< ac_int<8, true >, ac_int<8, true > > > output_golden;
+   bool _capture_output;
+   static int output_wait_cycles;
+   static mc_wait_ctrl output_wait_ctrl;
+   int output_capture_count;
+   int output_iteration_count;
+   int wait_cnt;
+   
+   // Named Objects
+   
+   // Module instance pointers
+   mc_comparator< ac_int<8, true > , ac_int<8, true > > *output_comp;
+   
+   // Declare processes (SC_METHOD and SC_THREAD)
+   void wait_for_end();
+   void run();
+   
+   // Constructor
+   SC_HAS_PROCESS(testbench);
+   testbench(
+      const sc_module_name& name
+   )
+      : clk("clk")
+      , ccs_input_a("ccs_input_a")
+      , ccs_wait_ctrl_input_a("ccs_wait_ctrl_input_a")
+      , ccs_input_b("ccs_input_b")
+      , ccs_wait_ctrl_input_b("ccs_wait_ctrl_input_b")
+      , ccs_output("ccs_output")
+      , ccs_wait_ctrl_output("ccs_wait_ctrl_output")
+      , cpp_testbench_active("cpp_testbench_active")
+      , output_golden("output_golden",-1)
+   {
+      // Instantiate other modules
+      output_comp = new mc_comparator< ac_int<8, true > , ac_int<8, true > > (
+         "output_comp",
+         0,
+         1
+      );
+      output_comp->data_in(ccs_output);
+      output_comp->data_golden(output_golden);
+      
+      
+      // Register processes
+      SC_METHOD(wait_for_end);
+      sensitive << clk.pos() << testbench_end_event;
+      SC_THREAD(run);
+      // Other constructor statements
+      set_stack_size(64000000);
+      argc = sc_argc();
+      argv = sc_argv();
+      _checked_results = false;
+      that = this;
+      testbench_ended = false;
+      main_exit_code = 0;
+      atleast_one_active_input = true;
+      _capture_input_a = true;
+      _capture_input_b = true;
+      _capture_output = true;
+      wait_cnt = 0;
+   }
+   
+   ~testbench()
+   {
+      delete output_comp;
+      output_comp = 0;
+   }
+   
+   // C++ class functions
+   public:
+      void mc_testbench_process_wait_ctrl(const sc_string &var,int &var_wait_cycles,mc_wait_ctrl &var_wait_ctrl,tlm::tlm_fifo_put_if< mc_wait_ctrl > *ccs_wait_ctrl_fifo_if,const int var_capture_count,const int var_stopat) ;
+   public:
+      static void register_end_of_testbench_obj(mc_end_of_testbench* obj) ;
+   public:
+      void capture_input_a( ac_int<8, true > *input_a) ;
+   public:
+      void capture_input_b( ac_int<8, true > *input_b) ;
+   public:
+      void capture_output( ac_int<8, true > *output) ;
+   protected:
+      void wait_on_input_required() ;
+   public:
+      static void capture_IN( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output) ;
+   public:
+      static void capture_OUT( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output) ;
+   public:
+      static void exec_dot_product( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output) ;
+   protected:
+      void end_of_simulation() ;
+   public:
+      void check_results() ;
+   public:
+      bool failed() ;
+};
+#endif
+#endif
diff --git a/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp b/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp
new file mode 100644
index 0000000..f97e4c8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/scverify_top.cpp
@@ -0,0 +1,289 @@
+// ----------------------------------------------------------------------------
+// SystemC Top Module
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 15:39:35 +0000 2016
+//
+// ----------------------------------------------------------------------------
+//---------------------------------------------------
+// scverify_top.cpp
+//---------------------------------------------------
+
+#include <iostream>
+#include "scverify_top.h"
+#include <mc_simulator_extensions.h>
+// 
+// -------------------------------------
+// scverify_top
+// top module instantiating reference design,
+// DUT and comparator
+// -------------------------------------
+// 
+#include <mt19937ar.c>
+
+
+// ============================================
+// Function: setup_debug
+// --------------------------------------------
+
+void scverify_top::setup_debug()
+{
+   #ifdef MC_DEFAULT_TRANSACTOR_LOG
+      static int input_a_flags = MC_DEFAULT_TRANSACTOR_LOG;
+   #else
+      static int input_a_flags = MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT;
+   #endif
+      static int input_a_count = -1;
+   #ifdef MC_DEFAULT_TRANSACTOR_LOG
+      static int input_b_flags = MC_DEFAULT_TRANSACTOR_LOG;
+   #else
+      static int input_b_flags = MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT;
+   #endif
+      static int input_b_count = -1;
+   #ifdef MC_DEFAULT_TRANSACTOR_LOG
+      static int output_flags = MC_DEFAULT_TRANSACTOR_LOG;
+   #else
+      static int output_flags = MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT;
+   #endif
+      static int output_count = -1;
+   
+      // At the breakpoint, modify the local variables
+      // above to turn on/off different levels of transaction
+      // logging for each variable. Available flags are:
+      //   MC_TRANSACTOR_EMPTY       - log empty FIFOs (on by default)
+      //   MC_TRANSACTOR_UNDERFLOW   - log FIFOs that run empty and then are loaded again (off)
+      //   MC_TRANSACTOR_READ        - log all read events
+      //   MC_TRANSACTOR_WRITE       - log all write events
+      //   MC_TRANSACTOR_LOAD        - log all FIFO load events
+      //   MC_TRANSACTOR_DUMP        - log all FIFO dump events
+      //   MC_TRANSACTOR_STREAMCNT   - log all streamed port index counter events
+      //   MC_TRANSACTOR_WAIT        - log user specified handshake waits
+      //   MC_TRANSACTOR_SIZE        - log input FIFO size updates
+   
+      // In ModelSim, type ccs_extensions::ccs_opts to bring up a GUI to set these options
+   
+      debug("input_a:326:input_a",input_a_flags,input_a_count);
+      debug("input_b:328:input_b",input_b_flags,input_b_count);
+      debug("output:329:output",output_flags,output_count);
+}
+// ============================================
+// Function: install_observe_foreign_signals
+// --------------------------------------------
+
+void scverify_top::install_observe_foreign_signals()
+{
+   #if !defined(CCS_DUT_SYSC) && defined(DEADLOCK_DETECTION)
+   #if defined(CCS_DUT_CYCLE) || defined(CCS_DUT_RTL)
+   #ifdef MTI_SYSTEMC
+   #endif
+   #ifdef VCS_SYSTEMC
+   #if defined(CCS_DUT_VHDL)
+   #include <hdl_connect_vhdl.h>
+   #define HDL_CONNECT_FN hdl_connect_vhdl
+   #else
+   #if defined(CCS_DUT_VERILOG)
+   #include <hdl_connect_v.h>
+   #define HDL_CONNECT_FN hdl_connect_v
+   #endif
+   #endif
+   #endif
+   #ifdef NCSC
+   #endif
+   #endif
+   #endif
+}
+// ============================================
+// Function: debug
+// --------------------------------------------
+
+void scverify_top::debug(const char *varname, int flags, int count)
+{
+   sc_module *xlator_p = 0;
+   sc_attr_base *debug_attr_p = 0;
+   if (strcmp(varname,"input_a:326:input_a") == 0) {
+      xlator_p = input_a_transactor;
+   }
+   if (strcmp(varname,"input_b:328:input_b") == 0) {
+      xlator_p = input_b_transactor;
+   }
+   if (strcmp(varname,"output:329:output") == 0) {
+      xlator_p = output_transactor;
+   }
+   if (xlator_p) {
+      debug_attr_p = xlator_p->get_attribute("MC_TRANSACTOR_EVENT");
+      if (!debug_attr_p) {
+         debug_attr_p = new sc_attribute<int>("MC_TRANSACTOR_EVENT",flags);
+         xlator_p->add_attribute(*debug_attr_p);
+      }
+      ((sc_attribute<int>*)debug_attr_p)->value = flags;
+   }
+   if (count>=0) {
+      debug_attr_p = xlator_p->get_attribute("MC_TRANSACTOR_COUNT");
+      if (!debug_attr_p) {
+         debug_attr_p = new sc_attribute<int>("MC_TRANSACTOR_COUNT",count);
+         xlator_p->add_attribute(*debug_attr_p);
+      }
+      ((sc_attribute<int>*)debug_attr_p)->value = count;
+   }
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD deadlock_notify
+// Static sensitivity: sensitive << deadlock_event;
+
+void scverify_top::deadlock_notify() {
+   if (deadlocked.read() == SC_LOGIC_1) {
+      testbench_INST->check_results();
+      SC_REPORT_ERROR("System","Simulation deadlock detected");
+      sc_stop();
+   }
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD deadlock_watch
+// Static sensitivity: sensitive  << clk;
+
+void scverify_top::deadlock_watch() {
+   // DEADLOCK_WATCH
+   #if !defined(CCS_DUT_SYSC) && defined(DEADLOCK_DETECTION)
+   #if defined(CCS_DUT_CYCLE) || defined(CCS_DUT_RTL)
+   #if defined(MTI_SYSTEMC) || defined(NCSC) || defined(VCS_SYTEMC)
+   #endif
+   #endif
+   #endif
+   // DEADLOCK_WATCH END
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD generate_sync
+// Static sensitivity: sensitive << clk << rst;
+
+void scverify_top::generate_sync() {
+   static int active_edge = 1;
+   static CATMON_EX_TYPE latency = 6LL; // Total Cycles value
+   static CATMON_EX_TYPE init_interval = 1LL;
+   static CATMON_EX_TYPE csteps = 2LL;
+   static CATMON_EX_TYPE duration = latency - csteps + init_interval;
+   static CATMON_EX_TYPE latest_write = 1LL;
+   static bool top_loop_pipelined = true;
+   
+   static CATMON_EX_TYPE max_state = init_interval ? duration : latency;
+   
+   static CATMON_EX_TYPE initial_in_state = ((init_interval>0)&&top_loop_pipelined&&(latency!=csteps)) ? 0 : 1;
+   static CATMON_EX_TYPE initial_out_state = init_interval ? init_interval-latest_write+1 : 1;
+   
+   static int done_flag_used = 0;
+   
+   
+   static CATMON_EX_TYPE in_state = initial_in_state;
+   static CATMON_EX_TYPE out_state = initial_out_state;
+   static sc_logic last_done = SC_LOGIC_0; // if DONE_FLAG used
+   
+   if (rst.read() == 1) {
+      in_sync.write(SC_LOGIC_0);
+      out_sync.write(SC_LOGIC_0);
+      inout_sync.write(SC_LOGIC_0);
+      catapult_start.write(SC_LOGIC_0);
+      in_state = initial_in_state;
+      last_done = SC_LOGIC_1;
+      if (init_interval) {
+         out_state = initial_out_state;
+      } else {
+         if (done_flag_used && (catapult_done.read() == 0)) wait_for_init = 0;
+         out_state = initial_out_state;
+      }
+   } else {
+     if (done_flag_used) {
+         catapult_start.write(catapult_done.read()); // start follows done timing
+         if (catapult_done.read() == SC_LOGIC_0) {
+            // falling edge of done, deassert start
+            wait_for_init.write(wait_for_init.read()+1);
+            out_sync.write(SC_LOGIC_0);
+            in_sync.write(SC_LOGIC_0);
+            inout_sync.write(SC_LOGIC_0);
+         } else {
+            // rising edge of done, assert sync signals
+            if (wait_for_init.read() > 1) {
+               out_sync.write(SC_LOGIC_1);
+               in_sync.write(SC_LOGIC_1);
+               inout_sync.write(SC_LOGIC_1);
+            }
+         }
+     } else {
+      if ( clk.read() == active_edge ) {
+         // wait for static array initialization loop to complete
+         if (wait_for_init) {
+            if (done_flag_used && (catapult_done.read() == 1)) wait_for_init = false;
+         } else {
+            if (((out_state >= max_state) && (init_interval || !done_flag_used)) || (done_flag_used && ((catapult_done.read() == 1) && (last_done == SC_LOGIC_0)))) {
+               out_sync.write(SC_LOGIC_1);
+               inout_sync.write(SC_LOGIC_1);
+               out_state = 0;
+               if (!init_interval) last_done = SC_LOGIC_1;
+               if (init_interval == 0) in_state = max_state; // force in_sync to align with out_sync
+            } else {
+               if ( (init_interval == 0) && (catapult_done.read() == 0) && (last_done == SC_LOGIC_1) ) last_done = SC_LOGIC_0;
+               out_sync.write(SC_LOGIC_0);
+               inout_sync.write(SC_LOGIC_0);
+            }
+            out_state++;
+         } // if (wait_for_init)
+      } // if (clk.read() == active_edge)
+   
+      if ( clk.read() == active_edge ) {
+         // wait for static array initialization loop to complete
+         if (wait_for_init) {
+            if (done_flag_used && (catapult_done.read() == 1)) wait_for_init = false;
+         } else {
+            if ( in_state >= max_state ) {
+               in_sync.write(SC_LOGIC_1);
+               inout_sync.write(SC_LOGIC_1);
+               catapult_start.write(SC_LOGIC_1);
+               in_state = 0;
+            } else {
+               if ( in_state == 1 ) {
+                  catapult_start.write(SC_LOGIC_1);
+               }
+               in_sync.write(SC_LOGIC_0);
+               inout_sync.write(SC_LOGIC_0);
+               catapult_start.write(SC_LOGIC_0);
+            }
+            in_state++;
+         }
+      }
+     } // if (done_flag_used)
+   }
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD generate_reset
+// Static sensitivity: sensitive << reset_deactivation_event;
+
+void scverify_top::generate_reset() {
+      static bool first = true;
+      if (first || sc_time_stamp() == SC_ZERO_TIME)
+      {
+         setup_debug();
+         first = false;
+         rst.write(SC_LOGIC_1);
+         reset_deactivation_event.notify(40.0, SC_NS);
+         TLS_en.write(SC_LOGIC_1);
+      } else {
+         input_a_transactor->reset_streams();
+         input_b_transactor->reset_streams();
+         output_transactor->reset_streams();
+         rst.write(SC_LOGIC_0);
+      }
+   
+}
+#if defined(MC_SIMULATOR_OSCI) || defined(MC_SIMULATOR_VCS)
+int sc_main(int argc, char *argv[])
+{
+   sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
+   scverify_top scverify_top("scverify_top");
+   sc_start();
+   return scverify_top.testbench_INST->failed();
+}
+#else
+MC_MODULE_EXPORT(scverify_top);
+#endif
diff --git a/dot_product/dot_product/dot_product.v10/scverify/scverify_top.h b/dot_product/dot_product/dot_product.v10/scverify/scverify_top.h
new file mode 100644
index 0000000..35f394d
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v10/scverify/scverify_top.h
@@ -0,0 +1,274 @@
+// ----------------------------------------------------------------------------
+// SystemC Header for Top
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 15:39:35 +0000 2016
+//
+// ----------------------------------------------------------------------------
+// 
+// -------------------------------------
+// scverify_top
+// top module instantiating reference design,
+// DUT and comparator
+// -------------------------------------
+// 
+#ifndef INCLUDED_SCVERIFY_TOP_H
+#define INCLUDED_SCVERIFY_TOP_H
+
+#ifndef TO_QUOTED_STRING
+#define TO_QUOTED_STRING(x) TO_QUOTED_STRING1(x)
+#define TO_QUOTED_STRING1(x) #x
+#endif
+#ifndef TOP_HDL_ENTITY
+#define TOP_HDL_ENTITY dot_product
+#endif
+
+// Hold time for the SCVerify testbench to account for the gate delay after downstream synthesis in pico second(s)
+// Hold time value is obtained from 'top_gate_constraints.cpp', which is generated at the end of RTL synthesis
+#ifdef CCS_DUT_GATE
+extern double __scv_hold_time;
+extern double __scv_hold_time_RSCID_1;
+extern double __scv_hold_time_RSCID_2;
+extern double __scv_hold_time_RSCID_3;
+#else
+double __scv_hold_time = 0.0; // default for non-gate simulation is zero
+double __scv_hold_time_RSCID_1 = 0.0;
+double __scv_hold_time_RSCID_2 = 0.0;
+double __scv_hold_time_RSCID_3 = 0.0;
+#endif
+
+
+#include "mc_testbench.h"
+#include "mc_reset.h"
+#include "mc_transactors.h"
+#include "mgc_ioport_trans_rsc.h"
+#include "mc_monitor.h"
+#include "mc_dut_wrapper.h"
+
+
+class scverify_top : public sc_module
+{
+public:
+   // Interface Ports
+   
+   // Data objects
+   sc_event deadlock_event;
+   sc_signal< sc_logic >                      deadlocked;
+   sc_event reset_deactivation_event;
+   sc_signal< sc_logic >                      rst;
+   sc_signal< sc_logic >                      rst_n;
+   bool var_trdone;
+   sc_clock clk;
+   sc_signal< sc_logic >                      TLS_arst_n;
+   sc_signal< sc_logic >                      in_sync;
+   sc_signal< sc_logic >                      out_sync;
+   sc_signal< sc_logic >                      inout_sync;
+   sc_signal< unsigned >                      wait_for_init;
+   sc_signal< sc_logic >                      catapult_start;
+   sc_signal< sc_logic >                      catapult_done;
+   sc_signal< sc_logic >                      catapult_ready;
+   sc_signal< sc_logic >                      TLS_en;
+   sc_signal< sc_lv<8> >                      TLS_input_a_rsc_z;
+   sc_signal< sc_lv<8> >                      TLS_input_b_rsc_z;
+   sc_signal< sc_lv<8> >                      TLS_output_rsc_z;
+   tlm::tlm_fifo< mc_wait_ctrl > TLS_in_wait_ctrl_fifo_input_a;
+   tlm::tlm_fifo< ac_int<8, true > > TLS_fifo_in_input_a;
+   tlm::tlm_fifo< mc_wait_ctrl > TLS_in_wait_ctrl_fifo_input_b;
+   tlm::tlm_fifo< ac_int<8, true > > TLS_fifo_in_input_b;
+   tlm::tlm_fifo< mc_wait_ctrl > TLS_out_wait_ctrl_fifo_output;
+   tlm::tlm_fifo< ac_int<8, true > > TLS_fifo_out_output;
+   
+   // Named Objects
+   
+   // Module instance pointers
+   ccs_DUT_wrapper *dot_product_INST;
+   mc_programmable_reset *arst_n_driver;
+   mgc_in_wire_trans_rsc< 5,8 > *input_a_rsc_INST;
+   mgc_in_wire_trans_rsc< 5,8 > *input_b_rsc_INST;
+   mgc_out_stdreg_trans_rsc< 1,8 > *output_rsc_INST;
+   mc_input_transactor<ac_int<8, true >,8,true> *input_a_transactor;
+   mc_input_transactor<ac_int<8, true >,8,true> *input_b_transactor;
+   mc_output_transactor<ac_int<8, true >,8,true> *output_transactor;
+   testbench *testbench_INST;
+   
+   // Declare processes (SC_METHOD and SC_THREAD)
+   void deadlock_notify();
+   void deadlock_watch();
+   void generate_sync();
+   void generate_reset();
+   
+   // Constructor
+   SC_HAS_PROCESS(scverify_top);
+   scverify_top(
+      const sc_module_name& name
+   )
+      : deadlocked("deadlocked")
+      , rst("rst")
+      , rst_n("rst_n")
+      , var_trdone(false)
+      , clk("clk",20.000000,SC_NS,0.5,0.000000,SC_NS,false)
+      , TLS_arst_n("TLS_arst_n")
+      , in_sync("in_sync")
+      , out_sync("out_sync")
+      , inout_sync("inout_sync")
+      , wait_for_init("wait_for_init")
+      , catapult_start("catapult_start")
+      , catapult_done("catapult_done")
+      , catapult_ready("catapult_ready")
+      , TLS_en("TLS_en")
+      , TLS_input_a_rsc_z("TLS_input_a_rsc_z")
+      , TLS_input_b_rsc_z("TLS_input_b_rsc_z")
+      , TLS_output_rsc_z("TLS_output_rsc_z")
+      , TLS_in_wait_ctrl_fifo_input_a("TLS_in_wait_ctrl_fifo_input_a",-1)
+      , TLS_fifo_in_input_a("TLS_fifo_in_input_a",-1)
+      , TLS_in_wait_ctrl_fifo_input_b("TLS_in_wait_ctrl_fifo_input_b",-1)
+      , TLS_fifo_in_input_b("TLS_fifo_in_input_b",-1)
+      , TLS_out_wait_ctrl_fifo_output("TLS_out_wait_ctrl_fifo_output",-1)
+      , TLS_fifo_out_output("TLS_fifo_out_output",-1)
+   {
+      // Instantiate other modules
+      dot_product_INST = new ccs_DUT_wrapper(
+         "rtl",
+         TO_QUOTED_STRING(TOP_HDL_ENTITY)
+      );
+      dot_product_INST->clk(clk);
+      dot_product_INST->en(TLS_en);
+      dot_product_INST->arst_n(TLS_arst_n);
+      dot_product_INST->input_a_rsc_z(TLS_input_a_rsc_z);
+      dot_product_INST->input_b_rsc_z(TLS_input_b_rsc_z);
+      dot_product_INST->output_rsc_z(TLS_output_rsc_z);
+      
+      arst_n_driver = new mc_programmable_reset(
+         "arst_n_driver",
+         40.0,
+         1
+      );
+      arst_n_driver->reset_out(TLS_arst_n);
+      
+      input_a_rsc_INST = new mgc_in_wire_trans_rsc< 5,8 > (
+         "input_a_rsc",
+         true
+      );
+      input_a_rsc_INST->z(TLS_input_a_rsc_z);
+      input_a_rsc_INST->clk(clk);
+      input_a_rsc_INST->add_attribute(*(new sc_attribute<double>("CLK_SKEW_DELAY", __scv_hold_time_RSCID_1 )));
+      
+      input_b_rsc_INST = new mgc_in_wire_trans_rsc< 5,8 > (
+         "input_b_rsc",
+         true
+      );
+      input_b_rsc_INST->z(TLS_input_b_rsc_z);
+      input_b_rsc_INST->clk(clk);
+      input_b_rsc_INST->add_attribute(*(new sc_attribute<double>("CLK_SKEW_DELAY", __scv_hold_time_RSCID_2 )));
+      
+      output_rsc_INST = new mgc_out_stdreg_trans_rsc< 1,8 > (
+         "output_rsc",
+         true
+      );
+      output_rsc_INST->z(TLS_output_rsc_z);
+      output_rsc_INST->clk(clk);
+      output_rsc_INST->add_attribute(*(new sc_attribute<double>("CLK_SKEW_DELAY", __scv_hold_time_RSCID_3 )));
+      
+      input_a_transactor = new mc_input_transactor<ac_int<8, true >,8,true> (
+         "transactor_input_a",
+         0,
+         8,
+         0,
+         false
+      );
+      input_a_transactor->in_wait_ctrl_fifo(TLS_in_wait_ctrl_fifo_input_a);
+      input_a_transactor->in_fifo(TLS_fifo_in_input_a);
+      input_a_transactor->add_attribute(*(new sc_attribute<int>("MC_TRANSACTOR_EVENT", MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT )));
+      input_a_transactor->bind_clk(clk,true);
+      input_a_transactor->register_block(input_a_rsc_INST,input_a_rsc_INST->basename(),in_sync,0,4,1);
+      
+      input_b_transactor = new mc_input_transactor<ac_int<8, true >,8,true> (
+         "transactor_input_b",
+         0,
+         8,
+         0,
+         false
+      );
+      input_b_transactor->in_wait_ctrl_fifo(TLS_in_wait_ctrl_fifo_input_b);
+      input_b_transactor->in_fifo(TLS_fifo_in_input_b);
+      input_b_transactor->add_attribute(*(new sc_attribute<int>("MC_TRANSACTOR_EVENT", MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT )));
+      input_b_transactor->bind_clk(clk,true);
+      input_b_transactor->register_block(input_b_rsc_INST,input_b_rsc_INST->basename(),in_sync,0,4,1);
+      
+      output_transactor = new mc_output_transactor<ac_int<8, true >,8,true> (
+         "transactor_output",
+         0,
+         8,
+         0
+      );
+      output_transactor->out_wait_ctrl_fifo(TLS_out_wait_ctrl_fifo_output);
+      output_transactor->out_fifo(TLS_fifo_out_output);
+      output_transactor->add_attribute(*(new sc_attribute<int>("MC_TRANSACTOR_EVENT", MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT )));
+      output_transactor->bind_clk(clk,true);
+      output_transactor->register_block(output_rsc_INST,output_rsc_INST->basename(),out_sync,0,0,1);
+      
+      testbench_INST = new testbench(
+         "user_tb"
+      );
+      testbench_INST->clk(clk);
+      testbench_INST->ccs_input_a(TLS_fifo_in_input_a);
+      testbench_INST->ccs_wait_ctrl_input_a(TLS_in_wait_ctrl_fifo_input_a);
+      testbench_INST->ccs_input_b(TLS_fifo_in_input_b);
+      testbench_INST->ccs_wait_ctrl_input_b(TLS_in_wait_ctrl_fifo_input_b);
+      testbench_INST->ccs_output(TLS_fifo_out_output);
+      testbench_INST->ccs_wait_ctrl_output(TLS_out_wait_ctrl_fifo_output);
+      
+      
+      // Register processes
+      SC_METHOD(deadlock_notify);
+      sensitive << deadlock_event;
+      dont_initialize();
+      SC_METHOD(deadlock_watch);
+      sensitive  << clk;
+      dont_initialize();
+      SC_METHOD(generate_sync);
+      sensitive << clk << rst;
+      dont_initialize();
+      SC_METHOD(generate_reset);
+      sensitive << reset_deactivation_event;
+      // Other constructor statements
+      // set seed for random number generator used by wait_ctrl
+      mt19937_init_genrand(19650218UL);
+      install_observe_foreign_signals();
+   }
+   
+   ~scverify_top()
+   {
+      delete dot_product_INST;
+      dot_product_INST = 0;
+      delete arst_n_driver;
+      arst_n_driver = 0;
+      delete input_a_rsc_INST;
+      input_a_rsc_INST = 0;
+      delete input_b_rsc_INST;
+      input_b_rsc_INST = 0;
+      delete output_rsc_INST;
+      output_rsc_INST = 0;
+      delete input_a_transactor;
+      input_a_transactor = 0;
+      delete input_b_transactor;
+      input_b_transactor = 0;
+      delete output_transactor;
+      output_transactor = 0;
+      delete testbench_INST;
+      testbench_INST = 0;
+   }
+   
+   // C++ class functions
+   public:
+      void setup_debug() ;
+   public:
+      void install_observe_foreign_signals() ;
+   public:
+      void debug(const char *varname, int flags, int count) ;
+};
+#endif
diff --git a/dot_product/dot_product/dot_product.v2/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v2/ccs_env.mk b/dot_product/dot_product/dot_product.v2/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v2/directives.tcl b/dot_product/dot_product/dot_product.v2/directives.tcl
new file mode 100644
index 0000000..5f53aec
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/MAC -UNROLL yes
+go architect
+go allocate
diff --git a/dot_product/dot_product/dot_product.v2/messages.txt b/dot_product/dot_product/dot_product.v2/messages.txt
new file mode 100644
index 0000000..a8fdde2
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/messages.txt
@@ -0,0 +1,112 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v2' (SOL-8)
+Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v2': elapsed time 0.69 seconds, memory usage 162000kB, peak memory usage 170216kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v2' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11)
+Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1358.03, 0.00, 1358.03 (CRAAS-10)
+Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1027.78, 0.00, 1027.78 (CRAAS-10)
+Optimized LOOP 'main': Latency = 3, Area (Datapath, Register, Total) = 697.53, 0.00, 697.53 (CRAAS-10)
+Optimized LOOP 'main': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v2': elapsed time 0.05 seconds, memory usage 162000kB, peak memory usage 170216kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v2/schedule.gnt b/dot_product/dot_product/dot_product.v2/schedule.gnt
new file mode 100644
index 0000000..2028355
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/schedule.gnt
@@ -0,0 +1,29 @@
+set a(0-68) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-67 XREFS 406 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {} SUCCS {{258 0 0-70 {}} {258 0 0-73 {}} {258 0 0-77 {}} {258 0 0-81 {}} {258 0 0-84 {}}} CYCLES {}}
+set a(0-69) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-67 XREFS 407 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {} SUCCS {{258 0 0-71 {}} {258 0 0-74 {}} {258 0 0-78 {}} {258 0 0-82 {}} {258 0 0-85 {}}} CYCLES {}}
+set a(0-70) {NAME MAC:slc#3 TYPE READSLICE PAR 0-67 XREFS 408 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-68 {}}} SUCCS {{258 0 0-72 {}}} CYCLES {}}
+set a(0-71) {NAME MAC:slc#8 TYPE READSLICE PAR 0-67 XREFS 409 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-69 {}}} SUCCS {{259 0 0-72 {}}} CYCLES {}}
+set a(0-72) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-4:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-67 XREFS 410 LOC {1 0.0 3 0.833798775 3 0.833798775 3 0.9999999407433434 5 0.7819156907433434} PREDS {{258 0 0-70 {}} {259 0 0-71 {}}} SUCCS {{258 0 0-76 {}}} CYCLES {}}
+set a(0-73) {NAME MAC:slc#4 TYPE READSLICE PAR 0-67 XREFS 411 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-68 {}}} SUCCS {{258 0 0-75 {}}} CYCLES {}}
+set a(0-74) {NAME MAC:slc#9 TYPE READSLICE PAR 0-67 XREFS 412 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-69 {}}} SUCCS {{259 0 0-75 {}}} CYCLES {}}
+set a(0-75) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-5:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-67 XREFS 413 LOC {1 0.0 4 0.761104025 4 0.761104025 4 0.9273051907433434 5 0.7819156907433434} PREDS {{258 0 0-73 {}} {259 0 0-74 {}}} SUCCS {{259 0 0-76 {}}} CYCLES {}}
+set a(0-76) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#6 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-67 XREFS 414 LOC {1 0.16620122499999998 4 0.92730525 4 0.92730525 4 0.9999999527684257 5 0.8546104527684256} PREDS {{258 0 0-72 {}} {259 0 0-75 {}}} SUCCS {{258 0 0-80 {}}} CYCLES {}}
+set a(0-77) {NAME MAC:slc TYPE READSLICE PAR 0-67 XREFS 415 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-68 {}}} SUCCS {{258 0 0-79 {}}} CYCLES {}}
+set a(0-78) {NAME MAC:slc#5 TYPE READSLICE PAR 0-67 XREFS 416 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-69 {}}} SUCCS {{259 0 0-79 {}}} CYCLES {}}
+set a(0-79) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-1:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-67 XREFS 417 LOC {1 0.0 5 0.6884092749999999 5 0.6884092749999999 5 0.8546104407433434 5 0.8546104407433434} PREDS {{258 0 0-77 {}} {259 0 0-78 {}}} SUCCS {{259 0 0-80 {}}} CYCLES {}}
+set a(0-80) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-67 XREFS 418 LOC {1 0.23889597499999998 5 0.8546104999999999 5 0.8546104999999999 5 0.9273052027684257 5 0.9273052027684257} PREDS {{258 0 0-76 {}} {259 0 0-79 {}}} SUCCS {{258 0 0-88 {}}} CYCLES {}}
+set a(0-81) {NAME MAC:slc#1 TYPE READSLICE PAR 0-67 XREFS 419 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-68 {}}} SUCCS {{258 0 0-83 {}}} CYCLES {}}
+set a(0-82) {NAME MAC:slc#6 TYPE READSLICE PAR 0-67 XREFS 420 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-69 {}}} SUCCS {{259 0 0-83 {}}} CYCLES {}}
+set a(0-83) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-2:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-67 XREFS 421 LOC {1 0.0 2 0.761104025 2 0.761104025 2 0.9273051907433434 5 0.8546104407433434} PREDS {{258 0 0-81 {}} {259 0 0-82 {}}} SUCCS {{258 0 0-87 {}}} CYCLES {}}
+set a(0-84) {NAME MAC:slc#2 TYPE READSLICE PAR 0-67 XREFS 422 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-68 {}}} SUCCS {{258 0 0-86 {}}} CYCLES {}}
+set a(0-85) {NAME MAC:slc#7 TYPE READSLICE PAR 0-67 XREFS 423 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-69 {}}} SUCCS {{259 0 0-86 {}}} CYCLES {}}
+set a(0-86) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-3:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-67 XREFS 424 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.9999999407433434 5 0.8546104407433434} PREDS {{258 0 0-84 {}} {259 0 0-85 {}}} SUCCS {{259 0 0-87 {}}} CYCLES {}}
+set a(0-87) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#5 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-67 XREFS 425 LOC {1 0.16620122499999998 2 0.92730525 2 0.92730525 2 0.9999999527684257 5 0.9273052027684257} PREDS {{258 0 0-83 {}} {259 0 0-86 {}}} SUCCS {{259 0 0-88 {}}} CYCLES {}}
+set a(0-88) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC-5:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-67 XREFS 426 LOC {1 0.311590725 5 0.92730525 5 0.92730525 5 0.9999999527684257 5 0.9999999527684257} PREDS {{258 0 0-80 {}} {259 0 0-87 {}}} SUCCS {{259 0 0-89 {}}} CYCLES {}}
+set a(0-89) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-67 XREFS 427 LOC {1 1.0 5 1.0 5 1.0 6 0.0 5 0.9999} PREDS {{772 0 0-89 {}} {259 0 0-88 {}}} SUCCS {{772 0 0-89 {}}} CYCLES {}}
+set a(0-67) {CHI {0-68 0-69 0-70 0-71 0-72 0-73 0-74 0-75 0-76 0-77 0-78 0-79 0-80 0-81 0-82 0-83 0-84 0-85 0-86 0-87 0-88 0-89} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 6 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 6 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 6 TOTAL_CYCLES_IN 6 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 6 NAME main TYPE LOOP DELAY {140.00 ns} PAR {} XREFS 428 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-67-TOTALCYCLES) {6}
+set a(0-67-QMOD) {mgc_ioport.mgc_in_wire(1,40) 0-68 mgc_ioport.mgc_in_wire(2,40) 0-69 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) {0-72 0-75 0-79 0-83 0-86} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) {0-76 0-80 0-87 0-88} mgc_ioport.mgc_out_stdreg(3,8) 0-89}
+set a(0-67-PROC_NAME) {core}
+set a(0-67-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-67}
+
diff --git a/dot_product/dot_product/dot_product.v2/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v2/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..16c8eb1
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v2/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:32:05 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v2)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v2/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v3/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v3/ccs_env.mk b/dot_product/dot_product/dot_product.v3/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v3/directives.tcl b/dot_product/dot_product/dot_product.v3/directives.tcl
new file mode 100644
index 0000000..7683817
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/MAC -UNROLL no
+go architect
+go allocate
diff --git a/dot_product/dot_product/dot_product.v3/messages.txt b/dot_product/dot_product/dot_product.v3/messages.txt
new file mode 100644
index 0000000..6470eaa
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/messages.txt
@@ -0,0 +1,102 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v3' (SOL-8)
+Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+Design 'dot_product' contains '12' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 6, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 49, Real ops = 11, Vars = 22) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 27, Real ops = 10, Vars = 7) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v3': elapsed time 1.08 seconds, memory usage 166268kB, peak memory usage 178592kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v3' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-11)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v3': elapsed time 0.06 seconds, memory usage 166268kB, peak memory usage 178592kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v3/schedule.gnt b/dot_product/dot_product/dot_product.v3/schedule.gnt
new file mode 100644
index 0000000..e00a7d6
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/schedule.gnt
@@ -0,0 +1,43 @@
+set a(0-99) {NAME MAC:asn TYPE ASSIGN PAR 0-98 XREFS 441 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-134 {}}} SUCCS {{259 0 0-100 {}} {256 0 0-134 {}}} CYCLES {}}
+set a(0-100) {NAME MAC:select TYPE SELECT PAR 0-98 XREFS 442 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-99 {}}} SUCCS {} CYCLES {}}
+set a(0-101) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-98 XREFS 443 LOC {0 1.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{262 0 0-134 {}}} SUCCS {{259 0 0-102 {}} {256 0 0-134 {}}} CYCLES {}}
+set a(0-102) {NAME MAC:not#2 TYPE NOT PAR 0-98 XREFS 444 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-101 {}}} SUCCS {{259 0 0-103 {}}} CYCLES {}}
+set a(0-103) {NAME MAC:exs#1 TYPE SIGNEXTEND PAR 0-98 XREFS 445 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-102 {}}} SUCCS {{259 0 0-104 {}}} CYCLES {}}
+set a(0-104) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(3,2) AREA_SCORE 2.19 QUANTITY 1 NAME MAC:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-98 XREFS 446 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6671089812638539 1 0.6671089812638539} PREDS {{262 0 0-133 {}} {259 0 0-103 {}}} SUCCS {{258 0 0-116 {}} {258 0 0-122 {}} {258 0 0-125 {}} {256 0 0-133 {}}} CYCLES {}}
+set a(0-105) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-98 XREFS 447 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-106 {}}} SUCCS {{80 0 0-106 {}} {258 0 0-111 {}} {258 0 0-112 {}} {258 0 0-113 {}} {258 0 0-114 {}} {258 0 0-115 {}}} CYCLES {}}
+set a(0-106) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-98 XREFS 448 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-105 {}}} SUCCS {{80 0 0-105 {}} {258 0 0-117 {}} {258 0 0-118 {}} {258 0 0-119 {}} {258 0 0-120 {}} {258 0 0-121 {}}} CYCLES {}}
+set a(0-107) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-98 XREFS 449 LOC {0 1.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{262 0 0-134 {}}} SUCCS {{259 0 0-108 {}} {256 0 0-134 {}}} CYCLES {}}
+set a(0-108) {NAME MAC:not#1 TYPE NOT PAR 0-98 XREFS 450 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-107 {}}} SUCCS {{259 0 0-109 {}}} CYCLES {}}
+set a(0-109) {NAME MAC:exs TYPE SIGNEXTEND PAR 0-98 XREFS 451 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-108 {}}} SUCCS {{259 0 0-110 {}}} CYCLES {}}
+set a(0-110) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(8,2) AREA_SCORE 5.84 QUANTITY 1 NAME MAC:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-98 XREFS 452 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.9273052062638539 1 0.9273052062638539} PREDS {{262 0 0-132 {}} {259 0 0-109 {}}} SUCCS {{258 0 0-124 {}} {256 0 0-132 {}}} CYCLES {}}
+set a(0-111) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt) TYPE READSLICE PAR 0-98 XREFS 453 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
+set a(0-112) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#1 TYPE READSLICE PAR 0-98 XREFS 454 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
+set a(0-113) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#2 TYPE READSLICE PAR 0-98 XREFS 455 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
+set a(0-114) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#3 TYPE READSLICE PAR 0-98 XREFS 456 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{258 0 0-116 {}}} CYCLES {}}
+set a(0-115) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#4 TYPE READSLICE PAR 0-98 XREFS 457 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-105 {}}} SUCCS {{259 0 0-116 {}}} CYCLES {}}
+set a(0-116) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-98 XREFS 458 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-104 {}} {258 0 0-114 {}} {258 0 0-113 {}} {258 0 0-112 {}} {258 0 0-111 {}} {259 0 0-115 {}}} SUCCS {{258 0 0-123 {}}} CYCLES {}}
+set a(0-117) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt) TYPE READSLICE PAR 0-98 XREFS 459 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
+set a(0-118) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#1 TYPE READSLICE PAR 0-98 XREFS 460 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
+set a(0-119) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#2 TYPE READSLICE PAR 0-98 XREFS 461 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
+set a(0-120) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#3 TYPE READSLICE PAR 0-98 XREFS 462 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{258 0 0-122 {}}} CYCLES {}}
+set a(0-121) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#4 TYPE READSLICE PAR 0-98 XREFS 463 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-106 {}}} SUCCS {{259 0 0-122 {}}} CYCLES {}}
+set a(0-122) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux#3 TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-98 XREFS 464 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-104 {}} {258 0 0-120 {}} {258 0 0-119 {}} {258 0 0-118 {}} {258 0 0-117 {}} {259 0 0-121 {}}} SUCCS {{259 0 0-123 {}}} CYCLES {}}
+set a(0-123) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-98 XREFS 465 LOC {1 0.110401775 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-116 {}} {259 0 0-122 {}}} SUCCS {{259 0 0-124 {}}} CYCLES {}}
+set a(0-124) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-98 XREFS 466 LOC {1 0.276603 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-110 {}} {259 0 0-123 {}}} SUCCS {{258 0 0-131 {}} {258 0 0-132 {}}} CYCLES {}}
+set a(0-125) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-98 XREFS 467 LOC {1 0.016406775 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{258 0 0-104 {}}} SUCCS {{259 0 0-126 {}} {258 0 0-133 {}}} CYCLES {}}
+set a(0-126) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-98 XREFS 468 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-125 {}}} SUCCS {{259 0 0-127 {}}} CYCLES {}}
+set a(0-127) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-98 XREFS 469 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-126 {}}} SUCCS {{259 0 0-128 {}}} CYCLES {}}
+set a(0-128) {NAME MAC:slc TYPE READSLICE PAR 0-98 XREFS 470 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-127 {}}} SUCCS {{259 0 0-129 {}}} CYCLES {}}
+set a(0-129) {NAME MAC:not TYPE NOT PAR 0-98 XREFS 471 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-128 {}}} SUCCS {{259 0 0-130 {}} {258 0 0-134 {}}} CYCLES {}}
+set a(0-130) {NAME MAC:select#1 TYPE SELECT PAR 0-98 XREFS 472 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-129 {}}} SUCCS {{131 0 0-131 {}}} CYCLES {}}
+set a(0-131) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-98 XREFS 473 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-131 {}} {258 0 0-124 {}} {131 0 0-130 {}}} SUCCS {{260 0 0-131 {}}} CYCLES {}}
+set a(0-132) {NAME MAC:asn(acc.lpi) TYPE ASSIGN PAR 0-98 XREFS 474 LOC {1 0.34929774999999996 1 1.0 1 1.0 2 0.910898475} PREDS {{260 0 0-132 {}} {256 0 0-110 {}} {258 0 0-124 {}}} SUCCS {{262 0 0-110 {}} {260 0 0-132 {}}} CYCLES {}}
+set a(0-133) {NAME MAC:asn(i#1.lpi) TYPE ASSIGN PAR 0-98 XREFS 475 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 2 0.6507022499999999} PREDS {{260 0 0-133 {}} {256 0 0-104 {}} {258 0 0-125 {}}} SUCCS {{262 0 0-104 {}} {260 0 0-133 {}}} CYCLES {}}
+set a(0-134) {NAME MAC:asn(exit:MAC.lpi) TYPE ASSIGN PAR 0-98 XREFS 476 LOC {1 0.11770625 1 1.0 1 1.0 2 0.6507022499999999} PREDS {{260 0 0-134 {}} {256 0 0-99 {}} {256 0 0-101 {}} {256 0 0-107 {}} {258 0 0-129 {}}} SUCCS {{262 0 0-99 {}} {262 0 0-101 {}} {262 0 0-107 {}} {260 0 0-134 {}}} CYCLES {}}
+set a(0-98) {CHI {0-99 0-100 0-101 0-102 0-103 0-104 0-105 0-106 0-107 0-108 0-109 0-110 0-111 0-112 0-113 0-114 0-115 0-116 0-117 0-118 0-119 0-120 0-121 0-122 0-123 0-124 0-125 0-126 0-127 0-128 0-129 0-130 0-131 0-132 0-133 0-134} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME main TYPE LOOP DELAY {120.00 ns} PAR {} XREFS 477 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-98-TOTALCYCLES) {5}
+set a(0-98-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2) 0-104 mgc_ioport.mgc_in_wire(1,40) 0-105 mgc_ioport.mgc_in_wire(2,40) 0-106 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2) 0-110 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,3,8) {0-116 0-122} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-123 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-124 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-125 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-127 mgc_ioport.mgc_out_stdreg(3,8) 0-131}
+set a(0-98-PROC_NAME) {core}
+set a(0-98-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-98}
+
diff --git a/dot_product/dot_product/dot_product.v3/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v3/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..8beec1f
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v3/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:39:10 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v3)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v3/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v4/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v4/ccs_env.mk b/dot_product/dot_product/dot_product.v4/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v4/directives.tcl b/dot_product/dot_product/dot_product.v4/directives.tcl
new file mode 100644
index 0000000..17e63b7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0
+directive set /dot_product/core/MAC -UNROLL yes
+go architect
+go allocate
diff --git a/dot_product/dot_product/dot_product.v4/messages.txt b/dot_product/dot_product/dot_product.v4/messages.txt
new file mode 100644
index 0000000..d097385
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/messages.txt
@@ -0,0 +1,114 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v4' (SOL-8)
+Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v4': elapsed time 1.47 seconds, memory usage 169372kB, peak memory usage 178592kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v4' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11)
+Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1358.03, 0.00, 1358.03 (CRAAS-10)
+Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1027.78, 0.00, 1027.78 (CRAAS-10)
+Optimized LOOP 'main': Latency = 3, Area (Datapath, Register, Total) = 697.53, 0.00, 697.53 (CRAAS-10)
+Optimized LOOP 'main': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-10)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v4': elapsed time 0.06 seconds, memory usage 169372kB, peak memory usage 178592kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v4/schedule.gnt b/dot_product/dot_product/dot_product.v4/schedule.gnt
new file mode 100644
index 0000000..2044f34
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/schedule.gnt
@@ -0,0 +1,29 @@
+set a(0-160) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-159 XREFS 490 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {} SUCCS {{258 0 0-162 {}} {258 0 0-165 {}} {258 0 0-169 {}} {258 0 0-173 {}} {258 0 0-176 {}}} CYCLES {}}
+set a(0-161) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-159 XREFS 491 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {} SUCCS {{258 0 0-163 {}} {258 0 0-166 {}} {258 0 0-170 {}} {258 0 0-174 {}} {258 0 0-177 {}}} CYCLES {}}
+set a(0-162) {NAME MAC:slc#3 TYPE READSLICE PAR 0-159 XREFS 492 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-160 {}}} SUCCS {{258 0 0-164 {}}} CYCLES {}}
+set a(0-163) {NAME MAC:slc#8 TYPE READSLICE PAR 0-159 XREFS 493 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-161 {}}} SUCCS {{259 0 0-164 {}}} CYCLES {}}
+set a(0-164) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-4:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-159 XREFS 494 LOC {1 0.0 3 0.833798775 3 0.833798775 3 0.9999999407433434 5 0.7819156907433434} PREDS {{258 0 0-162 {}} {259 0 0-163 {}}} SUCCS {{258 0 0-168 {}}} CYCLES {}}
+set a(0-165) {NAME MAC:slc#4 TYPE READSLICE PAR 0-159 XREFS 495 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-160 {}}} SUCCS {{258 0 0-167 {}}} CYCLES {}}
+set a(0-166) {NAME MAC:slc#9 TYPE READSLICE PAR 0-159 XREFS 496 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.615714525} PREDS {{258 0 0-161 {}}} SUCCS {{259 0 0-167 {}}} CYCLES {}}
+set a(0-167) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-5:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-159 XREFS 497 LOC {1 0.0 4 0.761104025 4 0.761104025 4 0.9273051907433434 5 0.7819156907433434} PREDS {{258 0 0-165 {}} {259 0 0-166 {}}} SUCCS {{259 0 0-168 {}}} CYCLES {}}
+set a(0-168) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#6 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-159 XREFS 498 LOC {1 0.16620122499999998 4 0.92730525 4 0.92730525 4 0.9999999527684257 5 0.8546104527684256} PREDS {{258 0 0-164 {}} {259 0 0-167 {}}} SUCCS {{258 0 0-172 {}}} CYCLES {}}
+set a(0-169) {NAME MAC:slc TYPE READSLICE PAR 0-159 XREFS 499 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-160 {}}} SUCCS {{258 0 0-171 {}}} CYCLES {}}
+set a(0-170) {NAME MAC:slc#5 TYPE READSLICE PAR 0-159 XREFS 500 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-161 {}}} SUCCS {{259 0 0-171 {}}} CYCLES {}}
+set a(0-171) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-1:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-159 XREFS 501 LOC {1 0.0 5 0.6884092749999999 5 0.6884092749999999 5 0.8546104407433434 5 0.8546104407433434} PREDS {{258 0 0-169 {}} {259 0 0-170 {}}} SUCCS {{259 0 0-172 {}}} CYCLES {}}
+set a(0-172) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-159 XREFS 502 LOC {1 0.23889597499999998 5 0.8546104999999999 5 0.8546104999999999 5 0.9273052027684257 5 0.9273052027684257} PREDS {{258 0 0-168 {}} {259 0 0-171 {}}} SUCCS {{258 0 0-180 {}}} CYCLES {}}
+set a(0-173) {NAME MAC:slc#1 TYPE READSLICE PAR 0-159 XREFS 503 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-160 {}}} SUCCS {{258 0 0-175 {}}} CYCLES {}}
+set a(0-174) {NAME MAC:slc#6 TYPE READSLICE PAR 0-159 XREFS 504 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-161 {}}} SUCCS {{259 0 0-175 {}}} CYCLES {}}
+set a(0-175) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-2:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-159 XREFS 505 LOC {1 0.0 2 0.761104025 2 0.761104025 2 0.9273051907433434 5 0.8546104407433434} PREDS {{258 0 0-173 {}} {259 0 0-174 {}}} SUCCS {{258 0 0-179 {}}} CYCLES {}}
+set a(0-176) {NAME MAC:slc#2 TYPE READSLICE PAR 0-159 XREFS 506 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-160 {}}} SUCCS {{258 0 0-178 {}}} CYCLES {}}
+set a(0-177) {NAME MAC:slc#7 TYPE READSLICE PAR 0-159 XREFS 507 LOC {1 0.0 1 0.833798775 1 0.833798775 5 0.6884092749999999} PREDS {{258 0 0-161 {}}} SUCCS {{259 0 0-178 {}}} CYCLES {}}
+set a(0-178) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-3:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-159 XREFS 508 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.9999999407433434 5 0.8546104407433434} PREDS {{258 0 0-176 {}} {259 0 0-177 {}}} SUCCS {{259 0 0-179 {}}} CYCLES {}}
+set a(0-179) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#5 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-159 XREFS 509 LOC {1 0.16620122499999998 2 0.92730525 2 0.92730525 2 0.9999999527684257 5 0.9273052027684257} PREDS {{258 0 0-175 {}} {259 0 0-178 {}}} SUCCS {{259 0 0-180 {}}} CYCLES {}}
+set a(0-180) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC-5:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-159 XREFS 510 LOC {1 0.311590725 5 0.92730525 5 0.92730525 5 0.9999999527684257 5 0.9999999527684257} PREDS {{258 0 0-172 {}} {259 0 0-179 {}}} SUCCS {{259 0 0-181 {}}} CYCLES {}}
+set a(0-181) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-159 XREFS 511 LOC {1 1.0 5 1.0 5 1.0 6 0.0 5 0.9999} PREDS {{772 0 0-181 {}} {259 0 0-180 {}}} SUCCS {{772 0 0-181 {}}} CYCLES {}}
+set a(0-159) {CHI {0-160 0-161 0-162 0-163 0-164 0-165 0-166 0-167 0-168 0-169 0-170 0-171 0-172 0-173 0-174 0-175 0-176 0-177 0-178 0-179 0-180 0-181} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 6 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 6 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 6 TOTAL_CYCLES_IN 6 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 6 NAME main TYPE LOOP DELAY {140.00 ns} PAR {} XREFS 512 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-159-TOTALCYCLES) {6}
+set a(0-159-QMOD) {mgc_ioport.mgc_in_wire(1,40) 0-160 mgc_ioport.mgc_in_wire(2,40) 0-161 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) {0-164 0-167 0-171 0-175 0-178} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) {0-168 0-172 0-179 0-180} mgc_ioport.mgc_out_stdreg(3,8) 0-181}
+set a(0-159-PROC_NAME) {core}
+set a(0-159-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-159}
+
diff --git a/dot_product/dot_product/dot_product.v4/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v4/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..83fb95b
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v4/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:40:04 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v4)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v4/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v5/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v5/ccs_env.mk b/dot_product/dot_product/dot_product.v5/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v5/directives.tcl b/dot_product/dot_product/dot_product.v5/directives.tcl
new file mode 100644
index 0000000..a73f811
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/MAC -UNROLL no
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+go architect
+go allocate
diff --git a/dot_product/dot_product/dot_product.v5/messages.txt b/dot_product/dot_product/dot_product.v5/messages.txt
new file mode 100644
index 0000000..618da54
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/messages.txt
@@ -0,0 +1,104 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v5' (SOL-8)
+Loop '/dot_product/core/MAC' is left rolled. (LOOP-4)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10)
+Design 'dot_product' contains '12' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 6, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 49, Real ops = 11, Vars = 22) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 27, Real ops = 10, Vars = 7) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v5': elapsed time 1.79 seconds, memory usage 172008kB, peak memory usage 184332kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v5' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-11)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v5': elapsed time 0.06 seconds, memory usage 172008kB, peak memory usage 184332kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v5/schedule.gnt b/dot_product/dot_product/dot_product.v5/schedule.gnt
new file mode 100644
index 0000000..0f012ab
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/schedule.gnt
@@ -0,0 +1,43 @@
+set a(0-191) {NAME MAC:asn TYPE ASSIGN PAR 0-190 XREFS 525 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{262 0 0-226 {}}} SUCCS {{259 0 0-192 {}} {256 0 0-226 {}}} CYCLES {}}
+set a(0-192) {NAME MAC:select TYPE SELECT PAR 0-190 XREFS 526 LOC {0 1.0 0 1.0 0 1.0 2 1.0} PREDS {{259 0 0-191 {}}} SUCCS {} CYCLES {}}
+set a(0-193) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-190 XREFS 527 LOC {0 1.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{262 0 0-226 {}}} SUCCS {{259 0 0-194 {}} {256 0 0-226 {}}} CYCLES {}}
+set a(0-194) {NAME MAC:not#2 TYPE NOT PAR 0-190 XREFS 528 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-193 {}}} SUCCS {{259 0 0-195 {}}} CYCLES {}}
+set a(0-195) {NAME MAC:exs#1 TYPE SIGNEXTEND PAR 0-190 XREFS 529 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6507022499999999} PREDS {{259 0 0-194 {}}} SUCCS {{259 0 0-196 {}}} CYCLES {}}
+set a(0-196) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(3,2) AREA_SCORE 2.19 QUANTITY 1 NAME MAC:and#1 TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-190 XREFS 530 LOC {1 0.0 1 0.6507022499999999 1 0.6507022499999999 1 0.6671089812638539 1 0.6671089812638539} PREDS {{262 0 0-225 {}} {259 0 0-195 {}}} SUCCS {{258 0 0-208 {}} {258 0 0-214 {}} {258 0 0-217 {}} {256 0 0-225 {}}} CYCLES {}}
+set a(0-197) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-190 XREFS 531 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-198 {}}} SUCCS {{80 0 0-198 {}} {258 0 0-203 {}} {258 0 0-204 {}} {258 0 0-205 {}} {258 0 0-206 {}} {258 0 0-207 {}}} CYCLES {}}
+set a(0-198) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-190 XREFS 532 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{80 0 0-197 {}}} SUCCS {{80 0 0-197 {}} {258 0 0-209 {}} {258 0 0-210 {}} {258 0 0-211 {}} {258 0 0-212 {}} {258 0 0-213 {}}} CYCLES {}}
+set a(0-199) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-190 XREFS 533 LOC {0 1.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{262 0 0-226 {}}} SUCCS {{259 0 0-200 {}} {256 0 0-226 {}}} CYCLES {}}
+set a(0-200) {NAME MAC:not#1 TYPE NOT PAR 0-190 XREFS 534 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-199 {}}} SUCCS {{259 0 0-201 {}}} CYCLES {}}
+set a(0-201) {NAME MAC:exs TYPE SIGNEXTEND PAR 0-190 XREFS 535 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.910898475} PREDS {{259 0 0-200 {}}} SUCCS {{259 0 0-202 {}}} CYCLES {}}
+set a(0-202) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_and(8,2) AREA_SCORE 5.84 QUANTITY 1 NAME MAC:and TYPE AND DELAY {0.26 ns} LIBRARY_DELAY {0.26 ns} PAR 0-190 XREFS 536 LOC {1 0.0 1 0.910898475 1 0.910898475 1 0.9273052062638539 1 0.9273052062638539} PREDS {{262 0 0-224 {}} {259 0 0-201 {}}} SUCCS {{258 0 0-216 {}} {256 0 0-224 {}}} CYCLES {}}
+set a(0-203) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt) TYPE READSLICE PAR 0-190 XREFS 537 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}}
+set a(0-204) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#1 TYPE READSLICE PAR 0-190 XREFS 538 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}}
+set a(0-205) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#2 TYPE READSLICE PAR 0-190 XREFS 539 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}}
+set a(0-206) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#3 TYPE READSLICE PAR 0-190 XREFS 540 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{258 0 0-208 {}}} CYCLES {}}
+set a(0-207) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#4 TYPE READSLICE PAR 0-190 XREFS 541 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-197 {}}} SUCCS {{259 0 0-208 {}}} CYCLES {}}
+set a(0-208) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-190 XREFS 542 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-196 {}} {258 0 0-206 {}} {258 0 0-205 {}} {258 0 0-204 {}} {258 0 0-203 {}} {259 0 0-207 {}}} SUCCS {{258 0 0-215 {}}} CYCLES {}}
+set a(0-209) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt) TYPE READSLICE PAR 0-190 XREFS 543 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}}
+set a(0-210) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#1 TYPE READSLICE PAR 0-190 XREFS 544 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}}
+set a(0-211) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#2 TYPE READSLICE PAR 0-190 XREFS 545 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}}
+set a(0-212) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#3 TYPE READSLICE PAR 0-190 XREFS 546 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{258 0 0-214 {}}} CYCLES {}}
+set a(0-213) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#4 TYPE READSLICE PAR 0-190 XREFS 547 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-198 {}}} SUCCS {{259 0 0-214 {}}} CYCLES {}}
+set a(0-214) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux#3 TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-190 XREFS 548 LOC {1 0.016406775 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-196 {}} {258 0 0-212 {}} {258 0 0-211 {}} {258 0 0-210 {}} {258 0 0-209 {}} {259 0 0-213 {}}} SUCCS {{259 0 0-215 {}}} CYCLES {}}
+set a(0-215) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-190 XREFS 549 LOC {1 0.110401775 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-208 {}} {259 0 0-214 {}}} SUCCS {{259 0 0-216 {}}} CYCLES {}}
+set a(0-216) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-190 XREFS 550 LOC {1 0.276603 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-202 {}} {259 0 0-215 {}}} SUCCS {{258 0 0-223 {}} {258 0 0-224 {}}} CYCLES {}}
+set a(0-217) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-190 XREFS 551 LOC {1 0.016406775 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{258 0 0-196 {}}} SUCCS {{259 0 0-218 {}} {258 0 0-225 {}}} CYCLES {}}
+set a(0-218) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-190 XREFS 552 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-217 {}}} SUCCS {{259 0 0-219 {}}} CYCLES {}}
+set a(0-219) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-190 XREFS 553 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-218 {}}} SUCCS {{259 0 0-220 {}}} CYCLES {}}
+set a(0-220) {NAME MAC:slc TYPE READSLICE PAR 0-190 XREFS 554 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-219 {}}} SUCCS {{259 0 0-221 {}}} CYCLES {}}
+set a(0-221) {NAME MAC:not TYPE NOT PAR 0-190 XREFS 555 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-220 {}}} SUCCS {{259 0 0-222 {}} {258 0 0-226 {}}} CYCLES {}}
+set a(0-222) {NAME MAC:select#1 TYPE SELECT PAR 0-190 XREFS 556 LOC {1 0.11770625 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-221 {}}} SUCCS {{131 0 0-223 {}}} CYCLES {}}
+set a(0-223) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-190 XREFS 557 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-223 {}} {258 0 0-216 {}} {131 0 0-222 {}}} SUCCS {{260 0 0-223 {}}} CYCLES {}}
+set a(0-224) {NAME MAC:asn(acc.lpi) TYPE ASSIGN PAR 0-190 XREFS 558 LOC {1 0.34929774999999996 1 1.0 1 1.0 2 0.910898475} PREDS {{260 0 0-224 {}} {256 0 0-202 {}} {258 0 0-216 {}}} SUCCS {{262 0 0-202 {}} {260 0 0-224 {}}} CYCLES {}}
+set a(0-225) {NAME MAC:asn(i#1.lpi) TYPE ASSIGN PAR 0-190 XREFS 559 LOC {1 0.06418252499999999 1 0.946476275 1 0.946476275 2 0.6507022499999999} PREDS {{260 0 0-225 {}} {256 0 0-196 {}} {258 0 0-217 {}}} SUCCS {{262 0 0-196 {}} {260 0 0-225 {}}} CYCLES {}}
+set a(0-226) {NAME MAC:asn(exit:MAC.lpi) TYPE ASSIGN PAR 0-190 XREFS 560 LOC {1 0.11770625 1 1.0 1 1.0 2 0.6507022499999999} PREDS {{260 0 0-226 {}} {256 0 0-191 {}} {256 0 0-193 {}} {256 0 0-199 {}} {258 0 0-221 {}}} SUCCS {{262 0 0-191 {}} {262 0 0-193 {}} {262 0 0-199 {}} {260 0 0-226 {}}} CYCLES {}}
+set a(0-190) {CHI {0-191 0-192 0-193 0-194 0-195 0-196 0-197 0-198 0-199 0-200 0-201 0-202 0-203 0-204 0-205 0-206 0-207 0-208 0-209 0-210 0-211 0-212 0-213 0-214 0-215 0-216 0-217 0-218 0-219 0-220 0-221 0-222 0-223 0-224 0-225 0-226} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME main TYPE LOOP DELAY {120.00 ns} PAR {} XREFS 561 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-190-TOTALCYCLES) {5}
+set a(0-190-QMOD) {mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(3,2) 0-196 mgc_ioport.mgc_in_wire(1,40) 0-197 mgc_ioport.mgc_in_wire(2,40) 0-198 mgc_Altera-Cyclone-III-6_beh_psr.mgc_and(8,2) 0-202 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,3,8) {0-208 0-214} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-215 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-216 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-217 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-219 mgc_ioport.mgc_out_stdreg(3,8) 0-223}
+set a(0-190-PROC_NAME) {core}
+set a(0-190-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-190}
+
diff --git a/dot_product/dot_product/dot_product.v5/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v5/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..998c0dd
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v5/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:44:12 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v5)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v5/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v6/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v6/ccs_env.mk b/dot_product/dot_product/dot_product.v6/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v6/directives.tcl b/dot_product/dot_product/dot_product.v6/directives.tcl
new file mode 100644
index 0000000..40f78c3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/directives.tcl
@@ -0,0 +1,58 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/MAC -UNROLL yes
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/input_b -STREAM 8
+go architect
diff --git a/dot_product/dot_product/dot_product.v6/messages.txt b/dot_product/dot_product/dot_product.v6/messages.txt
new file mode 100644
index 0000000..d69a348
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/messages.txt
@@ -0,0 +1,100 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v6' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v6' (SOL-8)
+Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 23, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 23, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 24, Real ops = 7, Vars = 4) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v6': elapsed time 2.09 seconds, memory usage 174832kB, peak memory usage 184332kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v6/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v6/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..67915c3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v6/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:49:14 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v6)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v6/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v7/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v7/ccs_env.mk b/dot_product/dot_product/dot_product.v7/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v7/directives.tcl b/dot_product/dot_product/dot_product.v7/directives.tcl
new file mode 100644
index 0000000..ad1ddb6
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/MAC -UNROLL yes
+directive set /dot_product/input_b -STREAM 0
+directive set /dot_product/input_b -WORD_WIDTH 40
+go architect
+go allocate
diff --git a/dot_product/dot_product/dot_product.v7/messages.txt b/dot_product/dot_product/dot_product.v7/messages.txt
new file mode 100644
index 0000000..8c377d6
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/messages.txt
@@ -0,0 +1,113 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v6' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v7' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v7' (SOL-8)
+Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v7': elapsed time 2.60 seconds, memory usage 176692kB, peak memory usage 184908kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v7' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11)
+Final schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v7': elapsed time 0.06 seconds, memory usage 176692kB, peak memory usage 184908kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v7/schedule.gnt b/dot_product/dot_product/dot_product.v7/schedule.gnt
new file mode 100644
index 0000000..6cb8dc0
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/schedule.gnt
@@ -0,0 +1,29 @@
+set a(0-236) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-235 XREFS 585 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.615714525 1 0.615714525} PREDS {{80 0 0-237 {}}} SUCCS {{80 0 0-237 {}} {258 0 0-238 {}} {258 0 0-241 {}} {258 0 0-245 {}} {258 0 0-249 {}} {258 0 0-252 {}}} CYCLES {}}
+set a(0-237) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-235 XREFS 586 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.615714525 1 0.615714525} PREDS {{80 0 0-236 {}}} SUCCS {{80 0 0-236 {}} {258 0 0-239 {}} {258 0 0-242 {}} {258 0 0-246 {}} {258 0 0-250 {}} {258 0 0-253 {}}} CYCLES {}}
+set a(0-238) {NAME MAC:slc#3 TYPE READSLICE PAR 0-235 XREFS 587 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.615714525} PREDS {{258 0 0-236 {}}} SUCCS {{258 0 0-240 {}}} CYCLES {}}
+set a(0-239) {NAME MAC:slc#8 TYPE READSLICE PAR 0-235 XREFS 588 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.615714525} PREDS {{258 0 0-237 {}}} SUCCS {{259 0 0-240 {}}} CYCLES {}}
+set a(0-240) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 5 NAME MAC-4:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-235 XREFS 589 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.7819156907433434 1 0.7819156907433434} PREDS {{258 0 0-238 {}} {259 0 0-239 {}}} SUCCS {{258 0 0-244 {}}} CYCLES {}}
+set a(0-241) {NAME MAC:slc#4 TYPE READSLICE PAR 0-235 XREFS 590 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.615714525} PREDS {{258 0 0-236 {}}} SUCCS {{258 0 0-243 {}}} CYCLES {}}
+set a(0-242) {NAME MAC:slc#9 TYPE READSLICE PAR 0-235 XREFS 591 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.615714525} PREDS {{258 0 0-237 {}}} SUCCS {{259 0 0-243 {}}} CYCLES {}}
+set a(0-243) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 5 NAME MAC-5:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-235 XREFS 592 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.7819156907433434 1 0.7819156907433434} PREDS {{258 0 0-241 {}} {259 0 0-242 {}}} SUCCS {{259 0 0-244 {}}} CYCLES {}}
+set a(0-244) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#6 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-235 XREFS 593 LOC {1 0.16620122499999998 1 0.7819157499999999 1 0.7819157499999999 1 0.8546104527684256 1 0.8546104527684256} PREDS {{258 0 0-240 {}} {259 0 0-243 {}}} SUCCS {{258 0 0-248 {}}} CYCLES {}}
+set a(0-245) {NAME MAC:slc TYPE READSLICE PAR 0-235 XREFS 594 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.6884092749999999} PREDS {{258 0 0-236 {}}} SUCCS {{258 0 0-247 {}}} CYCLES {}}
+set a(0-246) {NAME MAC:slc#5 TYPE READSLICE PAR 0-235 XREFS 595 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.6884092749999999} PREDS {{258 0 0-237 {}}} SUCCS {{259 0 0-247 {}}} CYCLES {}}
+set a(0-247) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 5 NAME MAC-1:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-235 XREFS 596 LOC {1 0.0 1 0.6884092749999999 1 0.6884092749999999 1 0.8546104407433434 1 0.8546104407433434} PREDS {{258 0 0-245 {}} {259 0 0-246 {}}} SUCCS {{259 0 0-248 {}}} CYCLES {}}
+set a(0-248) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-235 XREFS 597 LOC {1 0.23889597499999998 1 0.8546104999999999 1 0.8546104999999999 1 0.9273052027684257 1 0.9273052027684257} PREDS {{258 0 0-244 {}} {259 0 0-247 {}}} SUCCS {{258 0 0-256 {}}} CYCLES {}}
+set a(0-249) {NAME MAC:slc#1 TYPE READSLICE PAR 0-235 XREFS 598 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.6884092749999999} PREDS {{258 0 0-236 {}}} SUCCS {{258 0 0-251 {}}} CYCLES {}}
+set a(0-250) {NAME MAC:slc#6 TYPE READSLICE PAR 0-235 XREFS 599 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.6884092749999999} PREDS {{258 0 0-237 {}}} SUCCS {{259 0 0-251 {}}} CYCLES {}}
+set a(0-251) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 5 NAME MAC-2:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-235 XREFS 600 LOC {1 0.0 1 0.6884092749999999 1 0.6884092749999999 1 0.8546104407433434 1 0.8546104407433434} PREDS {{258 0 0-249 {}} {259 0 0-250 {}}} SUCCS {{258 0 0-255 {}}} CYCLES {}}
+set a(0-252) {NAME MAC:slc#2 TYPE READSLICE PAR 0-235 XREFS 601 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.6884092749999999} PREDS {{258 0 0-236 {}}} SUCCS {{258 0 0-254 {}}} CYCLES {}}
+set a(0-253) {NAME MAC:slc#7 TYPE READSLICE PAR 0-235 XREFS 602 LOC {1 0.0 1 0.615714525 1 0.615714525 1 0.6884092749999999} PREDS {{258 0 0-237 {}}} SUCCS {{259 0 0-254 {}}} CYCLES {}}
+set a(0-254) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 5 NAME MAC-3:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-235 XREFS 603 LOC {1 0.0 1 0.6884092749999999 1 0.6884092749999999 1 0.8546104407433434 1 0.8546104407433434} PREDS {{258 0 0-252 {}} {259 0 0-253 {}}} SUCCS {{259 0 0-255 {}}} CYCLES {}}
+set a(0-255) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#5 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-235 XREFS 604 LOC {1 0.16620122499999998 1 0.8546104999999999 1 0.8546104999999999 1 0.9273052027684257 1 0.9273052027684257} PREDS {{258 0 0-251 {}} {259 0 0-254 {}}} SUCCS {{259 0 0-256 {}}} CYCLES {}}
+set a(0-256) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC-5:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-235 XREFS 605 LOC {1 0.311590725 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-248 {}} {259 0 0-255 {}}} SUCCS {{259 0 0-257 {}}} CYCLES {}}
+set a(0-257) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-235 XREFS 606 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{260 0 0-257 {}} {259 0 0-256 {}}} SUCCS {{260 0 0-257 {}}} CYCLES {}}
+set a(0-235) {CHI {0-236 0-237 0-238 0-239 0-240 0-241 0-242 0-243 0-244 0-245 0-246 0-247 0-248 0-249 0-250 0-251 0-252 0-253 0-254 0-255 0-256 0-257} ITERATIONS Infinite LATENCY 1 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 1 %_SHARING_ALLOC {20.0 %} PIPELINED Yes INITIATION 1 STAGES 2.0 CYCLES_IN 1 TOTAL_CYCLES_IN 1 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 1 NAME main TYPE LOOP DELAY {40.00 ns} PAR {} XREFS 607 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-235-TOTALCYCLES) {1}
+set a(0-235-QMOD) {mgc_ioport.mgc_in_wire(1,40) 0-236 mgc_ioport.mgc_in_wire(2,40) 0-237 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) {0-240 0-243 0-247 0-251 0-254} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) {0-244 0-248 0-255 0-256} mgc_ioport.mgc_out_stdreg(3,8) 0-257}
+set a(0-235-PROC_NAME) {core}
+set a(0-235-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-235}
+
diff --git a/dot_product/dot_product/dot_product.v7/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v7/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..6b851db
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v7/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:50:23 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v7)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v7/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v8/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v8/ccs_env.mk b/dot_product/dot_product/dot_product.v8/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v8/directives.tcl b/dot_product/dot_product/dot_product.v8/directives.tcl
new file mode 100644
index 0000000..308f7b1
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/directives.tcl
@@ -0,0 +1,58 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/core/MAC -UNROLL yes
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+go architect
diff --git a/dot_product/dot_product/dot_product.v8/messages.txt b/dot_product/dot_product/dot_product.v8/messages.txt
new file mode 100644
index 0000000..59c4030
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/messages.txt
@@ -0,0 +1,101 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v6' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v7' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v8' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v8' (SOL-8)
+Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v8': elapsed time 2.79 seconds, memory usage 179500kB, peak memory usage 187716kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v8/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v8/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..f109aa8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v8/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:51:59 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v8)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v8/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v9/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/SCVerify_INVOKE_ARGS.ts
diff --git a/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VCSELAB_OPTS.ts b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VCSELAB_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VHDLAN_OPTS.ts b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VHDLAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VLOGAN_OPTS.ts b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/.ccs_env_opts/VCS_VLOGAN_OPTS.ts
diff --git a/dot_product/dot_product/dot_product.v9/ccs_env.mk b/dot_product/dot_product/dot_product.v9/ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v9/concat_rtl.v b/dot_product/dot_product/dot_product.v9/concat_rtl.v
new file mode 100644
index 0000000..2192fb8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/concat_rtl.v
@@ -0,0 +1,1467 @@
+
+//------> ./rtl_mgc_ioport.v 
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
+
+//------> ./rtl_mgc_ioport_v2001.v 
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
+
+//------> ./rtl.v 
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 14:54:51 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core_fsm
+//  FSM Module
+// ------------------------------------------------------------------
+
+
+module dot_product_core_fsm (
+  clk, en, arst_n, fsm_output
+);
+  input clk;
+  input en;
+  input arst_n;
+  output [5:0] fsm_output;
+  reg [5:0] fsm_output;
+
+
+  // FSM State Type Declaration for dot_product_core_fsm_1
+  parameter
+    st_main = 3'd0,
+    st_main_1 = 3'd1,
+    st_main_2 = 3'd2,
+    st_main_3 = 3'd3,
+    st_main_4 = 3'd4,
+    st_main_5 = 3'd5,
+    state_x = 3'b000;
+
+  reg [2:0] state_var;
+  reg [2:0] state_var_NS;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : dot_product_core_fsm_1
+    case (state_var)
+      st_main : begin
+        fsm_output = 6'b1;
+        state_var_NS = st_main_1;
+      end
+      st_main_1 : begin
+        fsm_output = 6'b10;
+        state_var_NS = st_main_2;
+      end
+      st_main_2 : begin
+        fsm_output = 6'b100;
+        state_var_NS = st_main_3;
+      end
+      st_main_3 : begin
+        fsm_output = 6'b1000;
+        state_var_NS = st_main_4;
+      end
+      st_main_4 : begin
+        fsm_output = 6'b10000;
+        state_var_NS = st_main_5;
+      end
+      st_main_5 : begin
+        fsm_output = 6'b100000;
+        state_var_NS = st_main;
+      end
+      default : begin
+        fsm_output = 6'b000000;
+        state_var_NS = st_main;
+      end
+    endcase
+  end
+
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      state_var <= st_main;
+    end
+    else if ( en ) begin
+      state_var <= state_var_NS;
+    end
+  end
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire [5:0] fsm_output;
+  reg [7:0] MAC_4_mul_itm;
+  reg [7:0] MAC_acc_6_itm;
+  reg [7:0] MAC_acc_itm;
+  wire [7:0] z_out;
+  wire [8:0] nl_z_out;
+  wire [7:0] MAC_4_mul_itm_1;
+  wire [15:0] nl_MAC_4_mul_itm_1;
+
+  wire[7:0] mux_2_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  dot_product_core_fsm dot_product_core_fsm_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .fsm_output(fsm_output)
+    );
+  assign nl_MAC_4_mul_itm_1 = input_a_rsc_mgc_in_wire_d * input_b_rsc_mgc_in_wire_d;
+  assign MAC_4_mul_itm_1 = nl_MAC_4_mul_itm_1[7:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      output_rsc_mgc_out_stdreg_d <= 8'b0;
+      MAC_4_mul_itm <= 8'b0;
+      MAC_acc_6_itm <= 8'b0;
+      MAC_acc_itm <= 8'b0;
+    end
+    else begin
+      if ( en ) begin
+        output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({output_rsc_mgc_out_stdreg_d ,
+            (MAC_acc_itm + z_out)}, fsm_output[4]);
+        MAC_4_mul_itm <= MAC_4_mul_itm_1;
+        MAC_acc_6_itm <= z_out;
+        MAC_acc_itm <= MUX_v_8_2_2({MAC_acc_itm , z_out}, fsm_output[2]);
+      end
+    end
+  end
+  assign mux_2_nl = MUX_v_8_2_2({MAC_4_mul_itm , MAC_acc_6_itm}, fsm_output[2]);
+  assign nl_z_out = (mux_2_nl) + MAC_4_mul_itm_1;
+  assign z_out = nl_z_out[7:0];
+
+  function [7:0] MUX_v_8_2_2;
+    input [15:0] inputs;
+    input [0:0] sel;
+    reg [7:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[15:8];
+      end
+      1'b1 : begin
+        result = inputs[7:0];
+      end
+      default : begin
+        result = inputs[15:8];
+      end
+    endcase
+    MUX_v_8_2_2 = result;
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/dot_product.v9/cycle.rpt b/dot_product/dot_product/dot_product.v9/cycle.rpt
new file mode 100644
index 0000000..d325c92
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/cycle.rpt
@@ -0,0 +1,84 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-015                                 
+-- Generated date:              Tue Mar 01 14:54:47 +0000 2016                      
+
+Solution Settings: dot_product.v9
+  Current state: schedule
+  Project: dot_product
+  
+  Design Input Files Specified
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+      $MGC_HOME/shared/include/mc_scverify.h
+  
+  Processes/Blocks in Design
+    Process           Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ----------------- ----------------------- ------- ---------- ------------ -- --------
+    /dot_product/core                      20       5          6            0  0          
+    Design Total:                          20       5          6            0  0          
+    
+  Clock Information
+    Clock Signal Edge   Period Sharing Alloc (%) Uncertainty Used by Processes/Blocks 
+    ------------ ------ ------ ----------------- ----------- ------------------------
+    clk          rising 20.000             20.00    0.000000 /dot_product/core        
+    
+  I/O Data Ranges
+    Port          Mode DeclType DeclWidth DeclRange ActType ActWidth ActRange 
+    ------------- ---- -------- --------- --------- ------- -------- --------
+    input_a:rsc.z IN   Unsigned         8                                     
+    input_b:rsc.z IN   Unsigned         8                                     
+    clk           IN   Unsigned         1                                     
+    en            IN   Unsigned         1                                     
+    arst_n        IN   Unsigned         1                                     
+    output:rsc.z  OUT  Unsigned         8                                     
+    
+  Memory Resources
+    Resource Name: /dot_product/input_a:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 8
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable             Indices Phys Memory Address     
+      -------------------- ------- -----------------------
+      /dot_product/input_a     0:7 00000000-00000000 (0-0) 
+      
+    Resource Name: /dot_product/input_b:rsc
+      Memory Component: mgc_in_wire                  Size:         1 x 8
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable             Indices Phys Memory Address     
+      -------------------- ------- -----------------------
+      /dot_product/input_b     0:7 00000000-00000000 (0-0) 
+      
+    Resource Name: /dot_product/output:rsc
+      Memory Component: mgc_out_stdreg               Size:         1 x 8
+      External:         true                         Packing Mode: sidebyside
+      Memory Map:
+      Variable            Indices Phys Memory Address     
+      ------------------- ------- -----------------------
+      /dot_product/output     0:7 00000000-00000000 (0-0) 
+      
+  Multi-Cycle (Combinational) Component Usage
+    Instance Component Name Delay 
+    -------- -------------- -----
+    
+  Loops
+    Process           Loop             Iterations C-Steps Total Cycles   Duration  Unroll Init Comments 
+    ----------------- ---------------- ---------- ------- ------------- ---------- ------ ---- --------
+    /dot_product/core main               Infinite       6            6  120.00 ns                       
+    
+  Loop Execution Profile
+    Process           Loop             Total Cycles % of Overall Design Cycles Throughput Cycles Comments 
+    ----------------- ---------------- ------------ -------------------------- ----------------- --------
+    /dot_product/core main                       6                      100.00                6           
+    
+  End of Report
diff --git a/dot_product/dot_product/dot_product.v9/cycle.v b/dot_product/dot_product/dot_product.v9/cycle.v
new file mode 100644
index 0000000..6f33094
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/cycle.v
@@ -0,0 +1,178 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 14:54:47 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : core
+    // Interconnect Declarations
+    reg [7:0] MAC_4_mul_itm;
+    reg [7:0] MAC_acc_6_itm;
+    reg [7:0] MAC_acc_itm;
+    reg [7:0] MAC_2_mul_itm;
+
+    begin : mainExit
+      forever begin : main
+        // C-Step 0 of Loop 'main'
+        begin : waitLoop0Exit
+          forever begin : waitLoop0
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop0Exit;
+          end
+        end
+        // C-Step 1 of Loop 'main'
+        MAC_4_mul_itm = conv_u2u_16_8(input_a_rsc_mgc_in_wire_d * input_b_rsc_mgc_in_wire_d);
+        begin : waitLoop1Exit
+          forever begin : waitLoop1
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop1Exit;
+          end
+        end
+        // C-Step 2 of Loop 'main'
+        MAC_acc_6_itm = MAC_4_mul_itm + conv_u2u_16_8(input_a_rsc_mgc_in_wire_d *
+            input_b_rsc_mgc_in_wire_d);
+        begin : waitLoop2Exit
+          forever begin : waitLoop2
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop2Exit;
+          end
+        end
+        // C-Step 3 of Loop 'main'
+        MAC_acc_itm = MAC_acc_6_itm + conv_u2u_16_8(input_a_rsc_mgc_in_wire_d * input_b_rsc_mgc_in_wire_d);
+        begin : waitLoop3Exit
+          forever begin : waitLoop3
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop3Exit;
+          end
+        end
+        // C-Step 4 of Loop 'main'
+        MAC_2_mul_itm = conv_u2u_16_8(input_a_rsc_mgc_in_wire_d * input_b_rsc_mgc_in_wire_d);
+        begin : waitLoop4Exit
+          forever begin : waitLoop4
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop4Exit;
+          end
+        end
+        // C-Step 5 of Loop 'main'
+        output_rsc_mgc_out_stdreg_d <= MAC_acc_itm + (MAC_2_mul_itm + conv_u2u_16_8(input_a_rsc_mgc_in_wire_d
+            * input_b_rsc_mgc_in_wire_d));
+        begin : waitLoop5Exit
+          forever begin : waitLoop5
+            @(posedge clk or negedge ( arst_n ));
+            if ( ~ arst_n )
+              disable mainExit;
+            if ( en )
+              disable waitLoop5Exit;
+          end
+        end
+        // C-Step 6 of Loop 'main'
+      end
+    end
+    MAC_2_mul_itm = 8'b0;
+    MAC_acc_itm = 8'b0;
+    MAC_acc_6_itm = 8'b0;
+    MAC_4_mul_itm = 8'b0;
+    output_rsc_mgc_out_stdreg_d <= 8'b0;
+  end
+
+
+  function  [7:0] conv_u2u_16_8 ;
+    input [15:0]  vector ;
+  begin
+    conv_u2u_16_8 = vector[7:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport.v b/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport_v2001.v b/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/cycle_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/dot_product/dot_product/dot_product.v9/cycle_set.tcl b/dot_product/dot_product/dot_product.v9/cycle_set.tcl
new file mode 100644
index 0000000..c060b46
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/cycle_set.tcl
@@ -0,0 +1,27 @@
+
+# Loop constraints
+directive set /dot_product/core/main CSTEPS_FROM {{. == 6}}
+
+# IO operation constraints
+directive set /dot_product/core/main/MAC:io_read(input_a:rsc.d)#3 CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:io_read(input_b:rsc.d)#3 CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC:io_read(input_a:rsc.d)#4 CSTEPS_FROM {{.. == 2}}
+directive set /dot_product/core/main/MAC:io_read(input_b:rsc.d)#4 CSTEPS_FROM {{.. == 2}}
+directive set /dot_product/core/main/MAC:io_read(input_a:rsc.d) CSTEPS_FROM {{.. == 3}}
+directive set /dot_product/core/main/MAC:io_read(input_b:rsc.d) CSTEPS_FROM {{.. == 3}}
+directive set /dot_product/core/main/MAC:io_read(input_a:rsc.d)#1 CSTEPS_FROM {{.. == 4}}
+directive set /dot_product/core/main/MAC:io_read(input_b:rsc.d)#1 CSTEPS_FROM {{.. == 4}}
+directive set /dot_product/core/main/MAC:io_read(input_a:rsc.d)#2 CSTEPS_FROM {{.. == 5}}
+directive set /dot_product/core/main/MAC:io_read(input_b:rsc.d)#2 CSTEPS_FROM {{.. == 5}}
+directive set /dot_product/core/main/io_write(output:rsc.d) CSTEPS_FROM {{.. == 5}}
+
+# Real operation constraints
+directive set /dot_product/core/main/MAC-4:mul CSTEPS_FROM {{.. == 1}}
+directive set /dot_product/core/main/MAC-5:mul CSTEPS_FROM {{.. == 2}}
+directive set /dot_product/core/main/MAC:acc#6 CSTEPS_FROM {{.. == 2}}
+directive set /dot_product/core/main/MAC-1:mul CSTEPS_FROM {{.. == 3}}
+directive set /dot_product/core/main/MAC:acc CSTEPS_FROM {{.. == 3}}
+directive set /dot_product/core/main/MAC-2:mul CSTEPS_FROM {{.. == 4}}
+directive set /dot_product/core/main/MAC-3:mul CSTEPS_FROM {{.. == 5}}
+directive set /dot_product/core/main/MAC:acc#5 CSTEPS_FROM {{.. == 5}}
+directive set /dot_product/core/main/MAC-5:acc#3 CSTEPS_FROM {{.. == 5}}
diff --git a/dot_product/dot_product/dot_product.v9/directives.tcl b/dot_product/dot_product/dot_product.v9/directives.tcl
new file mode 100644
index 0000000..5682058
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/directives.tcl
@@ -0,0 +1,59 @@
+//  Catapult University Version 2011a.126 (Production Release) Wed Aug  8 00:52:07 PDT 2012
+//  
+//  Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved.
+//                       UNPUBLISHED, LICENSED SOFTWARE.
+//            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
+//          PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS
+//  
+//  Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686
+//  
+//  Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, 
+//                       DesignPad v2.78_0.0
+//  
+//  This version may only be used for academic purposes.  Some optimizations 
+//  are disabled, so results obtained from this version may be sub-optimal.
+//  
+project new
+flow package require /SCVerify
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER
+solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++
+directive set -REGISTER_IDLE_SIGNAL false
+directive set -IDLE_SIGNAL {}
+directive set -TRANSACTION_DONE_SIGNAL false
+directive set -DONE_FLAG {}
+directive set -START_FLAG {}
+directive set -FSM_ENCODING none
+directive set -REG_MAX_FANOUT 0
+directive set -NO_X_ASSIGNMENTS true
+directive set -SAFE_FSM false
+directive set -RESET_CLEARS_ALL_REGS true
+directive set -ASSIGN_OVERHEAD 0
+directive set -DESIGN_GOAL area
+directive set -OLD_SCHED false
+directive set -PIPELINE_RAMP_UP true
+directive set -COMPGRADE fast
+directive set -SPECULATE true
+directive set -MERGEABLE true
+directive set -REGISTER_THRESHOLD 256
+directive set -MEM_MAP_THRESHOLD 32
+directive set -UNROLL no
+directive set -CLOCK_OVERHEAD 20.000000
+directive set -OPT_CONST_MULTS -1
+go analyze
+directive set -CLOCK_NAME clk
+directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}}
+directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}}
+directive set -DESIGN_HIERARCHY dot_product
+go compile
+directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true
+directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1
+directive set /dot_product/input_b -STREAM 8
+directive set /dot_product/input_b -WORD_WIDTH 8
+directive set /dot_product/input_a -STREAM 8
+directive set /dot_product/input_a -WORD_WIDTH 8
+directive set /dot_product/core/MAC -UNROLL yes
+directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0
+go architect
+go extract
diff --git a/dot_product/dot_product/dot_product.v9/dut_v_ports.map b/dot_product/dot_product/dot_product.v9/dut_v_ports.map
new file mode 100644
index 0000000..6890ebd
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/dut_v_ports.map
@@ -0,0 +1,6 @@
+clk 1 bit bool
+en 1 bit sc_logic
+arst_n 1 bit sc_logic
+input_a_rsc_z 8 bit_vector sc_lv
+input_b_rsc_z 8 bit_vector sc_lv
+output_rsc_z 8 bit_vector sc_lv
diff --git a/dot_product/dot_product/dot_product.v9/dut_vhdl_ports.map b/dot_product/dot_product/dot_product.v9/dut_vhdl_ports.map
new file mode 100644
index 0000000..23977c8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/dut_vhdl_ports.map
@@ -0,0 +1,6 @@
+clk 1 std_logic bool
+en 1 std_logic sc_logic
+arst_n 1 std_logic sc_logic
+input_a_rsc_z 8 std_logic_vector sc_lv
+input_b_rsc_z 8 std_logic_vector sc_lv
+output_rsc_z 8 std_logic_vector sc_lv
diff --git a/dot_product/dot_product/dot_product.v9/gate.v b/dot_product/dot_product/dot_product.v9/gate.v
new file mode 100644
index 0000000..42dcd48
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/gate.v
@@ -0,0 +1 @@
+Placeholder for gate netlist generated by Precision RTL Synthesis
diff --git a/dot_product/dot_product/dot_product.v9/mapped.v b/dot_product/dot_product/dot_product.v9/mapped.v
new file mode 100644
index 0000000..4345e81
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/mapped.v
@@ -0,0 +1 @@
+Placeholder for mapped netlist generated by Precision RTL Synthesis
diff --git a/dot_product/dot_product/dot_product.v9/messages.txt b/dot_product/dot_product/dot_product.v9/messages.txt
new file mode 100644
index 0000000..f19d3de
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/messages.txt
@@ -0,0 +1,205 @@
+
+# Messages from "go new"
+
+Creating project directory '\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\dot_product\dot_product'. (PRJ-1)
+
+# Messages from "go analyze"
+
+Front End called with arguments: -- {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\tb_dot_product.cpp} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.h} {\\icnas3.cc.ic.ac.uk\mg3115\EIE1 FPGA\Catapult C\student_files_2015\student_files_2015\prj1\dot_product_source\dot_product.cpp} (CIN-69)
+Edison Design Group C++/C Front End - Version 3.10.1 (CIN-1)
+Pragma 'hls_design<top>' detected on routine 'dot_product' (CIN-6)
+Source file analysis completed (CIN-68)
+Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
+Completed transformation 'analyze' on solution 'solution.v1': elapsed time 1.72 seconds, memory usage 145092kB, peak memory usage 219144kB (SOL-9)
+
+# Messages from "go compile"
+
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49)
+Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49)
+Starting transformation 'compile' on solution 'solution.v1' (SOL-8)
+Generating synthesis internal form... (CIN-3)
+Found top design routine 'dot_product' specified by directive (CIN-52)
+Synthesizing routine 'dot_product' (CIN-13)
+Inlining routine 'dot_product' (CIN-14)
+Optimizing block '/dot_product' ... (CIN-4)
+Inout port 'input_a' is only used as an input. (OPT-10)
+Inout port 'input_b' is only used as an input. (OPT-10)
+Inout port 'output' is only used as an output. (OPT-11)
+Loop '/dot_product/core/MAC' iterated at most 5 times. (LOOP-2)
+Design 'dot_product' was read (SOL-1)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15)
+    C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 29, Real ops = 7, Vars = 15) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 29, Real ops = 7, Vars = 12) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 7, Vars = 9) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 8) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 13, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 16, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 3) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 14, Real ops = 5, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 14, Real ops = 5, Vars = 2) (SOL-10)
+Completed transformation 'compile' on solution 'dot_product.v1': elapsed time 0.50 seconds, memory usage 161508kB, peak memory usage 219144kB (SOL-9)
+Variable 'input_a' array size reduced to 5 words (CIN-83)
+Variable 'input_b' array size reduced to 5 words (CIN-83)
+Branching solution 'dot_product.v2' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v3' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v4' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v5' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v6' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v7' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v8' at state 'compile' (PRJ-2)
+Branching solution 'dot_product.v9' at state 'compile' (PRJ-2)
+
+# Messages from "go architect"
+
+Starting transformation 'architect' on solution 'dot_product.v9' (SOL-8)
+Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7)
+Loop '/dot_product/core/main' is left rolled. (LOOP-4)
+Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2)
+I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10)
+Design 'dot_product' contains '10' real operations. (SOL-11)
+Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10)
+Completed transformation 'architect' on solution 'dot_product.v9': elapsed time 3.24 seconds, memory usage 182072kB, peak memory usage 190288kB (SOL-9)
+
+# Messages from "go allocate"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Prescheduled LOOP 'main' (2 c-steps) (SCHD-7)
+Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8)
+At least one feasible schedule exists. (CRAAS-9)
+Resource allocation and scheduling done. (CRAAS-2)
+Netlist written to file 'schedule.gnt' (NET-4)
+Starting transformation 'allocate' on solution 'dot_product.v9' (SOL-8)
+Select qualified components for data operations ... (CRAAS-3)
+Apply resource constraints on data operations ... (CRAAS-4)
+Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-11)
+Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12)
+Completed transformation 'allocate' on solution 'dot_product.v9': elapsed time 0.08 seconds, memory usage 182072kB, peak memory usage 190288kB (SOL-9)
+
+# Messages from "go schedule"
+
+Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1)
+Global signal 'input_a:rsc.z' added to design 'dot_product' for component 'input_a:rsc:mgc_in_wire' (LIB-3)
+Global signal 'input_b:rsc.z' added to design 'dot_product' for component 'input_b:rsc:mgc_in_wire' (LIB-3)
+Global signal 'output:rsc.z' added to design 'dot_product' for component 'output:rsc:mgc_out_stdreg' (LIB-3)
+Netlist written to file 'cycle.v' (NET-4)
+Starting transformation 'schedule' on solution 'dot_product.v9' (SOL-8)
+Optimizing partition '/dot_product': (Total ops = 40, Real ops = 11, Vars = 20) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 27, Real ops = 10, Vars = 10) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 21, Real ops = 10, Vars = 4) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 10, Real ops = 10, Vars = 4) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 28, Real ops = 10, Vars = 19) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 16, Real ops = 10, Vars = 10) (SOL-10)
+Completed transformation 'schedule' on solution 'dot_product.v9': elapsed time 1.08 seconds, memory usage 183844kB, peak memory usage 190288kB (SOL-9)
+
+# Messages from "go dpfsm"
+
+Performing FSM extraction... (FSM-1)
+Starting transformation 'dpfsm' on solution 'dot_product.v9' (SOL-8)
+Optimizing partition '/dot_product': (Total ops = 56, Real ops = 16, Vars = 50) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 44, Real ops = 16, Vars = 41) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 46, Real ops = 13, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 34, Real ops = 13, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Completed transformation 'dpfsm' on solution 'dot_product.v9': elapsed time 0.09 seconds, memory usage 184104kB, peak memory usage 190368kB (SOL-9)
+
+# Messages from "go extract"
+
+Shared Operations MAC:acc#5,MAC:acc#6,MAC:acc on resource MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8):mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) (ASG-3)
+Netlist written to file 'schematic.nlv' (NET-4)
+Starting transformation 'extract' on solution 'dot_product.v9' (SOL-8)
+Optimizing partition '/dot_product': (Total ops = 46, Real ops = 11, Vars = 36) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 34, Real ops = 11, Vars = 27) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 43, Real ops = 11, Vars = 33) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 11, Vars = 24) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Netlist written to file 'rtl.v' (NET-4)
+Optimizing partition '/dot_product': (Total ops = 43, Real ops = 11, Vars = 33) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 11, Vars = 24) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 29, Real ops = 11, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 28, Real ops = 11, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Optimizing partition '/dot_product': (Total ops = 40, Real ops = 11, Vars = 26) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core': (Total ops = 28, Real ops = 11, Vars = 17) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10)
+Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10)
+Completed transformation 'extract' on solution 'dot_product.v9': elapsed time 2.70 seconds, memory usage 188780kB, peak memory usage 192380kB (SOL-9)
diff --git a/dot_product/dot_product/dot_product.v9/new_ccs_env.mk b/dot_product/dot_product/dot_product.v9/new_ccs_env.mk
new file mode 100644
index 0000000..59be8e9
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/new_ccs_env.mk
@@ -0,0 +1,392 @@
+ifeq "$(CXX_HOME)" ""
+CXX_HOME                                      := c:/PROGRA~2/MICROS~4.0/VC
+export CXX_HOME
+endif
+ifeq "$(CXX_TYPE)" ""
+CXX_TYPE                                      := msvc
+export CXX_TYPE
+endif
+ifeq "$(CXX_VCO)" ""
+CXX_VCO                                       := ixn
+export CXX_VCO
+endif
+ifeq "$(PATH)" ""
+PATH                                          := c:/PROGRA~2/MICROS~4.0/VC/../Common7/IDE;c:/PROGRA~2/MICROS~4.0/VC/bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\bin;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\lib;C:\PROGRA~1\CALYPT~1\CATAPU~1.126\Mgc_home\pkgs\sif\.lib;
+export PATH
+endif
+ifeq "$(INCLUDE)" ""
+INCLUDE                                       := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include;c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Include;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Include
+export INCLUDE
+endif
+ifeq "$(LIB)" ""
+LIB                                           := c:/Program Files (x86)/Microsoft Visual Studio 9.0/VC/Lib;C:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib
+export LIB
+endif
+ifeq "$(SystemRoot)" ""
+SystemRoot                                    := C:\windows
+export SystemRoot
+endif
+ifeq "$(SYN_DIR)" ""
+SYN_DIR                                       := gate_synthesis_psr
+export SYN_DIR
+endif
+ifeq "$(HLD_CONSTRAINT_FNAME)" ""
+HLD_CONSTRAINT_FNAME                          := top_gate_constraints.cpp
+export HLD_CONSTRAINT_FNAME
+endif
+ifeq "$(ModelSim_Path)" ""
+ModelSim_Path                                 := 
+export ModelSim_Path
+endif
+ifeq "$(ModelSim_Flags)" ""
+ModelSim_Flags                                := 
+export ModelSim_Flags
+endif
+ifeq "$(ModelSim_RADIX)" ""
+ModelSim_RADIX                                := hex
+export ModelSim_RADIX
+endif
+ifeq "$(ModelSim_MSIM_AC_TYPES)" ""
+ModelSim_MSIM_AC_TYPES                        := true
+export ModelSim_MSIM_AC_TYPES
+endif
+ifeq "$(ModelSim_VCOM_OPTS)" ""
+ModelSim_VCOM_OPTS                            := 
+export ModelSim_VCOM_OPTS
+endif
+ifeq "$(ModelSim_VLOG_OPTS)" ""
+ModelSim_VLOG_OPTS                            := 
+export ModelSim_VLOG_OPTS
+endif
+ifeq "$(ModelSim_SCCOM_OPTS)" ""
+ModelSim_SCCOM_OPTS                           := -g -x c++
+export ModelSim_SCCOM_OPTS
+endif
+ifeq "$(ModelSim_FORCE_32BIT)" ""
+ModelSim_FORCE_32BIT                          := false
+export ModelSim_FORCE_32BIT
+endif
+ifeq "$(ModelSim_VSIM_OPTS)" ""
+ModelSim_VSIM_OPTS                            := -t ps -novopt
+export ModelSim_VSIM_OPTS
+endif
+ifeq "$(ModelSim_GATE_VSIM_OPTS)" ""
+ModelSim_GATE_VSIM_OPTS                       := +notimingchecks -sdfnoerror -noglitch
+export ModelSim_GATE_VSIM_OPTS
+endif
+ifeq "$(ModelSim_DEF_MODELSIM_INI)" ""
+ModelSim_DEF_MODELSIM_INI                     := 
+export ModelSim_DEF_MODELSIM_INI
+endif
+ifeq "$(ModelSim_SHOW_LIST)" ""
+ModelSim_SHOW_LIST                            := false
+export ModelSim_SHOW_LIST
+endif
+ifeq "$(ModelSim_MSIM_DOFILE)" ""
+ModelSim_MSIM_DOFILE                          := 
+export ModelSim_MSIM_DOFILE
+endif
+ifeq "$(ModelSim_ENABLE_OLD_MSIM_FLOW)" ""
+ModelSim_ENABLE_OLD_MSIM_FLOW                 := false
+export ModelSim_ENABLE_OLD_MSIM_FLOW
+endif
+ifeq "$(ModelSim_VCD_SIZE_LIMIT)" ""
+ModelSim_VCD_SIZE_LIMIT                       := 2000
+export ModelSim_VCD_SIZE_LIMIT
+endif
+ifeq "$(NCSim_NC_ROOT)" ""
+NCSim_NC_ROOT                                 := $(NC_ROOT)
+export NCSim_NC_ROOT
+endif
+ifeq "$(NCSim_NCVHDL_OPTS)" ""
+NCSim_NCVHDL_OPTS                             := -v93
+export NCSim_NCVHDL_OPTS
+endif
+ifeq "$(NCSim_NCVLOG_OPTS)" ""
+NCSim_NCVLOG_OPTS                             := 
+export NCSim_NCVLOG_OPTS
+endif
+ifeq "$(NCSim_NCSC_OPTS)" ""
+NCSim_NCSC_OPTS                               := 
+export NCSim_NCSC_OPTS
+endif
+ifeq "$(NCSim_NCSC_CXX_OPTS)" ""
+NCSim_NCSC_CXX_OPTS                           := -x c++ -Wno-deprecated
+export NCSim_NCSC_CXX_OPTS
+endif
+ifeq "$(NCSim_NCELAB_OPTS)" ""
+NCSim_NCELAB_OPTS                             := 
+export NCSim_NCELAB_OPTS
+endif
+ifeq "$(NCSim_NCSIM_OPTS)" ""
+NCSim_NCSIM_OPTS                              := 
+export NCSim_NCSIM_OPTS
+endif
+ifeq "$(NCSim_NCSIM_TIMESCALE)" ""
+NCSim_NCSIM_TIMESCALE                         := 1 ns / 1 ps
+export NCSim_NCSIM_TIMESCALE
+endif
+ifeq "$(NCSim_NCSIM_GCCVERSION)" ""
+NCSim_NCSIM_GCCVERSION                        := 4.1
+export NCSim_NCSIM_GCCVERSION
+endif
+ifeq "$(NCSim_FORCE_32BIT)" ""
+NCSim_FORCE_32BIT                             := false
+export NCSim_FORCE_32BIT
+endif
+ifeq "$(NCSim_GCC_HOME)" ""
+NCSim_GCC_HOME                                := 
+export NCSim_GCC_HOME
+endif
+ifeq "$(OSCI_SYSTEMC_INCLUDE)" ""
+OSCI_SYSTEMC_INCLUDE                          := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include
+export OSCI_SYSTEMC_INCLUDE
+endif
+ifeq "$(OSCI_SYSTEMC_LIB)" ""
+OSCI_SYSTEMC_LIB                              := C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/$(CXX_OS)/$(CXX_TYPE)
+export OSCI_SYSTEMC_LIB
+endif
+ifeq "$(OSCI_SYSTEMC_NAME)" ""
+OSCI_SYSTEMC_NAME                             := systemc
+export OSCI_SYSTEMC_NAME
+endif
+ifeq "$(OSCI_COMP_FLAGS)" ""
+OSCI_COMP_FLAGS                               := 
+export OSCI_COMP_FLAGS
+endif
+ifeq "$(OSCI_USE_32BIT_COMPILER)" ""
+OSCI_USE_32BIT_COMPILER                       := true
+export OSCI_USE_32BIT_COMPILER
+endif
+ifeq "$(OSCI_GDBGUI)" ""
+OSCI_GDBGUI                                   := ddd
+export OSCI_GDBGUI
+endif
+ifeq "$(Novas_NOVAS_INST_DIR)" ""
+Novas_NOVAS_INST_DIR                          := $(NOVAS_INST_DIR)
+export Novas_NOVAS_INST_DIR
+endif
+ifeq "$(Novas_NOVAS_PLATFORM)" ""
+Novas_NOVAS_PLATFORM                          := LINUX
+export Novas_NOVAS_PLATFORM
+endif
+ifeq "$(Novas_NOVAS_MSIM_PLI)" ""
+Novas_NOVAS_MSIM_PLI                          := modelsim_fli61
+export Novas_NOVAS_MSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_VER)" ""
+Novas_NOVAS_NCSIM_VER                         := nc57_vhdl
+export Novas_NOVAS_NCSIM_VER
+endif
+ifeq "$(Novas_NOVAS_NCSIM_PLI)" ""
+Novas_NOVAS_NCSIM_PLI                         := ncsc57/lib-linux_gcc3_23
+export Novas_NOVAS_NCSIM_PLI
+endif
+ifeq "$(Novas_NOVAS_NCSIM_LDV)" ""
+Novas_NOVAS_NCSIM_LDV                         := ius_vhpi_latest
+export Novas_NOVAS_NCSIM_LDV
+endif
+ifeq "$(Novas_NOVAS_NCSIM_FSDBW)" ""
+Novas_NOVAS_NCSIM_FSDBW                       := LINUX_GNU_296
+export Novas_NOVAS_NCSIM_FSDBW
+endif
+ifeq "$(Valgrind_VALGRIND)" ""
+Valgrind_VALGRIND                             := /usr/opt/bin/valgrind
+export Valgrind_VALGRIND
+endif
+ifeq "$(Valgrind_VALGRIND_OPTS)" ""
+Valgrind_VALGRIND_OPTS                        := --demangle=yes --leak-check=no --undef-value-errors=yes
+export Valgrind_VALGRIND_OPTS
+endif
+ifeq "$(Vista_VISTA_HOME)" ""
+Vista_VISTA_HOME                              := $(VISTA_HOME)
+export Vista_VISTA_HOME
+endif
+ifeq "$(Vista_MODEL_BUILDER_HOME)" ""
+Vista_MODEL_BUILDER_HOME                      := $(MODEL_BUILDER_HOME)
+export Vista_MODEL_BUILDER_HOME
+endif
+ifeq "$(VCS_VCS_HOME)" ""
+VCS_VCS_HOME                                  := $(VCS_HOME)
+export VCS_VCS_HOME
+endif
+ifeq "$(VCS_COMP_FLAGS)" ""
+VCS_COMP_FLAGS                                := -g
+export VCS_COMP_FLAGS
+endif
+ifeq "$(VCS_FORCE_32BIT)" ""
+VCS_FORCE_32BIT                               := false
+export VCS_FORCE_32BIT
+endif
+ifeq "$(VCS_VCS_GCC_VER)" ""
+VCS_VCS_GCC_VER                               := 4.2.2
+export VCS_VCS_GCC_VER
+endif
+ifeq "$(VCS_VHDLAN_OPTS)" ""
+VCS_VHDLAN_OPTS                               := 
+export VCS_VHDLAN_OPTS
+endif
+ifeq "$(VCS_VLOGAN_OPTS)" ""
+VCS_VLOGAN_OPTS                               := +v2k
+export VCS_VLOGAN_OPTS
+endif
+ifeq "$(VCS_VCSELAB_OPTS)" ""
+VCS_VCSELAB_OPTS                              := -debug_all -timescale=1ps/1ps
+export VCS_VCSELAB_OPTS
+endif
+ifeq "$(VCS_VCSSIM_OPTS)" ""
+VCS_VCSSIM_OPTS                               := 
+export VCS_VCSSIM_OPTS
+endif
+ifeq "$(Precision_Path)" ""
+Precision_Path                                := can't read "PRECISION_HOME": no such variable
+export Precision_Path
+endif
+ifeq "$(Precision_Flags)" ""
+Precision_Flags                               := 
+export Precision_Flags
+endif
+ifeq "$(Precision_addio)" ""
+Precision_addio                               := true
+export Precision_addio
+endif
+ifeq "$(Precision_retiming)" ""
+Precision_retiming                            := false
+export Precision_retiming
+endif
+ifeq "$(Precision_run_pnr)" ""
+Precision_run_pnr                             := false
+export Precision_run_pnr
+endif
+ifeq "$(Precision_newgui)" ""
+Precision_newgui                              := true
+export Precision_newgui
+endif
+ifeq "$(Precision_rtlplus)" ""
+Precision_rtlplus                             := false
+export Precision_rtlplus
+endif
+ifeq "$(Precision_OutputEDIF)" ""
+Precision_OutputEDIF                          := true
+export Precision_OutputEDIF
+endif
+ifeq "$(Precision_bottom_up_flow)" ""
+Precision_bottom_up_flow                      := false
+export Precision_bottom_up_flow
+endif
+ifeq "$(Precision_PlaceAndRouteInstallPath)" ""
+Precision_PlaceAndRouteInstallPath            := 
+export Precision_PlaceAndRouteInstallPath
+endif
+ifeq "$(Precision_GatherDetailedTimingData)" ""
+Precision_GatherDetailedTimingData            := true
+export Precision_GatherDetailedTimingData
+endif
+ifeq "$(Precision_TimingReportingMode)" ""
+Precision_TimingReportingMode                 := p2p
+export Precision_TimingReportingMode
+endif
+ifeq "$(Precision_EnableClockGating)" ""
+Precision_EnableClockGating                   := false
+export Precision_EnableClockGating
+endif
+ifeq "$(Altera_QUARTUS_ROOTDIR)" ""
+Altera_QUARTUS_ROOTDIR                        := C:/altera/15.0/quartus
+export Altera_QUARTUS_ROOTDIR
+endif
+ifeq "$(Altera_QUARTUS_LIB)" ""
+Altera_QUARTUS_LIB                            := $(QUARTUS_LIB)
+export Altera_QUARTUS_LIB
+endif
+ifeq "$(SCVerify_RESET_CYCLES)" ""
+SCVerify_RESET_CYCLES                         := 2
+export SCVerify_RESET_CYCLES
+endif
+ifeq "$(SCVerify_SYNC_ALL_RESETS)" ""
+SCVerify_SYNC_ALL_RESETS                      := true
+export SCVerify_SYNC_ALL_RESETS
+endif
+ifeq "$(SCVerify_TB_STACKSIZE)" ""
+SCVerify_TB_STACKSIZE                         := 64000000
+export SCVerify_TB_STACKSIZE
+endif
+ifeq "$(SCVerify_INVOKE_ARGS)" ""
+SCVerify_INVOKE_ARGS                          := 
+export SCVerify_INVOKE_ARGS
+endif
+ifeq "$(SCVerify_REPLAY_ARGS)" ""
+SCVerify_REPLAY_ARGS                          := 
+export SCVerify_REPLAY_ARGS
+endif
+ifeq "$(SCVerify_MSIM_DEBUG)" ""
+SCVerify_MSIM_DEBUG                           := false
+export SCVerify_MSIM_DEBUG
+endif
+ifeq "$(SCVerify_MAX_ERROR_CNT)" ""
+SCVerify_MAX_ERROR_CNT                        := 0
+export SCVerify_MAX_ERROR_CNT
+endif
+ifeq "$(SCVerify_DEADLOCK_DETECTION)" ""
+SCVerify_DEADLOCK_DETECTION                   := true
+export SCVerify_DEADLOCK_DETECTION
+endif
+ifeq "$(SCVerify_INCL_DIRS)" ""
+SCVerify_INCL_DIRS                            := 
+export SCVerify_INCL_DIRS
+endif
+ifeq "$(SCVerify_LINK_LIBPATHS)" ""
+SCVerify_LINK_LIBPATHS                        := 
+export SCVerify_LINK_LIBPATHS
+endif
+ifeq "$(SCVerify_LINK_LIBNAMES)" ""
+SCVerify_LINK_LIBNAMES                        := 
+export SCVerify_LINK_LIBNAMES
+endif
+ifeq "$(SCVerify_USE_MSIM)" ""
+SCVerify_USE_MSIM                             := true
+export SCVerify_USE_MSIM
+endif
+ifeq "$(SCVerify_USE_OSCI)" ""
+SCVerify_USE_OSCI                             := true
+export SCVerify_USE_OSCI
+endif
+ifeq "$(SCVerify_USE_NCSIM)" ""
+SCVerify_USE_NCSIM                            := false
+export SCVerify_USE_NCSIM
+endif
+ifeq "$(SCVerify_USE_VISTA)" ""
+SCVerify_USE_VISTA                            := false
+export SCVerify_USE_VISTA
+endif
+ifeq "$(SCVerify_USE_VCS)" ""
+SCVerify_USE_VCS                              := false
+export SCVerify_USE_VCS
+endif
+ifeq "$(SCVerify_DISABLE_EMPTY_INPUTS)" ""
+SCVerify_DISABLE_EMPTY_INPUTS                 := false
+export SCVerify_DISABLE_EMPTY_INPUTS
+endif
+ifeq "$(SCVerify_ENABLE_REPLAY_VERIFICATION)" ""
+SCVerify_ENABLE_REPLAY_VERIFICATION           := false
+export SCVerify_ENABLE_REPLAY_VERIFICATION
+endif
+ifeq "$(SCVerify_IDLE_SYNCHRONIZATION_MODE)" ""
+SCVerify_IDLE_SYNCHRONIZATION_MODE            := false
+export SCVerify_IDLE_SYNCHRONIZATION_MODE
+endif
+ifeq "$(SCVerify_MISMATCHED_OUTPUTS_ONLY)" ""
+SCVerify_MISMATCHED_OUTPUTS_ONLY              := true
+export SCVerify_MISMATCHED_OUTPUTS_ONLY
+endif
+ifeq "$(LINK_LIBPATHS)" ""
+LINK_LIBPATHS                                 := 
+export LINK_LIBPATHS
+endif
+ifeq "$(LINK_LIBNAMES)" ""
+LINK_LIBNAMES                                 := 
+export LINK_LIBNAMES
+endif
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                                     := 
+export INCL_DIRS
+endif
diff --git a/dot_product/dot_product/dot_product.v9/reg_sharing.tcl b/dot_product/dot_product/dot_product.v9/reg_sharing.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/reg_sharing.tcl
diff --git a/dot_product/dot_product/dot_product.v9/res_sharing.tcl b/dot_product/dot_product/dot_product.v9/res_sharing.tcl
new file mode 100644
index 0000000..7714860
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/res_sharing.tcl
@@ -0,0 +1,3 @@
+directive set /dot_product/dot_product:core/dot_product:core:conc/MAC:acc#5 RESOURCE_NAME MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)
+directive set /dot_product/dot_product:core/dot_product:core:conc/MAC:acc#6 RESOURCE_NAME MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)
+directive set /dot_product/dot_product:core/dot_product:core:conc/MAC:acc RESOURCE_NAME MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)
diff --git a/dot_product/dot_product/dot_product.v9/rtl.rpt b/dot_product/dot_product/dot_product.v9/rtl.rpt
new file mode 100644
index 0000000..f12cd6d
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl.rpt
@@ -0,0 +1,248 @@
+-- Catapult University Version: Report                                              
+-- ---------------------------- ---------------------------------------------------
+-- Version:                     2011a.126 Production Release                        
+-- Build Date:                  Wed Aug  8 00:52:07 PDT 2012                        
+                                                                                    
+-- Generated by:                mg3115@EEWS104A-015                                 
+-- Generated date:              Tue Mar 01 14:54:51 +0000 2016                      
+
+Solution Settings: dot_product.v9
+  Current state: extract
+  Project: dot_product
+  
+  Design Input Files Specified
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+      $MGC_HOME/shared/include/ac_int.h
+    $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+      $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
+        $MGC_HOME/shared/include/ac_int.h
+      $MGC_HOME/shared/include/mc_scverify.h
+  
+  Processes/Blocks in Design
+    Process           Real Operation(s) count Latency Throughput Reset Length II Comments 
+    ----------------- ----------------------- ------- ---------- ------------ -- --------
+    /dot_product/core                      20       5          6            0  0          
+    Design Total:                          20       5          6            0  0          
+    
+  Bill Of Materials (Datapath)
+    Component Name                          Area Score Area(DSP_block_9-bit_elems) Area(LUTs) Delay Post Alloc Post Assign 
+    --------------------------------------- ---------- --------------------------- ---------- ----- ---------- -----------
+    [Lib: mgc_Altera-Cyclone-III-6_beh_psr]                                                                                
+    mgc_add(8,0,8,0,8)                           9.259                       0.000      9.259 1.163          4           2 
+    mgc_mul(8,0,8,0,8)                         330.250                       2.000     10.250 2.659          1           1 
+    mgc_mux(8,1,2)                               7.355                       0.000      7.355 0.369          0           3 
+    mgc_reg_pos(8,1,0,0,0,1,1)                   0.000                       0.000      0.000 0.000          0           4 
+    [Lib: mgc_ioport]                                                                                                      
+    mgc_in_wire(1,8)                             0.000                       0.000      0.000 0.000          1           1 
+    mgc_in_wire(2,8)                             0.000                       0.000      0.000 0.000          1           1 
+    mgc_out_stdreg(3,8)                          0.000                       0.000      0.000 0.000          1           1 
+                                                                                                                           
+    TOTAL AREA (After Assignment):             370.833                       2.000     51.000                              
+    
+  Area Scores
+                      Post-Scheduling  Post-DP & FSM Post-Assignment 
+    ----------------- --------------- -------------- ---------------
+    Total Area Score:    367.3          382.0           370.8        
+    Total Reg:             0.0            0.0             0.0        
+                                                                     
+    DataPath:            367.3 (100%)   382.0 (100%)    370.8 (100%) 
+      MUX:                 0.0           14.7   (4%)     22.1   (6%) 
+      FUNC:              367.3 (100%)   367.3  (96%)    348.8  (94%) 
+      LOGIC:               0.0            0.0             0.0        
+      BUFFER:              0.0            0.0             0.0        
+      MEM:                 0.0            0.0             0.0        
+      ROM:                 0.0            0.0             0.0        
+      REG:                 0.0            0.0             0.0        
+                                                                     
+    
+    FSM:                   0.0            0.0             0.0   (0%) 
+      FSM-REG:             0.0            0.0             0.0        
+      FSM-COMB:            0.0            0.0             0.0 (100%) 
+                                                                     
+    
+  Register-to-Variable Mappings
+    Register                    Size(bits) Gated Register CG Opt Done Variables                                             
+    --------------------------- ---------- -------------- ----------- -----------------------------------------------------
+    MAC-4:mul.itm                        8         Y                  MAC-4:mul.itm                                         
+    MAC:acc#6.itm                        8         Y                  MAC:acc#6.itm                                         
+    MAC:acc.itm                          8         Y                  MAC:acc.itm                                           
+    output:rsc:mgc_out_stdreg.d          8         Y                  output:rsc:mgc_out_stdreg.d                           
+                                                                                                                            
+    Total:                              32             32           0 (Total Gating Ratio: 1.00, CG Opt Gating Ratio: 0.00) 
+    
+  Timing Report
+    Critical Path
+      Max Delay:  5.3544220000000005
+      Slack:      14.645578
+      
+      Path                                                                       Startpoint                                 Endpoint                                          Delay  Slack   
+      -------------------------------------------------------------------------- ------------------------------------------ ------------------------------------------------- ------ -------
+      1                                                                          dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 5.3544 14.6456 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_a:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/z.out                                                                                                                                                0.0000 3.8223  
+        dot_product:core/MAC-5:acc#3                                             mgc_add_8_0_8_0_8                                                                            1.1631 4.9855  
+        dot_product:core/MAC-5:acc#3.itm                                                                                                                                      0.0000 4.9855  
+        dot_product:core/mux                                                     mgc_mux_8_1_2                                                                                0.3690 5.3544  
+        dot_product:core/mux.itm                                                                                                                                              0.0000 5.3544  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d)                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 5.3544  
+                                                                                                                                                                                             
+      2                                                                          dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 5.3544 14.6456 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_b:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/z.out                                                                                                                                                0.0000 3.8223  
+        dot_product:core/MAC-5:acc#3                                             mgc_add_8_0_8_0_8                                                                            1.1631 4.9855  
+        dot_product:core/MAC-5:acc#3.itm                                                                                                                                      0.0000 4.9855  
+        dot_product:core/mux                                                     mgc_mux_8_1_2                                                                                0.3690 5.3544  
+        dot_product:core/mux.itm                                                                                                                                              0.0000 5.3544  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d)                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 5.3544  
+                                                                                                                                                                                             
+      3                                                                          dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(MAC:acc.itm)                 4.1913 15.8087 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_a:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/z.out                                                                                                                                                0.0000 3.8223  
+        dot_product:core/mux#1                                                   mgc_mux_8_1_2                                                                                0.3690 4.1913  
+        dot_product:core/mux#1.itm                                                                                                                                            0.0000 4.1913  
+        dot_product:core/reg(MAC:acc.itm)                                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 4.1913  
+                                                                                                                                                                                             
+      4                                                                          dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(MAC:acc.itm)                 4.1913 15.8087 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_b:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/z.out                                                                                                                                                0.0000 3.8223  
+        dot_product:core/mux#1                                                   mgc_mux_8_1_2                                                                                0.3690 4.1913  
+        dot_product:core/mux#1.itm                                                                                                                                            0.0000 4.1913  
+        dot_product:core/reg(MAC:acc.itm)                                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 4.1913  
+                                                                                                                                                                                             
+      5                                                                          dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 3.8223 16.1777 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_a:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/z.out                                                                                                                                                0.0000 3.8223  
+        dot_product:core/MAC-5:acc#3                                             mgc_add_8_0_8_0_8                                                                            1.1631 4.9855  
+        dot_product:core/MAC-5:acc#3.itm                                                                                                                                      0.0000 4.9855  
+        dot_product:core/mux                                                     mgc_mux_8_1_2                                                                                0.3690 5.3544  
+        dot_product:core/mux.itm                                                                                                                                              0.0000 5.3544  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d)                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 5.3544  
+                                                                                                                                                                                             
+      6                                                                          dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 3.8223 16.1777 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_b:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 3.8223  
+        dot_product:core/z.out                                                                                                                                                0.0000 3.8223  
+        dot_product:core/MAC-5:acc#3                                             mgc_add_8_0_8_0_8                                                                            1.1631 4.9855  
+        dot_product:core/MAC-5:acc#3.itm                                                                                                                                      0.0000 4.9855  
+        dot_product:core/mux                                                     mgc_mux_8_1_2                                                                                0.3690 5.3544  
+        dot_product:core/mux.itm                                                                                                                                              0.0000 5.3544  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d)                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 5.3544  
+                                                                                                                                                                                             
+      7                                                                          dot_product:core/input_a:rsc:mgc_in_wire.d dot_product:core/reg(MAC-4:mul.itm)               2.6592 17.3408 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_a:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/reg(MAC-4:mul.itm)                                      mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 2.6592  
+                                                                                                                                                                                             
+      8                                                                          dot_product:core/input_b:rsc:mgc_in_wire.d dot_product:core/reg(MAC-4:mul.itm)               2.6592 17.3408 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/input_b:rsc:mgc_in_wire.d                                                                                                                            0.0000 0.0000  
+        dot_product:core/MAC-4:mul                                               mgc_mul_8_0_8_0_8                                                                            2.6592 2.6592  
+        dot_product:core/MAC-4:mul.itm#1                                                                                                                                      0.0000 2.6592  
+        dot_product:core/reg(MAC-4:mul.itm)                                      mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 2.6592  
+                                                                                                                                                                                             
+      9                                                                          dot_product:core/reg(MAC:acc#6.itm)        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 1.5321 18.4679 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/reg(MAC:acc#6.itm)                                      mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/MAC:acc#6.itm                                                                                                                                        0.0000 0.0000  
+        dot_product:core/mux#2                                                   mgc_mux_8_1_2                                                                                0.3690 0.3690  
+        dot_product:core/mux#2.itm                                                                                                                                            0.0000 0.3690  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 1.5321  
+        dot_product:core/z.out                                                                                                                                                0.0000 1.5321  
+        dot_product:core/MAC-5:acc#3                                             mgc_add_8_0_8_0_8                                                                            1.1631 2.6952  
+        dot_product:core/MAC-5:acc#3.itm                                                                                                                                      0.0000 2.6952  
+        dot_product:core/mux                                                     mgc_mux_8_1_2                                                                                0.3690 3.0642  
+        dot_product:core/mux.itm                                                                                                                                              0.0000 3.0642  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d)                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 3.0642  
+                                                                                                                                                                                             
+      10                                                                         dot_product:core/reg(MAC-4:mul.itm)        dot_product:core/reg(output:rsc:mgc_out_stdreg.d) 1.5321 18.4679 
+                                                                                                                                                                                             
+        Instance                                                                 Component                                                                                    Delta  Delay   
+        --------                                                                 ---------                                                                                    -----  -----   
+        dot_product:core/reg(MAC-4:mul.itm)                                      mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 0.0000  
+        dot_product:core/MAC-4:mul.itm                                                                                                                                        0.0000 0.0000  
+        dot_product:core/mux#2                                                   mgc_mux_8_1_2                                                                                0.3690 0.3690  
+        dot_product:core/mux#2.itm                                                                                                                                            0.0000 0.3690  
+        dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) mgc_add_8_0_8_0_8                                                                            1.1631 1.5321  
+        dot_product:core/z.out                                                                                                                                                0.0000 1.5321  
+        dot_product:core/MAC-5:acc#3                                             mgc_add_8_0_8_0_8                                                                            1.1631 2.6952  
+        dot_product:core/MAC-5:acc#3.itm                                                                                                                                      0.0000 2.6952  
+        dot_product:core/mux                                                     mgc_mux_8_1_2                                                                                0.3690 3.0642  
+        dot_product:core/mux.itm                                                                                                                                              0.0000 3.0642  
+        dot_product:core/reg(output:rsc:mgc_out_stdreg.d)                        mgc_reg_pos_8_1_0_0_0_1_1                                                                    0.0000 3.0642  
+                                                                                                                                                                                             
+      
+    Register Input and Register-to-Output Slack
+      Clock period or pin-to-reg delay constraint (clk): 20.0
+      Clock uncertainty constraint (clk)               : 0.0
+      
+      Instance                                          Port              Slack (Delay) Messages 
+      ------------------------------------------------- --------------- ------- ------- --------
+      dot_product:core/reg(output:rsc:mgc_out_stdreg.d) mux.itm         14.6456  5.3544          
+      dot_product:core/reg(MAC-4:mul.itm)               MAC-4:mul.itm#1 14.6456  5.3544          
+      dot_product:core/reg(MAC:acc#6.itm)               z.out           14.6456  5.3544          
+      dot_product:core/reg(MAC:acc.itm)                 mux#1.itm       15.8087  4.1913          
+      dot_product                                       output:rsc.z    20.0000  0.0000          
+      
+  Operator Bitwidth Summary
+    Operation  Size (bits) Count 
+    ---------- ----------- -----
+    add                          
+    -                    8     2 
+    mul                          
+    -                    8     1 
+    mux                          
+    -                    1     3 
+    read_port                    
+    -                    8     2 
+    reg                          
+    -                    8     4 
+    write_port                   
+    -                    8     1 
+    
+  End of Report
diff --git a/dot_product/dot_product/dot_product.v9/rtl.v b/dot_product/dot_product/dot_product.v9/rtl.v
new file mode 100644
index 0000000..313b127
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl.v
@@ -0,0 +1,219 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 14:54:51 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core_fsm
+//  FSM Module
+// ------------------------------------------------------------------
+
+
+module dot_product_core_fsm (
+  clk, en, arst_n, fsm_output
+);
+  input clk;
+  input en;
+  input arst_n;
+  output [5:0] fsm_output;
+  reg [5:0] fsm_output;
+
+
+  // FSM State Type Declaration for dot_product_core_fsm_1
+  parameter
+    st_main = 3'd0,
+    st_main_1 = 3'd1,
+    st_main_2 = 3'd2,
+    st_main_3 = 3'd3,
+    st_main_4 = 3'd4,
+    st_main_5 = 3'd5,
+    state_x = 3'b000;
+
+  reg [2:0] state_var;
+  reg [2:0] state_var_NS;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : dot_product_core_fsm_1
+    case (state_var)
+      st_main : begin
+        fsm_output = 6'b1;
+        state_var_NS = st_main_1;
+      end
+      st_main_1 : begin
+        fsm_output = 6'b10;
+        state_var_NS = st_main_2;
+      end
+      st_main_2 : begin
+        fsm_output = 6'b100;
+        state_var_NS = st_main_3;
+      end
+      st_main_3 : begin
+        fsm_output = 6'b1000;
+        state_var_NS = st_main_4;
+      end
+      st_main_4 : begin
+        fsm_output = 6'b10000;
+        state_var_NS = st_main_5;
+      end
+      st_main_5 : begin
+        fsm_output = 6'b100000;
+        state_var_NS = st_main;
+      end
+      default : begin
+        fsm_output = 6'b000000;
+        state_var_NS = st_main;
+      end
+    endcase
+  end
+
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      state_var <= st_main;
+    end
+    else if ( en ) begin
+      state_var <= state_var_NS;
+    end
+  end
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire [5:0] fsm_output;
+  reg [7:0] MAC_4_mul_itm;
+  reg [7:0] MAC_acc_6_itm;
+  reg [7:0] MAC_acc_itm;
+  wire [7:0] z_out;
+  wire [8:0] nl_z_out;
+  wire [7:0] MAC_4_mul_itm_1;
+  wire [15:0] nl_MAC_4_mul_itm_1;
+
+  wire[7:0] mux_2_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  dot_product_core_fsm dot_product_core_fsm_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .fsm_output(fsm_output)
+    );
+  assign nl_MAC_4_mul_itm_1 = input_a_rsc_mgc_in_wire_d * input_b_rsc_mgc_in_wire_d;
+  assign MAC_4_mul_itm_1 = nl_MAC_4_mul_itm_1[7:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      output_rsc_mgc_out_stdreg_d <= 8'b0;
+      MAC_4_mul_itm <= 8'b0;
+      MAC_acc_6_itm <= 8'b0;
+      MAC_acc_itm <= 8'b0;
+    end
+    else begin
+      if ( en ) begin
+        output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({output_rsc_mgc_out_stdreg_d ,
+            (MAC_acc_itm + z_out)}, fsm_output[4]);
+        MAC_4_mul_itm <= MAC_4_mul_itm_1;
+        MAC_acc_6_itm <= z_out;
+        MAC_acc_itm <= MUX_v_8_2_2({MAC_acc_itm , z_out}, fsm_output[2]);
+      end
+    end
+  end
+  assign mux_2_nl = MUX_v_8_2_2({MAC_4_mul_itm , MAC_acc_6_itm}, fsm_output[2]);
+  assign nl_z_out = (mux_2_nl) + MAC_4_mul_itm_1;
+  assign z_out = nl_z_out[7:0];
+
+  function [7:0] MUX_v_8_2_2;
+    input [15:0] inputs;
+    input [0:0] sel;
+    reg [7:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[15:8];
+      end
+      1'b1 : begin
+        result = inputs[7:0];
+      end
+      default : begin
+        result = inputs[15:8];
+      end
+    endcase
+    MUX_v_8_2_2 = result;
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/dot_product.v9/rtl.v.psr b/dot_product/dot_product/dot_product.v9/rtl.v.psr
new file mode 100644
index 0000000..0da3cda
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl.v.psr
@@ -0,0 +1,304 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl.v}} -format verilog
+   setup_design -design=dot_product
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./rtl.v.psr_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'dot_product': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'dot_product': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'dot_product'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'dot_product'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to output_rsc_z(7:0)
+   report_timing -from en -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_a_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_a_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_b_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_b_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock clk] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock en] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'dot_product'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'dot_product'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 mapped.v]
+          puts "-- Writing mapped netlist for 'dot_product' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 gate.v]
+          set gate_sdf [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/dot_product/dot_product/dot_product.v9/rtl.v.psr_timing b/dot_product/dot_product/dot_product.v9/rtl.v.psr_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl.v.psr_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/dot_product/dot_product/dot_product.v9/rtl.v_order.txt b/dot_product/dot_product/dot_product.v9/rtl.v_order.txt
new file mode 100644
index 0000000..cfa6383
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl.v_order.txt
@@ -0,0 +1,3 @@
+./rtl_mgc_ioport.v
+./rtl_mgc_ioport_v2001.v
+./rtl.v
diff --git a/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport.v b/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport_v2001.v b/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/dot_product/dot_product/dot_product.v9/schedule.gnt b/dot_product/dot_product/dot_product.v9/schedule.gnt
new file mode 100644
index 0000000..fe5b44e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/schedule.gnt
@@ -0,0 +1,27 @@
+set a(0-283) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d)#3 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 631 LOC {1 0.0 1 0.0 1 0.0 1 0.0 5 0.615714525} PREDS {} SUCCS {{258 0 0-285 {}} {128 0 0-286 {}} {128 0 0-290 {}} {128 0 0-294 {}} {128 0 0-297 {}}} CYCLES {}}
+set a(0-284) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d)#3 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 632 LOC {1 0.0 1 0.0 1 0.0 1 0.0 5 0.615714525} PREDS {} SUCCS {{259 0 0-285 {}} {128 0 0-287 {}} {128 0 0-291 {}} {128 0 0-295 {}} {128 0 0-298 {}}} CYCLES {}}
+set a(0-285) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-4:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-282 XREFS 633 LOC {1 0.0 1 0.833798775 1 0.833798775 1 0.9999999407433434 5 0.7819156907433434} PREDS {{258 0 0-283 {}} {259 0 0-284 {}}} SUCCS {{258 0 0-289 {}}} CYCLES {}}
+set a(0-286) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d)#4 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 634 LOC {1 0.0 2 0.0 2 0.0 2 0.0 5 0.615714525} PREDS {{128 0 0-283 {}}} SUCCS {{258 0 0-288 {}} {128 0 0-290 {}} {128 0 0-294 {}} {128 0 0-297 {}}} CYCLES {}}
+set a(0-287) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d)#4 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 635 LOC {1 0.0 2 0.0 2 0.0 2 0.0 5 0.615714525} PREDS {{128 0 0-284 {}}} SUCCS {{259 0 0-288 {}} {128 0 0-291 {}} {128 0 0-295 {}} {128 0 0-298 {}}} CYCLES {}}
+set a(0-288) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-5:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-282 XREFS 636 LOC {1 0.0 2 0.761104025 2 0.761104025 2 0.9273051907433434 5 0.7819156907433434} PREDS {{258 0 0-286 {}} {259 0 0-287 {}}} SUCCS {{259 0 0-289 {}}} CYCLES {}}
+set a(0-289) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#6 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-282 XREFS 637 LOC {1 0.16620122499999998 2 0.92730525 2 0.92730525 2 0.9999999527684257 5 0.8546104527684256} PREDS {{258 0 0-285 {}} {259 0 0-288 {}}} SUCCS {{258 0 0-293 {}}} CYCLES {}}
+set a(0-290) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 638 LOC {1 0.0 3 0.0 3 0.0 3 0.0 5 0.6884092749999999} PREDS {{128 0 0-283 {}} {128 0 0-286 {}}} SUCCS {{258 0 0-292 {}} {128 0 0-294 {}} {128 0 0-297 {}}} CYCLES {}}
+set a(0-291) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 639 LOC {1 0.0 3 0.0 3 0.0 3 0.0 5 0.6884092749999999} PREDS {{128 0 0-284 {}} {128 0 0-287 {}}} SUCCS {{259 0 0-292 {}} {128 0 0-295 {}} {128 0 0-298 {}}} CYCLES {}}
+set a(0-292) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-1:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-282 XREFS 640 LOC {1 0.0 3 0.761104025 3 0.761104025 3 0.9273051907433434 5 0.8546104407433434} PREDS {{258 0 0-290 {}} {259 0 0-291 {}}} SUCCS {{259 0 0-293 {}}} CYCLES {}}
+set a(0-293) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-282 XREFS 641 LOC {1 0.23889597499999998 3 0.92730525 3 0.92730525 3 0.9999999527684257 5 0.9273052027684257} PREDS {{258 0 0-289 {}} {259 0 0-292 {}}} SUCCS {{258 0 0-301 {}}} CYCLES {}}
+set a(0-294) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d)#1 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 642 LOC {1 0.0 4 0.0 4 0.0 4 0.0 5 0.6884092749999999} PREDS {{128 0 0-283 {}} {128 0 0-286 {}} {128 0 0-290 {}}} SUCCS {{258 0 0-296 {}} {128 0 0-297 {}}} CYCLES {}}
+set a(0-295) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d)#1 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 643 LOC {1 0.0 4 0.0 4 0.0 4 0.0 5 0.6884092749999999} PREDS {{128 0 0-284 {}} {128 0 0-287 {}} {128 0 0-291 {}}} SUCCS {{259 0 0-296 {}} {128 0 0-298 {}}} CYCLES {}}
+set a(0-296) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-2:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-282 XREFS 644 LOC {1 0.0 4 0.833798775 4 0.833798775 4 0.9999999407433434 5 0.8546104407433434} PREDS {{258 0 0-294 {}} {259 0 0-295 {}}} SUCCS {{258 0 0-300 {}}} CYCLES {}}
+set a(0-297) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d)#2 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 645 LOC {1 0.0 5 0.0 5 0.0 5 0.0 5 0.6884092749999999} PREDS {{128 0 0-283 {}} {128 0 0-286 {}} {128 0 0-290 {}} {128 0 0-294 {}}} SUCCS {{258 0 0-299 {}}} CYCLES {}}
+set a(0-298) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,8) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d)#2 TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-282 XREFS 646 LOC {1 0.0 5 0.0 5 0.0 5 0.0 5 0.6884092749999999} PREDS {{128 0 0-284 {}} {128 0 0-287 {}} {128 0 0-291 {}} {128 0 0-295 {}}} SUCCS {{259 0 0-299 {}}} CYCLES {}}
+set a(0-299) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC-3:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-282 XREFS 647 LOC {1 0.0 5 0.6884092749999999 5 0.6884092749999999 5 0.8546104407433434 5 0.8546104407433434} PREDS {{258 0 0-297 {}} {259 0 0-298 {}}} SUCCS {{259 0 0-300 {}}} CYCLES {}}
+set a(0-300) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC:acc#5 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-282 XREFS 648 LOC {1 0.16620122499999998 5 0.8546104999999999 5 0.8546104999999999 5 0.9273052027684257 5 0.9273052027684257} PREDS {{258 0 0-296 {}} {259 0 0-299 {}}} SUCCS {{259 0 0-301 {}}} CYCLES {}}
+set a(0-301) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 4 NAME MAC-5:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-282 XREFS 649 LOC {1 0.311590725 5 0.92730525 5 0.92730525 5 0.9999999527684257 5 0.9999999527684257} PREDS {{258 0 0-293 {}} {259 0 0-300 {}}} SUCCS {{259 0 0-302 {}}} CYCLES {}}
+set a(0-302) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-282 XREFS 650 LOC {1 1.0 5 1.0 5 1.0 6 0.0 5 0.9999} PREDS {{772 0 0-302 {}} {259 0 0-301 {}}} SUCCS {{772 0 0-302 {}}} CYCLES {}}
+set a(0-282) {CHI {0-283 0-284 0-285 0-286 0-287 0-288 0-289 0-290 0-291 0-292 0-293 0-294 0-295 0-296 0-297 0-298 0-299 0-300 0-301 0-302} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 6 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 6 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 6 TOTAL_CYCLES_IN 6 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 6 NAME main TYPE LOOP DELAY {140.00 ns} PAR {} XREFS 651 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}}
+set a(0-282-TOTALCYCLES) {6}
+set a(0-282-QMOD) {mgc_ioport.mgc_in_wire(1,8) {0-283 0-286 0-290 0-294 0-297} mgc_ioport.mgc_in_wire(2,8) {0-284 0-287 0-291 0-295 0-298} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) {0-285 0-288 0-292 0-296 0-299} mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) {0-289 0-293 0-300 0-301} mgc_ioport.mgc_out_stdreg(3,8) 0-302}
+set a(0-282-PROC_NAME) {core}
+set a(0-282-HIER_NAME) {/dot_product/core}
+set a(TOP) {0-282}
+
diff --git a/dot_product/dot_product/dot_product.v9/schematic.nlv b/dot_product/dot_product/dot_product.v9/schematic.nlv
new file mode 100644
index 0000000..711a446
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/schematic.nlv
@@ -0,0 +1,684 @@
+
+# Program: Catapult University Version
+# Version: 2011a.126
+#    File: Nlview netlist
+
+module new "dot_product:core:fsm" "orig"
+load port {clk} input -attr xrf 825 -attr oid 1 -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/clk}
+load port {en} input -attr xrf 826 -attr oid 2 -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/en}
+load port {arst_n} input -attr xrf 827 -attr oid 3 -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/arst_n}
+load portBus {fsm_output(5:0)} output 6 {fsm_output(5)} {fsm_output(4)} {fsm_output(3)} {fsm_output(2)} {fsm_output(1)} {fsm_output(0)} -attr xrf 828 -attr oid 4 -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {clk} -attr xrf 829 -attr oid 5
+load net {clk} -port {clk} -attr xrf 830 -attr oid 6
+load net {en} -attr xrf 831 -attr oid 7
+load net {en} -port {en} -attr xrf 832 -attr oid 8
+load net {arst_n} -attr xrf 833 -attr oid 9
+load net {arst_n} -port {arst_n} -attr xrf 834 -attr oid 10
+load net {fsm_output(0)} -attr vt d
+load net {fsm_output(1)} -attr vt d
+load net {fsm_output(2)} -attr vt d
+load net {fsm_output(3)} -attr vt d
+load net {fsm_output(4)} -attr vt d
+load net {fsm_output(5)} -attr vt d
+load netBundle {fsm_output} 6 {fsm_output(0)} {fsm_output(1)} {fsm_output(2)} {fsm_output(3)} {fsm_output(4)} {fsm_output(5)} -attr xrf 835 -attr oid 11 -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {fsm_output(0)} -port {fsm_output(0)} -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {fsm_output(1)} -port {fsm_output(1)} -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {fsm_output(2)} -port {fsm_output(2)} -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {fsm_output(3)} -port {fsm_output(3)} -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {fsm_output(4)} -port {fsm_output(4)} -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+load net {fsm_output(5)} -port {fsm_output(5)} -attr vt d -attr @path {/dot_product/dot_product:core/dot_product:core:fsm/fsm_output}
+### END MODULE 
+
+module new "dot_product:core" "orig"
+load port {clk} input -attr xrf 836 -attr oid 12 -attr vt d -attr @path {/dot_product/dot_product:core/clk}
+load port {en} input -attr xrf 837 -attr oid 13 -attr vt d -attr @path {/dot_product/dot_product:core/en}
+load port {arst_n} input -attr xrf 838 -attr oid 14 -attr vt d -attr @path {/dot_product/dot_product:core/arst_n}
+load portBus {input_a:rsc:mgc_in_wire.d(7:0)} input 8 {input_a:rsc:mgc_in_wire.d(7)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(0)} -attr xrf 839 -attr oid 15 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load portBus {input_b:rsc:mgc_in_wire.d(7:0)} input 8 {input_b:rsc:mgc_in_wire.d(7)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(0)} -attr xrf 840 -attr oid 16 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load portBus {output:rsc:mgc_out_stdreg.d(7:0)} output 8 {output:rsc:mgc_out_stdreg.d(7)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(0)} -attr xrf 841 -attr oid 17 -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load symbol "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {a(7:0)} input 8 {a(7)} {a(6)} {a(5)} {a(4)} {a(3)} {a(2)} {a(1)} {a(0)} \
+     portBus {b(7:0)} input 8 {b(7)} {b(6)} {b(5)} {b(4)} {b(3)} {b(2)} {b(1)} {b(0)} \
+     portBus {z(7:0)} output 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "dot_product:core:fsm" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {fsm_output(5:0)} output 6 {fsm_output(5)} {fsm_output(4)} {fsm_output(3)} {fsm_output(2)} {fsm_output(1)} {fsm_output(0)} \
+
+load symbol "add(8,-1,8,-1,8)" "INTERFACE" RTL(+) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mux(2,8)" "INTERFACE" MUX boxcolor 0 \
+     portBus {A0(7:0)} input 8 {A0(7)} {A0(6)} {A0(5)} {A0(4)} {A0(3)} {A0(2)} {A0(1)} {A0(0)} \
+     portBus {A1(7:0)} input 8 {A1(7)} {A1(6)} {A1(5)} {A1(4)} {A1(3)} {A1(2)} {A1(1)} {A1(0)} \
+     portBus {S(0:0)} input.top 1 {S(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "reg(8,1,1,-1,0)" "INTERFACE" GEN boxcolor 1 \
+     portBus {D(7:0)} input 8 {D(7)} {D(6)} {D(5)} {D(4)} {D(3)} {D(2)} {D(1)} {D(0)} \
+     portBus {DRa(7:0)} input 8 {DRa(7)} {DRa(6)} {DRa(5)} {DRa(4)} {DRa(3)} {DRa(2)} {DRa(1)} {DRa(0)} \
+     port {clk} input.clk \
+     portBus {en(0:0)} input 1 {en(0)} \
+     portBus {Ra(0:0)} input 1 {Ra(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load symbol "mul(8,-1,8,-1,8)" "INTERFACE" RTL(*) boxcolor 0 \
+     portBus {A(7:0)} input 8 {A(7)} {A(6)} {A(5)} {A(4)} {A(3)} {A(2)} {A(1)} {A(0)} \
+     portBus {B(7:0)} input 8 {B(7)} {B(6)} {B(5)} {B(4)} {B(3)} {B(2)} {B(1)} {B(0)} \
+     portBus {Z(7:0)} output 8 {Z(7)} {Z(6)} {Z(5)} {Z(4)} {Z(3)} {Z(2)} {Z(1)} {Z(0)} \
+
+load net {MAC-4:mul.itm(0)} -attr vt d
+load net {MAC-4:mul.itm(1)} -attr vt d
+load net {MAC-4:mul.itm(2)} -attr vt d
+load net {MAC-4:mul.itm(3)} -attr vt d
+load net {MAC-4:mul.itm(4)} -attr vt d
+load net {MAC-4:mul.itm(5)} -attr vt d
+load net {MAC-4:mul.itm(6)} -attr vt d
+load net {MAC-4:mul.itm(7)} -attr vt d
+load netBundle {MAC-4:mul.itm} 8 {MAC-4:mul.itm(0)} {MAC-4:mul.itm(1)} {MAC-4:mul.itm(2)} {MAC-4:mul.itm(3)} {MAC-4:mul.itm(4)} {MAC-4:mul.itm(5)} {MAC-4:mul.itm(6)} {MAC-4:mul.itm(7)} -attr xrf 842 -attr oid 18 -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC:acc#6.itm(0)} -attr vt d
+load net {MAC:acc#6.itm(1)} -attr vt d
+load net {MAC:acc#6.itm(2)} -attr vt d
+load net {MAC:acc#6.itm(3)} -attr vt d
+load net {MAC:acc#6.itm(4)} -attr vt d
+load net {MAC:acc#6.itm(5)} -attr vt d
+load net {MAC:acc#6.itm(6)} -attr vt d
+load net {MAC:acc#6.itm(7)} -attr vt d
+load netBundle {MAC:acc#6.itm} 8 {MAC:acc#6.itm(0)} {MAC:acc#6.itm(1)} {MAC:acc#6.itm(2)} {MAC:acc#6.itm(3)} {MAC:acc#6.itm(4)} {MAC:acc#6.itm(5)} {MAC:acc#6.itm(6)} {MAC:acc#6.itm(7)} -attr xrf 843 -attr oid 19 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc.itm(0)} -attr vt d
+load net {MAC:acc.itm(1)} -attr vt d
+load net {MAC:acc.itm(2)} -attr vt d
+load net {MAC:acc.itm(3)} -attr vt d
+load net {MAC:acc.itm(4)} -attr vt d
+load net {MAC:acc.itm(5)} -attr vt d
+load net {MAC:acc.itm(6)} -attr vt d
+load net {MAC:acc.itm(7)} -attr vt d
+load netBundle {MAC:acc.itm} 8 {MAC:acc.itm(0)} {MAC:acc.itm(1)} {MAC:acc.itm(2)} {MAC:acc.itm(3)} {MAC:acc.itm(4)} {MAC:acc.itm(5)} {MAC:acc.itm(6)} {MAC:acc.itm(7)} -attr xrf 844 -attr oid 20 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {z.out(0)} -attr vt d
+load net {z.out(1)} -attr vt d
+load net {z.out(2)} -attr vt d
+load net {z.out(3)} -attr vt d
+load net {z.out(4)} -attr vt d
+load net {z.out(5)} -attr vt d
+load net {z.out(6)} -attr vt d
+load net {z.out(7)} -attr vt d
+load netBundle {z.out} 8 {z.out(0)} {z.out(1)} {z.out(2)} {z.out(3)} {z.out(4)} {z.out(5)} {z.out(6)} {z.out(7)} -attr xrf 845 -attr oid 21 -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {MAC-4:mul.itm#1(0)} -attr vt d
+load net {MAC-4:mul.itm#1(1)} -attr vt d
+load net {MAC-4:mul.itm#1(2)} -attr vt d
+load net {MAC-4:mul.itm#1(3)} -attr vt d
+load net {MAC-4:mul.itm#1(4)} -attr vt d
+load net {MAC-4:mul.itm#1(5)} -attr vt d
+load net {MAC-4:mul.itm#1(6)} -attr vt d
+load net {MAC-4:mul.itm#1(7)} -attr vt d
+load netBundle {MAC-4:mul.itm#1} 8 {MAC-4:mul.itm#1(0)} {MAC-4:mul.itm#1(1)} {MAC-4:mul.itm#1(2)} {MAC-4:mul.itm#1(3)} {MAC-4:mul.itm#1(4)} {MAC-4:mul.itm#1(5)} {MAC-4:mul.itm#1(6)} {MAC-4:mul.itm#1(7)} -attr xrf 846 -attr oid 22 -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {mux.itm(0)} -attr vt d
+load net {mux.itm(1)} -attr vt d
+load net {mux.itm(2)} -attr vt d
+load net {mux.itm(3)} -attr vt d
+load net {mux.itm(4)} -attr vt d
+load net {mux.itm(5)} -attr vt d
+load net {mux.itm(6)} -attr vt d
+load net {mux.itm(7)} -attr vt d
+load netBundle {mux.itm} 8 {mux.itm(0)} {mux.itm(1)} {mux.itm(2)} {mux.itm(3)} {mux.itm(4)} {mux.itm(5)} {mux.itm(6)} {mux.itm(7)} -attr xrf 847 -attr oid 23 -attr vt d -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {MAC-5:acc#3.itm(0)} -attr vt d
+load net {MAC-5:acc#3.itm(1)} -attr vt d
+load net {MAC-5:acc#3.itm(2)} -attr vt d
+load net {MAC-5:acc#3.itm(3)} -attr vt d
+load net {MAC-5:acc#3.itm(4)} -attr vt d
+load net {MAC-5:acc#3.itm(5)} -attr vt d
+load net {MAC-5:acc#3.itm(6)} -attr vt d
+load net {MAC-5:acc#3.itm(7)} -attr vt d
+load netBundle {MAC-5:acc#3.itm} 8 {MAC-5:acc#3.itm(0)} {MAC-5:acc#3.itm(1)} {MAC-5:acc#3.itm(2)} {MAC-5:acc#3.itm(3)} {MAC-5:acc#3.itm(4)} {MAC-5:acc#3.itm(5)} {MAC-5:acc#3.itm(6)} {MAC-5:acc#3.itm(7)} -attr xrf 848 -attr oid 24 -attr vt d -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {mux#1.itm(0)} -attr vt d
+load net {mux#1.itm(1)} -attr vt d
+load net {mux#1.itm(2)} -attr vt d
+load net {mux#1.itm(3)} -attr vt d
+load net {mux#1.itm(4)} -attr vt d
+load net {mux#1.itm(5)} -attr vt d
+load net {mux#1.itm(6)} -attr vt d
+load net {mux#1.itm(7)} -attr vt d
+load netBundle {mux#1.itm} 8 {mux#1.itm(0)} {mux#1.itm(1)} {mux#1.itm(2)} {mux#1.itm(3)} {mux#1.itm(4)} {mux#1.itm(5)} {mux#1.itm(6)} {mux#1.itm(7)} -attr xrf 849 -attr oid 25 -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#2.itm(0)} -attr vt d
+load net {mux#2.itm(1)} -attr vt d
+load net {mux#2.itm(2)} -attr vt d
+load net {mux#2.itm(3)} -attr vt d
+load net {mux#2.itm(4)} -attr vt d
+load net {mux#2.itm(5)} -attr vt d
+load net {mux#2.itm(6)} -attr vt d
+load net {mux#2.itm(7)} -attr vt d
+load netBundle {mux#2.itm} 8 {mux#2.itm(0)} {mux#2.itm(1)} {mux#2.itm(2)} {mux#2.itm(3)} {mux#2.itm(4)} {mux#2.itm(5)} {mux#2.itm(6)} {mux#2.itm(7)} -attr xrf 850 -attr oid 26 -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {clk} -attr xrf 851 -attr oid 27
+load net {clk} -port {clk} -attr xrf 852 -attr oid 28
+load net {en} -attr xrf 853 -attr oid 29
+load net {en} -port {en} -attr xrf 854 -attr oid 30
+load net {arst_n} -attr xrf 855 -attr oid 31
+load net {arst_n} -port {arst_n} -attr xrf 856 -attr oid 32
+load net {input_a:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_a:rsc:mgc_in_wire.d} 8 {input_a:rsc:mgc_in_wire.d(0)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(7)} -attr xrf 857 -attr oid 33 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(0)} -port {input_a:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(1)} -port {input_a:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(2)} -port {input_a:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(3)} -port {input_a:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(4)} -port {input_a:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(5)} -port {input_a:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(6)} -port {input_a:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d(7)} -port {input_a:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_a:rsc:mgc_in_wire.d} 8 {input_a:rsc:mgc_in_wire.d(0)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(7)} -attr xrf 858 -attr oid 34 -attr vt d -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_b:rsc:mgc_in_wire.d} 8 {input_b:rsc:mgc_in_wire.d(0)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(7)} -attr xrf 859 -attr oid 35 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(0)} -port {input_b:rsc:mgc_in_wire.d(0)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(1)} -port {input_b:rsc:mgc_in_wire.d(1)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(2)} -port {input_b:rsc:mgc_in_wire.d(2)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(3)} -port {input_b:rsc:mgc_in_wire.d(3)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(4)} -port {input_b:rsc:mgc_in_wire.d(4)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(5)} -port {input_b:rsc:mgc_in_wire.d(5)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(6)} -port {input_b:rsc:mgc_in_wire.d(6)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d(7)} -port {input_b:rsc:mgc_in_wire.d(7)} -attr vt d
+load netBundle {input_b:rsc:mgc_in_wire.d} 8 {input_b:rsc:mgc_in_wire.d(0)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(7)} -attr xrf 860 -attr oid 36 -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {output:rsc:mgc_out_stdreg.d(0)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(1)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(2)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(3)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(4)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(5)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(6)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d(7)} -attr vt d
+load netBundle {output:rsc:mgc_out_stdreg.d} 8 {output:rsc:mgc_out_stdreg.d(0)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(7)} -attr xrf 861 -attr oid 37 -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(0)} -port {output:rsc:mgc_out_stdreg.d(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(1)} -port {output:rsc:mgc_out_stdreg.d(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(2)} -port {output:rsc:mgc_out_stdreg.d(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(3)} -port {output:rsc:mgc_out_stdreg.d(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(4)} -port {output:rsc:mgc_out_stdreg.d(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(5)} -port {output:rsc:mgc_out_stdreg.d(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(6)} -port {output:rsc:mgc_out_stdreg.d(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(7)} -port {output:rsc:mgc_out_stdreg.d(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load inst "dot_product:core:fsm:inst" "dot_product:core:fsm" "orig" -attr xrf 862 -attr oid 38 -attr @path {/dot_product/dot_product:core/dot_product:core:fsm:inst} -attr area 0.001000 -attr hier "/dot_product/dot_product:core/dot_product:core:fsm" -pg 1 -lvl 3
+load net {clk} -pin  "dot_product:core:fsm:inst" {clk#1} -attr xrf 863 -attr oid 39 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "dot_product:core:fsm:inst" {en#1} -attr xrf 864 -attr oid 40 -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "dot_product:core:fsm:inst" {arst_n#1} -attr xrf 865 -attr oid 41 -attr @path {/dot_product/dot_product:core/arst_n}
+load net {fsm_output#1(0)} -pin  "dot_product:core:fsm:inst" {fsm_output(0)} -attr @path {/dot_product/dot_product:core/fsm_output}
+load net {fsm_output#1(1)} -pin  "dot_product:core:fsm:inst" {fsm_output(1)} -attr @path {/dot_product/dot_product:core/fsm_output}
+load net {fsm_output#1(2)} -pin  "dot_product:core:fsm:inst" {fsm_output(2)} -attr @path {/dot_product/dot_product:core/fsm_output}
+load net {fsm_output#1(3)} -pin  "dot_product:core:fsm:inst" {fsm_output(3)} -attr @path {/dot_product/dot_product:core/fsm_output}
+load net {fsm_output#1(4)} -pin  "dot_product:core:fsm:inst" {fsm_output(4)} -attr @path {/dot_product/dot_product:core/fsm_output}
+load net {fsm_output#1(5)} -pin  "dot_product:core:fsm:inst" {fsm_output(5)} -attr @path {/dot_product/dot_product:core/fsm_output}
+load inst "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)" "INTERFACE" -attr xrf 866 -attr oid 42 -attr vt d -attr @path {/dot_product/dot_product:core/MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)"
+load net {mux#2.itm(0)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(0)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(1)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(1)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(2)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(2)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(3)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(3)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(4)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(4)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(5)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(5)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(6)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(6)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(7)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {a(7)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {MAC-4:mul.itm#1(0)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(1)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(2)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(3)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(4)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(5)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(6)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(7)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {b(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {z.out(0)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(1)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(2)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(3)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(4)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(5)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(6)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(7)} -pin  "MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8_0_8_0_8)" {z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load inst "MAC-5:acc#3" "add(8,-1,8,-1,8)" "INTERFACE" -attr xrf 867 -attr oid 43 -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3} -attr area 9.258614 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8)"
+load net {MAC:acc.itm(0)} -pin  "MAC-5:acc#3" {A(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(1)} -pin  "MAC-5:acc#3" {A(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(2)} -pin  "MAC-5:acc#3" {A(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(3)} -pin  "MAC-5:acc#3" {A(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(4)} -pin  "MAC-5:acc#3" {A(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(5)} -pin  "MAC-5:acc#3" {A(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(6)} -pin  "MAC-5:acc#3" {A(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(7)} -pin  "MAC-5:acc#3" {A(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {z.out(0)} -pin  "MAC-5:acc#3" {B(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(1)} -pin  "MAC-5:acc#3" {B(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(2)} -pin  "MAC-5:acc#3" {B(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(3)} -pin  "MAC-5:acc#3" {B(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(4)} -pin  "MAC-5:acc#3" {B(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(5)} -pin  "MAC-5:acc#3" {B(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(6)} -pin  "MAC-5:acc#3" {B(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(7)} -pin  "MAC-5:acc#3" {B(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/z.out}
+load net {MAC-5:acc#3.itm(0)} -pin  "MAC-5:acc#3" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(1)} -pin  "MAC-5:acc#3" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(2)} -pin  "MAC-5:acc#3" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(3)} -pin  "MAC-5:acc#3" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(4)} -pin  "MAC-5:acc#3" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(5)} -pin  "MAC-5:acc#3" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(6)} -pin  "MAC-5:acc#3" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(7)} -pin  "MAC-5:acc#3" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load inst "mux" "mux(2,8)" "INTERFACE" -attr xrf 868 -attr oid 44 -attr vt dc -attr @path {/dot_product/dot_product:core/mux} -attr area 7.356384 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,1,2)"
+load net {MAC-5:acc#3.itm(0)} -pin  "mux" {A0(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(1)} -pin  "mux" {A0(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(2)} -pin  "mux" {A0(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(3)} -pin  "mux" {A0(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(4)} -pin  "mux" {A0(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(5)} -pin  "mux" {A0(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(6)} -pin  "mux" {A0(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {MAC-5:acc#3.itm(7)} -pin  "mux" {A0(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-5:acc#3.itm}
+load net {output:rsc:mgc_out_stdreg.d(0)} -pin  "mux" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(1)} -pin  "mux" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(2)} -pin  "mux" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(3)} -pin  "mux" {A1(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(4)} -pin  "mux" {A1(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(5)} -pin  "mux" {A1(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(6)} -pin  "mux" {A1(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(7)} -pin  "mux" {A1(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {fsm_output#1(4)} -pin  "mux" {S(0)} -attr @path {/dot_product/dot_product:core/slc(fsm_output)#4.itm}
+load net {mux.itm(0)} -pin  "mux" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(1)} -pin  "mux" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(2)} -pin  "mux" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(3)} -pin  "mux" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(4)} -pin  "mux" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(5)} -pin  "mux" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(6)} -pin  "mux" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(7)} -pin  "mux" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load inst "reg(output:rsc:mgc_out_stdreg.d)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 869 -attr oid 45 -attr vt dc -attr @path {/dot_product/dot_product:core/reg(output:rsc:mgc_out_stdreg.d)}
+load net {mux.itm(0)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(1)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(2)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(3)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(4)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(5)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(6)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {mux.itm(7)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {D(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/mux.itm}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {clk} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {clk} -attr xrf 870 -attr oid 46 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {output:rsc:mgc_out_stdreg.d(0)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(1)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(2)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(3)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(4)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(5)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(6)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d(7)} -pin  "reg(output:rsc:mgc_out_stdreg.d)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/output:rsc:mgc_out_stdreg.d}
+load inst "reg(MAC-4:mul.itm)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 871 -attr oid 47 -attr vt d -attr @path {/dot_product/dot_product:core/reg(MAC-4:mul.itm)}
+load net {MAC-4:mul.itm#1(0)} -pin  "reg(MAC-4:mul.itm)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(1)} -pin  "reg(MAC-4:mul.itm)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(2)} -pin  "reg(MAC-4:mul.itm)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(3)} -pin  "reg(MAC-4:mul.itm)" {D(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(4)} -pin  "reg(MAC-4:mul.itm)" {D(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(5)} -pin  "reg(MAC-4:mul.itm)" {D(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(6)} -pin  "reg(MAC-4:mul.itm)" {D(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(7)} -pin  "reg(MAC-4:mul.itm)" {D(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC-4:mul.itm)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {clk} -pin  "reg(MAC-4:mul.itm)" {clk} -attr xrf 872 -attr oid 48 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(MAC-4:mul.itm)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(MAC-4:mul.itm)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {MAC-4:mul.itm(0)} -pin  "reg(MAC-4:mul.itm)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(1)} -pin  "reg(MAC-4:mul.itm)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(2)} -pin  "reg(MAC-4:mul.itm)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(3)} -pin  "reg(MAC-4:mul.itm)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(4)} -pin  "reg(MAC-4:mul.itm)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(5)} -pin  "reg(MAC-4:mul.itm)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(6)} -pin  "reg(MAC-4:mul.itm)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(7)} -pin  "reg(MAC-4:mul.itm)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load inst "reg(MAC:acc#6.itm)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 873 -attr oid 49 -attr vt d -attr @path {/dot_product/dot_product:core/reg(MAC:acc#6.itm)}
+load net {z.out(0)} -pin  "reg(MAC:acc#6.itm)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(1)} -pin  "reg(MAC:acc#6.itm)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(2)} -pin  "reg(MAC:acc#6.itm)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(3)} -pin  "reg(MAC:acc#6.itm)" {D(3)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(4)} -pin  "reg(MAC:acc#6.itm)" {D(4)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(5)} -pin  "reg(MAC:acc#6.itm)" {D(5)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(6)} -pin  "reg(MAC:acc#6.itm)" {D(6)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(7)} -pin  "reg(MAC:acc#6.itm)" {D(7)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc#6.itm)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {clk} -pin  "reg(MAC:acc#6.itm)" {clk} -attr xrf 874 -attr oid 50 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(MAC:acc#6.itm)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(MAC:acc#6.itm)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {MAC:acc#6.itm(0)} -pin  "reg(MAC:acc#6.itm)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(1)} -pin  "reg(MAC:acc#6.itm)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(2)} -pin  "reg(MAC:acc#6.itm)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(3)} -pin  "reg(MAC:acc#6.itm)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(4)} -pin  "reg(MAC:acc#6.itm)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(5)} -pin  "reg(MAC:acc#6.itm)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(6)} -pin  "reg(MAC:acc#6.itm)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(7)} -pin  "reg(MAC:acc#6.itm)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load inst "mux#1" "mux(2,8)" "INTERFACE" -attr xrf 875 -attr oid 51 -attr vt d -attr @path {/dot_product/dot_product:core/mux#1} -attr area 7.356384 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,1,2)"
+load net {z.out(0)} -pin  "mux#1" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(1)} -pin  "mux#1" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(2)} -pin  "mux#1" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(3)} -pin  "mux#1" {A0(3)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(4)} -pin  "mux#1" {A0(4)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(5)} -pin  "mux#1" {A0(5)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(6)} -pin  "mux#1" {A0(6)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {z.out(7)} -pin  "mux#1" {A0(7)} -attr vt d -attr @path {/dot_product/dot_product:core/z.out}
+load net {MAC:acc.itm(0)} -pin  "mux#1" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(1)} -pin  "mux#1" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(2)} -pin  "mux#1" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(3)} -pin  "mux#1" {A1(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(4)} -pin  "mux#1" {A1(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(5)} -pin  "mux#1" {A1(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(6)} -pin  "mux#1" {A1(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(7)} -pin  "mux#1" {A1(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {fsm_output#1(2)} -pin  "mux#1" {S(0)} -attr @path {/dot_product/dot_product:core/slc(fsm_output)#6.itm}
+load net {mux#1.itm(0)} -pin  "mux#1" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "mux#1" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(2)} -pin  "mux#1" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(3)} -pin  "mux#1" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(4)} -pin  "mux#1" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(5)} -pin  "mux#1" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(6)} -pin  "mux#1" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(7)} -pin  "mux#1" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load inst "reg(MAC:acc.itm)" "reg(8,1,1,-1,0)" "INTERFACE" -attr xrf 876 -attr oid 52 -attr vt d -attr @path {/dot_product/dot_product:core/reg(MAC:acc.itm)}
+load net {mux#1.itm(0)} -pin  "reg(MAC:acc.itm)" {D(0)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(1)} -pin  "reg(MAC:acc.itm)" {D(1)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(2)} -pin  "reg(MAC:acc.itm)" {D(2)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(3)} -pin  "reg(MAC:acc.itm)" {D(3)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(4)} -pin  "reg(MAC:acc.itm)" {D(4)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(5)} -pin  "reg(MAC:acc.itm)" {D(5)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(6)} -pin  "reg(MAC:acc.itm)" {D(6)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {mux#1.itm(7)} -pin  "reg(MAC:acc.itm)" {D(7)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#1.itm}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(0)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(1)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(2)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(3)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(4)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(5)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(6)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {GND} -pin  "reg(MAC:acc.itm)" {DRa(7)} -attr @path {/dot_product/dot_product:core/C0_8}
+load net {clk} -pin  "reg(MAC:acc.itm)" {clk} -attr xrf 877 -attr oid 53 -attr @path {/dot_product/dot_product:core/clk}
+load net {en} -pin  "reg(MAC:acc.itm)" {en(0)} -attr @path {/dot_product/dot_product:core/en}
+load net {arst_n} -pin  "reg(MAC:acc.itm)" {Ra(0)} -attr @path {/dot_product/dot_product:core/arst_n}
+load net {MAC:acc.itm(0)} -pin  "reg(MAC:acc.itm)" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(1)} -pin  "reg(MAC:acc.itm)" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(2)} -pin  "reg(MAC:acc.itm)" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(3)} -pin  "reg(MAC:acc.itm)" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(4)} -pin  "reg(MAC:acc.itm)" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(5)} -pin  "reg(MAC:acc.itm)" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(6)} -pin  "reg(MAC:acc.itm)" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load net {MAC:acc.itm(7)} -pin  "reg(MAC:acc.itm)" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc.itm}
+load inst "MAC-4:mul" "mul(8,-1,8,-1,8)" "INTERFACE" -attr xrf 878 -attr oid 54 -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul} -attr area 330.249922 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8)"
+load net {input_a:rsc:mgc_in_wire.d(0)} -pin  "MAC-4:mul" {A(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(1)} -pin  "MAC-4:mul" {A(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(2)} -pin  "MAC-4:mul" {A(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(3)} -pin  "MAC-4:mul" {A(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(4)} -pin  "MAC-4:mul" {A(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(5)} -pin  "MAC-4:mul" {A(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(6)} -pin  "MAC-4:mul" {A(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d(7)} -pin  "MAC-4:mul" {A(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(0)} -pin  "MAC-4:mul" {B(0)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(1)} -pin  "MAC-4:mul" {B(1)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(2)} -pin  "MAC-4:mul" {B(2)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(3)} -pin  "MAC-4:mul" {B(3)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(4)} -pin  "MAC-4:mul" {B(4)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(5)} -pin  "MAC-4:mul" {B(5)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(6)} -pin  "MAC-4:mul" {B(6)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d(7)} -pin  "MAC-4:mul" {B(7)} -attr vt d -attr @path {/dot_product/dot_product:core/input_b:rsc:mgc_in_wire.d}
+load net {MAC-4:mul.itm#1(0)} -pin  "MAC-4:mul" {Z(0)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(1)} -pin  "MAC-4:mul" {Z(1)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(2)} -pin  "MAC-4:mul" {Z(2)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(3)} -pin  "MAC-4:mul" {Z(3)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(4)} -pin  "MAC-4:mul" {Z(4)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(5)} -pin  "MAC-4:mul" {Z(5)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(6)} -pin  "MAC-4:mul" {Z(6)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load net {MAC-4:mul.itm#1(7)} -pin  "MAC-4:mul" {Z(7)} -attr vt dc -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm#1}
+load inst "mux#2" "mux(2,8)" "INTERFACE" -attr xrf 879 -attr oid 55 -attr vt d -attr @path {/dot_product/dot_product:core/mux#2} -attr area 7.356384 -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,1,2)"
+load net {MAC:acc#6.itm(0)} -pin  "mux#2" {A0(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(1)} -pin  "mux#2" {A0(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(2)} -pin  "mux#2" {A0(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(3)} -pin  "mux#2" {A0(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(4)} -pin  "mux#2" {A0(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(5)} -pin  "mux#2" {A0(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(6)} -pin  "mux#2" {A0(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC:acc#6.itm(7)} -pin  "mux#2" {A0(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC:acc#6.itm}
+load net {MAC-4:mul.itm(0)} -pin  "mux#2" {A1(0)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(1)} -pin  "mux#2" {A1(1)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(2)} -pin  "mux#2" {A1(2)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(3)} -pin  "mux#2" {A1(3)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(4)} -pin  "mux#2" {A1(4)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(5)} -pin  "mux#2" {A1(5)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(6)} -pin  "mux#2" {A1(6)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {MAC-4:mul.itm(7)} -pin  "mux#2" {A1(7)} -attr vt d -attr @path {/dot_product/dot_product:core/MAC-4:mul.itm}
+load net {fsm_output#1(2)} -pin  "mux#2" {S(0)} -attr @path {/dot_product/dot_product:core/slc(fsm_output)#2.itm}
+load net {mux#2.itm(0)} -pin  "mux#2" {Z(0)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(1)} -pin  "mux#2" {Z(1)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(2)} -pin  "mux#2" {Z(2)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(3)} -pin  "mux#2" {Z(3)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(4)} -pin  "mux#2" {Z(4)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(5)} -pin  "mux#2" {Z(5)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(6)} -pin  "mux#2" {Z(6)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+load net {mux#2.itm(7)} -pin  "mux#2" {Z(7)} -attr vt d -attr @path {/dot_product/dot_product:core/mux#2.itm}
+### END MODULE 
+
+module new "dot_product" "orig"
+load portBus {input_a:rsc.z(7:0)} input 8 {input_a:rsc.z(7)} {input_a:rsc.z(6)} {input_a:rsc.z(5)} {input_a:rsc.z(4)} {input_a:rsc.z(3)} {input_a:rsc.z(2)} {input_a:rsc.z(1)} {input_a:rsc.z(0)} -attr xrf 880 -attr oid 56 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load portBus {input_b:rsc.z(7:0)} input 8 {input_b:rsc.z(7)} {input_b:rsc.z(6)} {input_b:rsc.z(5)} {input_b:rsc.z(4)} {input_b:rsc.z(3)} {input_b:rsc.z(2)} {input_b:rsc.z(1)} {input_b:rsc.z(0)} -attr xrf 881 -attr oid 57 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load portBus {output:rsc.z(7:0)} output 8 {output:rsc.z(7)} {output:rsc.z(6)} {output:rsc.z(5)} {output:rsc.z(4)} {output:rsc.z(3)} {output:rsc.z(2)} {output:rsc.z(1)} {output:rsc.z(0)} -attr xrf 882 -attr oid 58 -attr vt d -attr @path {/dot_product/output:rsc.z}
+load port {clk} input -attr xrf 883 -attr oid 59 -attr vt d -attr @path {/dot_product/clk}
+load port {en} input -attr xrf 884 -attr oid 60 -attr vt d -attr @path {/dot_product/en}
+load port {arst_n} input -attr xrf 885 -attr oid 61 -attr vt d -attr @path {/dot_product/arst_n}
+load symbol "mgc_ioport.mgc_in_wire(1,8)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(7:0)} output 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(7:0)} input 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_in_wire(2,8)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(7:0)} output 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(7:0)} input 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "mgc_ioport.mgc_out_stdreg(3,8)" "INTERFACE" GEN boxcolor 0 \
+     portBus {d(7:0)} input 8 {d(7)} {d(6)} {d(5)} {d(4)} {d(3)} {d(2)} {d(1)} {d(0)} \
+     portBus {z(7:0)} output 8 {z(7)} {z(6)} {z(5)} {z(4)} {z(3)} {z(2)} {z(1)} {z(0)} \
+
+load symbol "dot_product:core" "orig" GEN \
+     port {clk#1} input \
+     port {en#1} input \
+     port {arst_n#1} input \
+     portBus {input_a:rsc:mgc_in_wire.d(7:0)} input 8 {input_a:rsc:mgc_in_wire.d(7)} {input_a:rsc:mgc_in_wire.d(6)} {input_a:rsc:mgc_in_wire.d(5)} {input_a:rsc:mgc_in_wire.d(4)} {input_a:rsc:mgc_in_wire.d(3)} {input_a:rsc:mgc_in_wire.d(2)} {input_a:rsc:mgc_in_wire.d(1)} {input_a:rsc:mgc_in_wire.d(0)} \
+     portBus {input_b:rsc:mgc_in_wire.d(7:0)} input 8 {input_b:rsc:mgc_in_wire.d(7)} {input_b:rsc:mgc_in_wire.d(6)} {input_b:rsc:mgc_in_wire.d(5)} {input_b:rsc:mgc_in_wire.d(4)} {input_b:rsc:mgc_in_wire.d(3)} {input_b:rsc:mgc_in_wire.d(2)} {input_b:rsc:mgc_in_wire.d(1)} {input_b:rsc:mgc_in_wire.d(0)} \
+     portBus {output:rsc:mgc_out_stdreg.d(7:0)} output 8 {output:rsc:mgc_out_stdreg.d(7)} {output:rsc:mgc_out_stdreg.d(6)} {output:rsc:mgc_out_stdreg.d(5)} {output:rsc:mgc_out_stdreg.d(4)} {output:rsc:mgc_out_stdreg.d(3)} {output:rsc:mgc_out_stdreg.d(2)} {output:rsc:mgc_out_stdreg.d(1)} {output:rsc:mgc_out_stdreg.d(0)} \
+
+load net {input_a:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {input_a:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load netBundle {input_a:rsc:mgc_in_wire.d#1} 8 {input_a:rsc:mgc_in_wire.d#1(0)} {input_a:rsc:mgc_in_wire.d#1(1)} {input_a:rsc:mgc_in_wire.d#1(2)} {input_a:rsc:mgc_in_wire.d#1(3)} {input_a:rsc:mgc_in_wire.d#1(4)} {input_a:rsc:mgc_in_wire.d#1(5)} {input_a:rsc:mgc_in_wire.d#1(6)} {input_a:rsc:mgc_in_wire.d#1(7)} -attr xrf 886 -attr oid 62 -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(0)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(1)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(2)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(3)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(4)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(5)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(6)} -attr vt d
+load net {input_b:rsc:mgc_in_wire.d#1(7)} -attr vt d
+load netBundle {input_b:rsc:mgc_in_wire.d#1} 8 {input_b:rsc:mgc_in_wire.d#1(0)} {input_b:rsc:mgc_in_wire.d#1(1)} {input_b:rsc:mgc_in_wire.d#1(2)} {input_b:rsc:mgc_in_wire.d#1(3)} {input_b:rsc:mgc_in_wire.d#1(4)} {input_b:rsc:mgc_in_wire.d#1(5)} {input_b:rsc:mgc_in_wire.d#1(6)} {input_b:rsc:mgc_in_wire.d#1(7)} -attr xrf 887 -attr oid 63 -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {output:rsc:mgc_out_stdreg.d#1(0)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(1)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(2)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(3)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(4)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(5)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(6)} -attr vt d
+load net {output:rsc:mgc_out_stdreg.d#1(7)} -attr vt d
+load netBundle {output:rsc:mgc_out_stdreg.d#1} 8 {output:rsc:mgc_out_stdreg.d#1(0)} {output:rsc:mgc_out_stdreg.d#1(1)} {output:rsc:mgc_out_stdreg.d#1(2)} {output:rsc:mgc_out_stdreg.d#1(3)} {output:rsc:mgc_out_stdreg.d#1(4)} {output:rsc:mgc_out_stdreg.d#1(5)} {output:rsc:mgc_out_stdreg.d#1(6)} {output:rsc:mgc_out_stdreg.d#1(7)} -attr xrf 888 -attr oid 64 -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {input_a:rsc.z(0)} -attr vt d
+load net {input_a:rsc.z(1)} -attr vt d
+load net {input_a:rsc.z(2)} -attr vt d
+load net {input_a:rsc.z(3)} -attr vt d
+load net {input_a:rsc.z(4)} -attr vt d
+load net {input_a:rsc.z(5)} -attr vt d
+load net {input_a:rsc.z(6)} -attr vt d
+load net {input_a:rsc.z(7)} -attr vt d
+load netBundle {input_a:rsc.z} 8 {input_a:rsc.z(0)} {input_a:rsc.z(1)} {input_a:rsc.z(2)} {input_a:rsc.z(3)} {input_a:rsc.z(4)} {input_a:rsc.z(5)} {input_a:rsc.z(6)} {input_a:rsc.z(7)} -attr xrf 889 -attr oid 65 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(0)} -port {input_a:rsc.z(0)} -attr vt d
+load net {input_a:rsc.z(1)} -port {input_a:rsc.z(1)} -attr vt d
+load net {input_a:rsc.z(2)} -port {input_a:rsc.z(2)} -attr vt d
+load net {input_a:rsc.z(3)} -port {input_a:rsc.z(3)} -attr vt d
+load net {input_a:rsc.z(4)} -port {input_a:rsc.z(4)} -attr vt d
+load net {input_a:rsc.z(5)} -port {input_a:rsc.z(5)} -attr vt d
+load net {input_a:rsc.z(6)} -port {input_a:rsc.z(6)} -attr vt d
+load net {input_a:rsc.z(7)} -port {input_a:rsc.z(7)} -attr vt d
+load netBundle {input_a:rsc.z} 8 {input_a:rsc.z(0)} {input_a:rsc.z(1)} {input_a:rsc.z(2)} {input_a:rsc.z(3)} {input_a:rsc.z(4)} {input_a:rsc.z(5)} {input_a:rsc.z(6)} {input_a:rsc.z(7)} -attr xrf 890 -attr oid 66 -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_b:rsc.z(0)} -attr vt d
+load net {input_b:rsc.z(1)} -attr vt d
+load net {input_b:rsc.z(2)} -attr vt d
+load net {input_b:rsc.z(3)} -attr vt d
+load net {input_b:rsc.z(4)} -attr vt d
+load net {input_b:rsc.z(5)} -attr vt d
+load net {input_b:rsc.z(6)} -attr vt d
+load net {input_b:rsc.z(7)} -attr vt d
+load netBundle {input_b:rsc.z} 8 {input_b:rsc.z(0)} {input_b:rsc.z(1)} {input_b:rsc.z(2)} {input_b:rsc.z(3)} {input_b:rsc.z(4)} {input_b:rsc.z(5)} {input_b:rsc.z(6)} {input_b:rsc.z(7)} -attr xrf 891 -attr oid 67 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(0)} -port {input_b:rsc.z(0)} -attr vt d
+load net {input_b:rsc.z(1)} -port {input_b:rsc.z(1)} -attr vt d
+load net {input_b:rsc.z(2)} -port {input_b:rsc.z(2)} -attr vt d
+load net {input_b:rsc.z(3)} -port {input_b:rsc.z(3)} -attr vt d
+load net {input_b:rsc.z(4)} -port {input_b:rsc.z(4)} -attr vt d
+load net {input_b:rsc.z(5)} -port {input_b:rsc.z(5)} -attr vt d
+load net {input_b:rsc.z(6)} -port {input_b:rsc.z(6)} -attr vt d
+load net {input_b:rsc.z(7)} -port {input_b:rsc.z(7)} -attr vt d
+load netBundle {input_b:rsc.z} 8 {input_b:rsc.z(0)} {input_b:rsc.z(1)} {input_b:rsc.z(2)} {input_b:rsc.z(3)} {input_b:rsc.z(4)} {input_b:rsc.z(5)} {input_b:rsc.z(6)} {input_b:rsc.z(7)} -attr xrf 892 -attr oid 68 -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {output:rsc.z(0)} -attr vt d
+load net {output:rsc.z(1)} -attr vt d
+load net {output:rsc.z(2)} -attr vt d
+load net {output:rsc.z(3)} -attr vt d
+load net {output:rsc.z(4)} -attr vt d
+load net {output:rsc.z(5)} -attr vt d
+load net {output:rsc.z(6)} -attr vt d
+load net {output:rsc.z(7)} -attr vt d
+load netBundle {output:rsc.z} 8 {output:rsc.z(0)} {output:rsc.z(1)} {output:rsc.z(2)} {output:rsc.z(3)} {output:rsc.z(4)} {output:rsc.z(5)} {output:rsc.z(6)} {output:rsc.z(7)} -attr xrf 893 -attr oid 69 -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(0)} -port {output:rsc.z(0)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(1)} -port {output:rsc.z(1)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(2)} -port {output:rsc.z(2)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(3)} -port {output:rsc.z(3)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(4)} -port {output:rsc.z(4)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(5)} -port {output:rsc.z(5)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(6)} -port {output:rsc.z(6)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(7)} -port {output:rsc.z(7)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {clk} -attr xrf 894 -attr oid 70
+load net {clk} -port {clk} -attr xrf 895 -attr oid 71
+load net {en} -attr xrf 896 -attr oid 72
+load net {en} -port {en} -attr xrf 897 -attr oid 73
+load net {arst_n} -attr xrf 898 -attr oid 74
+load net {arst_n} -port {arst_n} -attr xrf 899 -attr oid 75
+load inst "dot_product:core:inst" "dot_product:core" "orig" -attr xrf 900 -attr oid 76 -attr vt dc -attr @path {/dot_product/dot_product:core:inst} -attr area 370.837302 -attr delay 3.064172 -attr hier "/dot_product/dot_product:core" -pg 1 -lvl 5
+load net {clk} -pin  "dot_product:core:inst" {clk#1} -attr xrf 901 -attr oid 77 -attr @path {/dot_product/clk}
+load net {en} -pin  "dot_product:core:inst" {en#1} -attr xrf 902 -attr oid 78 -attr @path {/dot_product/en}
+load net {arst_n} -pin  "dot_product:core:inst" {arst_n#1} -attr xrf 903 -attr oid 79 -attr @path {/dot_product/arst_n}
+load net {input_a:rsc:mgc_in_wire.d#1(0)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(1)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(2)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(3)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(4)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(5)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(6)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(7)} -pin  "dot_product:core:inst" {input_a:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(0)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(0)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(1)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(1)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(2)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(2)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(3)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(3)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(4)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(4)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(5)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(5)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(6)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(6)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(7)} -pin  "dot_product:core:inst" {input_b:rsc:mgc_in_wire.d(7)} -attr vt dc -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {output:rsc:mgc_out_stdreg.d#1(0)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(0)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(1)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(1)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(2)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(2)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(3)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(3)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(4)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(4)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(5)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(5)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(6)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(6)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(7)} -pin  "dot_product:core:inst" {output:rsc:mgc_out_stdreg.d(7)} -attr vt dc -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load inst "input_a:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(1,8)" "INTERFACE" -attr xrf 904 -attr oid 80 -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(1,8)" -pg 1 -lvl 1
+load net {input_a:rsc:mgc_in_wire.d#1(0)} -pin  "input_a:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(1)} -pin  "input_a:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(2)} -pin  "input_a:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(3)} -pin  "input_a:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(4)} -pin  "input_a:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(5)} -pin  "input_a:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(6)} -pin  "input_a:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc:mgc_in_wire.d#1(7)} -pin  "input_a:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/dot_product/input_a:rsc:mgc_in_wire.d}
+load net {input_a:rsc.z(0)} -pin  "input_a:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(1)} -pin  "input_a:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(2)} -pin  "input_a:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(3)} -pin  "input_a:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(4)} -pin  "input_a:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(5)} -pin  "input_a:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(6)} -pin  "input_a:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load net {input_a:rsc.z(7)} -pin  "input_a:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/dot_product/input_a:rsc.z}
+load inst "input_b:rsc:mgc_in_wire" "mgc_ioport.mgc_in_wire(2,8)" "INTERFACE" -attr xrf 905 -attr oid 81 -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_in_wire(2,8)" -pg 1 -lvl 1
+load net {input_b:rsc:mgc_in_wire.d#1(0)} -pin  "input_b:rsc:mgc_in_wire" {d(0)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(1)} -pin  "input_b:rsc:mgc_in_wire" {d(1)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(2)} -pin  "input_b:rsc:mgc_in_wire" {d(2)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(3)} -pin  "input_b:rsc:mgc_in_wire" {d(3)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(4)} -pin  "input_b:rsc:mgc_in_wire" {d(4)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(5)} -pin  "input_b:rsc:mgc_in_wire" {d(5)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(6)} -pin  "input_b:rsc:mgc_in_wire" {d(6)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc:mgc_in_wire.d#1(7)} -pin  "input_b:rsc:mgc_in_wire" {d(7)} -attr vt d -attr @path {/dot_product/input_b:rsc:mgc_in_wire.d}
+load net {input_b:rsc.z(0)} -pin  "input_b:rsc:mgc_in_wire" {z(0)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(1)} -pin  "input_b:rsc:mgc_in_wire" {z(1)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(2)} -pin  "input_b:rsc:mgc_in_wire" {z(2)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(3)} -pin  "input_b:rsc:mgc_in_wire" {z(3)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(4)} -pin  "input_b:rsc:mgc_in_wire" {z(4)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(5)} -pin  "input_b:rsc:mgc_in_wire" {z(5)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(6)} -pin  "input_b:rsc:mgc_in_wire" {z(6)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load net {input_b:rsc.z(7)} -pin  "input_b:rsc:mgc_in_wire" {z(7)} -attr vt d -attr @path {/dot_product/input_b:rsc.z}
+load inst "output:rsc:mgc_out_stdreg" "mgc_ioport.mgc_out_stdreg(3,8)" "INTERFACE" -attr xrf 906 -attr oid 82 -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg} -attr delay -1000000000000000000000000000000.000000 -attr qmod "mgc_ioport.mgc_out_stdreg(3,8)" -pg 1 -lvl 1002
+load net {output:rsc:mgc_out_stdreg.d#1(0)} -pin  "output:rsc:mgc_out_stdreg" {d(0)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(1)} -pin  "output:rsc:mgc_out_stdreg" {d(1)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(2)} -pin  "output:rsc:mgc_out_stdreg" {d(2)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(3)} -pin  "output:rsc:mgc_out_stdreg" {d(3)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(4)} -pin  "output:rsc:mgc_out_stdreg" {d(4)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(5)} -pin  "output:rsc:mgc_out_stdreg" {d(5)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(6)} -pin  "output:rsc:mgc_out_stdreg" {d(6)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc:mgc_out_stdreg.d#1(7)} -pin  "output:rsc:mgc_out_stdreg" {d(7)} -attr vt d -attr @path {/dot_product/output:rsc:mgc_out_stdreg.d}
+load net {output:rsc.z(0)} -pin  "output:rsc:mgc_out_stdreg" {z(0)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(1)} -pin  "output:rsc:mgc_out_stdreg" {z(1)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(2)} -pin  "output:rsc:mgc_out_stdreg" {z(2)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(3)} -pin  "output:rsc:mgc_out_stdreg" {z(3)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(4)} -pin  "output:rsc:mgc_out_stdreg" {z(4)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(5)} -pin  "output:rsc:mgc_out_stdreg" {z(5)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(6)} -pin  "output:rsc:mgc_out_stdreg" {z(6)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+load net {output:rsc.z(7)} -pin  "output:rsc:mgc_out_stdreg" {z(7)} -attr vt d -attr @path {/dot_product/output:rsc.z}
+### END MODULE 
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/Verify_cycle_v_msim.mk b/dot_product/dot_product/dot_product.v9/scverify/Verify_cycle_v_msim.mk
new file mode 100644
index 0000000..01773b8
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/Verify_cycle_v_msim.mk
@@ -0,0 +1,186 @@
+# ----------------------------------------------------------------------------
+# Cycle Verilog output 'cycle.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:54:48 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v9)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = cycle
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/cycle.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v9/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = mgc_hls work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = ./cycle.v/cycle.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC = ./cycle_mgc_ioport.v/cycle_mgc_ioport.v.vts ./cycle_mgc_ioport_v2001.v/cycle_mgc_ioport_v2001.v.vts $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = ./cycle_mgc_ioport.v/cycle_mgc_ioport.v.vts ./cycle_mgc_ioport_v2001.v/cycle_mgc_ioport_v2001.v.vts ./cycle.v/cycle.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp/scverify_top.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/cycle_mgc_ioport.v.vts: ./cycle_mgc_ioport.v
+$(TARGET)/cycle_mgc_ioport_v2001.v.vts: ./cycle_mgc_ioport_v2001.v
+$(TARGET)/cycle.v.vts: ./cycle.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/cycle.v.vts: HDL_LIB=work
+$(TARGET)/cycle_mgc_ioport_v2001.v.vts: HDL_LIB=mgc_hls
+$(TARGET)/cycle_mgc_ioport.v.vts: HDL_LIB=mgc_hls
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+$(TARGET)/cycle.v.vts: DUT_E=dot_product
+
+# Specify top design unit
+$(TARGET)/cycle.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/Verify_gate_v_msim.mk b/dot_product/dot_product/dot_product.v9/scverify/Verify_gate_v_msim.mk
new file mode 100644
index 0000000..e12274e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/Verify_gate_v_msim.mk
@@ -0,0 +1,192 @@
+# ----------------------------------------------------------------------------
+# Gate Verilog output 'gate.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:54:52 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v9)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = gate
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/rtl.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(RTLTOOL)" ""
+RTLTOOL                     = psr
+endif
+export RTLTOOL
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v9/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# Include auxillary makefiles based on simulation flows
+include $(MGC_HOME)/shared/include/mkfiles/ccs_Altera.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/gate.v/gate.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/gate.v/gate.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp/scverify_top.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/top_gate_constraints.cpp/top_gate_constraints.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/gate.psrv
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/gate.v.vts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/gate.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp
+$(TARGET)/top_gate_constraints.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/top_gate_constraints.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/top_gate_constraints.cpp.cxxts: CXX_OPTS=
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+$(TARGET)/top_gate_constraints.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/gate.v.vts: HDL_LIB=work
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+$(TARGET)/gate.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/Verify_mapped_v_msim.mk b/dot_product/dot_product/dot_product.v9/scverify/Verify_mapped_v_msim.mk
new file mode 100644
index 0000000..b0065d3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/Verify_mapped_v_msim.mk
@@ -0,0 +1,189 @@
+# ----------------------------------------------------------------------------
+# Mapped Verilog output 'rtl.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:54:52 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v9)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = mapped
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/rtl.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(RTLTOOL)" ""
+RTLTOOL                     = psr
+endif
+export RTLTOOL
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v9/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# Include auxillary makefiles based on simulation flows
+include $(MGC_HOME)/shared/include/mkfiles/ccs_Altera.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/mapped.v/mapped.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/mapped.v/mapped.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp/scverify_top.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/mapped.v.vts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/mapped.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/mapped.v.vts: HDL_LIB=work
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+$(TARGET)/mapped.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/Verify_orig_cxx_osci.mk b/dot_product/dot_product/dot_product.v9/scverify/Verify_orig_cxx_osci.mk
new file mode 100644
index 0000000..9b922c7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/Verify_orig_cxx_osci.mk
@@ -0,0 +1,171 @@
+# ----------------------------------------------------------------------------
+# Original Design + Testbench
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:54:20 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v9)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   =  .
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = orig
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = osci
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = cxx
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/dummy_netlist_file
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+LINK_SYSTEMC             += true
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+LINK_SYSTEMC             += true
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = 
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC =  $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = 
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+
+# Specify top design unit
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/Verify_rtl_v_msim.mk b/dot_product/dot_product/dot_product.v9/scverify/Verify_rtl_v_msim.mk
new file mode 100644
index 0000000..24f83b7
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/Verify_rtl_v_msim.mk
@@ -0,0 +1,186 @@
+# ----------------------------------------------------------------------------
+# RTL Verilog output 'rtl.v' vs Untimed C++
+#
+#    HLS version: 2011a.126 Production Release
+#       HLS date: Wed Aug  8 00:52:07 PDT 2012
+#  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+#
+#   Generated by: mg3115@EEWS104A-015
+# Generated date: Tue Mar 01 14:54:52 +0000 2016
+#
+# ----------------------------------------------------------------------------
+# ===================================================
+# DEFAULT GOAL is the help target
+.PHONY: all
+all: help
+
+# ===================================================
+# VARIABLES
+# 
+MGC_HOME          = C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home
+PROJDIR           = $(subst /,$(PATHSEP),../..)
+SOLNDIR           = $(subst /,$(PATHSEP),dot_product/dot_product.v9)
+export MGC_HOME
+
+# Variables that can be overridden from the make command line
+ifeq "$(INCL_DIRS)" ""
+INCL_DIRS                   = ./scverify . ../..
+endif
+export INCL_DIRS
+ifeq "$(STAGE)" ""
+STAGE                       = rtl
+endif
+export STAGE
+ifeq "$(SIMTOOL)" ""
+SIMTOOL                     = msim
+endif
+export SIMTOOL
+ifeq "$(NETLIST)" ""
+NETLIST                     = v
+endif
+export NETLIST
+ifeq "$(RTL_NETLIST_FNAME)" ""
+RTL_NETLIST_FNAME           = C:/CATAPU~1/dot_product/dot_product/dot_product.v9/rtl.v
+endif
+export RTL_NETLIST_FNAME
+ifeq "$(TARGET)" ""
+TARGET                      = scverify/$(STAGE)_$(NETLIST)_$(SIMTOOL)
+endif
+export TARGET
+ifeq "$(INVOKE_ARGS)" ""
+INVOKE_ARGS                 = 
+endif
+export INVOKE_ARGS
+export SCVLIBS
+export MODELSIM
+TOP_HDL_ENTITY           += dot_product
+TOP_DU                   += scverify_top
+CXX_TYPE                 += gcc
+MSIM_SCRIPT              += ./dot_product/dot_product.v9/scverify_msim.tcl
+
+ifeq ($(RECUR),)
+ifeq ($(STAGE),mapped)
+ifeq ($(RTLTOOL),)
+   $(error This makefile requires specifying the RTLTOOL variable on the make command line)
+endif
+endif
+endif
+# ===================================================
+# Include makefile for default commands and variables
+include $(MGC_HOME)/shared/include/mkfiles/ccs_default_cmds.mk
+
+# ===================================================
+# Include environment variables set by flow options
+include ./ccs_env.mk
+
+# ===================================================
+# SOURCES
+# 
+# Specify list of Modelsim libraries to create
+HDL_LIB_NAMES = mgc_hls work
+# Specify list of source files - MUST be ordered properly
+ifeq ($(STAGE),gate)
+ifeq ($(RTLTOOL),)
+ifeq ($(GATE_VHDL_DEP),)
+GATE_VHDL_DEP = 
+endif
+ifeq ($(GATE_VLOG_DEP),)
+GATE_VLOG_DEP = ./rtl.v/rtl.v.vts
+endif
+endif
+VHDL_SRC =  $(GATE_VHDL_DEP)
+VLOG_SRC = ./rtl_mgc_ioport.v/rtl_mgc_ioport.v.vts ./rtl_mgc_ioport_v2001.v/rtl_mgc_ioport_v2001.v.vts $(GATE_VLOG_DEP)
+else
+VHDL_SRC = 
+VLOG_SRC = ./rtl_mgc_ioport.v/rtl_mgc_ioport.v.vts ./rtl_mgc_ioport_v2001.v/rtl_mgc_ioport_v2001.v.vts ./rtl.v/rtl.v.vts
+endif
+CXX_SRC  = ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp/dot_product.cpp.cxxts ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp/tb_dot_product.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp/mc_testbench.cpp.cxxts C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp/scverify_top.cpp.cxxts
+# Specify RTL synthesis scripts (if any)
+RTL_SCRIPT = 
+
+# Specify hold time file name (for verifying synthesized netlists)
+HLD_CONSTRAINT_FNAME = top_gate_constraints.cpp
+
+# ===================================================
+# GLOBAL OPTIONS
+# 
+# CXXFLAGS - global C++ options (apply to all C++ compilations) except for include file search paths
+CXXFLAGS += -DCCS_SCVERIFY -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DSC_INCLUDE_MTI_AC -DTOP_HDL_ENTITY=$(TOP_HDL_ENTITY) -DCCS_MISMATCHED_OUTPUTS_ONLY
+# 
+# If the make command line includes a definition of the special variable MC_DEFAULT_TRANSACTOR_LOG
+# then define that value for all compilations as well
+ifneq "$(MC_DEFAULT_TRANSACTOR_LOG)" ""
+CXXFLAGS += -DMC_DEFAULT_TRANSACTOR_LOG=$(MC_DEFAULT_TRANSACTOR_LOG)
+endif
+# 
+# CXX_INCLUDES - include file search paths
+CXX_INCLUDES = ./scverify . ../..
+# 
+# TCL shell
+TCLSH_CMD = $(MGC_HOME)/bin/tclsh85.exe
+
+# Pass along SCVerify_DEADLOCK_DETECTION option
+ifneq "$(SCVerify_DEADLOCK_DETECTION)" ""
+CXXFLAGS += -DDEADLOCK_DETECTION
+endif
+# ===================================================
+# PER SOURCE FILE SPECIALIZATIONS
+# 
+# Specify source file paths
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): $(dir $(GATE_VHDL_DEP))
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): $(dir $(GATE_VLOG_DEP))
+endif
+endif
+$(TARGET)/rtl_mgc_ioport.v.vts: ./rtl_mgc_ioport.v
+$(TARGET)/rtl_mgc_ioport_v2001.v.vts: ./rtl_mgc_ioport_v2001.v
+$(TARGET)/rtl.v.vts: ./rtl.v
+$(TARGET)/dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+$(TARGET)/tb_dot_product.cpp.cxxts: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
+$(TARGET)/mc_testbench.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp
+$(TARGET)/scverify_top.cpp.cxxts: C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp
+# 
+# Specify additional C++ options per C++ source by setting CXX_OPTS
+$(TARGET)/scverify_top.cpp.cxxts: CXX_OPTS=
+$(TARGET)/mc_testbench.cpp.cxxts: CXX_OPTS=
+$(TARGET)/dot_product.cpp.cxxts: CXX_OPTS=
+$(TARGET)/tb_dot_product.cpp.cxxts: CXX_OPTS=
+# 
+# Specify dependencies
+$(TARGET)/dot_product.cpp.cxxts: 
+$(TARGET)/tb_dot_product.cpp.cxxts: 
+$(TARGET)/mc_testbench.cpp.cxxts: 
+$(TARGET)/scverify_top.cpp.cxxts: 
+# 
+# Specify compilation library for HDL source
+$(TARGET)/rtl.v.vts: HDL_LIB=work
+$(TARGET)/rtl_mgc_ioport_v2001.v.vts: HDL_LIB=mgc_hls
+$(TARGET)/rtl_mgc_ioport.v.vts: HDL_LIB=mgc_hls
+ifeq ($(STAGE),gate)
+ifneq ($(GATE_VHDL_DEP),)
+$(TARGET)/$(notdir $(GATE_VHDL_DEP)): HDL_LIB=work
+endif
+ifneq ($(GATE_VLOG_DEP),)
+$(TARGET)/$(notdir $(GATE_VLOG_DEP)): HDL_LIB=work
+endif
+endif
+# 
+# Specify top design unit for HDL source
+$(TARGET)/rtl.v.vts: DUT_E=dot_product
+
+# Specify top design unit
+$(TARGET)/rtl.v.vts: VLOG_TOP=1
+
+ifneq "$(RTLTOOL)" ""
+# ===================================================
+# Include makefile for RTL synthesis
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(RTLTOOL).mk
+else
+# ===================================================
+# Include makefile for simulator
+include $(MGC_HOME)/shared/include/mkfiles/ccs_$(SIMTOOL).mk
+endif
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/ccs_wave_signals.dat b/dot_product/dot_product/dot_product.v9/scverify/ccs_wave_signals.dat
new file mode 100644
index 0000000..50436ee
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/ccs_wave_signals.dat
@@ -0,0 +1,4 @@
+RADIX hex
+CDEBUG 0
+DEBUGVARS {input_a IN input_a:326:input_a input_b IN input_b:328:input_b output OUT output:329:output}
+WAVELIST {{DUT input_a:rsc input_a_rsc_z {scverify_top rtl input_a_rsc_z} {}} {DUT input_b:rsc input_b_rsc_z {scverify_top rtl input_b_rsc_z} {}} {DUT output:rsc output_rsc_z {scverify_top rtl output_rsc_z} {}} {OutputCompare output output-TRANS# {scverify_top user_tb output_comp _compare_cnt_sig} blue} {OutputCompare output output-GOLDEN {scverify_top user_tb output_comp _golden_sig} {}} {OutputCompare output output-DUT {scverify_top user_tb output_comp _dut_sig} {}} {OutputCompare output output-ERR# {scverify_top user_tb output_comp _error_cnt_sig} red} {Sync_Signals testbench clk {scverify_top rtl clk} {}} {Sync_Signals testbench Master_rst {scverify_top rst} {}} {Sync_Signals testbench cpp_testbench_active {scverify_top user_tb cpp_testbench_active} {}} {Sync_Signals testbench arst_n {scverify_top rtl arst_n} {}} {Sync_Signals testbench in_sync {scverify_top in_sync} {}} {Sync_Signals testbench out_sync {scverify_top out_sync} {}} {Sync_Signals testbench inout_sync {scverify_top inout_sync} {}} {DUT enable en {scverify_top rtl en} {}} {Active_Processes {} deadlock {scverify_top deadlocked} {}}}
diff --git a/dot_product/dot_product/dot_product.v9/scverify/gate.psrv b/dot_product/dot_product/dot_product.v9/scverify/gate.psrv
new file mode 100644
index 0000000..2fa8d17
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/gate.psrv
@@ -0,0 +1,304 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl.v}} -format verilog
+   setup_design -design=dot_product
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./scverify/gate.psrv_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'dot_product': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'dot_product': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'dot_product'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'dot_product'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to output_rsc_z(7:0)
+   report_timing -from en -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_a_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_a_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_b_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_b_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock clk] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock en] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=1"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'dot_product'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'dot_product'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 mapped.v]
+          puts "-- Writing mapped netlist for 'dot_product' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+       if {[get_state] != {pnr}} run_gate
+       if {$db(run_state) == {gate}} {
+          set gate_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 gate.v]
+          set gate_sdf [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 gate.v.sdf]
+          set IMPL_DIR [MGS_Core::get_design_impls -active]
+          set DESIGNNAME [report_project -basename]
+          set vendor [report_project -manufacturer]
+          set tech [report_project -libname]
+          set lang v
+          set vendor_var_list [vendor_vars $vendor $tech $lang "gate"]
+          foreach { vname vval } $vendor_var_list {
+             set $vname $vval
+          }
+          set NETLIST_FILE ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_NETSUF}
+          if { $lang == "v" } {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             remove_sdf_annotate $NETLIST_FILE $gate_netlist
+          } else {
+             puts "Copying vendor netlist '$NETLIST_FILE' to '$gate_netlist'"
+             file copy -force $NETLIST_FILE $gate_netlist
+          }
+          set NETLIST_SDF ${IMPL_DIR}/${VNDR_NETDIR}/${DESIGNNAME}${VNDR_SDFSUF}
+          puts "Copying SDF file '$NETLIST_SDF' to '$gate_sdf'"
+          file copy -force $NETLIST_SDF $gate_sdf
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/dot_product/dot_product/dot_product.v9/scverify/gate.psrv_timing b/dot_product/dot_product/dot_product.v9/scverify/gate.psrv_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/gate.psrv_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv b/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv
new file mode 100644
index 0000000..8782a66
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv
@@ -0,0 +1,277 @@
+puts {-- Note: Precision Synthesis Started}
+
+proc get_state { args } {
+   set state {}
+   catch {
+      set impl [get_impl_property -name]
+      set psi [open $impl/${impl}.psi r]
+      while {[gets $psi line] >= 0} {
+            if {[regexp -- "PROP key='statename' .*value='(.+)'" $line du state]} {
+                  break
+            }
+      }
+      close $psi
+   }
+   set state
+}
+proc run_setup { args } {
+   ## Setup Project
+   new_project -name psr_v -folder . -createimpl_name psr_v_impl -force
+   set_project_property -usetempdir false
+   set_input_dir .
+   setup_design -var "analyze_extra_options=-override -keeplast"
+
+   ## Add source HDL files
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl_mgc_ioport_v2001.v}} -format verilog
+   add_input_file {{C:/Catapult C/dot_product/dot_product/dot_product.v9/rtl.v}} -format verilog
+   setup_design -design=dot_product
+
+   ## Setup global frequence
+   setup_design -frequency 50.0
+
+   ## Setup technology settings
+   setup_design -manufacturer Altera -family {Cyclone III} -part EP3C16F484C -speed 6
+   setup_design -variable bumpup_device=true
+   setup_design -addio=true
+   setup_design -edif=true
+   setup_design -retiming=false
+
+if {[string compare [lindex [split [get_version] .] 0] "2010a"] >= 0} {
+setup_place_and_route -flow "Quartus II Modular" -command "Integrated Place and Route" -ba_format Verilog
+}
+
+   ## Add timing constraint file
+   add_input_file ./scverify/mapped.psrv_timing -format SDC
+
+   save_project
+}
+
+proc run_mapped { args } {
+   ## Synthesize design
+   puts "-- Starting synthesis for design 'dot_product': [clock format [clock seconds]]"
+   compile
+
+   # When a clock is not detected (e.g. combinational designs) Precision RTL
+   # creates the fake clock "Design_Clock" with the period corresponding to the frequency
+   # setting in the setup_design.
+
+   ## IO TIMING CONSTRAINTS
+   set hls_design_clk [lindex [concat [find_clocks -top] [all_clocks]] 0]
+   # These constraints prevent the 'No initialized timing analysis; 
+   # cannot define a Clock.' error message in combinational designs
+   set_input_delay 0.0 -clock $hls_design_clk [all_inputs]
+   set_output_delay 0.0 -clock $hls_design_clk [all_outputs]
+
+   synthesize
+   puts "-- Synthesis finished for design 'dot_product': [clock format [clock seconds]]"
+
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+   puts "-- BlockMulUnit (from /LIBS/mgc_Altera-Cyclone-III-6_beh_psr/MODS/mgc_mul_pipe/BINDINGS/all/PROPERTY_MAPPING/BlockMulUnit): 160.0"
+
+   puts "-- Characterization mode: p2p "
+
+   # Gather area and timing information
+   puts "-- Synthesis area report for design 'dot_product'"
+   report_area -cell_usage
+   puts "-- END Synthesis area report for design 'dot_product'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from en -to output_rsc_z(7:0)
+   report_timing -from en -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '0' 'INOUT' port 'en' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_a_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_a_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+   puts "-- Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+   set_max_delay 20.000000 -design rtl -from input_b_rsc_z(7:0) -to output_rsc_z(7:0)
+   report_timing -from input_b_rsc_z(7:0) -to output_rsc_z(7:0) -num_paths 1 -detail 
+   puts "-- END Synthesis input_to_output:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '3' 'OUT' port 'output_rsc_z'"
+
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 en
+      report_timing -from en -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+      set_input_delay -design rtl -clock clk 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_clk -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'clk'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+      #report_timing -from clk -to [all_registers -clock {clk}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'clk' '0' 'INOUT' CLOCK 'clk'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_a_rsc_z(7:0)
+      report_timing -from input_a_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '1' 'IN' port 'input_a_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      puts "-- Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+      set_input_delay -design rtl -clock en 0.0 input_b_rsc_z(7:0)
+      report_timing -from input_b_rsc_z(7:0) -to $regs_en -num_paths 1 -detail 
+      puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '2' 'IN' port 'input_b_rsc_z' '0' 'INOUT' CLOCK 'en'"
+
+      # this workaround ensures that there is a input delay for the cases
+      # where Precision does not have a complete timing model for a particular device
+      # the reported value is used if no other input delay value is reported
+      #puts "-- Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+      #report_timing -from en -to [all_registers -clock {en}] -num_paths 1 -detail 
+      #puts "-- END Synthesis input_to_register:timing report for design 'dot_product' '0' 'INOUT' port 'en' '0' 'INOUT' CLOCK 'en'"
+   }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_clk} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_clk [all_registers -clock {clk}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_clk} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_clk} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '0' 'INOUT' CLOCK 'en'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_clk [all_registers -clock {clk}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_clk} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+         report_timing -from ${regs_en} -to ${regs_clk} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'clk'"
+      }
+
+      set regsi_en [all_registers -clock {en}]
+      set regso_en [all_registers -clock {en}]
+      if { [llength ${regsi_en} ] > 0 && [llength ${regso_en} ] > 0 } {
+         puts "-- Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+         report_timing -from ${regs_en} -to ${regs_en} -num_paths 1 -detail 
+         puts "-- END Synthesis register_to_register:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '0' 'INOUT' CLOCK 'en'"
+      }
+
+   set regs_clk [all_registers -clock {clk}]
+   if { [llength ${regs_clk} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock clk 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock clk] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'clk' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   set regs_en [all_registers -clock {en}]
+   if { [llength ${regs_en} ] > 0 } {
+      puts "-- Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+      set_output_delay -design rtl -clock en 0.0 output_rsc_z(7:0)
+      report_timing -from [all_registers -clock en] -to output_rsc_z(7:0) -num_paths 1 -detail 
+      puts "-- END Synthesis register_to_output:timing report for design 'dot_product' '0' 'INOUT' CLOCK 'en' '3' 'OUT' port 'output_rsc_z'"
+   }
+
+   save_project
+}
+
+proc remove_sdf_annotate { infile outfile } {
+   if { ![file exists $infile] }  {
+      puts "Error - input file $infile not found"
+      return
+   }
+   set s [open $infile "r"]
+   set d [open $outfile "w"]
+   while { ! [eof $s] } {
+      gets $s line
+      if { [string match "*\$sdf_annotate*" $line] == 0 } {
+         puts $d $line
+      }
+   }
+   close $s
+   close $d
+}
+
+proc vendor_vars { vendor tech lang stage } {
+   # returns a list { netlist_output_directory netlist_file_suffix sdf_file_suffix sdf_inst sim_opts }
+      set SDFINST ""
+      switch -glob -- "${vendor}-${tech}" {
+         "Xilinx*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR . VNDR_NETSUF _out.vhd VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VLOG_OPTS \$(XILINX)/verilog/src/glbl.v SIM_OPTS glbl VNDR_NETDIR . VNDR_NETSUF _out.v VNDR_SDFSUF _out.sdf VNDR_SDFINST $SDFINST]
+            }
+         }
+         "Altera*" {
+            if { $stage == "gate" } {
+               set SDFINST scverify_top/rtl
+            }
+            if { $lang == "vhdl" } {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vho VNDR_SDFSUF _vhd.sdo VNDR_SDFINST $SDFINST]
+            } else {
+               return [list VNDR_NETDIR simulation/modelsim VNDR_NETSUF .vo VNDR_SDFSUF _v.sdo VNDR_SDFINST $SDFINST]
+            }
+         }
+      }
+   }
+proc run_gate { args } {
+   puts "PROC run_gate $args - enable_run_pnr=0"
+   place_and_route cl
+   save_project
+   puts "-- Synthesis design report for design 'dot_product'"
+   puts "-- Implementation directory: [MGS_Core::get_design_impls -active]"
+   puts "-- END Synthesis design report for design 'dot_product'"
+}
+
+proc run_flow { argv } {
+   global gui_mode
+   array set db $argv
+   if {[info exists db(-run_state)]} {
+       set db(run_state) $db(-run_state)
+   }
+   if {![info exists db(run_state)]} {
+       set db(run_state) {mapped}
+   }
+
+   if {$db(run_state) == {setup} || ![file exists ./psr_v.psp] || [catch {open_project ./psr_v.psp}]} {
+       run_setup
+   }
+   # verify that addio option is correct in the project
+   if { [string is true [report_project -addio]] != [string is true true] } {
+       puts "Note: Adjusting -addio constraint to true for proper mapped/gate simulation"
+       setup_design -addio=true
+       compile
+       run_mapped
+   }
+   if {$db(run_state) == {setup}} return
+
+   if {![info exists db(gui_mode)] || !$db(gui_mode) } {
+       set cstate [get_state]
+       if {$cstate != {synthesized} && $cstate != {pnr} } run_mapped
+       if {$db(run_state) == {mapped}} {
+          set mapped_netlist [file join C:/CATAPU~1/dot_product/dot_product/dot_product.v9 mapped.v]
+          puts "-- Writing mapped netlist for 'dot_product' to file '$mapped_netlist'"
+          auto_write $mapped_netlist
+          return
+       }
+
+   }
+}
+run_flow [expr {[info exists argv]?$argv:{}}]
diff --git a/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv_timing b/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv_timing
new file mode 100644
index 0000000..0bfaa4e
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/mapped.psrv_timing
@@ -0,0 +1,2 @@
+create_clock -domain clk -name clk -period 20.0 -waveform { 0.0 10.0 } clk
+set_clock_uncertainty -design rtl 0.0 clk
diff --git a/dot_product/dot_product/dot_product.v9/scverify/mc_dut_wrapper.h b/dot_product/dot_product/dot_product.v9/scverify/mc_dut_wrapper.h
new file mode 100644
index 0000000..5cbf161
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/mc_dut_wrapper.h
@@ -0,0 +1,75 @@
+// ----------------------------------------------------------------------------
+// SystemC Wrapper for Catapult Design HDL Netlist
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 14:54:48 +0000 2016
+//
+// ----------------------------------------------------------------------------
+#ifndef INCLUDED_CCS_DUT_WRAPPER_H
+#define INCLUDED_CCS_DUT_WRAPPER_H
+
+#ifndef SC_USE_STD_STRING
+#define SC_USE_STD_STRING
+#endif
+
+#include <systemc.h>
+#include <mc_simulator_extensions.h>
+
+#if defined(CCS_DUT_SYSC)
+
+// alias ccs_DUT_wrapper to namespace enclosure of either cycle or RTL SystemC netlist
+namespace ccs_design {
+#if defined(CCS_DUT_CYCLE)
+//#include "cycle.cxx"
+#include "cycle.cxx"
+#else
+#if defined(CCS_DUT_RTL)
+//#include "rtl.cxx"
+#include "rtl.cxx"
+#endif
+#endif
+}
+typedef ccs_design::HDL::dot_product ccs_DUT_wrapper;
+
+#else
+
+// Create a foreign module wrapper around the HDL
+class ccs_DUT_wrapper : public mc_foreign_module
+{
+public:
+   #ifndef VCS_SYSTEMC
+   // Interface Ports
+   sc_in<bool> clk;
+   sc_in< sc_logic > en;
+   sc_in< sc_logic > arst_n;
+   sc_in< sc_lv<8> > input_a_rsc_z;
+   sc_in< sc_lv<8> > input_b_rsc_z;
+   sc_out< sc_lv<8> > output_rsc_z;
+   #endif
+   
+public:
+   ccs_DUT_wrapper(const sc_module_name& nm, const char *hdl_name)
+      : mc_foreign_module(nm,hdl_name)
+      #ifndef VCS_SYSTEMC
+      ,clk("clk")
+      ,en("en")
+      ,arst_n("arst_n")
+      ,input_a_rsc_z("input_a_rsc_z")
+      ,input_b_rsc_z("input_b_rsc_z")
+      ,output_rsc_z("output_rsc_z")
+      #endif
+      {
+          // elaborate_foreign_module(hdl_name);
+      }
+      
+      ~ccs_DUT_wrapper() {}
+   };
+   
+   #endif
+
+#endif
+
diff --git a/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp b/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp
new file mode 100644
index 0000000..7015677
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.cpp
@@ -0,0 +1,337 @@
+// ----------------------------------------------------------------------------
+// SystemC Testbench Body
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 14:54:47 +0000 2016
+//
+// ----------------------------------------------------------------------------
+// 
+// -------------------------------------
+// testbench
+// User supplied testbench
+// -------------------------------------
+// 
+#include "mc_testbench.h"
+#include <mc_simulator_extensions.h>
+
+testbench* testbench::that;
+std::vector<mc_end_of_testbench*> testbench::_end_of_tb_objs;
+bool testbench::input_a_ignore;
+bool testbench::input_a_skip;
+void mc_testbench_input_a_skip(bool v) { testbench::input_a_skip = v; }
+int testbench::input_a_array_comp_first;
+int testbench::input_a_array_comp_last;
+int testbench::input_a_wait_cycles;
+mc_wait_ctrl testbench::input_a_wait_ctrl;
+bool testbench::input_b_ignore;
+bool testbench::input_b_skip;
+void mc_testbench_input_b_skip(bool v) { testbench::input_b_skip = v; }
+int testbench::input_b_array_comp_first;
+int testbench::input_b_array_comp_last;
+int testbench::input_b_wait_cycles;
+mc_wait_ctrl testbench::input_b_wait_ctrl;
+bool testbench::output_ignore;
+bool testbench::output_skip;
+void mc_testbench_output_skip(bool v) { testbench::output_skip = v; }
+int testbench::output_array_comp_first;
+int testbench::output_array_comp_last;
+bool testbench::output_use_mask;
+ac_int<8, true > testbench::output_output_mask;
+int testbench::output_wait_cycles;
+mc_wait_ctrl testbench::output_wait_ctrl;
+extern "C++" void dot_product( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output);
+
+// ============================================
+// Function: mc_testbench_process_wait_ctrl
+// --------------------------------------------
+
+void testbench::mc_testbench_process_wait_ctrl(const sc_string &var,int &var_wait_cycles,mc_wait_ctrl &var_wait_ctrl,tlm::tlm_fifo_put_if< mc_wait_ctrl > *ccs_wait_ctrl_fifo_if,const int var_capture_count,const int var_stopat)
+{
+   if (var_wait_cycles) {
+      // backward compatibility mode
+      var_wait_ctrl.cycles = var_wait_cycles;
+      var_wait_cycles = 0;
+      std::ostringstream msg; msg.str("");
+      msg << "Depricated use of '" << var << "_wait_cycles' variable. Use '" << var << "_wait_ctrl.cycles' instead.";
+      SC_REPORT_WARNING("User testbench", msg.str().c_str());
+   }
+   if (var_wait_ctrl.cycles != 0) {
+      var_wait_ctrl.iteration = var_capture_count;
+      var_wait_ctrl.stopat = var_stopat;
+      if (var_wait_ctrl.cycles < 0) {
+         std::ostringstream msg; msg.str("");
+         msg << "Ignoring negative value (" << var_wait_ctrl.cycles << ") for testbench control testbench::" << var << "_wait_ctrl.cycles.";
+         SC_REPORT_WARNING("User testbench", msg.str().c_str());
+         var_wait_ctrl.cycles = 0;
+      }
+      if (var_wait_ctrl.interval < 0) {
+         std::ostringstream msg; msg.str("");
+         msg << "Ignoring negative value (" << var_wait_ctrl.interval << ") for testbench control testbench::" << var << "_wait_ctrl.interval.";
+         SC_REPORT_WARNING("User testbench", msg.str().c_str());
+         var_wait_ctrl.interval = 0;
+      }
+      if (var_wait_ctrl.is_set()) {
+         std::ostringstream msg; msg.str("");
+         msg << "Captured wait_ctrl request " << var_wait_ctrl;
+         SC_REPORT_INFO("User testbench", msg.str().c_str());
+         ccs_wait_ctrl_fifo_if->put(var_wait_ctrl);
+      }
+   }
+   var_wait_ctrl.clear(); // reset wait_ctrl
+}
+// ============================================
+// Function: register_end_of_testbench_obj
+// --------------------------------------------
+
+void testbench::register_end_of_testbench_obj(mc_end_of_testbench* obj)
+{
+   _end_of_tb_objs.push_back(obj);
+}
+// ============================================
+// Function: capture_input_a
+// --------------------------------------------
+
+void testbench::capture_input_a( ac_int<8, true > *input_a)
+{
+   if (input_a_capture_count == wait_cnt)
+      wait_on_input_required();
+   if (_capture_input_a && !input_a_ignore)
+   {
+      int cur_iter=input_a_iteration_count;
+      ++input_a_iteration_count;
+      ccs_input_a->put((*input_a));
+      ++input_a_capture_count;
+      mc_testbench_process_wait_ctrl("input_a",input_a_wait_cycles,input_a_wait_ctrl,ccs_wait_ctrl_input_a.operator->(),cur_iter,input_a_capture_count);
+      input_a_ignore = false;
+   }
+}
+// ============================================
+// Function: capture_input_b
+// --------------------------------------------
+
+void testbench::capture_input_b( ac_int<8, true > *input_b)
+{
+   if (input_b_capture_count == wait_cnt)
+      wait_on_input_required();
+   if (_capture_input_b && !input_b_ignore)
+   {
+      int cur_iter=input_b_iteration_count;
+      ++input_b_iteration_count;
+      ccs_input_b->put((*input_b));
+      ++input_b_capture_count;
+      mc_testbench_process_wait_ctrl("input_b",input_b_wait_cycles,input_b_wait_ctrl,ccs_wait_ctrl_input_b.operator->(),cur_iter,input_b_capture_count);
+      input_b_ignore = false;
+   }
+}
+// ============================================
+// Function: capture_output
+// --------------------------------------------
+
+void testbench::capture_output( ac_int<8, true > *output)
+{
+   if (_capture_output)
+   {
+      int cur_iter=output_iteration_count;
+      ++output_iteration_count;
+      mc_golden_info< ac_int<8, true >, ac_int<8, true > > output_tmp((*output), output_ignore, ~0, false, output_iteration_count);
+      // BEGIN: testbench output_mask control for field_name output
+      if ( output_use_mask ) {
+         output_tmp._use_mask = true;
+         output_tmp._mask = output_output_mask ;
+      }
+      // END: testbench output_mask control for field_name output
+      if (!output_skip) {
+         output_golden.put(output_tmp);
+         ++output_capture_count;
+      } else {
+         std::ostringstream msg; msg.str("");
+         msg << "output_skip=true for iteration=" << output_iteration_count << " @ " << sc_time_stamp();
+         SC_REPORT_WARNING("User testbench", msg.str().c_str());
+      }
+      mc_testbench_process_wait_ctrl("output",output_wait_cycles,output_wait_ctrl,ccs_wait_ctrl_output.operator->(),cur_iter,output_capture_count);
+      output_ignore = false;
+      output_use_mask = false;
+   }
+   output_skip = false;
+}
+// ============================================
+// Function: wait_on_input_required
+// --------------------------------------------
+
+void testbench::wait_on_input_required()
+{
+   ++wait_cnt;
+   wait(SC_ZERO_TIME); // get fifos a chance to update
+   while (atleast_one_active_input) {
+      if (_capture_input_a && ccs_input_a->used() == 0) return;
+      if (_capture_input_b && ccs_input_b->used() == 0) return;
+      that->cpp_testbench_active.write(false);
+      wait(ccs_input_a->ok_to_put() | ccs_input_b->ok_to_put());
+      that->cpp_testbench_active.write(true);
+   }
+}
+// ============================================
+// Function: capture_IN
+// --------------------------------------------
+
+void testbench::capture_IN( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output)
+{
+   that->capture_input_a(input_a);
+   that->capture_input_b(input_b);
+}
+// ============================================
+// Function: capture_OUT
+// --------------------------------------------
+
+void testbench::capture_OUT( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output)
+{
+   that->capture_output(output);
+}
+// ============================================
+// Function: exec_dot_product
+// --------------------------------------------
+
+void testbench::exec_dot_product( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output)
+{
+   that->cpp_testbench_active.write(true);
+   capture_IN(input_a, input_b, output);
+   dot_product(input_a, input_b, output);
+   // throttle ac_channel based on number of calls to chan::size() or chan::empty() or chan::nb_read() (but not chan::available()) 
+   if (1) {
+      int cnt=0;
+      if (cnt) std::cout << "mc_testbench.cpp: CONTINUES @ " << sc_time_stamp() << std::endl;
+      if (cnt) that->cpp_testbench_active.write(true);
+   }
+   capture_OUT(input_a, input_b, output);
+}
+// ============================================
+// Function: end_of_simulation
+// --------------------------------------------
+
+void testbench::end_of_simulation()
+{
+   if (!_checked_results) {
+      SC_REPORT_INFO(name(), "Simulation ran into deadlock");
+      check_results();
+   }
+}
+// ============================================
+// Function: check_results
+// --------------------------------------------
+
+void testbench::check_results()
+{
+   for (std::vector<mc_end_of_testbench*>::iterator i = _end_of_tb_objs.begin(); i != _end_of_tb_objs.end(); ++i)
+      (*i)->end_of_testbench();
+   
+   _checked_results = true;
+   cout<<endl;
+   cout<<"Checking results"<<endl;
+   _failed = false;
+   if (main_exit_code) _failed = true;
+   int _num_outputs_checked = 0;
+   
+   if (!_capture_output) {
+      cout<<"'output' - warning, output was optimized away"<<endl;
+   } else {
+      _num_outputs_checked++;
+      cout<<"'output'"<<endl;
+      cout<<"   capture count        = "<<output_capture_count<<endl;
+      cout<<"   comparison count     = "<<output_comp->get_compare_count();
+      if (output_comp->get_partial_compare_count()) 
+         cout <<" ("<<output_comp->get_partial_compare_count()<<" partial)";
+      if (output_comp->get_mask_compare_count()) 
+         cout <<" ("<<output_comp->get_mask_compare_count()<<" masked)";
+      cout << endl;
+      cout<<"   ignore count         = "<<output_comp->get_ignore_count()<<endl;
+      cout<<"   error count          = "<<output_comp->get_error_count()<<endl;
+      cout<<"   stuck in dut fifo    = "<<ccs_output->used()<<endl;
+      cout<<"   stuck in golden fifo = "<<output_golden.used()<<endl;
+      if (output_comp->get_error_count() > 0) cout << "   Error: output 'output' had comparison errors"<<endl;
+      if (output_comp->get_compare_count() < output_capture_count) cout << "   Error: output 'output' has incomplete comparisons"<<endl;
+      if (output_capture_count == 0) cout << "   Error: output 'output' has no golden values to compare against"<<endl;
+      _failed = _failed || output_comp->get_error_count() > 0;
+      _failed = _failed || output_comp->get_compare_count() < output_capture_count;
+      _failed = _failed || output_capture_count == 0;
+      cout<<endl;
+   }
+   cout<<endl;
+   if (_num_outputs_checked == 0) {
+      cout<<"Error: All outputs were optimized away. No output values were compared."<<endl;
+      _failed = _failed || (_num_outputs_checked == 0);
+   }
+   if (main_exit_code) cout << "Error: C++ Testbench 'main()' returned a non-zero exit code ("<<main_exit_code<<"). Check your testbench." <<endl;
+   cout<<(_failed ? "Error: ":"Info: ")<<"Simulation "<<(_failed ? "FAILED":"PASSED")<<" @ "<<sc_time_stamp()<<endl;
+   
+   if (_failed) {
+      cout << endl;
+      cout << "Error: Simulation may have failed due to incorrect testbench stimulus synchronization. Try turning on the TRANSACTION_DONE_SIGNAL directive." << endl;
+   }
+}
+// ============================================
+// Function: failed
+// --------------------------------------------
+
+bool testbench::failed()
+{
+   return _failed;
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD wait_for_end
+// Static sensitivity: sensitive << clk.pos() << testbench_end_event;
+
+void testbench::wait_for_end() {
+   // If run() has not finished, we do nothing here
+   if (!testbench_ended) return;
+   // check for completed outputs
+   if (output_comp->get_compare_count() < output_capture_count) {testbench_end_event.notify(1,SC_NS); return;}
+   // If we made it here, all outputs have flushed. Check the results
+   SC_REPORT_INFO(name(), "Simulation completed");
+   check_results();
+   sc_stop();
+}
+// ---------------------------------------------------------------
+// Process: SC_THREAD run
+// Static sensitivity: 
+
+void testbench::run() {
+   input_a_ignore = false;
+   input_a_skip = false;
+   input_a_array_comp_first = -1;
+   input_a_array_comp_last = -1;
+   input_a_wait_cycles = 0;
+   input_a_wait_ctrl.clear();
+   input_a_capture_count = 0;
+   input_a_iteration_count = 0;
+   input_b_ignore = false;
+   input_b_skip = false;
+   input_b_array_comp_first = -1;
+   input_b_array_comp_last = -1;
+   input_b_wait_cycles = 0;
+   input_b_wait_ctrl.clear();
+   input_b_capture_count = 0;
+   input_b_iteration_count = 0;
+   output_ignore = false;
+   output_skip = false;
+   output_array_comp_first = -1;
+   output_array_comp_last = -1;
+   output_use_mask = false;
+   output_output_mask = ~0;
+   output_wait_cycles = 0;
+   output_wait_ctrl.clear();
+   output_capture_count = 0;
+   output_iteration_count = 0;
+   main_exit_code = main();
+   cout<<"Info: Execution of user-supplied C++ testbench 'main()' has completed with exit code = " << main_exit_code << endl;
+   cout<<endl;
+   cout<<"Info: Collecting data completed"<<endl;
+   cout<<"   captured "<<input_a_capture_count<<" values of input_a"<<endl;
+   cout<<"   captured "<<input_b_capture_count<<" values of input_b"<<endl;
+   cout<<"   captured "<<output_capture_count<<" values of output"<<endl;
+   testbench_ended = true;
+   testbench_end_event.notify(SC_ZERO_TIME);
+}
diff --git a/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.h b/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.h
new file mode 100644
index 0000000..f61573a
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/mc_testbench.h
@@ -0,0 +1,188 @@
+// ----------------------------------------------------------------------------
+// SystemC Testbench Header
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 14:54:47 +0000 2016
+//
+// ----------------------------------------------------------------------------
+#ifdef CCS_SCVERIFY
+
+// 
+// -------------------------------------
+// testbench
+// User supplied testbench
+// -------------------------------------
+// 
+#ifndef INCLUDED_TESTBENCH_H
+#define INCLUDED_TESTBENCH_H
+
+extern void mc_testbench_input_a_skip(bool v);
+extern void mc_testbench_input_b_skip(bool v);
+extern void mc_testbench_output_skip(bool v);
+
+#ifndef SC_USE_STD_STRING
+#define SC_USE_STD_STRING
+#endif
+
+#include "../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h"
+#include <systemc.h>
+#include <tlm.h>
+#include <ac_int.h>
+#include <mc_container_types.h>
+#include <mc_typeconv.h>
+#include <mc_transactors.h>
+#include <mc_comparator.h>
+#include <mc_end_of_testbench.h>
+#include <vector>
+
+
+class testbench : public sc_module
+{
+public:
+   // Interface Ports
+   sc_in< bool > clk;
+   sc_port< tlm::tlm_fifo_put_if< ac_int<8, true > > > ccs_input_a;
+   sc_port< tlm::tlm_fifo_put_if< mc_wait_ctrl > > ccs_wait_ctrl_input_a;
+   sc_port< tlm::tlm_fifo_put_if< ac_int<8, true > > > ccs_input_b;
+   sc_port< tlm::tlm_fifo_put_if< mc_wait_ctrl > > ccs_wait_ctrl_input_b;
+   sc_port< tlm::tlm_fifo_get_if< ac_int<8, true > > > ccs_output;
+   sc_port< tlm::tlm_fifo_put_if< mc_wait_ctrl > > ccs_wait_ctrl_output;
+   
+   // Data objects
+   bool testbench_ended;
+   int main_exit_code;
+   bool atleast_one_active_input;
+   sc_time last_event_time;
+   sc_time last_event_time2;
+   sc_signal< bool >                          cpp_testbench_active;
+   sc_event testbench_end_event;
+   int argc;
+   const char* const *argv;
+   bool _checked_results;
+   bool _failed;
+   static testbench* that;
+   static std::vector<mc_end_of_testbench*> _end_of_tb_objs;
+   int main();
+   static bool input_a_ignore;
+   static bool input_a_skip;
+   static int input_a_array_comp_first;
+   static int input_a_array_comp_last;
+   bool _capture_input_a;
+   static int input_a_wait_cycles;
+   static mc_wait_ctrl input_a_wait_ctrl;
+   int input_a_capture_count;
+   int input_a_iteration_count;
+   static bool input_b_ignore;
+   static bool input_b_skip;
+   static int input_b_array_comp_first;
+   static int input_b_array_comp_last;
+   bool _capture_input_b;
+   static int input_b_wait_cycles;
+   static mc_wait_ctrl input_b_wait_ctrl;
+   int input_b_capture_count;
+   int input_b_iteration_count;
+   static bool output_ignore;
+   static bool output_skip;
+   static int output_array_comp_first;
+   static int output_array_comp_last;
+   static bool output_use_mask;
+   static ac_int<8, true > output_output_mask;
+   tlm::tlm_fifo< mc_golden_info< ac_int<8, true >, ac_int<8, true > > > output_golden;
+   bool _capture_output;
+   static int output_wait_cycles;
+   static mc_wait_ctrl output_wait_ctrl;
+   int output_capture_count;
+   int output_iteration_count;
+   int wait_cnt;
+   
+   // Named Objects
+   
+   // Module instance pointers
+   mc_comparator< ac_int<8, true > , ac_int<8, true > > *output_comp;
+   
+   // Declare processes (SC_METHOD and SC_THREAD)
+   void wait_for_end();
+   void run();
+   
+   // Constructor
+   SC_HAS_PROCESS(testbench);
+   testbench(
+      const sc_module_name& name
+   )
+      : clk("clk")
+      , ccs_input_a("ccs_input_a")
+      , ccs_wait_ctrl_input_a("ccs_wait_ctrl_input_a")
+      , ccs_input_b("ccs_input_b")
+      , ccs_wait_ctrl_input_b("ccs_wait_ctrl_input_b")
+      , ccs_output("ccs_output")
+      , ccs_wait_ctrl_output("ccs_wait_ctrl_output")
+      , cpp_testbench_active("cpp_testbench_active")
+      , output_golden("output_golden",-1)
+   {
+      // Instantiate other modules
+      output_comp = new mc_comparator< ac_int<8, true > , ac_int<8, true > > (
+         "output_comp",
+         0,
+         1
+      );
+      output_comp->data_in(ccs_output);
+      output_comp->data_golden(output_golden);
+      
+      
+      // Register processes
+      SC_METHOD(wait_for_end);
+      sensitive << clk.pos() << testbench_end_event;
+      SC_THREAD(run);
+      // Other constructor statements
+      set_stack_size(64000000);
+      argc = sc_argc();
+      argv = sc_argv();
+      _checked_results = false;
+      that = this;
+      testbench_ended = false;
+      main_exit_code = 0;
+      atleast_one_active_input = true;
+      _capture_input_a = true;
+      _capture_input_b = true;
+      _capture_output = true;
+      wait_cnt = 0;
+   }
+   
+   ~testbench()
+   {
+      delete output_comp;
+      output_comp = 0;
+   }
+   
+   // C++ class functions
+   public:
+      void mc_testbench_process_wait_ctrl(const sc_string &var,int &var_wait_cycles,mc_wait_ctrl &var_wait_ctrl,tlm::tlm_fifo_put_if< mc_wait_ctrl > *ccs_wait_ctrl_fifo_if,const int var_capture_count,const int var_stopat) ;
+   public:
+      static void register_end_of_testbench_obj(mc_end_of_testbench* obj) ;
+   public:
+      void capture_input_a( ac_int<8, true > *input_a) ;
+   public:
+      void capture_input_b( ac_int<8, true > *input_b) ;
+   public:
+      void capture_output( ac_int<8, true > *output) ;
+   protected:
+      void wait_on_input_required() ;
+   public:
+      static void capture_IN( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output) ;
+   public:
+      static void capture_OUT( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output) ;
+   public:
+      static void exec_dot_product( ac_int<8, true > *input_a,  ac_int<8, true > *input_b,  ac_int<8, true > *output) ;
+   protected:
+      void end_of_simulation() ;
+   public:
+      void check_results() ;
+   public:
+      bool failed() ;
+};
+#endif
+#endif
diff --git a/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp b/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp
new file mode 100644
index 0000000..7d8ace3
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/scverify_top.cpp
@@ -0,0 +1,289 @@
+// ----------------------------------------------------------------------------
+// SystemC Top Module
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 14:54:47 +0000 2016
+//
+// ----------------------------------------------------------------------------
+//---------------------------------------------------
+// scverify_top.cpp
+//---------------------------------------------------
+
+#include <iostream>
+#include "scverify_top.h"
+#include <mc_simulator_extensions.h>
+// 
+// -------------------------------------
+// scverify_top
+// top module instantiating reference design,
+// DUT and comparator
+// -------------------------------------
+// 
+#include <mt19937ar.c>
+
+
+// ============================================
+// Function: setup_debug
+// --------------------------------------------
+
+void scverify_top::setup_debug()
+{
+   #ifdef MC_DEFAULT_TRANSACTOR_LOG
+      static int input_a_flags = MC_DEFAULT_TRANSACTOR_LOG;
+   #else
+      static int input_a_flags = MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT;
+   #endif
+      static int input_a_count = -1;
+   #ifdef MC_DEFAULT_TRANSACTOR_LOG
+      static int input_b_flags = MC_DEFAULT_TRANSACTOR_LOG;
+   #else
+      static int input_b_flags = MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT;
+   #endif
+      static int input_b_count = -1;
+   #ifdef MC_DEFAULT_TRANSACTOR_LOG
+      static int output_flags = MC_DEFAULT_TRANSACTOR_LOG;
+   #else
+      static int output_flags = MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT;
+   #endif
+      static int output_count = -1;
+   
+      // At the breakpoint, modify the local variables
+      // above to turn on/off different levels of transaction
+      // logging for each variable. Available flags are:
+      //   MC_TRANSACTOR_EMPTY       - log empty FIFOs (on by default)
+      //   MC_TRANSACTOR_UNDERFLOW   - log FIFOs that run empty and then are loaded again (off)
+      //   MC_TRANSACTOR_READ        - log all read events
+      //   MC_TRANSACTOR_WRITE       - log all write events
+      //   MC_TRANSACTOR_LOAD        - log all FIFO load events
+      //   MC_TRANSACTOR_DUMP        - log all FIFO dump events
+      //   MC_TRANSACTOR_STREAMCNT   - log all streamed port index counter events
+      //   MC_TRANSACTOR_WAIT        - log user specified handshake waits
+      //   MC_TRANSACTOR_SIZE        - log input FIFO size updates
+   
+      // In ModelSim, type ccs_extensions::ccs_opts to bring up a GUI to set these options
+   
+      debug("input_a:326:input_a",input_a_flags,input_a_count);
+      debug("input_b:328:input_b",input_b_flags,input_b_count);
+      debug("output:329:output",output_flags,output_count);
+}
+// ============================================
+// Function: install_observe_foreign_signals
+// --------------------------------------------
+
+void scverify_top::install_observe_foreign_signals()
+{
+   #if !defined(CCS_DUT_SYSC) && defined(DEADLOCK_DETECTION)
+   #if defined(CCS_DUT_CYCLE) || defined(CCS_DUT_RTL)
+   #ifdef MTI_SYSTEMC
+   #endif
+   #ifdef VCS_SYSTEMC
+   #if defined(CCS_DUT_VHDL)
+   #include <hdl_connect_vhdl.h>
+   #define HDL_CONNECT_FN hdl_connect_vhdl
+   #else
+   #if defined(CCS_DUT_VERILOG)
+   #include <hdl_connect_v.h>
+   #define HDL_CONNECT_FN hdl_connect_v
+   #endif
+   #endif
+   #endif
+   #ifdef NCSC
+   #endif
+   #endif
+   #endif
+}
+// ============================================
+// Function: debug
+// --------------------------------------------
+
+void scverify_top::debug(const char *varname, int flags, int count)
+{
+   sc_module *xlator_p = 0;
+   sc_attr_base *debug_attr_p = 0;
+   if (strcmp(varname,"input_a:326:input_a") == 0) {
+      xlator_p = input_a_transactor;
+   }
+   if (strcmp(varname,"input_b:328:input_b") == 0) {
+      xlator_p = input_b_transactor;
+   }
+   if (strcmp(varname,"output:329:output") == 0) {
+      xlator_p = output_transactor;
+   }
+   if (xlator_p) {
+      debug_attr_p = xlator_p->get_attribute("MC_TRANSACTOR_EVENT");
+      if (!debug_attr_p) {
+         debug_attr_p = new sc_attribute<int>("MC_TRANSACTOR_EVENT",flags);
+         xlator_p->add_attribute(*debug_attr_p);
+      }
+      ((sc_attribute<int>*)debug_attr_p)->value = flags;
+   }
+   if (count>=0) {
+      debug_attr_p = xlator_p->get_attribute("MC_TRANSACTOR_COUNT");
+      if (!debug_attr_p) {
+         debug_attr_p = new sc_attribute<int>("MC_TRANSACTOR_COUNT",count);
+         xlator_p->add_attribute(*debug_attr_p);
+      }
+      ((sc_attribute<int>*)debug_attr_p)->value = count;
+   }
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD deadlock_notify
+// Static sensitivity: sensitive << deadlock_event;
+
+void scverify_top::deadlock_notify() {
+   if (deadlocked.read() == SC_LOGIC_1) {
+      testbench_INST->check_results();
+      SC_REPORT_ERROR("System","Simulation deadlock detected");
+      sc_stop();
+   }
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD deadlock_watch
+// Static sensitivity: sensitive  << clk;
+
+void scverify_top::deadlock_watch() {
+   // DEADLOCK_WATCH
+   #if !defined(CCS_DUT_SYSC) && defined(DEADLOCK_DETECTION)
+   #if defined(CCS_DUT_CYCLE) || defined(CCS_DUT_RTL)
+   #if defined(MTI_SYSTEMC) || defined(NCSC) || defined(VCS_SYTEMC)
+   #endif
+   #endif
+   #endif
+   // DEADLOCK_WATCH END
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD generate_sync
+// Static sensitivity: sensitive << clk << rst;
+
+void scverify_top::generate_sync() {
+   static int active_edge = 1;
+   static CATMON_EX_TYPE latency = 6LL; // Total Cycles value
+   static CATMON_EX_TYPE init_interval = 0LL;
+   static CATMON_EX_TYPE csteps = 6LL;
+   static CATMON_EX_TYPE duration = latency - csteps + init_interval;
+   static CATMON_EX_TYPE latest_write = 5LL;
+   static bool top_loop_pipelined = false;
+   
+   static CATMON_EX_TYPE max_state = init_interval ? duration : latency;
+   
+   static CATMON_EX_TYPE initial_in_state = ((init_interval>0)&&top_loop_pipelined&&(latency!=csteps)) ? 0 : 1;
+   static CATMON_EX_TYPE initial_out_state = init_interval ? init_interval-latest_write+1 : 1;
+   
+   static int done_flag_used = 0;
+   
+   
+   static CATMON_EX_TYPE in_state = initial_in_state;
+   static CATMON_EX_TYPE out_state = initial_out_state;
+   static sc_logic last_done = SC_LOGIC_0; // if DONE_FLAG used
+   
+   if (rst.read() == 1) {
+      in_sync.write(SC_LOGIC_0);
+      out_sync.write(SC_LOGIC_0);
+      inout_sync.write(SC_LOGIC_0);
+      catapult_start.write(SC_LOGIC_0);
+      in_state = initial_in_state;
+      last_done = SC_LOGIC_1;
+      if (init_interval) {
+         out_state = initial_out_state;
+      } else {
+         if (done_flag_used && (catapult_done.read() == 0)) wait_for_init = 0;
+         out_state = initial_out_state;
+      }
+   } else {
+     if (done_flag_used) {
+         catapult_start.write(catapult_done.read()); // start follows done timing
+         if (catapult_done.read() == SC_LOGIC_0) {
+            // falling edge of done, deassert start
+            wait_for_init.write(wait_for_init.read()+1);
+            out_sync.write(SC_LOGIC_0);
+            in_sync.write(SC_LOGIC_0);
+            inout_sync.write(SC_LOGIC_0);
+         } else {
+            // rising edge of done, assert sync signals
+            if (wait_for_init.read() > 1) {
+               out_sync.write(SC_LOGIC_1);
+               in_sync.write(SC_LOGIC_1);
+               inout_sync.write(SC_LOGIC_1);
+            }
+         }
+     } else {
+      if ( clk.read() == active_edge ) {
+         // wait for static array initialization loop to complete
+         if (wait_for_init) {
+            if (done_flag_used && (catapult_done.read() == 1)) wait_for_init = false;
+         } else {
+            if (((out_state >= max_state) && (init_interval || !done_flag_used)) || (done_flag_used && ((catapult_done.read() == 1) && (last_done == SC_LOGIC_0)))) {
+               out_sync.write(SC_LOGIC_1);
+               inout_sync.write(SC_LOGIC_1);
+               out_state = 0;
+               if (!init_interval) last_done = SC_LOGIC_1;
+               if (init_interval == 0) in_state = max_state; // force in_sync to align with out_sync
+            } else {
+               if ( (init_interval == 0) && (catapult_done.read() == 0) && (last_done == SC_LOGIC_1) ) last_done = SC_LOGIC_0;
+               out_sync.write(SC_LOGIC_0);
+               inout_sync.write(SC_LOGIC_0);
+            }
+            out_state++;
+         } // if (wait_for_init)
+      } // if (clk.read() == active_edge)
+   
+      if ( clk.read() == active_edge ) {
+         // wait for static array initialization loop to complete
+         if (wait_for_init) {
+            if (done_flag_used && (catapult_done.read() == 1)) wait_for_init = false;
+         } else {
+            if ( in_state >= max_state ) {
+               in_sync.write(SC_LOGIC_1);
+               inout_sync.write(SC_LOGIC_1);
+               catapult_start.write(SC_LOGIC_1);
+               in_state = 0;
+            } else {
+               if ( in_state == 1 ) {
+                  catapult_start.write(SC_LOGIC_1);
+               }
+               in_sync.write(SC_LOGIC_0);
+               inout_sync.write(SC_LOGIC_0);
+               catapult_start.write(SC_LOGIC_0);
+            }
+            in_state++;
+         }
+      }
+     } // if (done_flag_used)
+   }
+}
+// ---------------------------------------------------------------
+// Process: SC_METHOD generate_reset
+// Static sensitivity: sensitive << reset_deactivation_event;
+
+void scverify_top::generate_reset() {
+      static bool first = true;
+      if (first || sc_time_stamp() == SC_ZERO_TIME)
+      {
+         setup_debug();
+         first = false;
+         rst.write(SC_LOGIC_1);
+         reset_deactivation_event.notify(40.0, SC_NS);
+         TLS_en.write(SC_LOGIC_1);
+      } else {
+         input_a_transactor->reset_streams();
+         input_b_transactor->reset_streams();
+         output_transactor->reset_streams();
+         rst.write(SC_LOGIC_0);
+      }
+   
+}
+#if defined(MC_SIMULATOR_OSCI) || defined(MC_SIMULATOR_VCS)
+int sc_main(int argc, char *argv[])
+{
+   sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
+   scverify_top scverify_top("scverify_top");
+   sc_start();
+   return scverify_top.testbench_INST->failed();
+}
+#else
+MC_MODULE_EXPORT(scverify_top);
+#endif
diff --git a/dot_product/dot_product/dot_product.v9/scverify/scverify_top.h b/dot_product/dot_product/dot_product.v9/scverify/scverify_top.h
new file mode 100644
index 0000000..9f28379
--- /dev/null
+++ b/dot_product/dot_product/dot_product.v9/scverify/scverify_top.h
@@ -0,0 +1,274 @@
+// ----------------------------------------------------------------------------
+// SystemC Header for Top
+//
+//    HLS version: 2011a.126 Production Release
+//       HLS date: Wed Aug  8 00:52:07 PDT 2012
+//  Flow Packages: HDL_Tcl 2008a.1, SCVerify 2009a.1
+//
+//   Generated by: mg3115@EEWS104A-015
+// Generated date: Tue Mar 01 14:54:47 +0000 2016
+//
+// ----------------------------------------------------------------------------
+// 
+// -------------------------------------
+// scverify_top
+// top module instantiating reference design,
+// DUT and comparator
+// -------------------------------------
+// 
+#ifndef INCLUDED_SCVERIFY_TOP_H
+#define INCLUDED_SCVERIFY_TOP_H
+
+#ifndef TO_QUOTED_STRING
+#define TO_QUOTED_STRING(x) TO_QUOTED_STRING1(x)
+#define TO_QUOTED_STRING1(x) #x
+#endif
+#ifndef TOP_HDL_ENTITY
+#define TOP_HDL_ENTITY dot_product
+#endif
+
+// Hold time for the SCVerify testbench to account for the gate delay after downstream synthesis in pico second(s)
+// Hold time value is obtained from 'top_gate_constraints.cpp', which is generated at the end of RTL synthesis
+#ifdef CCS_DUT_GATE
+extern double __scv_hold_time;
+extern double __scv_hold_time_RSCID_1;
+extern double __scv_hold_time_RSCID_2;
+extern double __scv_hold_time_RSCID_3;
+#else
+double __scv_hold_time = 0.0; // default for non-gate simulation is zero
+double __scv_hold_time_RSCID_1 = 0.0;
+double __scv_hold_time_RSCID_2 = 0.0;
+double __scv_hold_time_RSCID_3 = 0.0;
+#endif
+
+
+#include "mc_testbench.h"
+#include "mc_reset.h"
+#include "mc_transactors.h"
+#include "mgc_ioport_trans_rsc.h"
+#include "mc_monitor.h"
+#include "mc_dut_wrapper.h"
+
+
+class scverify_top : public sc_module
+{
+public:
+   // Interface Ports
+   
+   // Data objects
+   sc_event deadlock_event;
+   sc_signal< sc_logic >                      deadlocked;
+   sc_event reset_deactivation_event;
+   sc_signal< sc_logic >                      rst;
+   sc_signal< sc_logic >                      rst_n;
+   bool var_trdone;
+   sc_clock clk;
+   sc_signal< sc_logic >                      TLS_arst_n;
+   sc_signal< sc_logic >                      in_sync;
+   sc_signal< sc_logic >                      out_sync;
+   sc_signal< sc_logic >                      inout_sync;
+   sc_signal< unsigned >                      wait_for_init;
+   sc_signal< sc_logic >                      catapult_start;
+   sc_signal< sc_logic >                      catapult_done;
+   sc_signal< sc_logic >                      catapult_ready;
+   sc_signal< sc_logic >                      TLS_en;
+   sc_signal< sc_lv<8> >                      TLS_input_a_rsc_z;
+   sc_signal< sc_lv<8> >                      TLS_input_b_rsc_z;
+   sc_signal< sc_lv<8> >                      TLS_output_rsc_z;
+   tlm::tlm_fifo< mc_wait_ctrl > TLS_in_wait_ctrl_fifo_input_a;
+   tlm::tlm_fifo< ac_int<8, true > > TLS_fifo_in_input_a;
+   tlm::tlm_fifo< mc_wait_ctrl > TLS_in_wait_ctrl_fifo_input_b;
+   tlm::tlm_fifo< ac_int<8, true > > TLS_fifo_in_input_b;
+   tlm::tlm_fifo< mc_wait_ctrl > TLS_out_wait_ctrl_fifo_output;
+   tlm::tlm_fifo< ac_int<8, true > > TLS_fifo_out_output;
+   
+   // Named Objects
+   
+   // Module instance pointers
+   ccs_DUT_wrapper *dot_product_INST;
+   mc_programmable_reset *arst_n_driver;
+   mgc_in_wire_trans_rsc< 5,8 > *input_a_rsc_INST;
+   mgc_in_wire_trans_rsc< 5,8 > *input_b_rsc_INST;
+   mgc_out_stdreg_trans_rsc< 1,8 > *output_rsc_INST;
+   mc_input_transactor<ac_int<8, true >,8,true> *input_a_transactor;
+   mc_input_transactor<ac_int<8, true >,8,true> *input_b_transactor;
+   mc_output_transactor<ac_int<8, true >,8,true> *output_transactor;
+   testbench *testbench_INST;
+   
+   // Declare processes (SC_METHOD and SC_THREAD)
+   void deadlock_notify();
+   void deadlock_watch();
+   void generate_sync();
+   void generate_reset();
+   
+   // Constructor
+   SC_HAS_PROCESS(scverify_top);
+   scverify_top(
+      const sc_module_name& name
+   )
+      : deadlocked("deadlocked")
+      , rst("rst")
+      , rst_n("rst_n")
+      , var_trdone(false)
+      , clk("clk",20.000000,SC_NS,0.5,0.000000,SC_NS,false)
+      , TLS_arst_n("TLS_arst_n")
+      , in_sync("in_sync")
+      , out_sync("out_sync")
+      , inout_sync("inout_sync")
+      , wait_for_init("wait_for_init")
+      , catapult_start("catapult_start")
+      , catapult_done("catapult_done")
+      , catapult_ready("catapult_ready")
+      , TLS_en("TLS_en")
+      , TLS_input_a_rsc_z("TLS_input_a_rsc_z")
+      , TLS_input_b_rsc_z("TLS_input_b_rsc_z")
+      , TLS_output_rsc_z("TLS_output_rsc_z")
+      , TLS_in_wait_ctrl_fifo_input_a("TLS_in_wait_ctrl_fifo_input_a",-1)
+      , TLS_fifo_in_input_a("TLS_fifo_in_input_a",-1)
+      , TLS_in_wait_ctrl_fifo_input_b("TLS_in_wait_ctrl_fifo_input_b",-1)
+      , TLS_fifo_in_input_b("TLS_fifo_in_input_b",-1)
+      , TLS_out_wait_ctrl_fifo_output("TLS_out_wait_ctrl_fifo_output",-1)
+      , TLS_fifo_out_output("TLS_fifo_out_output",-1)
+   {
+      // Instantiate other modules
+      dot_product_INST = new ccs_DUT_wrapper(
+         "rtl",
+         TO_QUOTED_STRING(TOP_HDL_ENTITY)
+      );
+      dot_product_INST->clk(clk);
+      dot_product_INST->en(TLS_en);
+      dot_product_INST->arst_n(TLS_arst_n);
+      dot_product_INST->input_a_rsc_z(TLS_input_a_rsc_z);
+      dot_product_INST->input_b_rsc_z(TLS_input_b_rsc_z);
+      dot_product_INST->output_rsc_z(TLS_output_rsc_z);
+      
+      arst_n_driver = new mc_programmable_reset(
+         "arst_n_driver",
+         40.0,
+         1
+      );
+      arst_n_driver->reset_out(TLS_arst_n);
+      
+      input_a_rsc_INST = new mgc_in_wire_trans_rsc< 5,8 > (
+         "input_a_rsc",
+         true
+      );
+      input_a_rsc_INST->z(TLS_input_a_rsc_z);
+      input_a_rsc_INST->clk(clk);
+      input_a_rsc_INST->add_attribute(*(new sc_attribute<double>("CLK_SKEW_DELAY", __scv_hold_time_RSCID_1 )));
+      
+      input_b_rsc_INST = new mgc_in_wire_trans_rsc< 5,8 > (
+         "input_b_rsc",
+         true
+      );
+      input_b_rsc_INST->z(TLS_input_b_rsc_z);
+      input_b_rsc_INST->clk(clk);
+      input_b_rsc_INST->add_attribute(*(new sc_attribute<double>("CLK_SKEW_DELAY", __scv_hold_time_RSCID_2 )));
+      
+      output_rsc_INST = new mgc_out_stdreg_trans_rsc< 1,8 > (
+         "output_rsc",
+         true
+      );
+      output_rsc_INST->z(TLS_output_rsc_z);
+      output_rsc_INST->clk(clk);
+      output_rsc_INST->add_attribute(*(new sc_attribute<double>("CLK_SKEW_DELAY", __scv_hold_time_RSCID_3 )));
+      
+      input_a_transactor = new mc_input_transactor<ac_int<8, true >,8,true> (
+         "transactor_input_a",
+         0,
+         8,
+         0,
+         false
+      );
+      input_a_transactor->in_wait_ctrl_fifo(TLS_in_wait_ctrl_fifo_input_a);
+      input_a_transactor->in_fifo(TLS_fifo_in_input_a);
+      input_a_transactor->add_attribute(*(new sc_attribute<int>("MC_TRANSACTOR_EVENT", MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT )));
+      input_a_transactor->bind_clk(clk,true);
+      input_a_transactor->register_block(input_a_rsc_INST,input_a_rsc_INST->basename(),in_sync,0,4,1);
+      
+      input_b_transactor = new mc_input_transactor<ac_int<8, true >,8,true> (
+         "transactor_input_b",
+         0,
+         8,
+         0,
+         false
+      );
+      input_b_transactor->in_wait_ctrl_fifo(TLS_in_wait_ctrl_fifo_input_b);
+      input_b_transactor->in_fifo(TLS_fifo_in_input_b);
+      input_b_transactor->add_attribute(*(new sc_attribute<int>("MC_TRANSACTOR_EVENT", MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT )));
+      input_b_transactor->bind_clk(clk,true);
+      input_b_transactor->register_block(input_b_rsc_INST,input_b_rsc_INST->basename(),in_sync,0,4,1);
+      
+      output_transactor = new mc_output_transactor<ac_int<8, true >,8,true> (
+         "transactor_output",
+         0,
+         8,
+         0
+      );
+      output_transactor->out_wait_ctrl_fifo(TLS_out_wait_ctrl_fifo_output);
+      output_transactor->out_fifo(TLS_fifo_out_output);
+      output_transactor->add_attribute(*(new sc_attribute<int>("MC_TRANSACTOR_EVENT", MC_TRANSACTOR_UNDERFLOW | MC_TRANSACTOR_WAIT )));
+      output_transactor->bind_clk(clk,true);
+      output_transactor->register_block(output_rsc_INST,output_rsc_INST->basename(),out_sync,0,0,1);
+      
+      testbench_INST = new testbench(
+         "user_tb"
+      );
+      testbench_INST->clk(clk);
+      testbench_INST->ccs_input_a(TLS_fifo_in_input_a);
+      testbench_INST->ccs_wait_ctrl_input_a(TLS_in_wait_ctrl_fifo_input_a);
+      testbench_INST->ccs_input_b(TLS_fifo_in_input_b);
+      testbench_INST->ccs_wait_ctrl_input_b(TLS_in_wait_ctrl_fifo_input_b);
+      testbench_INST->ccs_output(TLS_fifo_out_output);
+      testbench_INST->ccs_wait_ctrl_output(TLS_out_wait_ctrl_fifo_output);
+      
+      
+      // Register processes
+      SC_METHOD(deadlock_notify);
+      sensitive << deadlock_event;
+      dont_initialize();
+      SC_METHOD(deadlock_watch);
+      sensitive  << clk;
+      dont_initialize();
+      SC_METHOD(generate_sync);
+      sensitive << clk << rst;
+      dont_initialize();
+      SC_METHOD(generate_reset);
+      sensitive << reset_deactivation_event;
+      // Other constructor statements
+      // set seed for random number generator used by wait_ctrl
+      mt19937_init_genrand(19650218UL);
+      install_observe_foreign_signals();
+   }
+   
+   ~scverify_top()
+   {
+      delete dot_product_INST;
+      dot_product_INST = 0;
+      delete arst_n_driver;
+      arst_n_driver = 0;
+      delete input_a_rsc_INST;
+      input_a_rsc_INST = 0;
+      delete input_b_rsc_INST;
+      input_b_rsc_INST = 0;
+      delete output_rsc_INST;
+      output_rsc_INST = 0;
+      delete input_a_transactor;
+      input_a_transactor = 0;
+      delete input_b_transactor;
+      input_b_transactor = 0;
+      delete output_transactor;
+      output_transactor = 0;
+      delete testbench_INST;
+      testbench_INST = 0;
+   }
+   
+   // C++ class functions
+   public:
+      void setup_debug() ;
+   public:
+      void install_observe_foreign_signals() ;
+   public:
+      void debug(const char *varname, int flags, int count) ;
+};
+#endif
diff --git a/dot_product/dot_product/rtl (2).v b/dot_product/dot_product/rtl (2).v
new file mode 100644
index 0000000..fb3b8d5
--- /dev/null
+++ b/dot_product/dot_product/rtl (2).v
@@ -0,0 +1,163 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 15:39:39 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg exit_MAC_lpi;
+  reg [7:0] acc_sva_1;
+  reg [2:0] i_1_sva_1;
+  wire [2:0] MAC_acc_itm;
+  wire [3:0] nl_MAC_acc_itm;
+  wire [7:0] acc_sva_2;
+  wire [8:0] nl_acc_sva_2;
+  wire [2:0] i_1_sva_2;
+  wire [3:0] nl_i_1_sva_2;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign nl_acc_sva_2 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
+      * input_b_rsc_mgc_in_wire_d);
+  assign acc_sva_2 = nl_acc_sva_2[7:0];
+  assign nl_i_1_sva_2 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
+  assign i_1_sva_2 = nl_i_1_sva_2[2:0];
+  assign nl_MAC_acc_itm = i_1_sva_2 + 3'b11;
+  assign MAC_acc_itm = nl_MAC_acc_itm[2:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      output_rsc_mgc_out_stdreg_d <= 8'b0;
+      acc_sva_1 <= 8'b0;
+      i_1_sva_1 <= 3'b0;
+      exit_MAC_lpi <= 1'b1;
+    end
+    else begin
+      if ( en ) begin
+        output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({acc_sva_2 , output_rsc_mgc_out_stdreg_d},
+            MAC_acc_itm[2]);
+        acc_sva_1 <= acc_sva_2;
+        i_1_sva_1 <= i_1_sva_2;
+        exit_MAC_lpi <= ~ (MAC_acc_itm[2]);
+      end
+    end
+  end
+
+  function [7:0] signext_8_1;
+    input [0:0] vector;
+  begin
+    signext_8_1= {{7{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [2:0] signext_3_1;
+    input [0:0] vector;
+  begin
+    signext_3_1= {{2{vector[0]}}, vector};
+  end
+  endfunction
+
+
+  function [7:0] MUX_v_8_2_2;
+    input [15:0] inputs;
+    input [0:0] sel;
+    reg [7:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[15:8];
+      end
+      1'b1 : begin
+        result = inputs[7:0];
+      end
+      default : begin
+        result = inputs[15:8];
+      end
+    endcase
+    MUX_v_8_2_2 = result;
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_16_8 ;
+    input signed [15:0]  vector ;
+  begin
+    conv_s2s_16_8 = vector[7:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/rtl.v b/dot_product/dot_product/rtl.v
new file mode 100644
index 0000000..313b127
--- /dev/null
+++ b/dot_product/dot_product/rtl.v
@@ -0,0 +1,219 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   mg3115@EEWS104A-015
+//  Generated date: Tue Mar 01 14:54:51 2016
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core_fsm
+//  FSM Module
+// ------------------------------------------------------------------
+
+
+module dot_product_core_fsm (
+  clk, en, arst_n, fsm_output
+);
+  input clk;
+  input en;
+  input arst_n;
+  output [5:0] fsm_output;
+  reg [5:0] fsm_output;
+
+
+  // FSM State Type Declaration for dot_product_core_fsm_1
+  parameter
+    st_main = 3'd0,
+    st_main_1 = 3'd1,
+    st_main_2 = 3'd2,
+    st_main_3 = 3'd3,
+    st_main_4 = 3'd4,
+    st_main_5 = 3'd5,
+    state_x = 3'b000;
+
+  reg [2:0] state_var;
+  reg [2:0] state_var_NS;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  always @(*)
+  begin : dot_product_core_fsm_1
+    case (state_var)
+      st_main : begin
+        fsm_output = 6'b1;
+        state_var_NS = st_main_1;
+      end
+      st_main_1 : begin
+        fsm_output = 6'b10;
+        state_var_NS = st_main_2;
+      end
+      st_main_2 : begin
+        fsm_output = 6'b100;
+        state_var_NS = st_main_3;
+      end
+      st_main_3 : begin
+        fsm_output = 6'b1000;
+        state_var_NS = st_main_4;
+      end
+      st_main_4 : begin
+        fsm_output = 6'b10000;
+        state_var_NS = st_main_5;
+      end
+      st_main_5 : begin
+        fsm_output = 6'b100000;
+        state_var_NS = st_main;
+      end
+      default : begin
+        fsm_output = 6'b000000;
+        state_var_NS = st_main;
+      end
+    endcase
+  end
+
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      state_var <= st_main;
+    end
+    else if ( en ) begin
+      state_var <= state_var_NS;
+    end
+  end
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product_core
+// ------------------------------------------------------------------
+
+
+module dot_product_core (
+  clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [7:0] input_a_rsc_mgc_in_wire_d;
+  input [7:0] input_b_rsc_mgc_in_wire_d;
+  output [7:0] output_rsc_mgc_out_stdreg_d;
+  reg [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  wire [5:0] fsm_output;
+  reg [7:0] MAC_4_mul_itm;
+  reg [7:0] MAC_acc_6_itm;
+  reg [7:0] MAC_acc_itm;
+  wire [7:0] z_out;
+  wire [8:0] nl_z_out;
+  wire [7:0] MAC_4_mul_itm_1;
+  wire [15:0] nl_MAC_4_mul_itm_1;
+
+  wire[7:0] mux_2_nl;
+
+  // Interconnect Declarations for Component Instantiations 
+  dot_product_core_fsm dot_product_core_fsm_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .fsm_output(fsm_output)
+    );
+  assign nl_MAC_4_mul_itm_1 = input_a_rsc_mgc_in_wire_d * input_b_rsc_mgc_in_wire_d;
+  assign MAC_4_mul_itm_1 = nl_MAC_4_mul_itm_1[7:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      output_rsc_mgc_out_stdreg_d <= 8'b0;
+      MAC_4_mul_itm <= 8'b0;
+      MAC_acc_6_itm <= 8'b0;
+      MAC_acc_itm <= 8'b0;
+    end
+    else begin
+      if ( en ) begin
+        output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({output_rsc_mgc_out_stdreg_d ,
+            (MAC_acc_itm + z_out)}, fsm_output[4]);
+        MAC_4_mul_itm <= MAC_4_mul_itm_1;
+        MAC_acc_6_itm <= z_out;
+        MAC_acc_itm <= MUX_v_8_2_2({MAC_acc_itm , z_out}, fsm_output[2]);
+      end
+    end
+  end
+  assign mux_2_nl = MUX_v_8_2_2({MAC_4_mul_itm , MAC_acc_6_itm}, fsm_output[2]);
+  assign nl_z_out = (mux_2_nl) + MAC_4_mul_itm_1;
+  assign z_out = nl_z_out[7:0];
+
+  function [7:0] MUX_v_8_2_2;
+    input [15:0] inputs;
+    input [0:0] sel;
+    reg [7:0] result;
+  begin
+    case (sel)
+      1'b0 : begin
+        result = inputs[15:8];
+      end
+      1'b1 : begin
+        result = inputs[7:0];
+      end
+      default : begin
+        result = inputs[15:8];
+      end
+    endcase
+    MUX_v_8_2_2 = result;
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    dot_product
+//  Generated from file(s):
+//    2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
+// ------------------------------------------------------------------
+
+
+module dot_product (
+  input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
+);
+  input [7:0] input_a_rsc_z;
+  input [7:0] input_b_rsc_z;
+  output [7:0] output_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [7:0] input_a_rsc_mgc_in_wire_d;
+  wire [7:0] input_b_rsc_mgc_in_wire_d;
+  wire [7:0] output_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(8)) input_a_rsc_mgc_in_wire (
+      .d(input_a_rsc_mgc_in_wire_d),
+      .z(input_a_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(8)) input_b_rsc_mgc_in_wire (
+      .d(input_b_rsc_mgc_in_wire_d),
+      .z(input_b_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(3),
+  .width(8)) output_rsc_mgc_out_stdreg (
+      .d(output_rsc_mgc_out_stdreg_d),
+      .z(output_rsc_z)
+    );
+  dot_product_core dot_product_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
+      .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
+      .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/dot_product/dot_product/rtl_mgc_ioport (2).v b/dot_product/dot_product/rtl_mgc_ioport (2).v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/dot_product/dot_product/rtl_mgc_ioport (2).v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/dot_product/dot_product/rtl_mgc_ioport.v b/dot_product/dot_product/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/dot_product/dot_product/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v b/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/dot_product/dot_product/rtl_mgc_ioport_v2001.v b/dot_product/dot_product/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/dot_product/dot_product/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015.zip b/student_files_2015.zip
new file mode 100644
index 0000000..56639ce
--- /dev/null
+++ b/student_files_2015.zip
diff --git a/student_files_2015/__MACOSX/student_files_2015/._.DS_Store b/student_files_2015/__MACOSX/student_files_2015/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/._.DS_Store
diff --git a/student_files_2015/__MACOSX/student_files_2015/._launch_catapult.bat b/student_files_2015/__MACOSX/student_files_2015/._launch_catapult.bat
new file mode 100644
index 0000000..14f037e
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/._launch_catapult.bat
diff --git a/student_files_2015/__MACOSX/student_files_2015/._prj1 b/student_files_2015/__MACOSX/student_files_2015/._prj1
new file mode 100644
index 0000000..9e21eaa
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/._prj1
diff --git a/student_files_2015/__MACOSX/student_files_2015/._prj2 b/student_files_2015/__MACOSX/student_files_2015/._prj2
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/._prj2
diff --git a/student_files_2015/__MACOSX/student_files_2015/DE0_user_manual/._.DS_Store b/student_files_2015/__MACOSX/student_files_2015/DE0_user_manual/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/DE0_user_manual/._.DS_Store
diff --git a/student_files_2015/__MACOSX/student_files_2015/DE0_user_manual/._DE0_User_manual_2012.pdf b/student_files_2015/__MACOSX/student_files_2015/DE0_user_manual/._DE0_User_manual_2012.pdf
new file mode 100644
index 0000000..f706d5e
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/DE0_user_manual/._DE0_User_manual_2012.pdf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/._.DS_Store b/student_files_2015/__MACOSX/student_files_2015/prj1/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/._.DS_Store
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/._dot_product_source b/student_files_2015/__MACOSX/student_files_2015/prj1/._dot_product_source
new file mode 100644
index 0000000..9e21eaa
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/._dot_product_source
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/._quartus_proj_DE0 b/student_files_2015/__MACOSX/student_files_2015/prj1/._quartus_proj_DE0
new file mode 100644
index 0000000..c6b7c72
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/._quartus_proj_DE0
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.cpp b/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.cpp
new file mode 100644
index 0000000..5ddb363
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.cpp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.h b/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.h
new file mode 100644
index 0000000..5ddb363
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._tb_dot_product.cpp b/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._tb_dot_product.cpp
new file mode 100644
index 0000000..5ddb363
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/dot_product_source/._tb_dot_product.cpp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._.DS_Store b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._.DS_Store
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.bdf b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.bdf
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.bdf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.pin b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.pin
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.pin
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qpf b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qpf
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qpf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qsf b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qsf
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/._.DS_Store b/student_files_2015/__MACOSX/student_files_2015/prj2/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/._.DS_Store
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/._catapult_proj b/student_files_2015/__MACOSX/student_files_2015/prj2/._catapult_proj
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/._catapult_proj
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/._instructions.doc b/student_files_2015/__MACOSX/student_files_2015/prj2/._instructions.doc
new file mode 100644
index 0000000..43630d1
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/._instructions.doc
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/._quartus_proj b/student_files_2015/__MACOSX/student_files_2015/prj2/._quartus_proj
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/._quartus_proj
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._.DS_Store b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._.DS_Store
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_blur b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_blur
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_blur
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_mouse b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_mouse
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_mouse
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.c b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.c
new file mode 100644
index 0000000..1ba2247
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.c
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.h b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.cpp b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.cpp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.cpp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.h b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._shift_class.h b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._shift_class.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._shift_class.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._tb_blur.cpp b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._tb_blur.cpp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._tb_blur.cpp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_mouse/._vga_mouse_square.c b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_mouse/._vga_mouse_square.c
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/catapult_proj/vga_mouse/._vga_mouse_square.c
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA_MOUSE b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA_MOUSE
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA_MOUSE
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Copy of DE1_D5M.qsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Copy of DE1_D5M.qsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Copy of DE1_D5M.qsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.asm.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.asm.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.asm.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.done b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.done
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.done
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.smsg b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.smsg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.smsg
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.summary b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.summary
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.flow.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.flow.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.flow.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.jdi b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.jdi
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.jdi
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.summary b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.summary
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pin b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pin
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pin
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pof b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pof
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qpf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qpf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qpf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qws b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qws
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qws
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sdc b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sdc
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sdc
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sof b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sof
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.summary b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.summary
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.tis_db_list.ddb b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE1_D5M_assignment_defaults.qdf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE1_D5M_assignment_defaults.qdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE1_D5M_assignment_defaults.qdf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Line_Buffer.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Line_Buffer.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Line_Buffer.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_Control_4Port b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_Control_4Port
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_Control_4Port
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_FIFO.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_FIFO.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._TOP_CAMERA.bdf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._TOP_CAMERA.bdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._TOP_CAMERA.bdf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._V b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._V
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._V
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._demo batch b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._demo batch
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._demo batch
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._greybox_tmp b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._greybox_tmp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._greybox_tmp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._qmegawiz_errors_log.txt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._qmegawiz_errors_log.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._qmegawiz_errors_log.txt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._sdram_pll.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._sdram_pll.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Control_4Port.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Control_4Port.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Control_4Port.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Params.h b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Params.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Params.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._command.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._command.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._command.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._control_interface.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._control_interface.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._control_interface.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._sdr_data_path.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._sdr_data_path.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._sdr_data_path.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._CCD_Capture.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._CCD_Capture.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._CCD_Capture.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_Controller.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_Controller.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._RAW2RGB.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._RAW2RGB.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._RAW2RGB.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Reset_Delay.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Reset_Delay.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Reset_Delay.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT_8.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT_8.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT_8.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Controller.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Controller.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Param.h b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Param.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Param.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.ppf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.ppf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.ppf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_wave0.jpg b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_wave0.jpg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_wave0.jpg
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_waveforms.html b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_waveforms.html
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_waveforms.html
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.bat b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.bat
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.bat
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.sof b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.sof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.sof
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/._cbx_args.txt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/._cbx_args.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/._cbx_args.txt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.asm.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.asm.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.asm.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.cdf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.cdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.cdf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.done b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.done
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.done
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.smsg b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.smsg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.smsg
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.summary b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.summary
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.flow.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.flow.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.flow.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.jdi b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.jdi
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.jdi
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.summary b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.summary
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pin b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pin
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pin
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pof b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pof
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qpf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qpf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qpf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qws b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qws
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qws
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sdc b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sdc
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sdc
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sof b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sof
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.rpt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.rpt
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.summary b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.summary
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.tis_db_list.ddb b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Line_Buffer.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Line_Buffer.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Line_Buffer.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_Control_4Port b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_Control_4Port
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_Control_4Port
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_FIFO.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_FIFO.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._V b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._V
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._V
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._catapult_ip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._catapult_ip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._catapult_ip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._greybox_tmp b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._greybox_tmp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._greybox_tmp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga_core.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga_core.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga_core.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._ps2.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._ps2.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._ps2.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._sdram_pll.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._sdram_pll.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square_core.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square_core.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square_core.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.cmp b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.cmp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.cmp
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.vhd b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.vhd
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.vhd
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Control_4Port.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Control_4Port.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Control_4Port.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Params.h b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Params.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Params.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._command.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._command.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._command.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._control_interface.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._control_interface.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._control_interface.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._sdr_data_path.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._sdr_data_path.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._sdr_data_path.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._CCD_Capture.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._CCD_Capture.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._CCD_Capture.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_Controller.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_Controller.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._RAW2RGB.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._RAW2RGB.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._RAW2RGB.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Reset_Delay.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Reset_Delay.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Reset_Delay.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT_8.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT_8.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT_8.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._TOP_DE0_CAMERA_MOUSE.bdf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._TOP_DE0_CAMERA_MOUSE.bdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._TOP_DE0_CAMERA_MOUSE.bdf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Param.h b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Param.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Param.h
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._ps2.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._ps2.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._ps2.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.bsf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.bsf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.ppf b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.ppf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.ppf
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.qip b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.qip
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v.bak b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v.bak
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3 b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v
diff --git a/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt
diff --git a/student_files_2015/student_files_2015/.DS_Store b/student_files_2015/student_files_2015/.DS_Store
new file mode 100644
index 0000000..2095bfd
--- /dev/null
+++ b/student_files_2015/student_files_2015/.DS_Store
diff --git a/student_files_2015/student_files_2015/DE0_user_manual/.DS_Store b/student_files_2015/student_files_2015/DE0_user_manual/.DS_Store
new file mode 100644
index 0000000..5008ddf
--- /dev/null
+++ b/student_files_2015/student_files_2015/DE0_user_manual/.DS_Store
diff --git a/student_files_2015/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf b/student_files_2015/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf
new file mode 100644
index 0000000..c4831e1
--- /dev/null
+++ b/student_files_2015/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf
diff --git a/student_files_2015/student_files_2015/launch_catapult.bat b/student_files_2015/student_files_2015/launch_catapult.bat
new file mode 100644
index 0000000..f6e649e
--- /dev/null
+++ b/student_files_2015/student_files_2015/launch_catapult.bat
@@ -0,0 +1,3 @@
+@echo off
+set Path=
+"C:\Program Files\Calypto Design Systems\Catapult Synthesis 2011a.126 Production Release\Mgc_home\bin\catapult.exe"
diff --git a/student_files_2015/student_files_2015/prj1/.DS_Store b/student_files_2015/student_files_2015/prj1/.DS_Store
new file mode 100644
index 0000000..fd7d3a6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
new file mode 100644
index 0000000..8fc78d5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
@@ -0,0 +1,39 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           dot_product.cpp
+//  Description:    dot product calculator
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+#include "dot_product.h"
+#include "stdio.h"
+
+#pragma design top
+void dot_product(ac_int<8> *input_a, ac_int<8> *input_b, ac_int<8> *output) {
+  ac_int<8> acc = 0;
+  int i; 
+
+  MAC: for(i = 0; i < VECTOR_LEN; i++) {
+    acc += input_a[i] * *(input_b + i); 
+    /* you can access the values in the vector in either way: var[i] = *(var + i) */
+  }
+  *output = acc;
+}
+
+
+// end of file
diff --git a/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
new file mode 100644
index 0000000..e67cc7f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h
@@ -0,0 +1,35 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           dot_product.h
+//  Description:    dot product calculator
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _DOT_PROD_H
+#define _DOT_PROD_H
+
+#include "ac_int.h"
+
+#define VECTOR_LEN 5
+
+void dot_product(ac_int<8> *input_a, ac_int<8> *input_b, ac_int<8> *output);
+
+#endif
+
+// end of file
diff --git a/student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp b/student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
new file mode 100644
index 0000000..7f382cd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
@@ -0,0 +1,51 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_dot_product.cpp
+//  Description:    dot product calculator testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+#include "dot_product.h"
+#include <mc_scverify.h>
+
+CCS_MAIN(int argc, char *argv[])
+{
+  ac_int<8> inA[VECTOR_LEN] = {1,2,3,4,5};
+  ac_int<8> inB[VECTOR_LEN] = {5,4,3,2,1};
+  ac_int<8> output;
+  int i, exp_out;
+
+  // Test design
+  CCS_DESIGN(dot_product)(inA,inB,&output);
+
+  // Expected result  
+  exp_out = 0;
+  for(i = 0; i < VECTOR_LEN; i++) {
+    exp_out += inA[i] * inB[i];
+  }
+
+  // Display results
+  for(i = 0; i < VECTOR_LEN; i++) {
+    printf ("Inputs: A = %d, B = %d \n", (int)inA[i], (int)inB[i]);
+  }
+  printf ("Design output  : %d \n", (int)output);
+  printf ("Expected output: %d \n", exp_out);
+   
+  CCS_RETURN(0);
+}
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/.DS_Store b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/.DS_Store
new file mode 100644
index 0000000..5008ddf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.cdb
new file mode 100644
index 0000000..f17ff5c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.hdb
new file mode 100644
index 0000000..5b2fc5a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.cdb
new file mode 100644
index 0000000..5f275ae
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.hdb
new file mode 100644
index 0000000..a4b3c2e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.cdb
new file mode 100644
index 0000000..170554e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.hdb
new file mode 100644
index 0000000..c2deb00
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.cdb
new file mode 100644
index 0000000..b8eaa8c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.hdb
new file mode 100644
index 0000000..c2deb00
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.cdb
new file mode 100644
index 0000000..16b4ad9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.hdb
new file mode 100644
index 0000000..adadbad
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.cdb
new file mode 100644
index 0000000..eb51587
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.hdb
new file mode 100644
index 0000000..2cc297f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.cdb
new file mode 100644
index 0000000..cb00fd8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.hdb
new file mode 100644
index 0000000..48c6949
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.cdb
new file mode 100644
index 0000000..ef54552
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.hdb
new file mode 100644
index 0000000..c7d7dac
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(8).cnf.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(8).cnf.cdb
new file mode 100644
index 0000000..dea2046
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(8).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(8).cnf.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(8).cnf.hdb
new file mode 100644
index 0000000..4cd64e4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(8).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.bpm b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.bpm
new file mode 100644
index 0000000..7b721a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.bpm
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.cdb
new file mode 100644
index 0000000..d68105a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.hdb
new file mode 100644
index 0000000..2dcb7fa
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.qmsg b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.qmsg
new file mode 100644
index 0000000..8dd7e97
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848312273 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848312274 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:05:11 2016 " "Processing started: Tue Mar 01 16:05:11 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848312274 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456848312274 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456848312274 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456848312922 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456848312942 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "424 " "Peak virtual memory: 424 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848313176 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:13 2016 " "Processing ended: Tue Mar 01 16:05:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848313176 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848313176 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848313176 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456848313176 ""}
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.rdb
new file mode 100644
index 0000000..fc98213
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm_labs.ddb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm_labs.ddb
new file mode 100644
index 0000000..002bf67
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm_labs.ddb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cbx.xml b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cbx.xml
new file mode 100644
index 0000000..1aca15d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cbx.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ise_proj">
+	</PROJECT>
+</LOG_ROOT>
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.bpm b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.bpm
new file mode 100644
index 0000000..7b721a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.bpm
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.cdb
new file mode 100644
index 0000000..905f4c4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.hdb
new file mode 100644
index 0000000..d1dc9ef
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.idb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.idb
new file mode 100644
index 0000000..efb6ff7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.idb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.kpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.kpt
new file mode 100644
index 0000000..a6e2c9a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.kpt
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.logdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.logdb
new file mode 100644
index 0000000..1799878
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.logdb
@@ -0,0 +1,93 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,48;0;48;0;0;51;48;0;51;51;0;3;0;0;17;0;3;17;0;0;0;3;0;0;0;0;0;51;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,3;51;3;51;51;0;3;51;0;0;51;48;51;51;34;51;48;34;51;51;51;48;51;51;51;51;51;0;51;51,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,VGA_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_SYNC,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_BLANK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_VS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_HS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_MSDAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_MSCLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50_2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BUTTON[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BUTTON[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BUTTON[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.rdb
new file mode 100644
index 0000000..36a5c87
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp_merge.kpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp_merge.kpt
new file mode 100644
index 0000000..3f1d0e8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp_merge.kpt
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..da9e360
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..759dcc7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.db_info b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.db_info
new file mode 100644
index 0000000..9b47fd8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 01 16:04:52 2016
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.eco.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.eco.cdb
new file mode 100644
index 0000000..74d5728
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.eco.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.fit.qmsg b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.fit.qmsg
new file mode 100644
index 0000000..4b18963
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.fit.qmsg
@@ -0,0 +1,51 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456848306819 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ise_proj EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"ise_proj\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456848307039 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456848307089 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456848307089 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456848307089 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456848307157 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456848307344 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456848307344 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456848307344 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456848307344 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 452 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848307346 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 454 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848307346 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 456 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848307346 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 458 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848307346 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456848307346 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456848307347 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 51 " "No exact pin location assignment(s) for 3 pins of 51 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_CLK " "Pin VGA_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_CLK } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 680 32 208 696 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 52 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456848308059 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_SYNC " "Pin VGA_SYNC not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_SYNC } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 656 32 208 672 "VGA_SYNC" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_SYNC } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 53 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456848308059 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_BLANK " "Pin VGA_BLANK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_BLANK } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 632 32 208 648 "VGA_BLANK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_BLANK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 54 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456848308059 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456848308059 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ise_proj.sdc " "Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456848308182 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456848308183 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Fitter" 0 -1 1456848308183 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1456848308183 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456848308184 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456848308184 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456848308184 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456848308185 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456848308185 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456848308185 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456848308186 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456848308186 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456848308186 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456848308186 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456848308186 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456848308187 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456848308187 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456848308187 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 2.5V 0 3 0 " "Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 0 input, 3 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456848308195 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456848308195 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456848308195 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 27 6 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 2 44 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  44 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 15 28 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 8 39 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  39 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848308196 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456848308196 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456848308196 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA_0 " "Ignored I/O standard assignment to node \"DRAM_BA_0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA_1 " "Ignored I/O standard assignment to node \"DRAM_BA_1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_LDQM " "Ignored I/O standard assignment to node \"DRAM_LDQM\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_UDQM " "Ignored I/O standard assignment to node \"DRAM_UDQM\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_BYTE_N " "Ignored I/O standard assignment to node \"FL_BYTE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ15_AM1 " "Ignored I/O standard assignment to node \"FL_DQ15_AM1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[10\] " "Ignored I/O standard assignment to node \"FL_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[11\] " "Ignored I/O standard assignment to node \"FL_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[12\] " "Ignored I/O standard assignment to node \"FL_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[13\] " "Ignored I/O standard assignment to node \"FL_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[14\] " "Ignored I/O standard assignment to node \"FL_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[8\] " "Ignored I/O standard assignment to node \"FL_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[9\] " "Ignored I/O standard assignment to node \"FL_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[0\] " "Ignored I/O standard assignment to node \"GPIO0_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[10\] " "Ignored I/O standard assignment to node \"GPIO0_D\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[11\] " "Ignored I/O standard assignment to node \"GPIO0_D\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[12\] " "Ignored I/O standard assignment to node \"GPIO0_D\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[13\] " "Ignored I/O standard assignment to node \"GPIO0_D\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[14\] " "Ignored I/O standard assignment to node \"GPIO0_D\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[15\] " "Ignored I/O standard assignment to node \"GPIO0_D\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[16\] " "Ignored I/O standard assignment to node \"GPIO0_D\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[17\] " "Ignored I/O standard assignment to node \"GPIO0_D\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[18\] " "Ignored I/O standard assignment to node \"GPIO0_D\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[19\] " "Ignored I/O standard assignment to node \"GPIO0_D\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[1\] " "Ignored I/O standard assignment to node \"GPIO0_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[20\] " "Ignored I/O standard assignment to node \"GPIO0_D\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[21\] " "Ignored I/O standard assignment to node \"GPIO0_D\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[22\] " "Ignored I/O standard assignment to node \"GPIO0_D\[22\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[22\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[23\] " "Ignored I/O standard assignment to node \"GPIO0_D\[23\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[23\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[24\] " "Ignored I/O standard assignment to node \"GPIO0_D\[24\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[24\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[25\] " "Ignored I/O standard assignment to node \"GPIO0_D\[25\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[25\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[26\] " "Ignored I/O standard assignment to node \"GPIO0_D\[26\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[26\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[27\] " "Ignored I/O standard assignment to node \"GPIO0_D\[27\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[27\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[28\] " "Ignored I/O standard assignment to node \"GPIO0_D\[28\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[28\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[29\] " "Ignored I/O standard assignment to node \"GPIO0_D\[29\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[29\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[2\] " "Ignored I/O standard assignment to node \"GPIO0_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[30\] " "Ignored I/O standard assignment to node \"GPIO0_D\[30\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[30\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[31\] " "Ignored I/O standard assignment to node \"GPIO0_D\[31\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[31\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[3\] " "Ignored I/O standard assignment to node \"GPIO0_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[4\] " "Ignored I/O standard assignment to node \"GPIO0_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[5\] " "Ignored I/O standard assignment to node \"GPIO0_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[6\] " "Ignored I/O standard assignment to node \"GPIO0_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[7\] " "Ignored I/O standard assignment to node \"GPIO0_D\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[8\] " "Ignored I/O standard assignment to node \"GPIO0_D\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[9\] " "Ignored I/O standard assignment to node \"GPIO0_D\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[0\] " "Ignored I/O standard assignment to node \"GPIO1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[10\] " "Ignored I/O standard assignment to node \"GPIO1_D\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[11\] " "Ignored I/O standard assignment to node \"GPIO1_D\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[12\] " "Ignored I/O standard assignment to node \"GPIO1_D\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[13\] " "Ignored I/O standard assignment to node \"GPIO1_D\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[14\] " "Ignored I/O standard assignment to node \"GPIO1_D\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[15\] " "Ignored I/O standard assignment to node \"GPIO1_D\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[16\] " "Ignored I/O standard assignment to node \"GPIO1_D\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[17\] " "Ignored I/O standard assignment to node \"GPIO1_D\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[18\] " "Ignored I/O standard assignment to node \"GPIO1_D\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[19\] " "Ignored I/O standard assignment to node \"GPIO1_D\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[1\] " "Ignored I/O standard assignment to node \"GPIO1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[20\] " "Ignored I/O standard assignment to node \"GPIO1_D\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[21\] " "Ignored I/O standard assignment to node \"GPIO1_D\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[22\] " "Ignored I/O standard assignment to node \"GPIO1_D\[22\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[22\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[23\] " "Ignored I/O standard assignment to node \"GPIO1_D\[23\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[23\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[24\] " "Ignored I/O standard assignment to node \"GPIO1_D\[24\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[24\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[25\] " "Ignored I/O standard assignment to node \"GPIO1_D\[25\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[25\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[26\] " "Ignored I/O standard assignment to node \"GPIO1_D\[26\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[26\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[27\] " "Ignored I/O standard assignment to node \"GPIO1_D\[27\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[27\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[28\] " "Ignored I/O standard assignment to node \"GPIO1_D\[28\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[28\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[29\] " "Ignored I/O standard assignment to node \"GPIO1_D\[29\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[29\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[2\] " "Ignored I/O standard assignment to node \"GPIO1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[30\] " "Ignored I/O standard assignment to node \"GPIO1_D\[30\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[30\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[31\] " "Ignored I/O standard assignment to node \"GPIO1_D\[31\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[31\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[3\] " "Ignored I/O standard assignment to node \"GPIO1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[4\] " "Ignored I/O standard assignment to node \"GPIO1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[5\] " "Ignored I/O standard assignment to node \"GPIO1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[6\] " "Ignored I/O standard assignment to node \"GPIO1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[7\] " "Ignored I/O standard assignment to node \"GPIO1_D\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[8\] " "Ignored I/O standard assignment to node \"GPIO1_D\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[9\] " "Ignored I/O standard assignment to node \"GPIO1_D\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_DP " "Ignored I/O standard assignment to node \"HEX0_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_DP " "Ignored I/O standard assignment to node \"HEX1_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[0\] " "Ignored I/O standard assignment to node \"HEX1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[1\] " "Ignored I/O standard assignment to node \"HEX1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[2\] " "Ignored I/O standard assignment to node \"HEX1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[3\] " "Ignored I/O standard assignment to node \"HEX1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[4\] " "Ignored I/O standard assignment to node \"HEX1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[5\] " "Ignored I/O standard assignment to node \"HEX1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[6\] " "Ignored I/O standard assignment to node \"HEX1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_DP " "Ignored I/O standard assignment to node \"HEX2_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[0\] " "Ignored I/O standard assignment to node \"HEX2_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[1\] " "Ignored I/O standard assignment to node \"HEX2_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[2\] " "Ignored I/O standard assignment to node \"HEX2_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[3\] " "Ignored I/O standard assignment to node \"HEX2_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[4\] " "Ignored I/O standard assignment to node \"HEX2_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[5\] " "Ignored I/O standard assignment to node \"HEX2_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[6\] " "Ignored I/O standard assignment to node \"HEX2_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_DP " "Ignored I/O standard assignment to node \"HEX3_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[0\] " "Ignored I/O standard assignment to node \"HEX3_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[1\] " "Ignored I/O standard assignment to node \"HEX3_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[2\] " "Ignored I/O standard assignment to node \"HEX3_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[3\] " "Ignored I/O standard assignment to node \"HEX3_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[4\] " "Ignored I/O standard assignment to node \"HEX3_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[5\] " "Ignored I/O standard assignment to node \"HEX3_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[6\] " "Ignored I/O standard assignment to node \"HEX3_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_BLON " "Ignored I/O standard assignment to node \"LCD_BLON\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[0\] " "Ignored I/O standard assignment to node \"LCD_DATA\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[1\] " "Ignored I/O standard assignment to node \"LCD_DATA\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[2\] " "Ignored I/O standard assignment to node \"LCD_DATA\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[3\] " "Ignored I/O standard assignment to node \"LCD_DATA\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[4\] " "Ignored I/O standard assignment to node \"LCD_DATA\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[5\] " "Ignored I/O standard assignment to node \"LCD_DATA\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[6\] " "Ignored I/O standard assignment to node \"LCD_DATA\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[7\] " "Ignored I/O standard assignment to node \"LCD_DATA\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RS " "Ignored I/O standard assignment to node \"LCD_RS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RW " "Ignored I/O standard assignment to node \"LCD_RW\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBCLK " "Ignored I/O standard assignment to node \"PS2_KBCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBDAT " "Ignored I/O standard assignment to node \"PS2_KBDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT0 " "Ignored I/O standard assignment to node \"SD_DAT0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT3 " "Ignored I/O standard assignment to node \"SD_DAT3\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848308220 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1456848308220 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_0 " "Node \"DRAM_BA_0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_1 " "Node \"DRAM_BA_1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_BYTE_N " "Node \"FL_BYTE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ15_AM1 " "Node \"FL_DQ15_AM1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[10\] " "Node \"FL_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[11\] " "Node \"FL_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[12\] " "Node \"FL_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[13\] " "Node \"FL_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[14\] " "Node \"FL_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[8\] " "Node \"FL_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[9\] " "Node \"FL_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Node \"GPIO0_CLKIN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Node \"GPIO0_CLKIN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Node \"GPIO0_CLKOUT\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Node \"GPIO0_CLKOUT\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[0\] " "Node \"GPIO0_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[10\] " "Node \"GPIO0_D\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[11\] " "Node \"GPIO0_D\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[12\] " "Node \"GPIO0_D\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[13\] " "Node \"GPIO0_D\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[14\] " "Node \"GPIO0_D\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[15\] " "Node \"GPIO0_D\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[16\] " "Node \"GPIO0_D\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[17\] " "Node \"GPIO0_D\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[18\] " "Node \"GPIO0_D\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[19\] " "Node \"GPIO0_D\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[1\] " "Node \"GPIO0_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[20\] " "Node \"GPIO0_D\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[21\] " "Node \"GPIO0_D\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[22\] " "Node \"GPIO0_D\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[23\] " "Node \"GPIO0_D\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[24\] " "Node \"GPIO0_D\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[25\] " "Node \"GPIO0_D\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[26\] " "Node \"GPIO0_D\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[27\] " "Node \"GPIO0_D\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[28\] " "Node \"GPIO0_D\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[29\] " "Node \"GPIO0_D\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[2\] " "Node \"GPIO0_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[30\] " "Node \"GPIO0_D\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[31\] " "Node \"GPIO0_D\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[3\] " "Node \"GPIO0_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[4\] " "Node \"GPIO0_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[5\] " "Node \"GPIO0_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[6\] " "Node \"GPIO0_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[7\] " "Node \"GPIO0_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[8\] " "Node \"GPIO0_D\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[9\] " "Node \"GPIO0_D\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Node \"GPIO1_CLKIN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Node \"GPIO1_CLKIN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Node \"GPIO1_CLKOUT\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Node \"GPIO1_CLKOUT\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[0\] " "Node \"GPIO1_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[10\] " "Node \"GPIO1_D\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[11\] " "Node \"GPIO1_D\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[12\] " "Node \"GPIO1_D\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[13\] " "Node \"GPIO1_D\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[14\] " "Node \"GPIO1_D\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[15\] " "Node \"GPIO1_D\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[16\] " "Node \"GPIO1_D\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[17\] " "Node \"GPIO1_D\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[18\] " "Node \"GPIO1_D\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[19\] " "Node \"GPIO1_D\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[1\] " "Node \"GPIO1_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[20\] " "Node \"GPIO1_D\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[21\] " "Node \"GPIO1_D\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[22\] " "Node \"GPIO1_D\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[23\] " "Node \"GPIO1_D\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[24\] " "Node \"GPIO1_D\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[25\] " "Node \"GPIO1_D\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[26\] " "Node \"GPIO1_D\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[27\] " "Node \"GPIO1_D\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[28\] " "Node \"GPIO1_D\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[29\] " "Node \"GPIO1_D\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[2\] " "Node \"GPIO1_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[30\] " "Node \"GPIO1_D\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[31\] " "Node \"GPIO1_D\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[3\] " "Node \"GPIO1_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[4\] " "Node \"GPIO1_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[5\] " "Node \"GPIO1_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[6\] " "Node \"GPIO1_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[7\] " "Node \"GPIO1_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[8\] " "Node \"GPIO1_D\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[9\] " "Node \"GPIO1_D\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_N0 " "Node \"GPIO_CLKIN_N0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_N0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_N1 " "Node \"GPIO_CLKIN_N1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_N1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_P0 " "Node \"GPIO_CLKIN_P0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_P0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_P1 " "Node \"GPIO_CLKIN_P1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_P1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_N0 " "Node \"GPIO_CLKOUT_N0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_N0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_N1 " "Node \"GPIO_CLKOUT_N1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_N1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_P0 " "Node \"GPIO_CLKOUT_P0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_P0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_P1 " "Node \"GPIO_CLKOUT_P1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_P1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[7\] " "Node \"HEX0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[7\] " "Node \"HEX1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[0\] " "Node \"HEX1_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[1\] " "Node \"HEX1_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[2\] " "Node \"HEX1_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[3\] " "Node \"HEX1_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[4\] " "Node \"HEX1_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[5\] " "Node \"HEX1_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[6\] " "Node \"HEX1_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[7\] " "Node \"HEX2\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[0\] " "Node \"HEX2_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[1\] " "Node \"HEX2_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[2\] " "Node \"HEX2_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[3\] " "Node \"HEX2_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[4\] " "Node \"HEX2_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[5\] " "Node \"HEX2_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[6\] " "Node \"HEX2_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[7\] " "Node \"HEX3\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[0\] " "Node \"HEX3_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[1\] " "Node \"HEX3_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[2\] " "Node \"HEX3_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[3\] " "Node \"HEX3_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[4\] " "Node \"HEX3_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[5\] " "Node \"HEX3_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[6\] " "Node \"HEX3_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_KBCLK " "Node \"PS2_KBCLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_KBDAT " "Node \"PS2_KBDAT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT0 " "Node \"SD_DAT0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT3 " "Node \"SD_DAT3\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848308229 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1456848308229 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848308244 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456848308699 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848308742 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456848308750 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456848308890 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848308890 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456848309067 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456848309346 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456848309346 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848309415 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456848309416 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1456848309416 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456848309416 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456848309420 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456848309446 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456848309678 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456848309704 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456848309973 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848310285 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1456848310973 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "17 Cyclone III " "17 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_MSDAT 3.3-V LVTTL R22 " "Pin PS2_MSDAT uses I/O standard 3.3-V LVTTL at R22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_MSDAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_MSDAT" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 416 40 208 432 "PS2_MSDAT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_MSDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_MSCLK 3.3-V LVTTL R21 " "Pin PS2_MSCLK uses I/O standard 3.3-V LVTTL at R21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_MSCLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_MSCLK" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 440 40 208 456 "PS2_MSCLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_MSCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 58 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL G21 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 88 40 208 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 59 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50_2 3.3-V LVTTL B12 " "Pin CLOCK_50_2 uses I/O standard 3.3-V LVTTL at B12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50_2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 56 40 208 72 "CLOCK_50_2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 60 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BUTTON\[2\] 3.3-V LVTTL F1 " "Pin BUTTON\[2\] uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BUTTON[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[2\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BUTTON[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 39 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BUTTON\[1\] 3.3-V LVTTL G3 " "Pin BUTTON\[1\] uses I/O standard 3.3-V LVTTL at G3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BUTTON[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[1\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BUTTON[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 40 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BUTTON\[0\] 3.3-V LVTTL H2 " "Pin BUTTON\[0\] uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BUTTON[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[0\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BUTTON[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 41 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[9\] 3.3-V LVTTL D2 " "Pin SW\[9\] uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 42 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[8\] 3.3-V LVTTL E4 " "Pin SW\[8\] uses I/O standard 3.3-V LVTTL at E4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 43 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[7\] 3.3-V LVTTL E3 " "Pin SW\[7\] uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 44 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[6\] 3.3-V LVTTL H7 " "Pin SW\[6\] uses I/O standard 3.3-V LVTTL at H7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 45 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[5\] 3.3-V LVTTL J7 " "Pin SW\[5\] uses I/O standard 3.3-V LVTTL at J7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 46 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[4\] 3.3-V LVTTL G5 " "Pin SW\[4\] uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 47 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL G4 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at G4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 48 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL H6 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at H6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 49 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL H5 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at H5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 50 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL J6 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at J6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 51 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848310978 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1456848310978 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg " "Generated suppressed messages file C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456848311056 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 525 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 525 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1054 " "Peak virtual memory: 1054 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848311223 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:11 2016 " "Processing ended: Tue Mar 01 16:05:11 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848311223 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848311223 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848311223 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456848311223 ""}
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hier_info b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hier_info
new file mode 100644
index 0000000..c14f77e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hier_info
@@ -0,0 +1,54 @@
+|ise_proj
+VGA_CLK <= <GND>
+VGA_SYNC <= <GND>
+VGA_BLANK <= <GND>
+VGA_VS <= <GND>
+VGA_HS <= <GND>
+HEX0_D[0] <= <GND>
+HEX0_D[1] <= <GND>
+HEX0_D[2] <= <GND>
+HEX0_D[3] <= <GND>
+HEX0_D[4] <= <GND>
+HEX0_D[5] <= <GND>
+HEX0_D[6] <= <GND>
+LEDG[0] <= <GND>
+LEDG[1] <= <GND>
+LEDG[2] <= <GND>
+LEDG[3] <= <GND>
+LEDG[4] <= <GND>
+LEDG[5] <= <GND>
+LEDG[6] <= <GND>
+LEDG[7] <= <GND>
+LEDG[8] <= <GND>
+LEDG[9] <= <GND>
+VGA_B[0] <= <GND>
+VGA_B[1] <= <GND>
+VGA_B[2] <= <GND>
+VGA_B[3] <= <GND>
+VGA_G[0] <= <GND>
+VGA_G[1] <= <GND>
+VGA_G[2] <= <GND>
+VGA_G[3] <= <GND>
+VGA_R[0] <= <GND>
+VGA_R[1] <= <GND>
+VGA_R[2] <= <GND>
+VGA_R[3] <= <GND>
+PS2_MSDAT => ~NO_FANOUT~
+PS2_MSCLK => ~NO_FANOUT~
+CLOCK_50 => ~NO_FANOUT~
+CLOCK_50_2 => ~NO_FANOUT~
+BUTTON[0] => ~NO_FANOUT~
+BUTTON[1] => ~NO_FANOUT~
+BUTTON[2] => ~NO_FANOUT~
+SW[0] => ~NO_FANOUT~
+SW[1] => ~NO_FANOUT~
+SW[2] => ~NO_FANOUT~
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hif b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hif
new file mode 100644
index 0000000..b23e028
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hif
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ipinfo b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ipinfo
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.html b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.html
new file mode 100644
index 0000000..fbc5ab5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.html
@@ -0,0 +1,18 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+</TABLE>
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.rdb
new file mode 100644
index 0000000..da6029a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.txt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.txt
new file mode 100644
index 0000000..a463804
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.txt
@@ -0,0 +1,5 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                     ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.ammdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.ammdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.bpm b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.bpm
new file mode 100644
index 0000000..139cff4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.bpm
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.cdb
new file mode 100644
index 0000000..01f0a22
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.hdb
new file mode 100644
index 0000000..93c3909
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.kpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.kpt
new file mode 100644
index 0000000..d12a977
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.kpt
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.logdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.qmsg b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.qmsg
new file mode 100644
index 0000000..a8373a9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.qmsg
@@ -0,0 +1,32 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848304780 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848304782 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:05:04 2016 " "Processing started: Tue Mar 01 16:05:04 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848304782 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456848304782 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj " "Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456848304783 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456848305055 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001.v 7 7 " "Found 7 design units, including 7 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848305094 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848305097 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl.v 3 3 " "Found 3 design units, including 3 entities, in source file /catapult c/dot_product/dot_product/rtl.v" { { "Info" "ISGN_ENTITY_NAME" "1 dot_product_core_fsm " "Found entity 1: dot_product_core_fsm" {  } { { "../../../../dot_product/dot_product/rtl.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305100 ""} { "Info" "ISGN_ENTITY_NAME" "2 dot_product_core " "Found entity 2: dot_product_core" {  } { { "../../../../dot_product/dot_product/rtl.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl.v" 92 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305100 ""} { "Info" "ISGN_ENTITY_NAME" "3 dot_product " "Found entity 3: dot_product" {  } { { "../../../../dot_product/dot_product/rtl.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl.v" 175 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305100 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848305100 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "ise_proj.bdf 1 1 " "Using design file ise_proj.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ise_proj " "Found entity 1: ise_proj" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848305129 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1456848305129 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ise_proj " "Elaborating entity \"ise_proj\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456848305131 ""}
+{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "No superset bus at connection" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 80 432 432 104 "" "" } { 48 432 432 64 "" "" } { 64 432 432 80 "" "" } { 32 432 499 48 "A\[7..4\]" "" } { 48 432 505 64 "B\[7..4\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } } } }  } 0 275002 "No superset bus at connection" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_CLK " "Pin \"VGA_CLK\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 680 32 208 696 "VGA_CLK" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_SYNC " "Pin \"VGA_SYNC\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 656 32 208 672 "VGA_SYNC" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_BLANK " "Pin \"VGA_BLANK\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 632 32 208 648 "VGA_BLANK" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_VS " "Pin \"VGA_VS\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 608 32 208 624 "VGA_VS" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_HS " "Pin \"VGA_HS\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 584 32 208 600 "VGA_HS" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "HEX0_D\[6..0\] " "Pin \"HEX0_D\[6..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_B\[3..0\] " "Pin \"VGA_B\[3..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_G\[3..0\] " "Pin \"VGA_G\[3..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_R\[3..0\] " "Pin \"VGA_R\[3..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "PS2_MSDAT " "Pin \"PS2_MSDAT\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 416 40 208 432 "PS2_MSDAT" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "PS2_MSCLK " "Pin \"PS2_MSCLK\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 440 40 208 456 "PS2_MSCLK" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "CLOCK_50 " "Pin \"CLOCK_50\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 88 40 208 104 "CLOCK_50" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848305132 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "CLOCK_50_2 " "Pin \"CLOCK_50_2\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 56 40 208 72 "CLOCK_50_2" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848305133 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "BUTTON " "Pin \"BUTTON\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON\[2..0\]" "" } { 208 212 296 220 "BUTTON\[2\]" "" } { 112 208 280 128 "BUTTON\[2..0\]" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848305133 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "SW " "Pin \"SW\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW\[9\]" "" } { 224 40 208 240 "SW\[8\]" "" } { 176 40 208 192 "SW\[7..4\]" "" } { 152 40 208 168 "SW\[3..0\]" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848305133 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_CLK GND " "Pin \"VGA_CLK\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 680 32 208 696 "VGA_CLK" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_CLK"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_SYNC GND " "Pin \"VGA_SYNC\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 656 32 208 672 "VGA_SYNC" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_SYNC"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_BLANK GND " "Pin \"VGA_BLANK\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 632 32 208 648 "VGA_BLANK" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_BLANK"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_VS GND " "Pin \"VGA_VS\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 608 32 208 624 "VGA_VS" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_VS"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_HS GND " "Pin \"VGA_HS\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 584 32 208 600 "VGA_HS" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_HS"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[6\] GND " "Pin \"HEX0_D\[6\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[5\] GND " "Pin \"HEX0_D\[5\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[4\] GND " "Pin \"HEX0_D\[4\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[3\] GND " "Pin \"HEX0_D\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[2\] GND " "Pin \"HEX0_D\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[1\] GND " "Pin \"HEX0_D\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[0\] GND " "Pin \"HEX0_D\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|HEX0_D[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[9\] GND " "Pin \"LEDG\[9\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[8\] GND " "Pin \"LEDG\[8\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[7\] GND " "Pin \"LEDG\[7\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[6\] GND " "Pin \"LEDG\[6\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[5\] GND " "Pin \"LEDG\[5\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[4\] GND " "Pin \"LEDG\[4\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[3\] GND " "Pin \"LEDG\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[2\] GND " "Pin \"LEDG\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[1\] GND " "Pin \"LEDG\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[0\] GND " "Pin \"LEDG\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 64 432 525 80 "LEDG\[9..8\]" "" } { 304 208 281 320 "LEDG\[9..0\]" "" } { 168 544 607 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|LEDG[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[3\] GND " "Pin \"VGA_B\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_B[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[2\] GND " "Pin \"VGA_B\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_B[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Pin \"VGA_B\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_B[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Pin \"VGA_B\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_B[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[3\] GND " "Pin \"VGA_G\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_G[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[2\] GND " "Pin \"VGA_G\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_G[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Pin \"VGA_G\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_G[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Pin \"VGA_G\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_G[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[3\] GND " "Pin \"VGA_R\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_R[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[2\] GND " "Pin \"VGA_R\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_R[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[1\] GND " "Pin \"VGA_R\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_R[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[0\] GND " "Pin \"VGA_R\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848305386 "|ise_proj|VGA_R[0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456848305386 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_TOP " "Ignored assignments for entity \"DE0_TOP\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305395 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848305395 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_VGA " "Ignored assignments for entity \"DE0_VGA\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848305396 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848305396 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456848305504 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305504 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "17 " "Design contains 17 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PS2_MSDAT " "No output dependent on input pin \"PS2_MSDAT\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 416 40 208 432 "PS2_MSDAT" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|PS2_MSDAT"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PS2_MSCLK " "No output dependent on input pin \"PS2_MSCLK\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 440 40 208 456 "PS2_MSCLK" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|PS2_MSCLK"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_50 " "No output dependent on input pin \"CLOCK_50\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 88 40 208 104 "CLOCK_50" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|CLOCK_50"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_50_2 " "No output dependent on input pin \"CLOCK_50_2\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 56 40 208 72 "CLOCK_50_2" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|CLOCK_50_2"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "BUTTON\[2\] " "No output dependent on input pin \"BUTTON\[2\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|BUTTON[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "BUTTON\[1\] " "No output dependent on input pin \"BUTTON\[1\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|BUTTON[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "BUTTON\[0\] " "No output dependent on input pin \"BUTTON\[0\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|BUTTON[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[8]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "No output dependent on input pin \"SW\[7\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "No output dependent on input pin \"SW\[6\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "No output dependent on input pin \"SW\[5\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "No output dependent on input pin \"SW\[4\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[3\] " "No output dependent on input pin \"SW\[3\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[2\] " "No output dependent on input pin \"SW\[2\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[1\] " "No output dependent on input pin \"SW\[1\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[0\] " "No output dependent on input pin \"SW\[0\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848305528 "|ise_proj|SW[0]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1456848305528 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "51 " "Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Implemented 17 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456848305529 ""} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Implemented 34 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456848305529 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456848305529 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 120 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 120 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "448 " "Peak virtual memory: 448 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848305543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:05 2016 " "Processing ended: Tue Mar 01 16:05:05 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848305543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848305543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848305543 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456848305543 ""}
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.rdb
new file mode 100644
index 0000000..b251f6d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.cdb
new file mode 100644
index 0000000..33a7169
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.hdb
new file mode 100644
index 0000000..7fc4b79
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.logdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pplq.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pplq.rdb
new file mode 100644
index 0000000..8502917
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pplq.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pre_map.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pre_map.hdb
new file mode 100644
index 0000000..dea8997
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pre_map.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pti_db_list.ddb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pti_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.root_partition.map.reg_db.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..0089964
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.root_partition.map.reg_db.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.routing.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.routing.rdb
new file mode 100644
index 0000000..81d00cc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.routing.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv.hdb
new file mode 100644
index 0000000..68d88e2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg.cdb
new file mode 100644
index 0000000..17e5ba8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg_swap.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..c194c18
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg_swap.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.cdb
new file mode 100644
index 0000000..c87cb92
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.hdb
new file mode 100644
index 0000000..5677007
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry.sci b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry.sci
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry_dsc.sci b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry_dsc.sci
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smart_action.txt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smp_dump.txt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smp_dump.txt
new file mode 100644
index 0000000..3e8c4d3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smp_dump.txt
@@ -0,0 +1,9 @@
+
+State Machine - |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|dot_product_core_fsm:dot_product_core_fsm_inst|state_var
+Name state_var.st_main_5 state_var.st_main_4 state_var.st_main_3 state_var.st_main_2 state_var.st_main_1 state_var.st_main 
+state_var.st_main 0 0 0 0 0 0 
+state_var.st_main_1 0 0 0 0 1 1 
+state_var.st_main_2 0 0 0 1 0 1 
+state_var.st_main_3 0 0 1 0 0 1 
+state_var.st_main_4 0 1 0 0 0 1 
+state_var.st_main_5 1 0 0 0 0 1 
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.qmsg b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.qmsg
new file mode 100644
index 0000000..20aa5d4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.qmsg
@@ -0,0 +1,51 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848314454 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848314455 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:05:13 2016 " "Processing started: Tue Mar 01 16:05:13 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848314455 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456848314455 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ise_proj -c ise_proj " "Command: quartus_sta ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456848314455 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456848314515 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_TOP " "Ignored assignments for entity \"DE0_TOP\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314565 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848314565 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_VGA " "Ignored assignments for entity \"DE0_VGA\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848314567 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848314567 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456848314671 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456848314671 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456848314713 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456848314713 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ise_proj.sdc " "Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456848314842 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456848314842 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1456848314842 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1456848314843 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456848314843 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456848314843 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456848314843 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1456848314848 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456848314850 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848314851 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848314855 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848314857 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848314858 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848314860 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848314861 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456848314867 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456848314884 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456848315289 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456848315308 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1456848315308 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1456848315308 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456848315309 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315309 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315312 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315314 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315315 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315317 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315318 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456848315323 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456848315388 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Quartus II" 0 -1 1456848315389 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1456848315389 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456848315389 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315391 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315393 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315394 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315396 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848315397 ""}
+{ "Info" "ISTA_UCP_CONSTRAINED" "setup " "Design is fully constrained for setup requirements" {  } {  } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456848315506 ""}
+{ "Info" "ISTA_UCP_CONSTRAINED" "hold " "Design is fully constrained for hold requirements" {  } {  } 0 332101 "Design is fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456848315506 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 54 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "480 " "Peak virtual memory: 480 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848315535 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:15 2016 " "Processing ended: Tue Mar 01 16:05:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848315535 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848315535 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848315535 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456848315535 ""}
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.rdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.rdb
new file mode 100644
index 0000000..03921f6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.rdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta_cmp.6_slow_1200mv_85c.tdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..45e21c4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.syn_hier_info b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.syn_hier_info
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tis_db_list.ddb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.fast_1200mv_0c.ddb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..7a4a179
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.fast_1200mv_0c.ddb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_0c.ddb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..24cd6fd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_0c.ddb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_85c.ddb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..5739c3b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_85c.ddb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tmw_info b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tmw_info
new file mode 100644
index 0000000..85c3651
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:12
+start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:05-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:03-start_full_compilation
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.vpr.ammdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.vpr.ammdb
new file mode 100644
index 0000000..90306e7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.vpr.ammdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/logic_util_heursitic.dat b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..0f250c4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/logic_util_heursitic.dat
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf
new file mode 100644
index 0000000..96eb86d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf
@@ -0,0 +1,93 @@
+--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=4 LPM_WIDTHB=4 LPM_WIDTHP=8 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_mult 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_padd 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+FUNCTION lcell (in)
+RETURNS ( out);
+FUNCTION soft (in)
+RETURNS ( out);
+
+--synthesis_resources = lut 45 
+SUBDESIGN mult_a7t
+( 
+	dataa[3..0]	:	input;
+	datab[3..0]	:	input;
+	result[7..0]	:	output;
+) 
+VARIABLE
+	add10_result[7..0]	:	WIRE;
+	add14_result[2..0]	:	WIRE;
+	add6_result[10..0]	:	WIRE;
+	cs1a[2..0] : carry_sum;
+	cs2a[2..0] : carry_sum;
+	le3a[5..0] : lcell;
+	le4a[5..0] : lcell;
+	le5a[4..0] : lcell;
+	sft11a[7..0] : soft;
+	sft12a[7..0] : soft;
+	sft13a[7..0] : soft;
+	sft15a[2..0] : soft;
+	sft16a[2..0] : soft;
+	sft17a[2..0] : soft;
+	sft7a[10..0] : soft;
+	sft8a[10..0] : soft;
+	sft9a[10..0] : soft;
+	dataa_node[3..0]	: WIRE;
+	datab_node[3..0]	: WIRE;
+	final_result_node[7..0]	: WIRE;
+	w117w[5..0]	: WIRE;
+	w183w	: WIRE;
+	w196w	: WIRE;
+	w257w[10..0]	: WIRE;
+	w70w[5..0]	: WIRE;
+	w7w[5..0]	: WIRE;
+
+BEGIN 
+	add10_result[] = sft11a[].out + sft12a[].out;
+	add14_result[] = sft15a[].out + sft16a[].out;
+	add6_result[] = sft7a[].out + sft8a[].out;
+	cs1a[].cin = ( ((w7w[4..4] & cs1a[1].cout) # w7w[5..5]), ((w7w[2..2] & cs1a[0].cout) # w7w[3..3]), w7w[1..1]);
+	cs1a[].sin = ( ((((((! w7w[5..5]) & w7w[4..4]) & cs1a[1].cout) # ((w7w[5..5] & w7w[4..4]) & (! cs1a[1].cout))) # ((w7w[5..5] & (! w7w[4..4])) & cs1a[1].cout)) # ((w7w[5..5] & (! w7w[4..4])) & (! cs1a[1].cout))), ((((((! w7w[3..3]) & w7w[2..2]) & cs1a[0].cout) # ((w7w[3..3] & w7w[2..2]) & (! cs1a[0].cout))) # ((w7w[3..3] & (! w7w[2..2])) & cs1a[0].cout)) # ((w7w[3..3] & (! w7w[2..2])) & (! cs1a[0].cout))), w7w[1..1]);
+	cs2a[].cin = ( ((w7w[4..4] & cs2a[1].cout) # w7w[5..5]), ((w7w[2..2] & cs2a[0].cout) # w7w[3..3]), w7w[1..1]);
+	cs2a[].sin = ( ((((((! w7w[5..5]) & (! w7w[4..4])) & cs2a[1].cout) # (((! w7w[5..5]) & w7w[4..4]) & (! cs2a[1].cout))) # ((w7w[5..5] & w7w[4..4]) & (! cs2a[1].cout))) # ((w7w[5..5] & (! w7w[4..4])) & cs2a[1].cout)), ((((((! w7w[3..3]) & (! w7w[2..2])) & cs2a[0].cout) # (((! w7w[3..3]) & w7w[2..2]) & (! cs2a[0].cout))) # ((w7w[3..3] & w7w[2..2]) & (! cs2a[0].cout))) # ((w7w[3..3] & (! w7w[2..2])) & cs2a[0].cout)), w7w[0..0]);
+	le3a[].in = (! ((! (((! ( B"0", dataa_node[], B"0")) & cs1a[0].sout) & (! cs2a[0].sout))) & (! ((((! ( B"0", B"0", dataa_node[])) & cs1a[0].sout) & cs2a[0].sout) # ((( B"0", B"0", dataa_node[]) & (! cs1a[0].sout)) & cs2a[0].sout)))));
+	le4a[].in = (! ((! (((! ( B"0", dataa_node[], B"0")) & cs1a[1].sout) & (! cs2a[1].sout))) & (! ((((! ( B"0", B"0", dataa_node[])) & cs1a[1].sout) & cs2a[1].sout) # ((( B"0", B"0", dataa_node[]) & (! cs1a[1].sout)) & cs2a[1].sout)))));
+	le5a[].in = ((cs1a[2].sout & ( dataa_node[], B"0")) # (cs2a[2].sout & ( B"0", dataa_node[])));
+	sft11a[].in = ( w196w, ( w183w, ( le5a[3..3].out, ( le5a[2..2].out, ( le5a[1..1].out, ( le4a[2..2].out, ( le3a[3..2].out)))))));
+	sft12a[].in = ( w196w, ( w196w, ( (! w117w[5..5]), ( le4a[4..4].out, ( le4a[3..3].out, ( le3a[4..4].out, ( w196w, cs1a[1].sout)))))));
+	sft13a[].in = add10_result[];
+	sft15a[].in = ( w196w, ( w183w, w183w));
+	sft16a[].in = ( w196w, ( w196w, (! w70w[5..5])));
+	sft17a[].in = add14_result[];
+	sft7a[].in = ( w183w, ( w183w, ( le5a[4..4].out, ( sft13a[5..5].out, ( sft13a[4..4].out, ( sft13a[3..3].out, ( le5a[0..0].out, ( le4a[1..1].out, ( le4a[0..0].out, ( le3a[1..0].out))))))))));
+	sft8a[].in = ( w196w, ( sft13a[7..7].out, ( sft13a[6..6].out, ( sft17a[2..2].out, ( sft17a[1..1].out, ( sft17a[0..0].out, ( sft13a[2..2].out, ( sft13a[1..1].out, ( sft13a[0..0].out, ( w196w, cs1a[0].sout))))))))));
+	sft9a[].in = add6_result[];
+	dataa_node[] = ( dataa[3..0]);
+	datab_node[] = ( datab[3..0]);
+	final_result_node[] = ( w257w[7..0]);
+	result[] = ( final_result_node[7..0]);
+	w117w[] = le4a[].out;
+	w183w = B"1";
+	w196w = B"0";
+	w257w[] = ( sft9a[10..9].out, sft9a[8..7].out, sft9a[6..5].out, sft9a[4..3].out, sft9a[2..1].out, sft9a[0..0].out);
+	w70w[] = le3a[].out;
+	w7w[] = ( B"00", datab_node[]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/prev_cmp_ise_proj.qmsg b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/prev_cmp_ise_proj.qmsg
new file mode 100644
index 0000000..3265beb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/db/prev_cmp_ise_proj.qmsg
@@ -0,0 +1,43 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848117176 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848117178 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:01:56 2016 " "Processing started: Tue Mar 01 16:01:56 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848117178 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456848117178 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj " "Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456848117178 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456848117439 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v 7 7 " "Found 7 design units, including 7 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848117472 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport (2).v 20 20 " "Found 20 design units, including 20 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport (2).v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848117476 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl (2).v 2 2 " "Found 2 design units, including 2 entities, in source file /catapult c/dot_product/dot_product/rtl (2).v" { { "Info" "ISGN_ENTITY_NAME" "1 dot_product_core " "Found entity 1: dot_product_core" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117478 ""} { "Info" "ISGN_ENTITY_NAME" "2 dot_product " "Found entity 2: dot_product" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 119 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848117478 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848117478 ""}
+{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "mgc_out_reg_pos rtl_mgc_ioport_v2001.v(3) " "Verilog HDL error at rtl_mgc_ioport_v2001.v(3): module \"mgc_out_reg_pos\" cannot be declared more than once" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 3 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "Quartus II" 0 -1 1456848117480 ""}
+{ "Info" "IVRFX_HDL_SEE_DECLARATION" "mgc_out_reg_pos rtl_mgc_ioport_v2001 (2).v(3) " "HDL info at rtl_mgc_ioport_v2001 (2).v(3): see declaration for object \"mgc_out_reg_pos\"" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 3 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848117480 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_reg_neg rtl_mgc_ioport_v2001.v(68) " "Ignored design unit \"mgc_out_reg_neg\" at rtl_mgc_ioport_v2001.v(68) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 68 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117481 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_reg rtl_mgc_ioport_v2001.v(133) " "Ignored design unit \"mgc_out_reg\" at rtl_mgc_ioport_v2001.v(133) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 133 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117481 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_buf_wait rtl_mgc_ioport_v2001.v(210) " "Ignored design unit \"mgc_out_buf_wait\" at rtl_mgc_ioport_v2001.v(210) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 210 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117481 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_fifo_wait rtl_mgc_ioport_v2001.v(296) " "Ignored design unit \"mgc_out_fifo_wait\" at rtl_mgc_ioport_v2001.v(296) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 296 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117481 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_fifo_wait_core rtl_mgc_ioport_v2001.v(353) " "Ignored design unit \"mgc_out_fifo_wait_core\" at rtl_mgc_ioport_v2001.v(353) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 353 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117481 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_pipe rtl_mgc_ioport_v2001.v(644) " "Ignored design unit \"mgc_pipe\" at rtl_mgc_ioport_v2001.v(644) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001.v" 644 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117482 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001.v 0 0 " "Found 0 design units, including 0 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848117482 ""}
+{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "mgc_in_wire rtl_mgc_ioport.v(13) " "Verilog HDL error at rtl_mgc_ioport.v(13): module \"mgc_in_wire\" cannot be declared more than once" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 13 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "Quartus II" 0 -1 1456848117483 ""}
+{ "Info" "IVRFX_HDL_SEE_DECLARATION" "mgc_in_wire rtl_mgc_ioport (2).v(13) " "HDL info at rtl_mgc_ioport (2).v(13): see declaration for object \"mgc_in_wire\"" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 13 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848117483 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_in_wire_en rtl_mgc_ioport.v(29) " "Ignored design unit \"mgc_in_wire_en\" at rtl_mgc_ioport.v(29) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 29 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117483 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_in_wire_wait rtl_mgc_ioport.v(49) " "Ignored design unit \"mgc_in_wire_wait\" at rtl_mgc_ioport.v(49) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 49 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_chan_in rtl_mgc_ioport.v(72) " "Ignored design unit \"mgc_chan_in\" at rtl_mgc_ioport.v(72) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 72 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_stdreg rtl_mgc_ioport.v(109) " "Ignored design unit \"mgc_out_stdreg\" at rtl_mgc_ioport.v(109) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 109 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_stdreg_en rtl_mgc_ioport.v(125) " "Ignored design unit \"mgc_out_stdreg_en\" at rtl_mgc_ioport.v(125) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 125 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_stdreg_wait rtl_mgc_ioport.v(145) " "Ignored design unit \"mgc_out_stdreg_wait\" at rtl_mgc_ioport.v(145) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 145 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_out_prereg_en rtl_mgc_ioport.v(169) " "Ignored design unit \"mgc_out_prereg_en\" at rtl_mgc_ioport.v(169) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 169 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_inout_stdreg_en rtl_mgc_ioport.v(191) " "Ignored design unit \"mgc_inout_stdreg_en\" at rtl_mgc_ioport.v(191) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 191 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "hid_tribuf rtl_mgc_ioport.v(217) " "Ignored design unit \"hid_tribuf\" at rtl_mgc_ioport.v(217) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 217 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_inout_stdreg_wait rtl_mgc_ioport.v(229) " "Ignored design unit \"mgc_inout_stdreg_wait\" at rtl_mgc_ioport.v(229) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 229 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_inout_buf_wait rtl_mgc_ioport.v(269) " "Ignored design unit \"mgc_inout_buf_wait\" at rtl_mgc_ioport.v(269) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 269 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_inout_fifo_wait rtl_mgc_ioport.v(339) " "Ignored design unit \"mgc_inout_fifo_wait\" at rtl_mgc_ioport.v(339) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 339 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117484 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_io_sync rtl_mgc_ioport.v(419) " "Ignored design unit \"mgc_io_sync\" at rtl_mgc_ioport.v(419) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 419 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_bsync_rdy rtl_mgc_ioport.v(428) " "Ignored design unit \"mgc_bsync_rdy\" at rtl_mgc_ioport.v(428) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 428 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_bsync_vld rtl_mgc_ioport.v(443) " "Ignored design unit \"mgc_bsync_vld\" at rtl_mgc_ioport.v(443) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 443 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_bsync_rv rtl_mgc_ioport.v(458) " "Ignored design unit \"mgc_bsync_rv\" at rtl_mgc_ioport.v(458) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 458 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "mgc_sync rtl_mgc_ioport.v(479) " "Ignored design unit \"mgc_sync\" at rtl_mgc_ioport.v(479) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 479 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "funccall_inout rtl_mgc_ioport.v(498) " "Ignored design unit \"funccall_inout\" at rtl_mgc_ioport.v(498) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport.v" 498 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport.v 0 0 " "Found 0 design units, including 0 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848117485 ""}
+{ "Error" "EVRFX_VERI_FOUND_DUPLICATE_MODULE_DEFINITION" "dot_product_core rtl.v(92) " "Verilog HDL error at rtl.v(92): module \"dot_product_core\" cannot be declared more than once" {  } { { "../../../../dot_product/dot_product/rtl.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl.v" 92 0 0 } }  } 0 10228 "Verilog HDL error at %2!s!: module \"%1!s!\" cannot be declared more than once" 0 0 "Quartus II" 0 -1 1456848117487 ""}
+{ "Info" "IVRFX_HDL_SEE_DECLARATION" "dot_product_core rtl (2).v(16) " "HDL info at rtl (2).v(16): see declaration for object \"dot_product_core\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 16 0 0 } }  } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848117487 ""}
+{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "dot_product rtl.v(175) " "Ignored design unit \"dot_product\" at rtl.v(175) due to previous errors" {  } { { "../../../../dot_product/dot_product/rtl.v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl.v" 175 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Quartus II" 0 -1 1456848117487 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl.v 0 0 " "Found 0 design units, including 0 entities, in source file /catapult c/dot_product/dot_product/rtl.v" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848117487 ""}
+{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 28 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 28 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848117550 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Mar 01 16:01:57 2016 " "Processing ended: Tue Mar 01 16:01:57 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848117550 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848117550 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848117550 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456848117550 ""}
+{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 30 s 0 s " "Quartus II Full Compilation was unsuccessful. 30 errors, 0 warnings" {  } {  } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456848118141 ""}
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product.bsf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product.bsf
new file mode 100644
index 0000000..8dbba23
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 264 160)
+	(text "dot_product" (rect 5 0 52 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "input_a_rsc_z[7..0]" (rect 0 0 76 12)(font "Arial" ))
+		(text "input_a_rsc_z[7..0]" (rect 21 27 97 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input_b_rsc_z[7..0]" (rect 0 0 76 12)(font "Arial" ))
+		(text "input_b_rsc_z[7..0]" (rect 21 43 97 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 59 31 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 75 30 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 91 46 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 248 32)
+		(output)
+		(text "output_rsc_z[7..0]" (rect 0 0 71 12)(font "Arial" ))
+		(text "output_rsc_z[7..0]" (rect 156 27 227 39)(font "Arial" ))
+		(line (pt 248 32)(pt 232 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 232 128)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product_core.bsf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product_core.bsf
new file mode 100644
index 0000000..4691fe9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product_core.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 400 160)
+	(text "dot_product_core" (rect 5 0 75 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "input_a_rsc_mgc_in_wire_d[7..0]" (rect 0 0 134 12)(font "Arial" ))
+		(text "input_a_rsc_mgc_in_wire_d[7..0]" (rect 21 75 155 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "input_b_rsc_mgc_in_wire_d[7..0]" (rect 0 0 134 12)(font "Arial" ))
+		(text "input_b_rsc_mgc_in_wire_d[7..0]" (rect 21 91 155 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 384 32)
+		(output)
+		(text "output_rsc_mgc_out_stdreg_d[7..0]" (rect 0 0 145 12)(font "Arial" ))
+		(text "output_rsc_mgc_out_stdreg_d[7..0]" (rect 218 27 363 39)(font "Arial" ))
+		(line (pt 384 32)(pt 368 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 368 128)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product_core_fsm.bsf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product_core_fsm.bsf
new file mode 100644
index 0000000..4a7d025
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/dot_product_core_fsm.bsf
@@ -0,0 +1,93 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 208 128)
+	(text "dot_product_core_fsm" (rect 5 0 98 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 192 32)
+		(output)
+		(text "fsm_output[5..0]" (rect 0 0 66 12)(font "Arial" ))
+		(text "fsm_output[5..0]" (rect 105 27 171 39)(font "Arial" ))
+		(line (pt 192 32)(pt 176 32)(line_width 3))
+	)
+	(parameter
+		"st_main"
+		"000"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"st_main_1"
+		"001"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"st_main_2"
+		"010"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"st_main_3"
+		"011"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"st_main_4"
+		"100"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"st_main_5"
+		"101"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"state_x"
+		"000"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(drawing
+		(rectangle (rect 16 16 176 96)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 208 -64 308 16))
+)
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/README b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.db_info b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.db_info
new file mode 100644
index 0000000..b2a0c96
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 01 15:21:42 2016
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.ammdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.ammdb
new file mode 100644
index 0000000..391d97c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.ammdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.cdb
new file mode 100644
index 0000000..5039f5d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.dfp b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.dfp
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.hdb
new file mode 100644
index 0000000..8b312c1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.kpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.kpt
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.logdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.rcfdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..495099e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.rcfdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.cdb
new file mode 100644
index 0000000..b6dbbd5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.dpi b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.dpi
new file mode 100644
index 0000000..11a9352
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.dpi
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.cdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..953f806
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.cdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hb_info b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hb_info
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..172fe96
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.sig b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hdb b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hdb
new file mode 100644
index 0000000..f115f01
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hdb
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.kpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.kpt
new file mode 100644
index 0000000..c70889f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.kpt
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.asm.rpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.asm.rpt
new file mode 100644
index 0000000..2742fdd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for ise_proj
+Tue Mar 01 16:05:13 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Mar 01 16:05:13 2016 ;
+; Revision Name         ; ise_proj                              ;
+; Top-level Entity Name ; ise_proj                              ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++----------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                              ;
++----------------------------------------------------------------------------------------+
+; File Name                                                                              ;
++----------------------------------------------------------------------------------------+
+; C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof ;
++----------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof ;
++----------------+-------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                         ;
++----------------+-------------------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                                    ;
+; JTAG usercode  ; 0x000C858E                                                                                      ;
+; Checksum       ; 0x000C858E                                                                                      ;
++----------------+-------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 16:05:11 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 424 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:13 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf
new file mode 100644
index 0000000..4c3c55f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf
@@ -0,0 +1,462 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 40 120 208 136)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BUTTON[2..0]" (rect 5 0 74 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 112 32 120))
+)
+(pin
+	(input)
+	(rect 40 416 208 432)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "PS2_MSDAT" (rect 5 0 67 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 224 416 280 424))
+)
+(pin
+	(input)
+	(rect 40 440 208 456)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "PS2_MSCLK" (rect 5 0 67 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 232 440 288 456))
+)
+(pin
+	(input)
+	(rect 40 240 208 256)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9]" (rect 5 0 35 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 240 32 256))
+)
+(pin
+	(input)
+	(rect 40 224 208 240)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[8]" (rect 5 0 35 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -32 208 24 224))
+)
+(pin
+	(input)
+	(rect 40 176 208 192)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[7..4]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 176 32 192))
+)
+(pin
+	(input)
+	(rect 40 152 208 168)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[3..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 136 32 152))
+)
+(pin
+	(input)
+	(rect 40 88 208 104)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 72 32 88))
+)
+(pin
+	(input)
+	(rect 40 56 208 72)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50_2" (rect 5 0 72 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 40 32 56))
+)
+(pin
+	(output)
+	(rect 32 536 208 552)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 536 272 544))
+)
+(pin
+	(output)
+	(rect 32 680 208 696)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 5 0 54 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 352 704 408 720))
+)
+(pin
+	(output)
+	(rect 32 656 208 672)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_SYNC" (rect 5 0 65 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 560 752 616 768))
+)
+(pin
+	(output)
+	(rect 32 632 208 648)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_BLANK" (rect 5 0 68 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 616 688 672 704))
+)
+(pin
+	(output)
+	(rect 32 608 208 624)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_VS" (rect 5 0 47 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 240 608 296 624))
+)
+(pin
+	(output)
+	(rect 32 584 208 600)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_HS" (rect 5 0 48 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 240 584 296 600))
+)
+(pin
+	(output)
+	(rect 32 504 208 520)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_R[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 504 264 520))
+)
+(pin
+	(output)
+	(rect 32 560 208 576)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_B[3..0]" (rect 5 0 66 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 560 280 568))
+)
+(pin
+	(output)
+	(rect 32 360 208 376)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX0_D[6..0]" (rect 5 0 72 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 208 376 264 392))
+)
+(pin
+	(output)
+	(rect 32 312 208 328)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "LEDG[9..0]" (rect 5 0 60 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 176 336 232 352))
+)
+(symbol
+	(rect 416 104 448 136)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst1" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(connector
+	(pt 296 232)
+	(pt 208 232)
+)
+(connector
+	(pt 208 248)
+	(pt 296 248)
+)
+(connector
+	(text "BUTTON[2]" (rect 212 208 268 220)(font "Arial" ))
+	(pt 296 216)
+	(pt 272 216)
+)
+(connector
+	(text "B[7..0]" (rect 243 184 276 196)(font "Arial" ))
+	(pt 296 200)
+	(pt 272 200)
+	(bus)
+)
+(connector
+	(text "A[7..0]" (rect 266 168 299 180)(font "Arial" ))
+	(pt 296 184)
+	(pt 272 184)
+	(bus)
+)
+(connector
+	(text "B[3..0]" (rect 212 144 245 156)(font "Arial" ))
+	(pt 208 160)
+	(pt 216 160)
+	(bus)
+)
+(connector
+	(text "A[3..0]" (rect 212 168 245 180)(font "Arial" ))
+	(pt 208 184)
+	(pt 216 184)
+	(bus)
+)
+(connector
+	(text "BUTTON[2..0]" (rect 211 112 280 124)(font "Arial" ))
+	(pt 208 128)
+	(pt 216 128)
+	(bus)
+)
+(connector
+	(pt 432 104)
+	(pt 432 80)
+	(bus)
+)
+(connector
+	(pt 432 48)
+	(pt 432 64)
+	(bus)
+)
+(connector
+	(pt 432 64)
+	(pt 432 80)
+	(bus)
+)
+(connector
+	(text "A[7..4]" (rect 466 32 499 44)(font "Arial" ))
+	(pt 432 48)
+	(pt 480 48)
+	(bus)
+)
+(connector
+	(text "B[7..4]" (rect 472 48 505 60)(font "Arial" ))
+	(pt 432 64)
+	(pt 480 64)
+	(bus)
+)
+(connector
+	(text "LEDG[9..8]" (rect 470 64 525 76)(font "Arial" ))
+	(pt 432 80)
+	(pt 480 80)
+	(bus)
+)
+(connector
+	(text "LEDG[9..0]" (rect 226 304 281 316)(font "Arial" ))
+	(pt 208 320)
+	(pt 232 320)
+	(bus)
+)
+(connector
+	(text "LEDG[7..0]" (rect 552 168 607 180)(font "Arial" ))
+	(pt 576 184)
+	(pt 544 184)
+	(bus)
+)
+(junction (pt 432 80))
+(junction (pt 432 64))
+(text "FPGA PINS" (rect 72 16 202 38)(font "Arial" (font_size 14)))
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.done b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.done
new file mode 100644
index 0000000..b6c73d9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.done
@@ -0,0 +1 @@
+Tue Mar 01 16:05:16 2016
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt
new file mode 100644
index 0000000..11e69ce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt
@@ -0,0 +1,2369 @@
+Fitter report for ise_proj
+Tue Mar 01 16:05:11 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Dual Purpose and Dedicated Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Other Routing Usage Summary
+ 22. I/O Rules Summary
+ 23. I/O Rules Details
+ 24. I/O Rules Matrix
+ 25. Fitter Device Options
+ 26. Operating Settings and Conditions
+ 27. Fitter Messages
+ 28. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Mar 01 16:05:11 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ise_proj                                         ;
+; Top-level Entity Name              ; ise_proj                                         ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 0 / 15,408 ( 0 % )                               ;
+;     Total combinational functions  ; 0 / 15,408 ( 0 % )                               ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                               ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 51 / 347 ( 15 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------+
+; I/O Assignment Warnings                          ;
++-----------+--------------------------------------+
+; Pin Name  ; Reason                               ;
++-----------+--------------------------------------+
+; VGA_CLK   ; Missing drive strength and slew rate ;
+; VGA_SYNC  ; Missing drive strength and slew rate ;
+; VGA_BLANK ; Missing drive strength and slew rate ;
+; VGA_VS    ; Missing drive strength               ;
+; VGA_HS    ; Missing drive strength               ;
+; HEX0_D[6] ; Missing drive strength               ;
+; HEX0_D[5] ; Missing drive strength               ;
+; HEX0_D[4] ; Missing drive strength               ;
+; HEX0_D[3] ; Missing drive strength               ;
+; HEX0_D[2] ; Missing drive strength               ;
+; HEX0_D[1] ; Missing drive strength               ;
+; HEX0_D[0] ; Missing drive strength               ;
+; LEDG[9]   ; Missing drive strength               ;
+; LEDG[8]   ; Missing drive strength               ;
+; LEDG[7]   ; Missing drive strength               ;
+; LEDG[6]   ; Missing drive strength               ;
+; LEDG[5]   ; Missing drive strength               ;
+; LEDG[4]   ; Missing drive strength               ;
+; LEDG[3]   ; Missing drive strength               ;
+; LEDG[2]   ; Missing drive strength               ;
+; LEDG[1]   ; Missing drive strength               ;
+; LEDG[0]   ; Missing drive strength               ;
+; VGA_B[3]  ; Missing drive strength               ;
+; VGA_B[2]  ; Missing drive strength               ;
+; VGA_B[1]  ; Missing drive strength               ;
+; VGA_B[0]  ; Missing drive strength               ;
+; VGA_G[3]  ; Missing drive strength               ;
+; VGA_G[2]  ; Missing drive strength               ;
+; VGA_G[1]  ; Missing drive strength               ;
+; VGA_G[0]  ; Missing drive strength               ;
+; VGA_R[3]  ; Missing drive strength               ;
+; VGA_R[2]  ; Missing drive strength               ;
+; VGA_R[1]  ; Missing drive strength               ;
+; VGA_R[0]  ; Missing drive strength               ;
++-----------+--------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                             ;
++--------------+----------------+--------------+-----------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+-----------------+---------------+----------------+
+; Location     ;                ;              ; DRAM_ADDR[0]    ; PIN_C4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[10]   ; PIN_B4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[11]   ; PIN_A7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[1]    ; PIN_A3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[2]    ; PIN_B3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[3]    ; PIN_C3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[4]    ; PIN_A5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[5]    ; PIN_C6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[6]    ; PIN_B6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[7]    ; PIN_A6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[8]    ; PIN_C7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[9]    ; PIN_B7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA[0]      ; PIN_B5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA[1]      ; PIN_A4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA_0       ; PIN_B5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA_1       ; PIN_A4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CAS_N      ; PIN_G8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CKE        ; PIN_E6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CLK        ; PIN_E5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CS_N       ; PIN_G7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[0]      ; PIN_D10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[10]     ; PIN_A9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[11]     ; PIN_C10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[12]     ; PIN_B10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[13]     ; PIN_A10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[14]     ; PIN_E10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[15]     ; PIN_F10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[1]      ; PIN_G10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[2]      ; PIN_H10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[3]      ; PIN_E9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[4]      ; PIN_F9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[5]      ; PIN_G9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[6]      ; PIN_H9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[7]      ; PIN_F8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[8]      ; PIN_A8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[9]      ; PIN_B9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_LDQM       ; PIN_E7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_RAS_N      ; PIN_F7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_UDQM       ; PIN_B8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_WE_N       ; PIN_D6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[0]      ; PIN_P7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[10]     ; PIN_N1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[11]     ; PIN_M3        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[12]     ; PIN_M2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[13]     ; PIN_M1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[14]     ; PIN_L7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[15]     ; PIN_L6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[16]     ; PIN_AA2       ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[17]     ; PIN_M5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[18]     ; PIN_M6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[19]     ; PIN_P1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[1]      ; PIN_P5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[20]     ; PIN_P3        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[21]     ; PIN_R2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[2]      ; PIN_P6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[3]      ; PIN_N7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[4]      ; PIN_N5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[5]      ; PIN_N6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[6]      ; PIN_M8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[7]      ; PIN_M4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[8]      ; PIN_P2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[9]      ; PIN_N2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_BYTE_N       ; PIN_AA1       ; QSF Assignment ;
+; Location     ;                ;              ; FL_CE_N         ; PIN_N8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ15_AM1     ; PIN_Y2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[0]        ; PIN_R7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[10]       ; PIN_T4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[11]       ; PIN_U2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[12]       ; PIN_V1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[13]       ; PIN_V4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[14]       ; PIN_W2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[1]        ; PIN_P8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[2]        ; PIN_R8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[3]        ; PIN_U1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[4]        ; PIN_V2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[5]        ; PIN_V3        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[6]        ; PIN_W1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[7]        ; PIN_Y1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[8]        ; PIN_T5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[9]        ; PIN_T7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_OE_N         ; PIN_R6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_RST_N        ; PIN_R1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_RY           ; PIN_M7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_WE_N         ; PIN_P4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_WP_N         ; PIN_T3        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKIN[0]  ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKIN[1]  ; PIN_AA12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKOUT[0] ; PIN_AB3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKOUT[1] ; PIN_AA3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[0]      ; PIN_AB16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[10]     ; PIN_AB8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[11]     ; PIN_AA8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[12]     ; PIN_AB5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[13]     ; PIN_AA5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[14]     ; PIN_AB4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[15]     ; PIN_AA4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[16]     ; PIN_V14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[17]     ; PIN_U14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[18]     ; PIN_Y13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[19]     ; PIN_W13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[1]      ; PIN_AA16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[20]     ; PIN_U13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[21]     ; PIN_V12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[22]     ; PIN_R10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[23]     ; PIN_V11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[24]     ; PIN_Y10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[25]     ; PIN_W10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[26]     ; PIN_T8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[27]     ; PIN_V8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[28]     ; PIN_W7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[29]     ; PIN_W6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[2]      ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[30]     ; PIN_V5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[31]     ; PIN_U7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[3]      ; PIN_AB15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[4]      ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[5]      ; PIN_AB14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[6]      ; PIN_AB13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[7]      ; PIN_AA13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[8]      ; PIN_AB10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[9]      ; PIN_AA10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKIN[0]  ; PIN_AB11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKIN[1]  ; PIN_AA11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKOUT[0] ; PIN_R16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKOUT[1] ; PIN_T16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[0]      ; PIN_AA20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[10]     ; PIN_U15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[11]     ; PIN_T15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[12]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[13]     ; PIN_V15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[14]     ; PIN_AB9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[15]     ; PIN_AA9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[16]     ; PIN_AA7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[17]     ; PIN_AB7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[18]     ; PIN_T14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[19]     ; PIN_R14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[1]      ; PIN_AB20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[20]     ; PIN_U12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[21]     ; PIN_T12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[22]     ; PIN_R11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[23]     ; PIN_R12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[24]     ; PIN_U10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[25]     ; PIN_T10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[26]     ; PIN_U9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[27]     ; PIN_T9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[28]     ; PIN_Y7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[29]     ; PIN_U8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[2]      ; PIN_AA19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[30]     ; PIN_V6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[31]     ; PIN_V7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[3]      ; PIN_AB19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[4]      ; PIN_AB18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[5]      ; PIN_AA18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[6]      ; PIN_AA17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[7]      ; PIN_AB17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[8]      ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[9]      ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[0]       ; PIN_AB16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[10]      ; PIN_AB8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[11]      ; PIN_AA8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[12]      ; PIN_AB5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[13]      ; PIN_AA5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[14]      ; PIN_AB4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[15]      ; PIN_AA4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[16]      ; PIN_V14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[17]      ; PIN_U14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[18]      ; PIN_Y13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[19]      ; PIN_W13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[1]       ; PIN_AA16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[20]      ; PIN_U13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[21]      ; PIN_V12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[22]      ; PIN_R10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[23]      ; PIN_V11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[24]      ; PIN_Y10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[25]      ; PIN_W10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[26]      ; PIN_T8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[27]      ; PIN_V8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[28]      ; PIN_W7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[29]      ; PIN_W6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[2]       ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[30]      ; PIN_V5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[31]      ; PIN_U7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[3]       ; PIN_AB15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[4]       ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[5]       ; PIN_AB14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[6]       ; PIN_AB13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[7]       ; PIN_AA13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[8]       ; PIN_AB10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[9]       ; PIN_AA10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[0]       ; PIN_AA20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[10]      ; PIN_U15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[11]      ; PIN_T15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[12]      ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[13]      ; PIN_V15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[14]      ; PIN_AB9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[15]      ; PIN_AA9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[16]      ; PIN_AA7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[17]      ; PIN_AB7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[18]      ; PIN_T14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[19]      ; PIN_R14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[1]       ; PIN_AB20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[20]      ; PIN_U12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[21]      ; PIN_T12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[22]      ; PIN_R11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[23]      ; PIN_R12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[24]      ; PIN_U10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[25]      ; PIN_T10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[26]      ; PIN_U9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[27]      ; PIN_T9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[28]      ; PIN_Y7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[29]      ; PIN_U8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[2]       ; PIN_AA19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[30]      ; PIN_V6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[31]      ; PIN_V7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[3]       ; PIN_AB19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[4]       ; PIN_AB18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[5]       ; PIN_AA18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[6]       ; PIN_AA17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[7]       ; PIN_AB17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[8]       ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[9]       ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_N0   ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_N1   ; PIN_AB11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_P0   ; PIN_AA12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_P1   ; PIN_AA11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_N0  ; PIN_AB3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_N1  ; PIN_R16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_P0  ; PIN_AA3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_P1  ; PIN_T16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[0]         ; PIN_E11       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[1]         ; PIN_F11       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[2]         ; PIN_H12       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[3]         ; PIN_H13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[4]         ; PIN_G12       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[5]         ; PIN_F12       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[6]         ; PIN_F13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[7]         ; PIN_D13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[0]         ; PIN_A13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[1]         ; PIN_B13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[2]         ; PIN_C13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[3]         ; PIN_A14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[4]         ; PIN_B14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[5]         ; PIN_E14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[6]         ; PIN_A15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[7]         ; PIN_B15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[0]       ; PIN_A13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[1]       ; PIN_B13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[2]       ; PIN_C13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[3]       ; PIN_A14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[4]       ; PIN_B14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[5]       ; PIN_E14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[6]       ; PIN_A15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[0]         ; PIN_D15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[1]         ; PIN_A16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[2]         ; PIN_B16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[3]         ; PIN_E15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[4]         ; PIN_A17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[5]         ; PIN_B17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[6]         ; PIN_F14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[7]         ; PIN_A18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[0]       ; PIN_D15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[1]       ; PIN_A16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[2]       ; PIN_B16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[3]       ; PIN_E15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[4]       ; PIN_A17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[5]       ; PIN_B17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[6]       ; PIN_F14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[0]         ; PIN_B18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[1]         ; PIN_F15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[2]         ; PIN_A19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[3]         ; PIN_B19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[4]         ; PIN_C19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[5]         ; PIN_D19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[6]         ; PIN_G15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[7]         ; PIN_G16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[0]       ; PIN_B18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[1]       ; PIN_F15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[2]       ; PIN_A19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[3]       ; PIN_B19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[4]       ; PIN_C19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[5]       ; PIN_D19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[6]       ; PIN_G15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]          ; PIN_H2        ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]          ; PIN_G3        ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]          ; PIN_F1        ; QSF Assignment ;
+; Location     ;                ;              ; LCD_BLON        ; PIN_F21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[0]     ; PIN_D22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[1]     ; PIN_D21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[2]     ; PIN_C22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[3]     ; PIN_C21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[4]     ; PIN_B22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[5]     ; PIN_B21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[6]     ; PIN_D20       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[7]     ; PIN_C20       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_EN          ; PIN_E21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_RS          ; PIN_F22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_RW          ; PIN_E22       ; QSF Assignment ;
+; Location     ;                ;              ; PS2_KBCLK       ; PIN_P22       ; QSF Assignment ;
+; Location     ;                ;              ; PS2_KBDAT       ; PIN_P21       ; QSF Assignment ;
+; Location     ;                ;              ; SD_CLK          ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; SD_CMD          ; PIN_Y22       ; QSF Assignment ;
+; Location     ;                ;              ; SD_DAT0         ; PIN_AA22      ; QSF Assignment ;
+; Location     ;                ;              ; SD_DAT3         ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; SD_WP_N         ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; UART_CTS        ; PIN_V21       ; QSF Assignment ;
+; Location     ;                ;              ; UART_RTS        ; PIN_V22       ; QSF Assignment ;
+; Location     ;                ;              ; UART_RXD        ; PIN_U22       ; QSF Assignment ;
+; Location     ;                ;              ; UART_TXD        ; PIN_U21       ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[10]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[11]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_BA_0       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_BA_1       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CAS_N      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CKE        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CLK        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CS_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_LDQM       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_RAS_N      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_UDQM       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_WE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[22]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[23]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[24]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[25]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[26]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[27]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[28]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[29]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[30]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[31]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[22]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[23]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[24]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[25]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[26]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[27]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[28]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[29]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[30]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[31]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+-----------------+---------------+----------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 111 ( 0.00 % )     ;
+;     -- Achieved     ; 0 / 111 ( 0.00 % )     ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 103     ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 8       ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin.
+
+
++-------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                     ;
++---------------------------------------------+---------------------+
+; Resource                                    ; Usage               ;
++---------------------------------------------+---------------------+
+; Total logic elements                        ; 0 / 15,408 ( 0 % )  ;
+;     -- Combinational with no register       ; 0                   ;
+;     -- Register only                        ; 0                   ;
+;     -- Combinational with a register        ; 0                   ;
+;                                             ;                     ;
+; Logic element usage by number of LUT inputs ;                     ;
+;     -- 4 input functions                    ; 0                   ;
+;     -- 3 input functions                    ; 0                   ;
+;     -- <=2 input functions                  ; 0                   ;
+;     -- Register only                        ; 0                   ;
+;                                             ;                     ;
+; Logic elements by mode                      ;                     ;
+;     -- normal mode                          ; 0                   ;
+;     -- arithmetic mode                      ; 0                   ;
+;                                             ;                     ;
+; Total registers*                            ; 0 / 17,068 ( 0 % )  ;
+;     -- Dedicated logic registers            ; 0 / 15,408 ( 0 % )  ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )   ;
+;                                             ;                     ;
+; Total LABs:  partially or completely used   ; 0 / 963 ( 0 % )     ;
+; Virtual pins                                ; 0                   ;
+; I/O pins                                    ; 51 / 347 ( 15 % )   ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )      ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )       ;
+;                                             ;                     ;
+; Global signals                              ; 0                   ;
+; M9Ks                                        ; 0 / 56 ( 0 % )      ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % ) ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )     ;
+; PLLs                                        ; 0 / 4 ( 0 % )       ;
+; Global clocks                               ; 0 / 20 ( 0 % )      ;
+; JTAGs                                       ; 0 / 1 ( 0 % )       ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )       ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )       ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )       ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%        ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%        ;
+; Maximum fan-out                             ; 1                   ;
+; Highest non-global fan-out                  ; 1                   ;
+; Total fan-out                               ; 55                  ;
+; Average fan-out                             ; 0.50                ;
++---------------------------------------------+---------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++--------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                      ;
++---------------------------------------------+-------------------+--------------------------------+
+; Statistic                                   ; Top               ; hard_block:auto_generated_inst ;
++---------------------------------------------+-------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low               ; Low                            ;
+;                                             ;                   ;                                ;
+; Total logic elements                        ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 0                 ; 0                              ;
+;     -- Register only                        ; 0                 ; 0                              ;
+;     -- Combinational with a register        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Logic element usage by number of LUT inputs ;                   ;                                ;
+;     -- 4 input functions                    ; 0                 ; 0                              ;
+;     -- 3 input functions                    ; 0                 ; 0                              ;
+;     -- <=2 input functions                  ; 0                 ; 0                              ;
+;     -- Register only                        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Logic elements by mode                      ;                   ;                                ;
+;     -- normal mode                          ; 0                 ; 0                              ;
+;     -- arithmetic mode                      ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Total registers                             ; 0                 ; 0                              ;
+;     -- Dedicated logic registers            ; 0 / 15408 ( 0 % ) ; 0 / 15408 ( 0 % )              ;
+;                                             ;                   ;                                ;
+; Total LABs:  partially or completely used   ; 0 / 963 ( 0 % )   ; 0 / 963 ( 0 % )                ;
+;                                             ;                   ;                                ;
+; Virtual pins                                ; 0                 ; 0                              ;
+; I/O pins                                    ; 51                ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )   ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                 ; 0                              ;
+; Total RAM block bits                        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Connections                                 ;                   ;                                ;
+;     -- Input Connections                    ; 0                 ; 0                              ;
+;     -- Registered Input Connections         ; 0                 ; 0                              ;
+;     -- Output Connections                   ; 0                 ; 0                              ;
+;     -- Registered Output Connections        ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Internal Connections                        ;                   ;                                ;
+;     -- Total Connections                    ; 51                ; 4                              ;
+;     -- Registered Connections               ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; External Connections                        ;                   ;                                ;
+;     -- Top                                  ; 0                 ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Partition Interface                         ;                   ;                                ;
+;     -- Input Ports                          ; 17                ; 0                              ;
+;     -- Output Ports                         ; 34                ; 0                              ;
+;     -- Bidir Ports                          ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Registered Ports                            ;                   ;                                ;
+;     -- Registered Input Ports               ; 0                 ; 0                              ;
+;     -- Registered Output Ports              ; 0                 ; 0                              ;
+;                                             ;                   ;                                ;
+; Port Connectivity                           ;                   ;                                ;
+;     -- Input Ports driven by GND            ; 0                 ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                 ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                 ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                 ; 0                              ;
+;     -- Input Ports with no Source           ; 0                 ; 0                              ;
+;     -- Output Ports with no Source          ; 0                 ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                 ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                 ; 0                              ;
++---------------------------------------------+-------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                      ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; BUTTON[0]  ; H2    ; 1        ; 0            ; 21           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; BUTTON[1]  ; G3    ; 1        ; 0            ; 23           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; BUTTON[2]  ; F1    ; 1        ; 0            ; 23           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; CLOCK_50   ; G21   ; 6        ; 41           ; 15           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; CLOCK_50_2 ; B12   ; 7        ; 19           ; 29           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; PS2_MSCLK  ; R21   ; 5        ; 41           ; 10           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; PS2_MSDAT  ; R22   ; 5        ; 41           ; 10           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]      ; J6    ; 1        ; 0            ; 24           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]      ; H5    ; 1        ; 0            ; 27           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]      ; H6    ; 1        ; 0            ; 25           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]      ; G4    ; 1        ; 0            ; 23           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]      ; G5    ; 1        ; 0            ; 27           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]      ; J7    ; 1        ; 0            ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]      ; H7    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]      ; E3    ; 1        ; 0            ; 26           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]      ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]      ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0_D[0] ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[1] ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[2] ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[3] ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[4] ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[5] ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[6] ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]   ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]   ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]   ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]   ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]   ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]   ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]   ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]   ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]   ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]   ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_BLANK ; AA15  ; 4        ; 26           ; 0            ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_B[0]  ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]  ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]  ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]  ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK   ; AB9   ; 3        ; 16           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]  ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]  ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]  ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]  ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS    ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]  ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]  ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]  ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]  ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_SYNC  ; A10   ; 8        ; 16           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_VS    ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                   ;
++----------+---------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                              ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+---------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                    ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO               ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO           ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                               ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                  ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                 ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                               ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                             ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                     ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                   ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO        ; HEX0_D[6]               ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                   ; Use as regular IO        ; HEX0_D[0]               ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                   ; Use as regular IO        ; HEX0_D[1]               ; Dual Purpose Pin          ;
++----------+---------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 1 / 46 ( 2 % )   ; 2.5V          ; --           ;
+; 4        ; 1 / 41 ( 2 % )   ; 2.5V          ; --           ;
+; 5        ; 2 / 46 ( 4 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 8 / 47 ( 17 % )  ; 3.3V          ; --           ;
+; 8        ; 1 / 43 ( 2 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; VGA_SYNC                                                  ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; VGA_BLANK                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; VGA_CLK                                                   ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; CLOCK_50_2                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; HEX0_D[0]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; BUTTON[2]                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; HEX0_D[1]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0_D[5]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0_D[6]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; BUTTON[1]                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0_D[4]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; BUTTON[0]                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0_D[2]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0_D[3]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; PS2_MSCLK                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R22      ; 206        ; 5        ; PS2_MSDAT                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                           ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+; |ise_proj                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 51   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |ise_proj           ; work         ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                        ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name       ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; VGA_CLK    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_SYNC   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_BLANK  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; PS2_MSDAT  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; PS2_MSCLK  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; CLOCK_50   ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; CLOCK_50_2 ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; BUTTON[2]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; BUTTON[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; BUTTON[0]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[7]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[6]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[5]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[4]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[3]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[2]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[1]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[0]      ; Input    ; --            ; --            ; --                    ; --  ; --   ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout                    ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; PS2_MSDAT           ;                   ;         ;
+; PS2_MSCLK           ;                   ;         ;
+; CLOCK_50            ;                   ;         ;
+; CLOCK_50_2          ;                   ;         ;
+; BUTTON[2]           ;                   ;         ;
+; BUTTON[1]           ;                   ;         ;
+; BUTTON[0]           ;                   ;         ;
+; SW[9]               ;                   ;         ;
+; SW[8]               ;                   ;         ;
+; SW[7]               ;                   ;         ;
+; SW[6]               ;                   ;         ;
+; SW[5]               ;                   ;         ;
+; SW[4]               ;                   ;         ;
+; SW[3]               ;                   ;         ;
+; SW[2]               ;                   ;         ;
+; SW[1]               ;                   ;         ;
+; SW[0]               ;                   ;         ;
++---------------------+-------------------+---------+
+
+
++--------------------------------------------------+
+; Other Routing Usage Summary                      ;
++-----------------------------+--------------------+
+; Other Routing Resource Type ; Usage              ;
++-----------------------------+--------------------+
+; Block interconnects         ; 0 / 47,787 ( 0 % ) ;
+; C16 interconnects           ; 0 / 1,804 ( 0 % )  ;
+; C4 interconnects            ; 0 / 31,272 ( 0 % ) ;
+; Global clocks               ; 0 / 20 ( 0 % )     ;
+; Local interconnects         ; 0 / 15,408 ( 0 % ) ;
+; R24 interconnects           ; 0 / 1,775 ( 0 % )  ;
+; R4 interconnects            ; 0 / 41,310 ( 0 % ) ;
++-----------------------------+--------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 48           ; 0            ; 48           ; 0            ; 0            ; 51        ; 48           ; 0            ; 51        ; 51        ; 0            ; 3            ; 0            ; 0            ; 17           ; 0            ; 3            ; 17           ; 0            ; 0            ; 0            ; 3            ; 0            ; 0            ; 0            ; 0            ; 0            ; 51        ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 3            ; 51           ; 3            ; 51           ; 51           ; 0         ; 3            ; 51           ; 0         ; 0         ; 51           ; 48           ; 51           ; 51           ; 34           ; 51           ; 48           ; 34           ; 51           ; 51           ; 51           ; 48           ; 51           ; 51           ; 51           ; 51           ; 51           ; 0         ; 51           ; 51           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_SYNC           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_BLANK          ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_MSDAT          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_MSCLK          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50_2         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BUTTON[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BUTTON[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BUTTON[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; On                       ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "ise_proj"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 51 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+    Info (169086): Pin VGA_SYNC not assigned to an exact location on the device
+    Info (169086): Pin VGA_BLANK not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 0 input, 3 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  44 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  39 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
+Warning (15709): Ignored I/O standard assignments to the following nodes
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[0]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[10]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[11]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[1]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[2]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[3]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[4]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[5]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[6]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[7]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[8]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[9]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_BA_0"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_BA_1"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CAS_N"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CKE"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CLK"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CS_N"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[0]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[10]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[11]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[12]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[13]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[14]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[15]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[1]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[2]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[3]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[4]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[5]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[6]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[7]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[8]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[9]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_LDQM"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_RAS_N"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_UDQM"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_WE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_BYTE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_CE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ15_AM1"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_OE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RST_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RY"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[10]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[11]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[12]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[13]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[14]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[15]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[16]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[17]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[18]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[19]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[20]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[21]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[22]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[23]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[24]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[25]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[26]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[27]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[28]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[29]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[30]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[31]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[7]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[8]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[9]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[10]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[11]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[12]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[13]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[14]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[15]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[16]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[17]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[18]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[19]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[20]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[21]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[22]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[23]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[24]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[25]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[26]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[27]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[28]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[29]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[30]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[31]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[7]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[8]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[9]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_BLON"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[0]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[1]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[2]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[3]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[4]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[5]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[6]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[7]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_EN"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RS"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RW"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBCLK"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBDAT"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CLK"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CMD"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT0"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT3"
+    Warning (15710): Ignored I/O standard assignment to node "SD_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "UART_CTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RXD"
+    Warning (15710): Ignored I/O standard assignment to node "UART_TXD"
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA_0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA_1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_LDQM" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_UDQM" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_BYTE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ15_AM1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKIN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKIN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKOUT[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKOUT[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKIN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKIN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKOUT[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKOUT[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_N0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_N1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_P0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_P1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_N0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_N1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_P0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_P1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_KBCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_KBDAT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_DAT0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_DAT3" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 17 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin PS2_MSDAT uses I/O standard 3.3-V LVTTL at R22
+    Info (169178): Pin PS2_MSCLK uses I/O standard 3.3-V LVTTL at R21
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin CLOCK_50_2 uses I/O standard 3.3-V LVTTL at B12
+    Info (169178): Pin BUTTON[2] uses I/O standard 3.3-V LVTTL at F1
+    Info (169178): Pin BUTTON[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin BUTTON[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+Info (144001): Generated suppressed messages file C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 525 warnings
+    Info: Peak virtual memory: 1054 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:11 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:05
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg.
+
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.summary b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.summary
new file mode 100644
index 0000000..7fbd693
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Mar 01 16:05:11 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : ise_proj
+Top-level Entity Name : ise_proj
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 0 / 15,408 ( 0 % )
+    Total combinational functions : 0 / 15,408 ( 0 % )
+    Dedicated logic registers : 0 / 15,408 ( 0 % )
+Total registers : 0
+Total pins : 51 / 347 ( 15 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.flow.rpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.flow.rpt
new file mode 100644
index 0000000..f2cda95
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.flow.rpt
@@ -0,0 +1,132 @@
+Flow report for ise_proj
+Tue Mar 01 16:05:15 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Mar 01 16:05:13 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ise_proj                                         ;
+; Top-level Entity Name              ; ise_proj                                         ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 0 / 15,408 ( 0 % )                               ;
+;     Total combinational functions  ; 0 / 15,408 ( 0 % )                               ;
+;     Dedicated logic registers      ; 0 / 15,408 ( 0 % )                               ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 51 / 347 ( 15 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/01/2016 16:05:05 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ise_proj            ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; ALLOW_POWER_UP_DONT_CARE            ; Off                                   ; On            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID               ; 260248564268246.145684830405960       ; --            ; --          ; --         ;
+; CYCLONEII_OPTIMIZATION_TECHNIQUE    ; Speed                                 ; Balanced      ; --          ; --         ;
+; ENABLE_ADVANCED_IO_TIMING           ; On                                    ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                  ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; DE0_TOP     ; Top        ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; DE0_VGA     ; Top        ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; DE0_TOP     ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; DE0_VGA     ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                                   ; --            ; --          ; eda_palace ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 437 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:05     ; 1.0                     ; 1054 MB             ; 00:00:05                           ;
+; Assembler                 ; 00:00:02     ; 1.0                     ; 424 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 480 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:10     ; --                      ; --                  ; 00:00:08                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj
+quartus_fit --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj
+quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj
+quartus_sta ise_proj -c ise_proj
+
+
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.jdi b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.jdi
new file mode 100644
index 0000000..a957b87
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="5f3f38a2322191ad942a"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="ise_proj.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.rpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.rpt
new file mode 100644
index 0000000..a51aa1b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.rpt
@@ -0,0 +1,412 @@
+Analysis & Synthesis report for ise_proj
+Tue Mar 01 16:05:05 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Elapsed Time Per Partition
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Mar 01 16:05:05 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ise_proj                                         ;
+; Top-level Entity Name              ; ise_proj                                         ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 0                                                ;
+;     Total combinational functions  ; 0                                                ;
+;     Dedicated logic registers      ; 0                                                ;
+; Total registers                    ; 0                                                ;
+; Total pins                         ; 51                                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; ise_proj           ; ise_proj           ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Power-Up Don't Care                                                        ; Off                ; On                 ;
+; Optimization Technique                                                     ; Speed              ; Balanced           ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                           ;
++----------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type                                ; File Name with Absolute Path                                                           ; Library ;
++----------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------+---------+
+; ise_proj.bdf                     ; yes             ; Auto-Found Block Diagram/Schematic File  ; C:/Catapult C/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf ;         ;
++----------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                  ;
++---------------------------------------------+----------------+
+; Resource                                    ; Usage          ;
++---------------------------------------------+----------------+
+;                                             ;                ;
+; Total combinational functions               ; 0              ;
+; Logic element usage by number of LUT inputs ;                ;
+;     -- 4 input functions                    ; 0              ;
+;     -- 3 input functions                    ; 0              ;
+;     -- <=2 input functions                  ; 0              ;
+;                                             ;                ;
+; Logic elements by mode                      ;                ;
+;     -- normal mode                          ; 0              ;
+;     -- arithmetic mode                      ; 0              ;
+;                                             ;                ;
+; Total registers                             ; 0              ;
+;     -- Dedicated logic registers            ; 0              ;
+;     -- I/O registers                        ; 0              ;
+;                                             ;                ;
+; I/O pins                                    ; 51             ;
+; Embedded Multiplier 9-bit elements          ; 0              ;
+; Maximum fan-out node                        ; VGA_CLK~output ;
+; Maximum fan-out                             ; 1              ;
+; Total fan-out                               ; 51             ;
+; Average fan-out                             ; 0.50           ;
++---------------------------------------------+----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+; |ise_proj                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 51   ; 0            ; |ise_proj           ; work         ;
++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 0     ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 0     ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 0     ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 16:05:04 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 7 design units, including 7 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001.v
+    Info (12023): Found entity 1: mgc_out_reg_pos
+    Info (12023): Found entity 2: mgc_out_reg_neg
+    Info (12023): Found entity 3: mgc_out_reg
+    Info (12023): Found entity 4: mgc_out_buf_wait
+    Info (12023): Found entity 5: mgc_out_fifo_wait
+    Info (12023): Found entity 6: mgc_out_fifo_wait_core
+    Info (12023): Found entity 7: mgc_pipe
+Info (12021): Found 20 design units, including 20 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport.v
+    Info (12023): Found entity 1: mgc_in_wire
+    Info (12023): Found entity 2: mgc_in_wire_en
+    Info (12023): Found entity 3: mgc_in_wire_wait
+    Info (12023): Found entity 4: mgc_chan_in
+    Info (12023): Found entity 5: mgc_out_stdreg
+    Info (12023): Found entity 6: mgc_out_stdreg_en
+    Info (12023): Found entity 7: mgc_out_stdreg_wait
+    Info (12023): Found entity 8: mgc_out_prereg_en
+    Info (12023): Found entity 9: mgc_inout_stdreg_en
+    Info (12023): Found entity 10: hid_tribuf
+    Info (12023): Found entity 11: mgc_inout_stdreg_wait
+    Info (12023): Found entity 12: mgc_inout_buf_wait
+    Info (12023): Found entity 13: mgc_inout_fifo_wait
+    Info (12023): Found entity 14: mgc_io_sync
+    Info (12023): Found entity 15: mgc_bsync_rdy
+    Info (12023): Found entity 16: mgc_bsync_vld
+    Info (12023): Found entity 17: mgc_bsync_rv
+    Info (12023): Found entity 18: mgc_sync
+    Info (12023): Found entity 19: funccall_inout
+    Info (12023): Found entity 20: modulario_en_in
+Info (12021): Found 3 design units, including 3 entities, in source file /catapult c/dot_product/dot_product/rtl.v
+    Info (12023): Found entity 1: dot_product_core_fsm
+    Info (12023): Found entity 2: dot_product_core
+    Info (12023): Found entity 3: dot_product
+Warning (12125): Using design file ise_proj.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
+    Info (12023): Found entity 1: ise_proj
+Info (12127): Elaborating entity "ise_proj" for the top level hierarchy
+Warning (275002): No superset bus at connection
+Warning (275043): Pin "VGA_CLK" is missing source
+Warning (275043): Pin "VGA_SYNC" is missing source
+Warning (275043): Pin "VGA_BLANK" is missing source
+Warning (275043): Pin "VGA_VS" is missing source
+Warning (275043): Pin "VGA_HS" is missing source
+Warning (275043): Pin "HEX0_D[6..0]" is missing source
+Warning (275043): Pin "VGA_B[3..0]" is missing source
+Warning (275043): Pin "VGA_G[3..0]" is missing source
+Warning (275043): Pin "VGA_R[3..0]" is missing source
+Warning (275009): Pin "PS2_MSDAT" not connected
+Warning (275009): Pin "PS2_MSCLK" not connected
+Warning (275009): Pin "CLOCK_50" not connected
+Warning (275009): Pin "CLOCK_50_2" not connected
+Warning (275009): Pin "BUTTON" not connected
+Warning (275009): Pin "SW" not connected
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "VGA_CLK" is stuck at GND
+    Warning (13410): Pin "VGA_SYNC" is stuck at GND
+    Warning (13410): Pin "VGA_BLANK" is stuck at GND
+    Warning (13410): Pin "VGA_VS" is stuck at GND
+    Warning (13410): Pin "VGA_HS" is stuck at GND
+    Warning (13410): Pin "HEX0_D[6]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[5]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[4]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[3]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[2]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[1]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[0]" is stuck at GND
+    Warning (13410): Pin "LEDG[9]" is stuck at GND
+    Warning (13410): Pin "LEDG[8]" is stuck at GND
+    Warning (13410): Pin "LEDG[7]" is stuck at GND
+    Warning (13410): Pin "LEDG[6]" is stuck at GND
+    Warning (13410): Pin "LEDG[5]" is stuck at GND
+    Warning (13410): Pin "LEDG[4]" is stuck at GND
+    Warning (13410): Pin "LEDG[3]" is stuck at GND
+    Warning (13410): Pin "LEDG[2]" is stuck at GND
+    Warning (13410): Pin "LEDG[1]" is stuck at GND
+    Warning (13410): Pin "LEDG[0]" is stuck at GND
+    Warning (13410): Pin "VGA_B[3]" is stuck at GND
+    Warning (13410): Pin "VGA_B[2]" is stuck at GND
+    Warning (13410): Pin "VGA_B[1]" is stuck at GND
+    Warning (13410): Pin "VGA_B[0]" is stuck at GND
+    Warning (13410): Pin "VGA_G[3]" is stuck at GND
+    Warning (13410): Pin "VGA_G[2]" is stuck at GND
+    Warning (13410): Pin "VGA_G[1]" is stuck at GND
+    Warning (13410): Pin "VGA_G[0]" is stuck at GND
+    Warning (13410): Pin "VGA_R[3]" is stuck at GND
+    Warning (13410): Pin "VGA_R[2]" is stuck at GND
+    Warning (13410): Pin "VGA_R[1]" is stuck at GND
+    Warning (13410): Pin "VGA_R[0]" is stuck at GND
+Warning (20013): Ignored assignments for entity "DE0_TOP" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored
+Warning (20013): Ignored assignments for entity "DE0_VGA" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 17 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "PS2_MSDAT"
+    Warning (15610): No output dependent on input pin "PS2_MSCLK"
+    Warning (15610): No output dependent on input pin "CLOCK_50"
+    Warning (15610): No output dependent on input pin "CLOCK_50_2"
+    Warning (15610): No output dependent on input pin "BUTTON[2]"
+    Warning (15610): No output dependent on input pin "BUTTON[1]"
+    Warning (15610): No output dependent on input pin "BUTTON[0]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+    Warning (15610): No output dependent on input pin "SW[7]"
+    Warning (15610): No output dependent on input pin "SW[6]"
+    Warning (15610): No output dependent on input pin "SW[5]"
+    Warning (15610): No output dependent on input pin "SW[4]"
+    Warning (15610): No output dependent on input pin "SW[3]"
+    Warning (15610): No output dependent on input pin "SW[2]"
+    Warning (15610): No output dependent on input pin "SW[1]"
+    Warning (15610): No output dependent on input pin "SW[0]"
+Info (21057): Implemented 51 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 17 input pins
+    Info (21059): Implemented 34 output pins
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 120 warnings
+    Info: Peak virtual memory: 448 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:05 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.summary b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.summary
new file mode 100644
index 0000000..a4c6e04
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Mar 01 16:05:05 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : ise_proj
+Top-level Entity Name : ise_proj
+Family : Cyclone III
+Total logic elements : 0
+    Total combinational functions : 0
+    Dedicated logic registers : 0
+Total registers : 0
+Total pins : 51
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin
new file mode 100644
index 0000000..f006820
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "ise_proj"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+VGA_SYNC                     : A10       : output : 2.5 V             :         : 8         : N              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+VGA_BLANK                    : AA15      : output : 2.5 V             :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+VGA_CLK                      : AB9       : output : 2.5 V             :         : 3         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+CLOCK_50_2                   : B12       : input  : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+HEX0_D[0]                    : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+BUTTON[2]                    : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+HEX0_D[1]                    : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0_D[5]                    : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0_D[6]                    : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+BUTTON[1]                    : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0_D[4]                    : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+BUTTON[0]                    : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0_D[2]                    : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0_D[3]                    : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R12       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+PS2_MSCLK                    : R21       : input  : 3.3-V LVTTL       :         : 5         : Y              
+PS2_MSDAT                    : R22       : input  : 3.3-V LVTTL       :         : 5         : Y              
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf
new file mode 100644
index 0000000..57c6904
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Full Version
+# Date created = 04:19:33  August 08, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.0"
+DATE = "04:19:33  August 08, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "ise_proj"
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf
new file mode 100644
index 0000000..adb5d40
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf
@@ -0,0 +1,689 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Full Version
+# Date created = 04:19:33  August 08, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ise_proj_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY ise_proj
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "04:19:33  AUGUST 08, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_location_assignment PIN_F1 -to BUTTON[2]
+set_location_assignment PIN_G3 -to BUTTON[1]
+set_location_assignment PIN_H2 -to BUTTON[0]
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+set_location_assignment PIN_U7 -to GPIO0_D[31]
+set_location_assignment PIN_V5 -to GPIO0_D[30]
+set_location_assignment PIN_W6 -to GPIO0_D[29]
+set_location_assignment PIN_W7 -to GPIO0_D[28]
+set_location_assignment PIN_V8 -to GPIO0_D[27]
+set_location_assignment PIN_T8 -to GPIO0_D[26]
+set_location_assignment PIN_W10 -to GPIO0_D[25]
+set_location_assignment PIN_Y10 -to GPIO0_D[24]
+set_location_assignment PIN_V11 -to GPIO0_D[23]
+set_location_assignment PIN_R10 -to GPIO0_D[22]
+set_location_assignment PIN_V12 -to GPIO0_D[21]
+set_location_assignment PIN_U13 -to GPIO0_D[20]
+set_location_assignment PIN_W13 -to GPIO0_D[19]
+set_location_assignment PIN_Y13 -to GPIO0_D[18]
+set_location_assignment PIN_U14 -to GPIO0_D[17]
+set_location_assignment PIN_V14 -to GPIO0_D[16]
+set_location_assignment PIN_AA4 -to GPIO0_D[15]
+set_location_assignment PIN_AB4 -to GPIO0_D[14]
+set_location_assignment PIN_AA5 -to GPIO0_D[13]
+set_location_assignment PIN_AB5 -to GPIO0_D[12]
+set_location_assignment PIN_AA8 -to GPIO0_D[11]
+set_location_assignment PIN_AB8 -to GPIO0_D[10]
+set_location_assignment PIN_AA10 -to GPIO0_D[9]
+set_location_assignment PIN_AB10 -to GPIO0_D[8]
+set_location_assignment PIN_AA13 -to GPIO0_D[7]
+set_location_assignment PIN_AB13 -to GPIO0_D[6]
+set_location_assignment PIN_AB14 -to GPIO0_D[5]
+set_location_assignment PIN_AA14 -to GPIO0_D[4]
+set_location_assignment PIN_AB15 -to GPIO0_D[3]
+set_location_assignment PIN_AA15 -to GPIO0_D[2]
+set_location_assignment PIN_AA16 -to GPIO0_D[1]
+set_location_assignment PIN_AB16 -to GPIO0_D[0]
+set_location_assignment PIN_AB12 -to GPIO0_CLKIN[0]
+set_location_assignment PIN_AA12 -to GPIO0_CLKIN[1]
+set_location_assignment PIN_AB3 -to GPIO0_CLKOUT[0]
+set_location_assignment PIN_AA3 -to GPIO0_CLKOUT[1]
+set_location_assignment PIN_AA11 -to GPIO1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO1_CLKIN[0]
+set_location_assignment PIN_T16 -to GPIO1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO1_CLKOUT[0]
+set_location_assignment PIN_V7 -to GPIO1_D[31]
+set_location_assignment PIN_V6 -to GPIO1_D[30]
+set_location_assignment PIN_U8 -to GPIO1_D[29]
+set_location_assignment PIN_Y7 -to GPIO1_D[28]
+set_location_assignment PIN_T9 -to GPIO1_D[27]
+set_location_assignment PIN_U9 -to GPIO1_D[26]
+set_location_assignment PIN_T10 -to GPIO1_D[25]
+set_location_assignment PIN_U10 -to GPIO1_D[24]
+set_location_assignment PIN_R12 -to GPIO1_D[23]
+set_location_assignment PIN_R11 -to GPIO1_D[22]
+set_location_assignment PIN_T12 -to GPIO1_D[21]
+set_location_assignment PIN_U12 -to GPIO1_D[20]
+set_location_assignment PIN_R14 -to GPIO1_D[19]
+set_location_assignment PIN_T14 -to GPIO1_D[18]
+set_location_assignment PIN_AB7 -to GPIO1_D[17]
+set_location_assignment PIN_AA7 -to GPIO1_D[16]
+set_location_assignment PIN_AA9 -to GPIO1_D[15]
+set_location_assignment PIN_AB9 -to GPIO1_D[14]
+set_location_assignment PIN_V15 -to GPIO1_D[13]
+set_location_assignment PIN_W15 -to GPIO1_D[12]
+set_location_assignment PIN_T15 -to GPIO1_D[11]
+set_location_assignment PIN_U15 -to GPIO1_D[10]
+set_location_assignment PIN_W17 -to GPIO1_D[9]
+set_location_assignment PIN_Y17 -to GPIO1_D[8]
+set_location_assignment PIN_AB17 -to GPIO1_D[7]
+set_location_assignment PIN_AA17 -to GPIO1_D[6]
+set_location_assignment PIN_AA18 -to GPIO1_D[5]
+set_location_assignment PIN_AB18 -to GPIO1_D[4]
+set_location_assignment PIN_AB19 -to GPIO1_D[3]
+set_location_assignment PIN_AA19 -to GPIO1_D[2]
+set_location_assignment PIN_AB20 -to GPIO1_D[1]
+set_location_assignment PIN_AA20 -to GPIO1_D[0]
+set_location_assignment PIN_P22 -to PS2_KBCLK
+set_location_assignment PIN_P21 -to PS2_KBDAT
+set_location_assignment PIN_R21 -to PS2_MSCLK
+set_location_assignment PIN_R22 -to PS2_MSDAT
+set_location_assignment PIN_U22 -to UART_RXD
+set_location_assignment PIN_U21 -to UART_TXD
+set_location_assignment PIN_V22 -to UART_RTS
+set_location_assignment PIN_V21 -to UART_CTS
+set_location_assignment PIN_Y21 -to SD_CLK
+set_location_assignment PIN_Y22 -to SD_CMD
+set_location_assignment PIN_AA22 -to SD_DAT0
+set_location_assignment PIN_W21 -to SD_DAT3
+set_location_assignment PIN_W20 -to SD_WP_N
+set_location_assignment PIN_C20 -to LCD_DATA[7]
+set_location_assignment PIN_D20 -to LCD_DATA[6]
+set_location_assignment PIN_B21 -to LCD_DATA[5]
+set_location_assignment PIN_B22 -to LCD_DATA[4]
+set_location_assignment PIN_C21 -to LCD_DATA[3]
+set_location_assignment PIN_C22 -to LCD_DATA[2]
+set_location_assignment PIN_D21 -to LCD_DATA[1]
+set_location_assignment PIN_D22 -to LCD_DATA[0]
+set_location_assignment PIN_E22 -to LCD_RW
+set_location_assignment PIN_F22 -to LCD_RS
+set_location_assignment PIN_E21 -to LCD_EN
+set_location_assignment PIN_F21 -to LCD_BLON
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region"
+set_location_assignment PIN_F1 -to KEY[2]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_U7 -to GPIO_0[31]
+set_location_assignment PIN_V5 -to GPIO_0[30]
+set_location_assignment PIN_W6 -to GPIO_0[29]
+set_location_assignment PIN_W7 -to GPIO_0[28]
+set_location_assignment PIN_V8 -to GPIO_0[27]
+set_location_assignment PIN_T8 -to GPIO_0[26]
+set_location_assignment PIN_W10 -to GPIO_0[25]
+set_location_assignment PIN_Y10 -to GPIO_0[24]
+set_location_assignment PIN_V11 -to GPIO_0[23]
+set_location_assignment PIN_R10 -to GPIO_0[22]
+set_location_assignment PIN_V12 -to GPIO_0[21]
+set_location_assignment PIN_U13 -to GPIO_0[20]
+set_location_assignment PIN_W13 -to GPIO_0[19]
+set_location_assignment PIN_Y13 -to GPIO_0[18]
+set_location_assignment PIN_U14 -to GPIO_0[17]
+set_location_assignment PIN_V14 -to GPIO_0[16]
+set_location_assignment PIN_AA4 -to GPIO_0[15]
+set_location_assignment PIN_AB4 -to GPIO_0[14]
+set_location_assignment PIN_AA5 -to GPIO_0[13]
+set_location_assignment PIN_AB5 -to GPIO_0[12]
+set_location_assignment PIN_AA8 -to GPIO_0[11]
+set_location_assignment PIN_AB8 -to GPIO_0[10]
+set_location_assignment PIN_AA10 -to GPIO_0[9]
+set_location_assignment PIN_AB10 -to GPIO_0[8]
+set_location_assignment PIN_AA13 -to GPIO_0[7]
+set_location_assignment PIN_AB13 -to GPIO_0[6]
+set_location_assignment PIN_AB14 -to GPIO_0[5]
+set_location_assignment PIN_AA14 -to GPIO_0[4]
+set_location_assignment PIN_AB15 -to GPIO_0[3]
+set_location_assignment PIN_AA15 -to GPIO_0[2]
+set_location_assignment PIN_AA16 -to GPIO_0[1]
+set_location_assignment PIN_AB16 -to GPIO_0[0]
+set_location_assignment PIN_AB12 -to GPIO_CLKIN_N0
+set_location_assignment PIN_AA12 -to GPIO_CLKIN_P0
+set_location_assignment PIN_AB3 -to GPIO_CLKOUT_N0
+set_location_assignment PIN_AA3 -to GPIO_CLKOUT_P0
+set_location_assignment PIN_AA11 -to GPIO_CLKIN_P1
+set_location_assignment PIN_AB11 -to GPIO_CLKIN_N1
+set_location_assignment PIN_T16 -to GPIO_CLKOUT_P1
+set_location_assignment PIN_R16 -to GPIO_CLKOUT_N1
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0[7]
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1[7]
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2[7]
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3[7]
+set_location_assignment PIN_B5 -to DRAM_BA[0]
+set_location_assignment PIN_A4 -to DRAM_BA[1]
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE ../../../../dot_product/dot_product/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE ../../../../dot_product/dot_product/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE ../../../../dot_product/dot_product/rtl.v
+set_global_assignment -name CDF_FILE ../../../../dot_product/dot_product_pipelined/output_files/Chain1.cdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qws b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qws
new file mode 100644
index 0000000..79cd35d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qws
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof
new file mode 100644
index 0000000..2256378
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt
new file mode 100644
index 0000000..b364c36
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt
@@ -0,0 +1,558 @@
+TimeQuest Timing Analyzer report for ise_proj
+Tue Mar 01 16:05:15 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Datasheet Report
+ 13. Slow 1200mV 85C Model Metastability Report
+ 14. Slow 1200mV 0C Model Fmax Summary
+ 15. Slow 1200mV 0C Model Setup Summary
+ 16. Slow 1200mV 0C Model Hold Summary
+ 17. Slow 1200mV 0C Model Recovery Summary
+ 18. Slow 1200mV 0C Model Removal Summary
+ 19. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 20. Slow 1200mV 0C Model Datasheet Report
+ 21. Slow 1200mV 0C Model Metastability Report
+ 22. Fast 1200mV 0C Model Setup Summary
+ 23. Fast 1200mV 0C Model Hold Summary
+ 24. Fast 1200mV 0C Model Recovery Summary
+ 25. Fast 1200mV 0C Model Removal Summary
+ 26. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 27. Fast 1200mV 0C Model Datasheet Report
+ 28. Fast 1200mV 0C Model Metastability Report
+ 29. Multicorner Timing Analysis Summary
+ 30. Board Trace Model Assignments
+ 31. Input Transition Times
+ 32. Slow Corner Signal Integrity Metrics
+ 33. Fast Corner Signal Integrity Metrics
+ 34. Clock Transfers
+ 35. Report TCCS
+ 36. Report RSKM
+ 37. Unconstrained Paths
+ 38. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; ise_proj                                                           ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
+----------
+; Clocks ;
+----------
+No clocks to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
+-----------------------------------------------------
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------------------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Datasheet Report ;
+------------------------------------------
+Nothing to report.
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Datasheet Report ;
+-----------------------------------------
+Nothing to report.
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
+----------------------------------------------------
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Datasheet Report ;
+-----------------------------------------
+Nothing to report.
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                        ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; N/A                 ;
+; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; VGA_CLK       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_SYNC      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_BLANK     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; PS2_MSDAT               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_MSCLK               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50_2              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; BUTTON[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; BUTTON[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; BUTTON[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; VGA_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_SYNC      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_BLANK     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_VS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_HS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; HEX0_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; VGA_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_SYNC      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_BLANK     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_VS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_HS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; HEX0_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 0     ; 0    ;
+; Unconstrained Input Port Paths  ; 0     ; 0    ;
+; Unconstrained Output Ports      ; 0     ; 0    ;
+; Unconstrained Output Port Paths ; 0     ; 0    ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 16:05:13 2016
+Info: Command: quartus_sta ise_proj -c ise_proj
+Info: qsta_default_script.tcl version: #1
+Warning (20013): Ignored assignments for entity "DE0_TOP" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored
+Warning (20013): Ignored assignments for entity "DE0_VGA" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info (332159): No clocks to report
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info: Analyzing Fast 1200mV 0C Model
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Warning (332068): No clocks defined in design.
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332140): No Minimum Pulse Width paths to report
+Info (332101): Design is fully constrained for setup requirements
+Info (332101): Design is fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 54 warnings
+    Info: Peak virtual memory: 480 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:15 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.summary b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.summary
new file mode 100644
index 0000000..33f7436
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.summary
@@ -0,0 +1,5 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+------------------------------------------------------------
diff --git a/student_files_2015/student_files_2015/prj2/.DS_Store b/student_files_2015/student_files_2015/prj2/.DS_Store
new file mode 100644
index 0000000..d3509f7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/.DS_Store b/student_files_2015/student_files_2015/prj2/catapult_proj/.DS_Store
new file mode 100644
index 0000000..7eb20ea
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/.DS_Store
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.c b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.c
new file mode 100644
index 0000000..37811dc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.c
@@ -0,0 +1,136 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           blur.cpp
+//  Description:    video to vga blur filter - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+// based on the FIR design - page 230 of HLS Blue Book
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 27 MHz
+//  Top design: vga_blur
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraints:
+//  interface>vin: wordlength = 150, streaming = 150
+//  interface>vout: wordlength = 30, streaming = 30
+//  core>main: pipeline + distributed + merged
+//  core>main>frame: merged
+//  core>main>frame>shift, mac1, mac2: unroll + merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+#include <ac_fixed.h>
+#include "blur.h"
+#include <iostream>
+
+// shift_class: page 119 HLS Blue Book
+#include "shift_class.h" 
+
+
+
+
+#pragma hls_design top
+void mean_vga(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS])
+{
+    ac_int<16, false> red, green, blue, r[KERNEL_WIDTH], g[KERNEL_WIDTH], b[KERNEL_WIDTH];
+    
+
+// #if 1: use filter
+// #if 0: copy input to output bypassing filter
+#if 1
+
+    // shifts pixels from KERNEL_WIDTH rows and keeps KERNEL_WIDTH columns (KERNEL_WIDTHxKERNEL_WIDTH pixels stored)
+    static shift_class<ac_int<PIXEL_WL*KERNEL_WIDTH,false>, KERNEL_WIDTH> regs;
+    int i;
+
+    FRAME: for(int p = 0; p < NUM_PIXELS; p++) {
+		// init
+		red = 0; 
+		green = 0; 
+		blue = 0;
+		RESET: for(i = 0; i < KERNEL_WIDTH; i++) {
+			r[i] = 0;
+			g[i] = 0;
+			b[i] = 0;
+		}
+	    
+		// shift input data in the filter fifo
+		regs << vin[p]; // advance the pointer address by the pixel number (testbench/simulation only)
+		// accumulate
+		ACC1: for(i = 0; i < KERNEL_WIDTH; i++) {
+			// current line
+			r[0] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL));
+			g[0] += (regs[i].slc<COLOUR_WL>(COLOUR_WL));
+			b[0] += (regs[i].slc<COLOUR_WL>(0));
+			// the line before ...
+			r[1] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + PIXEL_WL));
+			g[1] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + PIXEL_WL));
+			b[1] += (regs[i].slc<COLOUR_WL>(0 + PIXEL_WL));
+			// the line before ...
+			r[2] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 2*PIXEL_WL));
+			g[2] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 2*PIXEL_WL)) ;
+			b[2] += (regs[i].slc<COLOUR_WL>(0 + 2*PIXEL_WL)) ;
+			// the line before ... 
+			r[3] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 3*PIXEL_WL));
+			g[3] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 3*PIXEL_WL)) ;
+			b[3] += (regs[i].slc<COLOUR_WL>(0 + 3*PIXEL_WL)) ;
+			// the line before ...
+			r[4] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 4*PIXEL_WL));
+			g[4] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 4*PIXEL_WL)) ;
+			b[4] += (regs[i].slc<COLOUR_WL>(0 + 4*PIXEL_WL)) ;
+		}
+		// add the accumualted value for all processed lines
+		ACC2: for(i = 0; i < KERNEL_WIDTH; i++) {    
+			red += r[i];
+			green += g[i];
+			blue += b[i];
+		}
+		// normalize result
+		red /= KERNEL_NUMEL;
+		green /= KERNEL_NUMEL;
+		blue /= KERNEL_NUMEL;
+	    
+		// group the RGB components into a single signal
+		vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);
+	    
+    }
+}
+     
+     
+     
+     
+     
+     
+#else    
+// display input  (test only)
+    FRAME: for(p = 0; p < NUM_PIXELS; p++) {
+        // copy the value of each colour component from the input stream
+        red = vin[p].slc<COLOUR_WL>(2*COLOUR_WL);
+        green = vin[p].slc<COLOUR_WL>(COLOUR_WL);
+        blue = vin[p].slc<COLOUR_WL>(0);
+
+		// combine the 3 color components into 1 signal only
+        vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);   
+    }
+}
+#endif
+
+
+// end of file
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.h b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.h
new file mode 100644
index 0000000..565b7c3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/blur.h
@@ -0,0 +1,45 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           blur.h
+//  Description:    vga blur - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _BLUR
+#define _BLUR
+
+#include <ac_int.h>
+#include <iostream>
+
+// total number of pixels from screen frame/image read in testbench
+#define NUM_PIXELS (640*480)
+
+#define KERNEL_WIDTH      5
+#define KERNEL_NUMEL      (KERNEL_WIDTH * KERNEL_WIDTH)
+#define COLOUR_WL         10
+#define PIXEL_WL          (3 * COLOUR_WL)
+
+#define  COORD_WL          10
+
+
+void mean_vga(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS]);
+
+#endif
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp
new file mode 100644
index 0000000..a3d7bff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp
@@ -0,0 +1,2967 @@
+#include <cstdlib>
+#include <iostream>
+#include <iomanip>
+#include <fstream>
+
+using namespace std;
+
+#include "bmp_io.h"
+
+//
+//  BMP_BYTE_SWAP controls how the program assumes that the bytes in 
+//  multi-byte data are ordered.
+//
+//  "true" is the correct value to use when running on a little-endian machine,
+//  and "false" is for big-endian.
+//
+
+static bool bmp_byte_swap = true;
+
+//****************************************************************************80
+
+bool bmp_byte_swap_get ( void )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_GET returns the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, bool BMP_BYTE_SWAP_GET, the internal value of BMP_BYTE_SWAP.
+//
+{
+  return bmp_byte_swap;
+}
+//****************************************************************************80
+
+void bmp_byte_swap_set ( bool value )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_SET sets the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, bool VALUE, the new value of BMP_BYTE_SWAP.
+//
+{
+  bmp_byte_swap = value;
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_READ reads 8 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//    Thanks to Kelly Anderson for pointing out how to modify the program
+//    to handle monochrome images.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    01 April 2005
+//
+//  Author:
+//
+//    Kelly Anderson
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, a pointer to the red color arrays.
+//
+//    Output, bool BMP_08_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_WRITE writes 8 bit image data to a BMP file.
+//
+//  Discussion:
+//
+//    This routine does not seem to be performing properly.  The monochrome
+//    images it creates cannot be read by the XV program, which says that 
+//    they seem to have been prematurely truncated.
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexr;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_READ reads 24 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the 
+//    red, green and blue color arrays.
+//
+//    Output, bool BMP_24_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading B for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexb = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexb = indexb + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading G for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexg = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexg = indexg + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_WRITE writes 24 bit image data to the BMP file.
+//
+//  Discussion:
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexb;
+      file_out << *indexg;
+      file_out << *indexr;
+
+      indexb = indexb + 1;
+      indexg = indexg + 1;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_PRINT prints the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file header:\n";
+  cout << "\n";
+  cout << "    FILETYPE =     " << filetype     << "\n";
+  cout << "    FILESIZE =     " << filesize     << "\n";
+  cout << "    RESERVED1 =    " << reserved1    << "\n";
+  cout << "    RESERVED2 =    " << reserved2    << "\n";
+  cout << "    BITMAPOFFSET = " << bitmapoffset << "\n";
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned short int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_READ reads the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    15 December 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned short int *FILETYPE, the file type.
+//
+//    Output, unsigned long int *FILESIZE, the file size.
+//
+//    Output, unsigned short int *RESERVED1, a reserved value.
+//
+//    Output, unsigned short int *RESERVED2, a reserved value.
+//
+//    Output, unsigned long int *BITMAPOFFSET, the bitmap offset.
+//
+{
+  bool error;
+  char i1;
+  char i2;  
+//
+//  Read FILETYPE.
+//
+  error = u_short_int_read ( filetype, file_in );
+
+  if ( error )
+  {
+    return error;
+  }
+//
+//  If you are doing swapping, you have to reunswap the filetype, I think, JVB 15 December 2004.
+//
+  if ( bmp_byte_swap )
+  {
+    i1 = ( char ) ( *filetype / 256 );
+    i2 = ( char ) ( *filetype % 256 );
+    *filetype = i2 * 256 + i1;
+  }
+//
+//  Read FILESIZE.
+//
+  error = u_long_int_read ( filesize, file_in );
+  if ( error ) 
+  {
+    return error;
+  }
+//
+//  Read RESERVED1.
+//
+  error = u_short_int_read ( reserved1, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read RESERVED2.
+//
+  error = u_short_int_read ( reserved2, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITMAPOFFSET.
+//
+  error = u_long_int_read ( bitmapoffset, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_WRITE writes the header information to a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  u_short_int_write ( filetype, file_out );
+  u_long_int_write ( filesize, file_out );
+  u_short_int_write ( reserved1, file_out );
+  u_short_int_write ( reserved2, file_out );
+  u_long_int_write ( bitmapoffset, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_PRINT prints the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header ( = 40 bytes).
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    06 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file bitmap header:\n";
+  cout << "\n";
+  cout << "    SIZE =            " << size            << "\n";
+  cout << "    WIDTH =           " << width           << "\n";
+  cout << "    HEIGHT =          " << height          << "\n";
+  cout << "    PLANES =          " << planes          << "\n";
+  cout << "    BITSPERPIXEL =    " << bitsperpixel    << "\n";
+  cout << "    COMPRESSION =     " << compression     << "\n";
+  cout << "    SIZEOFBITMAP =    " << sizeofbitmap    << "\n";
+  cout << "    HORZRESOLUTION =  " << horzresolution  << "\n";
+  cout << "    VERTRESOLUTION =  " << vertresolution  << "\n";
+  cout << "    COLORSUSED =      " << colorsused      << "\n";
+  cout << "    COLORSIMPORTANT = " << colorsimportant << "\n";
+
+  return;
+} 
+//****************************************************************************80
+
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_READ reads the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned long int *SIZE, the size of this header in bytes.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned short int *PLANES, the number of color planes.
+//
+//    Output, unsigned short int *BITSPERPIXEL, color bits per pixel.
+//
+//    Output, unsigned long int *COMPRESSION, the compression option.
+//
+//    Output, unsigned long int *SIZEOFBITMAP, the size of the bitmap.
+//
+//    Output, unsigned long int *HORZRESOLUTION, the horizontal resolution.
+//
+//    Output, unsigned long int *VERTRESOLUTION, the vertical resolution.
+//
+//    Output, unsigned long int *COLORSUSED, the number of colors in the palette.
+//
+//    Output, unsigned long int *COLORSIMPORTANT, the minimum number of colors.
+//
+//    Output, bool BMP_HEADER2_READ, is true if an error occurred.
+//
+{
+  bool error;
+//
+//  Read SIZE, the size of the header in bytes.
+//
+  error = u_long_int_read ( size, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read WIDTH, the image width in pixels.
+//
+  error = u_long_int_read ( width, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HEIGHT, the image height in pixels.
+//
+  error = long_int_read ( height, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read PLANES, the number of color planes.
+//
+  error = u_short_int_read ( planes, file_in ); 
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITSPERPIXEL.
+//
+  error = u_short_int_read ( bitsperpixel, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COMPRESSION.
+//
+  error = u_long_int_read ( compression, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read SIZEOFBITMAP.
+//
+  error = u_long_int_read ( sizeofbitmap, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HORZRESOLUTION.
+//
+  error = u_long_int_read ( horzresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read VERTRESOLUTION.
+//
+  error = u_long_int_read ( vertresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSUSED.
+//
+  error = u_long_int_read ( colorsused, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSIMPORTANT.
+//
+  error = u_long_int_read ( colorsimportant, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_WRITE writes the bitmap header information to a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Mark Cave-Ayland, mca198@ecs.soton.ac.uk, for pointing out an 
+//    error which caused the code to write one too many long ints, 19 May 2001.
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimensions of the image.
+//
+//    Input, long int HEIGHT, the Y dimensions of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  u_long_int_write ( size, file_out );
+  u_long_int_write ( width, file_out );
+  long_int_write ( height, file_out );
+  u_short_int_write ( planes, file_out ); 
+  u_short_int_write ( bitsperpixel, file_out );
+  u_long_int_write ( compression, file_out );
+  u_long_int_write ( sizeofbitmap, file_out );
+  u_long_int_write ( horzresolution, file_out );
+  u_long_int_write ( vertresolution, file_out );
+  u_long_int_write ( colorsused, file_out );
+  u_long_int_write ( colorsimportant, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_PRINT prints the palette data in a BMP file.
+// 
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  cout << "\n";
+  cout << "  Palette information from BMP file:\n";
+  cout << "\n";
+
+  if ( colorsused < 1 )
+  {
+    cout << "    There are NO colors defined for the palette.\n";
+    return;
+  }
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  cout << "\n";
+  cout << " Color    Blue   Green     Red   Trans\n";
+  cout << "\n";
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    cout << setw(6) << i       << "  "
+         << setw(6) << *indexb << "  "
+         << setw(6) << *indexg << "  "
+         << setw(6) << *indexr << "  "
+         << setw(6) << *indexa << "\n";
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_PALETTE_READ reads the palette information of a BMP file.
+//
+//  Discussion:
+// 
+//    There are COLORSUSED colors listed.  For each color, the values of
+//    (B,G,R,A) are listed, where A is a quantity reserved for future use.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2003
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+//    Output, bool BMP_PALETTE_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading B for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexb = ( unsigned char ) c;
+    indexb = indexb + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading G for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexg = ( unsigned char ) c;
+    indexg = indexg + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading R for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexr = ( unsigned char ) c;
+    indexr = indexr + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading A for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexa = ( unsigned char ) c;
+    indexa = indexa + 1;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_WRITE writes the palette data to the BMP file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    file_out << *indexb;
+    file_out << *indexg;
+    file_out << *indexr;
+    file_out << *indexa;
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_print_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_PRINT_TEST tests the BMP print routines.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    13 August 2007
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_PRINT_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *aparray;
+  unsigned char *barray;
+  unsigned char *bparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *garray;
+  unsigned char *gparray;
+  long int height;
+  unsigned long int horzresolution;
+  int numbytes;
+  unsigned short int planes;
+  unsigned char *rarray;
+  unsigned char *rparray;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+  unsigned long int width;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_PRINT_TEST - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+  cout << "\n";
+  cout << "BMP_PRINT_TEST:\n";
+  cout << "  Contents of BMP file \"" << file_in_name << "\"\n";
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+
+  bmp_header1_print ( filetype, filesize, reserved1, reserved2, bitmapoffset );
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, &width, &height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+
+  bmp_header2_print ( size, width, height, planes, bitsperpixel,
+    compression, sizeofbitmap, horzresolution, vertresolution, 
+    colorsused, colorsimportant );
+//
+//  Read the palette.
+//
+//if ( 0 < colorsused )
+//{
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+
+    bmp_palette_print ( colorsused, rparray, gparray, bparray, aparray );
+
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+//}
+//
+//  Allocate storage.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, width, height, rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    rarray = new unsigned char[numbytes];
+    garray = new unsigned char[numbytes];
+    barray = new unsigned char[numbytes];
+    
+    error = bmp_24_data_read ( file_in, width, height, rarray, garray, 
+      barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_READ reads the header and data of a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//    Thanks to Kelly Anderson for discovering that the routine could not read
+//    monochrome images (bitsperpixel = 8 ) and suggesting how to fix that.
+//
+//    Thanks to Vladimir Levin for correcting a memory leak in the monochrome
+//    image portion of the test, 13 August 2007.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    13 August 2007
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned char **RARRAY, **GARRAY, **BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_READ, is true if an error occurred.
+//
+{
+  unsigned char *aparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray;
+  unsigned long int horzresolution;
+  unsigned short int magic;
+  int numbytes;
+  unsigned short int planes;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned char *rparray;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_READ - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+//
+//  Make sure the filetype is 'BM'.
+//
+  magic = 'B' * 256 + 'M';
+
+  if ( filetype != magic )
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  The file's internal magic number is not \"BM\".\n";
+    cout << "  with the numeric value " << magic << "\n";
+    cout << "\n";
+    cout << "  Instead, it is \"" 
+         << ( char ) ( filetype / 256 ) 
+         << ( char ) ( filetype % 256 )
+         << "\".\n";
+    cout << "  with the numeric value " << filetype << "\n";
+    cout << "\n";
+    cout << "  (Perhaps you need to reverse the byte swapping option!)\n";
+    return 1;
+  }
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, width, height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+//
+//  Read the palette.
+//
+  if ( 0 < colorsused )
+  {
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+  }
+//
+//  Allocate storage.
+//
+  numbytes = ( *width ) * ( abs ( *height ) ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    *rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, *width, *height, *rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    *rarray = new unsigned char[numbytes];
+    *garray = new unsigned char[numbytes];
+    *barray = new unsigned char[numbytes];
+
+    error = bmp_24_data_read ( file_in, *width, *height, *rarray, *garray, 
+      *barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_read_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_READ_TEST tests the BMP read routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_READ_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  rarray = NULL;
+  garray = NULL;
+  barray = NULL;
+//
+//  Read the data from file.
+//
+  error = bmp_read ( file_in_name, &width, &height, &rarray, &garray, 
+    &barray );
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST - Fatal error!\n";
+      cout << "  The test failed.\n";
+    }
+    else
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  WIDTH =  " << width  << ".\n";
+      cout << "  HEIGHT = " << height << ".\n";
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  The test was successful.\n";
+    }
+  }
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width,
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_08_WRITE writes the header and data for a monochrome BMP file.
+//
+//  Discussion:
+//
+//    XV seems to think the resulting BMP file is "unexpectedly truncated".
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+//    Output, bool BMP_08_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( width + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 8;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_08_data_write ( file_out, width, height, rarray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_08_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_08_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    02 April 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_08_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  bool error;
+  long int height;
+  int i;
+  unsigned char *indexr;
+  int j;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 255;
+  height = 255;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+//
+//  Set the data.
+//
+  indexr = rarray;
+
+  for ( j = 0; j < height; j++ )
+  {
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      *indexr = i % ( j + 1 );
+      indexr = indexr + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_08_write ( file_out_name, width, height, rarray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_24_WRITE writes the header and data for a BMP file using three colors.
+//
+//  Discussion
+//
+//    Thanks to Keefe Roedersheimer for pointing out that I was creating
+//    a filetype of 'MB' instead of 'BM'.
+//
+//    Lee Mulcahy pointed out that the BMP format requires that horizonal lines
+//    must have a length that is a multiple of 4, or be padded so that this is the case.
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_24_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( ( 3 * width ) + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 24;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_24_data_write ( file_out, width, height, rarray, garray, barray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_24_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_24_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_24_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  int i;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int j2;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 200;
+  height = 200;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+  garray = new unsigned char[numbytes];
+  barray = new unsigned char[numbytes];
+//
+//  Set the data.
+//  Note that BMP files go from "bottom" up, so we'll reverse the
+//  sense of "J" here to get what we want.
+//
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j2 = 0; j2 < abs ( height ); j2++ )
+  {
+    j = abs ( height ) - j2;
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      if ( i <= j )
+      {
+        *indexr = 255;
+        *indexg = 0;
+        *indexb = 0;
+      }
+      else if ( ( width - 1 ) * j + ( abs ( height ) - 1 ) * i <= 
+        ( width - 1 ) * ( abs ( height ) - 1 ) )
+      {
+        *indexr = 0;
+        *indexg = 255;
+        *indexb = 0;
+      }
+      else
+      {
+        *indexr = 0;
+        *indexg = 0;
+        *indexb = 255;
+      }
+      indexr = indexr + 1;
+      indexg = indexg + 1;
+      indexb = indexb + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_24_write ( file_out_name, width, height, rarray, garray, barray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_READ reads a long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, long int *LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+
+  *long_int_val = ( long int ) 
+    ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void long_int_write ( long int long_int_val, ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_WRITE writes a long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, long int *LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  long int temp;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  temp = long_int_val / 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_hi = ( unsigned short ) temp;
+
+  temp = long_int_val % 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_lo = ( unsigned short ) temp;
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_READ reads an unsigned long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned long int *U_LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+//
+//  Acknowledgement:
+//
+//    A correction to the following line was supplied by
+//    Peter Kionga-Kamau, 20 May 2000.
+//
+
+  *u_long_int_val = ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_long_int_write ( unsigned long int u_long_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_WRITE writes an unsigned long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned long int *U_LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  u_short_int_val_hi = ( unsigned short ) ( u_long_int_val / 65536 );
+  u_short_int_val_lo = ( unsigned short ) ( u_long_int_val % 65536 );
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_READ reads an unsigned short int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    30 March 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned short int *U_SHORT_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_SHORT_INT_READ, is true if an error occurred.
+//
+{
+  char c;
+  unsigned char chi;
+  unsigned char clo;
+
+  if ( bmp_byte_swap )
+    {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+  }
+  else
+  {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+  }
+
+  *u_short_int_val = ( chi << 8 ) | clo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_short_int_write ( unsigned short int u_short_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_WRITE writes an unsigned short int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    26 February 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned short int *U_SHORT_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned char chi;
+  unsigned char clo;
+
+  chi = ( unsigned char ) ( u_short_int_val / 256 );
+  clo = ( unsigned char ) ( u_short_int_val % 256 );
+
+  if ( bmp_byte_swap )
+  {
+    file_out << clo << chi;
+  }
+  else
+  {
+    file_out << chi << clo;
+  }
+
+  return;
+}
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h
new file mode 100644
index 0000000..2fe3298
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h
@@ -0,0 +1,80 @@
+#include <fstream>
+#include <iostream>
+
+using namespace std;
+
+
+bool bmp_byte_swap_get ( void );
+void bmp_byte_swap_set ( bool value );
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, long int height, 
+  unsigned char *rarray );
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray );
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned long int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset );
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned long int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant );
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant );
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant );
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray );
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+
+bool bmp_print_test ( char *file_in_name );
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray );
+bool bmp_read_test ( char *file_in_name );
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_08_write_test ( char *file_out_name );
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_24_write_test ( char *file_out_name );
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in );
+void long_int_write ( long int long_int_val, ofstream &file_out );
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, ifstream &file_in );
+void u_long_int_write ( unsigned long int u_long_int_val, ofstream &file_out );
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, ifstream &file_in );
+void u_short_int_write ( unsigned short int u_short_int_val, ofstream &file_out );
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h
new file mode 100644
index 0000000..be64c0f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h
@@ -0,0 +1,54 @@
+#ifndef __SHIFT_CLASS__
+#define __SHIFT_CLASS__
+
+template<typename dataType, int NUM_REGS>
+class shift_class{
+private:
+    dataType regs[NUM_REGS];
+    bool en;
+    bool sync_rst;
+    bool ld;
+    dataType *load_data;
+public:
+    shift_class():en(true),sync_rst(false),ld(false){}
+    shift_class(dataType din[NUM_REGS]):
+    en(true),sync_rst(false),ld(false){ load_data = din; }
+
+    void set_sync_rst(bool srst)
+    {
+        sync_rst = srst;
+    }
+
+    void load(bool load_in)
+    {
+        ld = load_in;
+    }
+
+    void set_enable(bool enable)
+    {
+        en = enable;
+    }
+
+    void operator << (dataType din)
+    {
+    SHIFT:for(int i=NUM_REGS-1;i>=0;i--){
+    if(en)
+        if(sync_rst)
+            regs[i] = 0;
+        else if(ld)
+            regs[i] = load_data[i];
+        else
+        if(i==0)
+            regs[i] = din;
+        else
+            regs[i] = regs[i-1];
+        }
+    }
+
+    dataType operator [](int i)
+    {
+        return regs[i];
+    }
+};
+
+#endif
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp
new file mode 100644
index 0000000..b3df259
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp
@@ -0,0 +1,341 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_blur.cpp
+//  Description:    blur filter testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// Testbench to test the blur filter design.
+// It uses an input BMP image with the same resolution as the VGA in the DE2
+// Use images with the same size only and 24 bits (3colours*8bits)
+// Source: icl1.bmp,  width = 640,  height = 480
+// 
+// Settings: 
+// Exclude from compilation (same applies to bmp*.h/cpp files)
+// Enable SCVerify in Flow Manager
+////////////////////////////////////////////////////////////////////////////////
+//
+// WARNING: this testbench is incomplete.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include "mc_testbench.h"
+#include <mc_scverify.h>
+
+
+#include <iostream>
+#include "ac_int.h"
+// filter defs and protos
+#include "blur.h"
+// bmp lib
+#include "bmp_io.h"
+
+// file names
+char *source_bmp_file = "icl1.bmp";
+char *hw_bmp_file = "icl2.bmp";
+char *sw_bmp_file = "icl3.bmp";
+
+// pointers to input image contents
+unsigned char *red_in, *green_in, *blue_in;
+// image information
+long int height;
+unsigned long int width;
+int num_pixels;   
+
+   
+// function prototypes:
+void testbench();
+void sw_test();
+
+
+
+
+
+// Main Verification Function
+CCS_MAIN(int argc, char *argv[])
+{
+	// teste your design
+	// blur filter
+    cout << "*** start testbench *** " << endl;
+    testbench();
+    cout << "*** end of testbench *** " << endl;
+
+	// test your algorithm in sw
+	// grayscale convertion
+    cout << "*** start sw test *** " << endl;
+    sw_test();
+    cout << "*** end of sw test *** " << endl;
+
+
+    //  Free the memory
+    delete [] red_in;
+    delete [] green_in;
+    delete [] blue_in;
+       
+    CCS_RETURN(0);
+}
+
+
+
+
+
+
+// this function tests your image processing algorithm implmented 
+// in hardware using the RGB streams from BMP file
+void testbench()
+{
+ 
+    unsigned char *red_out, *green_out, *blue_out;
+    bool error;
+    int i, j;
+
+
+	// these signals have to match the ones in the block diagram 
+	// where they are connected
+    ac_int<PIXEL_WL * KERNEL_WIDTH, false> *input_stream;
+    ac_int<PIXEL_WL, false> *output_stream;
+
+
+
+	/************************************************************************
+    * reads the original/source BMP file, to emulate video frame
+  	* colour arrays are automatically allocated inside the function
+  	* size of the image is extracted from the BMP header
+  	* bmp_read(filename, *width, *height, *red, *green, *blue);
+	************************************************************************/
+	error = bmp_read(source_bmp_file, &width, &height, &red_in, &green_in, &blue_in);
+    if (error)
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << width << "x" << height << endl;
+    }
+
+
+    num_pixels = width * abs (height) * sizeof ( unsigned char );     
+
+    if(num_pixels != NUM_PIXELS) {
+        cout << "ERROR: Expecting a 640x480 BMP image!" << endl;
+        delete [] red_in;
+        delete [] green_in;
+        delete [] blue_in;
+        return;
+    }
+    
+    
+
+    // need to reserve memory to store results from the filter
+    // allocate memory to input & output streams from/to your hardware block
+    input_stream = new ac_int<PIXEL_WL * KERNEL_WIDTH, false>[num_pixels];
+    output_stream = new ac_int<PIXEL_WL, false>[num_pixels];
+
+
+    // RGB colour components to be written in file
+    // the output must have the same number of bytes/pixels as the input
+    red_out = new unsigned char[num_pixels];
+    green_out = new unsigned char[num_pixels];
+    blue_out = new unsigned char[num_pixels];
+
+
+    // filter buffer = shift register from input column (KERNEL_WIDTH columns)
+    ac_int<PIXEL_WL, false>col_pixel_buf[KERNEL_WIDTH];
+
+    // group the 3 colour components into 1 single steam
+    // generate the input stream emulating the camera
+    for(i = 0; i < num_pixels; i++) {
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+			// bits 29..20 = RED,  19..10 = GREEN, 9..0 = BLUE
+            col_pixel_buf[j] = ((((ac_int<PIXEL_WL, false>)red_in[i + j * width]) << (2*COLOUR_WL)) | 
+                                (((ac_int<PIXEL_WL, false>)green_in[i + j * width]) << COLOUR_WL) 
+                                | (ac_int<PIXEL_WL, false>)blue_in[i + j * width]);
+        }
+        input_stream[i] = 0;
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+            input_stream[i] |= ((ac_int<PIXEL_WL * KERNEL_WIDTH, false>)col_pixel_buf[j]) << (j * PIXEL_WL);
+        }
+    }
+    
+    
+    
+    
+    
+    /******************************************************************/
+    /* test your design                                               */
+    /******************************************************************/
+
+    CCS_DESIGN(mean_vga)(input_stream, output_stream); 
+
+/*  by-pass your block - check I/Os  
+	for(int i = 0; i < num_pixels; i++) {
+        output_stream[i] = input_stream[i].slc<PIXEL_WL>(0); // copy current pixel (0,30,60,90,120)
+    }    */
+
+
+    
+    
+    // recover your RGB colour signals from the output stream
+    for(int i = 0; i < num_pixels; i++) {
+        red_out[i] = (output_stream[i].slc<COLOUR_WL>(2*COLOUR_WL));
+        green_out[i] = (output_stream[i].slc<COLOUR_WL>(COLOUR_WL));
+        blue_out[i] = (output_stream[i].slc<COLOUR_WL>(0));
+    }    
+
+ 
+
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(hw_bmp_file, width, height, red_out, green_out, blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+
+
+
+   // release memory
+    delete [] input_stream;
+    delete [] output_stream;
+    
+
+    delete [] red_out;
+    delete [] green_out;
+    delete [] blue_out;
+
+    return;        
+
+}
+
+
+
+
+
+
+// this function tests your algorithm in software 
+// usefull to generate the expected result
+void sw_test()
+{
+   // this test copies the original image with swapped colours
+    //unsigned char *red_in, *green_in, *blue_in;
+    unsigned char *sw_red_out, *sw_green_out, *sw_blue_out;
+    bool error;
+    int i, j;
+
+
+
+    
+    
+    
+    // need to reserve memory to store results from the filter
+    // the output must have the same number of bytes/pixels as the input
+    sw_red_out = new unsigned char[num_pixels];
+    sw_green_out = new unsigned char[num_pixels];
+    sw_blue_out = new unsigned char[num_pixels];
+
+
+
+
+    /************************************************************************/
+	/* test of the algorithm in software  
+	/* - data not being processed by your unit
+    /* you can compare the results of your design block 
+    /* e.g. convert from colour to grayscale 
+    /************************************************************************/
+    for(int i = 0; i < num_pixels; i++) {
+        sw_red_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_green_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_blue_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+    }
+
+
+
+    /************************************************************************/
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(sw_bmp_file, width, height, sw_red_out, sw_green_out, sw_blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    /************************************************************************/
+	//  Free the memory
+    delete [] sw_red_out;
+    delete [] sw_green_out;
+    delete [] sw_blue_out;
+
+    return;        
+}
+
+
+
+
+
+void bmp_io_test()
+{
+    // this test copies the original image with swapped colours
+    unsigned char *barray, *garray, *rarray;
+    bool error;
+    long int height;
+    unsigned long int width;
+
+    //  read the original BMP file
+  	// bmp_read(filename, *width, *height, *red, *green, *blue);
+  	// colour arrays are automatically allocated inside the function
+  	// size of the image is also extracted from the BMP header
+	error = bmp_read("icl1.bmp", &width, &height, &rarray,&garray,&barray);
+    if ( error )
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << " width = " <<  width << ", height = " << height << endl;
+    }
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write("icl2.bmp", width, height, rarray, barray, garray );
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    //  Free the memory
+    delete [] rarray;
+    delete [] garray;
+    delete [] barray;
+
+    return;
+}
+
diff --git a/student_files_2015/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c
new file mode 100644
index 0000000..7e11f9d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c
@@ -0,0 +1,94 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           vga_mouse_square.cpp
+//  Description:    video to vga with mouse pointer - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA scanning coordinates, 
+// the mouse coordinates and then replaces the mouse pointer 
+// with a different value for the pixel
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 27 MHz
+//  Top design: vga_mouse_square
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraint:
+//  core>main: enable pipeline + loop can be merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#include "stdio.h"
+#include "ac_int.h"
+
+#define COLOR_WL          10
+#define PIXEL_WL          (3*COLOR_WL)
+
+#define  COORD_WL          10
+
+#pragma hls_design top
+void vga_mouse_square(ac_int<(COORD_WL+COORD_WL), false> * vga_xy, ac_int<(COORD_WL+COORD_WL), false> * mouse_xy, ac_int<(8), false> cursor_size, 
+    ac_int<PIXEL_WL, false> * video_in, ac_int<PIXEL_WL, false> * video_out)
+{
+    ac_int<10, false> i_red, i_green, i_blue; // current pixel
+    ac_int<10, false> o_red, o_green, o_blue; // output pixel
+    ac_int<10, false> mouse_x, mouse_y, vga_x, vga_y; // mouse and screen coordinates
+
+    
+/*  --extract the 3 color components from the 30 bit signal--
+    the 2 blocks are identical - you can shift and mask the desired bits or "slice" the signal <length>(location)
+    
+    i_red = *video_in >> 20;
+    i_green = (*video_in >> 10) & (ac_int<10>)1023;
+    i_blue = *video_in & ((ac_int<10>)1023); 
+*/    
+    i_red = (*video_in).slc<COLOR_WL>(20);
+    i_green = (*video_in).slc<COLOR_WL>(10);
+    i_blue = (*video_in).slc<COLOR_WL>(0);
+
+    // extract mouse X-Y coordinates
+    mouse_x = (*mouse_xy).slc<COORD_WL>(0);
+    mouse_y = (*mouse_xy).slc<COORD_WL>(10);
+    // extract VGA pixel X-Y coordinates
+    vga_x = (*vga_xy).slc<COORD_WL>(0);
+    vga_y = (*vga_xy).slc<COORD_WL>(10);
+   
+   
+    
+    /// something here...
+     
+    
+    /// show pixel
+    if ((vga_x >= mouse_x - cursor_size) && (vga_x <= mouse_x + cursor_size) && (vga_y >= mouse_y - cursor_size) && (vga_y <= mouse_y + cursor_size)){
+        // if it is inside the mouse square
+        o_red = 0;
+        o_green = i_green;
+        o_blue = 0;
+    }
+    else {
+        // if it is outside the mouse square
+        o_red = i_red;
+        o_green = i_green;
+        o_blue = i_blue;
+    }
+    
+    // combine the 3 color components into 1 signal only
+    *video_out = ((((ac_int<PIXEL_WL, false>)o_red) << 20) | (((ac_int<PIXEL_WL, false>)o_green) << 10) | (ac_int<PIXEL_WL, false>)o_blue);
+}
+
diff --git a/student_files_2015/student_files_2015/prj2/instructions.doc b/student_files_2015/student_files_2015/prj2/instructions.doc
new file mode 100644
index 0000000..dfe3225
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/instructions.doc
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf
new file mode 100644
index 0000000..b02e201
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf
@@ -0,0 +1,702 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE1_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE1_D5M
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1[16]
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_location_assignment PIN_U7 -to GPIO_0[31]
+set_location_assignment PIN_V5 -to GPIO_0[30]
+set_location_assignment PIN_W6 -to GPIO_0[29]
+set_location_assignment PIN_W7 -to GPIO_0[28]
+set_location_assignment PIN_V8 -to GPIO_0[27]
+set_location_assignment PIN_T8 -to GPIO_0[26]
+set_location_assignment PIN_W10 -to GPIO_0[25]
+set_location_assignment PIN_Y10 -to GPIO_0[24]
+set_location_assignment PIN_V11 -to GPIO_0[23]
+set_location_assignment PIN_R10 -to GPIO_0[22]
+set_location_assignment PIN_V12 -to GPIO_0[21]
+set_location_assignment PIN_U13 -to GPIO_0[20]
+set_location_assignment PIN_W13 -to GPIO_0[19]
+set_location_assignment PIN_Y13 -to GPIO_0[18]
+set_location_assignment PIN_U14 -to GPIO_0[17]
+set_location_assignment PIN_V14 -to GPIO_0[16]
+set_location_assignment PIN_AA4 -to GPIO_0[15]
+set_location_assignment PIN_AB4 -to GPIO_0[14]
+set_location_assignment PIN_AA5 -to GPIO_0[13]
+set_location_assignment PIN_AB5 -to GPIO_0[12]
+set_location_assignment PIN_AA8 -to GPIO_0[11]
+set_location_assignment PIN_AB8 -to GPIO_0[10]
+set_location_assignment PIN_AA10 -to GPIO_0[9]
+set_location_assignment PIN_AB10 -to GPIO_0[8]
+set_location_assignment PIN_AA13 -to GPIO_0[7]
+set_location_assignment PIN_AB13 -to GPIO_0[6]
+set_location_assignment PIN_AB14 -to GPIO_0[5]
+set_location_assignment PIN_AA14 -to GPIO_0[4]
+set_location_assignment PIN_AB15 -to GPIO_0[3]
+set_location_assignment PIN_AA15 -to GPIO_0[2]
+set_location_assignment PIN_AA16 -to GPIO_0[1]
+set_location_assignment PIN_AB16 -to GPIO_0[0]
+
+set_location_assignment PIN_AB12 -to GPIO_0[32]
+set_location_assignment PIN_AA12 -to GPIO_0[33]
+set_location_assignment PIN_AB3 -to GPIO_0[34]
+set_location_assignment PIN_AA3 -to GPIO_0[35]
+
+
+set_location_assignment PIN_AA11 -to GPIO_1[32]
+set_location_assignment PIN_AB11 -to GPIO_1[33]
+set_location_assignment PIN_T16 -to GPIO_1[34]
+set_location_assignment PIN_R16 -to GPIO_1[35]
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+#set_location_assignment PIN_E8 -to TDI
+#set_location_assignment PIN_D8 -to TCS
+#set_location_assignment PIN_C7 -to TCK
+#set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE1_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE1_D5M.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt
new file mode 100644
index 0000000..a7b1105
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt
@@ -0,0 +1,130 @@
+Assembler report for DE0_D5M
+Mon Mar 17 10:02:44 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof
+  6. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Mon Mar 17 10:02:44 2014 ;
+; Revision Name         ; DE0_D5M                               ;
+; Top-level Entity Name ; TOP_CAMERA                            ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; On       ; Off           ;
+; Use configuration device                                                    ; On       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------------------------------------------+
+; Assembler Generated Files                                                 ;
++---------------------------------------------------------------------------+
+; File Name                                                                 ;
++---------------------------------------------------------------------------+
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof ;
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof ;
++---------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof ;
++----------------+------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                            ;
++----------------+------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                       ;
+; JTAG usercode  ; 0x0019C8D3                                                                         ;
+; Checksum       ; 0x0019C8D3                                                                         ;
++----------------+------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof ;
++--------------------+--------------------------------------------------------------------------------+
+; Option             ; Setting                                                                        ;
++--------------------+--------------------------------------------------------------------------------+
+; Device             ; EPCS4                                                                          ;
+; JTAG usercode      ; 0x00000000                                                                     ;
+; Checksum           ; 0x05BFF881                                                                     ;
+; Compression Ratio  ; 3                                                                              ;
++--------------------+--------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:39 2014
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 450 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:44 2014
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf
new file mode 100644
index 0000000..b4e6ef4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf
@@ -0,0 +1,232 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 480)
+	(text "DE0_D5M" (rect 5 0 49 12)(font "Arial" ))
+	(text "inst" (rect 8 448 20 460)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 49 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 36 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 47 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 220 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 267 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 224 59 267 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 267 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 267 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 177 123 267 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 66 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 201 139 267 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 200 155 267 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160)(line_width 1))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 199 171 267 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176)(line_width 1))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 71 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 196 187 267 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192)(line_width 1))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 73 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 194 203 267 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208)(line_width 1))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 204 219 267 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224)(line_width 1))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 62 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 205 235 267 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240)(line_width 1))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 61 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 206 251 267 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256)(line_width 1))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 57 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 210 267 267 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272)(line_width 1))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 208 283 267 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288)(line_width 1))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_HS" (rect 225 299 267 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304)(line_width 1))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_VS" (rect 224 315 267 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320)(line_width 1))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[3..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_R[3..0]" (rect 210 331 267 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[3..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "VGA_G[3..0]" (rect 211 347 267 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[3..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "VGA_B[3..0]" (rect 212 363 267 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 218 379 267 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384)(line_width 1))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 395 267 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 267 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 411 267 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 448)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done
new file mode 100644
index 0000000..fc5804a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done
@@ -0,0 +1 @@
+Mon Mar 17 10:02:50 2014
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt
new file mode 100644
index 0000000..b7a9f1b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt
@@ -0,0 +1,3610 @@
+Fitter report for DE0_D5M
+Mon Mar 17 10:02:37 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Non-Global High Fan-Out Signals
+ 27. Fitter RAM Summary
+ 28. Routing Usage Summary
+ 29. LAB Logic Elements
+ 30. LAB-wide Signals
+ 31. LAB Signals Sourced
+ 32. LAB Signals Sourced Out
+ 33. LAB Distinct Inputs
+ 34. I/O Rules Summary
+ 35. I/O Rules Details
+ 36. I/O Rules Matrix
+ 37. Fitter Device Options
+ 38. Operating Settings and Conditions
+ 39. Estimated Delay Added for Hold Timing Summary
+ 40. Estimated Delay Added for Hold Timing Details
+ 41. Fitter Messages
+ 42. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Mon Mar 17 10:02:37 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 1,467 / 15,408 ( 10 % )                     ;
+;     Total combinational functions  ; 1,198 / 15,408 ( 8 % )                      ;
+;     Dedicated logic registers      ; 1,030 / 15,408 ( 7 % )                      ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200 / 516,096 ( 10 % )                   ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Use smart compilation                                                      ; On                                    ; Off                                   ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.43        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  14.3%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------+
+; I/O Assignment Warnings                   ;
++------------------+------------------------+
+; Pin Name         ; Reason                 ;
++------------------+------------------------+
+; DRAM_LDQM        ; Missing drive strength ;
+; DRAM_UDQM        ; Missing drive strength ;
+; DRAM_BA_1        ; Missing drive strength ;
+; DRAM_BA_0        ; Missing drive strength ;
+; DRAM_CAS_N       ; Missing drive strength ;
+; DRAM_CKE         ; Missing drive strength ;
+; DRAM_CS_N        ; Missing drive strength ;
+; DRAM_RAS_N       ; Missing drive strength ;
+; DRAM_WE_N        ; Missing drive strength ;
+; DRAM_CLK         ; Missing drive strength ;
+; VGA_CLK          ; Missing drive strength ;
+; VGA_HS           ; Missing drive strength ;
+; VGA_VS           ; Missing drive strength ;
+; DRAM_ADDR[11]    ; Missing drive strength ;
+; DRAM_ADDR[10]    ; Missing drive strength ;
+; DRAM_ADDR[9]     ; Missing drive strength ;
+; DRAM_ADDR[8]     ; Missing drive strength ;
+; DRAM_ADDR[7]     ; Missing drive strength ;
+; DRAM_ADDR[6]     ; Missing drive strength ;
+; DRAM_ADDR[5]     ; Missing drive strength ;
+; DRAM_ADDR[4]     ; Missing drive strength ;
+; DRAM_ADDR[3]     ; Missing drive strength ;
+; DRAM_ADDR[2]     ; Missing drive strength ;
+; DRAM_ADDR[1]     ; Missing drive strength ;
+; DRAM_ADDR[0]     ; Missing drive strength ;
+; GPIO_1_CLKOUT[1] ; Missing drive strength ;
+; GPIO_1_CLKOUT[0] ; Missing drive strength ;
+; HEX0[6]          ; Missing drive strength ;
+; HEX0[5]          ; Missing drive strength ;
+; HEX0[4]          ; Missing drive strength ;
+; HEX0[3]          ; Missing drive strength ;
+; HEX0[2]          ; Missing drive strength ;
+; HEX0[1]          ; Missing drive strength ;
+; HEX0[0]          ; Missing drive strength ;
+; HEX1[6]          ; Missing drive strength ;
+; HEX1[5]          ; Missing drive strength ;
+; HEX1[4]          ; Missing drive strength ;
+; HEX1[3]          ; Missing drive strength ;
+; HEX1[2]          ; Missing drive strength ;
+; HEX1[1]          ; Missing drive strength ;
+; HEX1[0]          ; Missing drive strength ;
+; HEX2[6]          ; Missing drive strength ;
+; HEX2[5]          ; Missing drive strength ;
+; HEX2[4]          ; Missing drive strength ;
+; HEX2[3]          ; Missing drive strength ;
+; HEX2[2]          ; Missing drive strength ;
+; HEX2[1]          ; Missing drive strength ;
+; HEX2[0]          ; Missing drive strength ;
+; HEX3[6]          ; Missing drive strength ;
+; HEX3[5]          ; Missing drive strength ;
+; HEX3[4]          ; Missing drive strength ;
+; HEX3[3]          ; Missing drive strength ;
+; HEX3[2]          ; Missing drive strength ;
+; HEX3[1]          ; Missing drive strength ;
+; HEX3[0]          ; Missing drive strength ;
+; LEDG[9]          ; Missing drive strength ;
+; LEDG[8]          ; Missing drive strength ;
+; LEDG[7]          ; Missing drive strength ;
+; LEDG[6]          ; Missing drive strength ;
+; LEDG[5]          ; Missing drive strength ;
+; LEDG[4]          ; Missing drive strength ;
+; LEDG[3]          ; Missing drive strength ;
+; LEDG[2]          ; Missing drive strength ;
+; LEDG[1]          ; Missing drive strength ;
+; LEDG[0]          ; Missing drive strength ;
+; VGA_B[3]         ; Missing drive strength ;
+; VGA_B[2]         ; Missing drive strength ;
+; VGA_B[1]         ; Missing drive strength ;
+; VGA_B[0]         ; Missing drive strength ;
+; VGA_G[3]         ; Missing drive strength ;
+; VGA_G[2]         ; Missing drive strength ;
+; VGA_G[1]         ; Missing drive strength ;
+; VGA_G[0]         ; Missing drive strength ;
+; VGA_R[3]         ; Missing drive strength ;
+; VGA_R[2]         ; Missing drive strength ;
+; VGA_R[1]         ; Missing drive strength ;
+; VGA_R[0]         ; Missing drive strength ;
+; DRAM_DQ[15]      ; Missing drive strength ;
+; DRAM_DQ[14]      ; Missing drive strength ;
+; DRAM_DQ[13]      ; Missing drive strength ;
+; DRAM_DQ[12]      ; Missing drive strength ;
+; DRAM_DQ[11]      ; Missing drive strength ;
+; DRAM_DQ[10]      ; Missing drive strength ;
+; DRAM_DQ[9]       ; Missing drive strength ;
+; DRAM_DQ[8]       ; Missing drive strength ;
+; DRAM_DQ[7]       ; Missing drive strength ;
+; DRAM_DQ[6]       ; Missing drive strength ;
+; DRAM_DQ[5]       ; Missing drive strength ;
+; DRAM_DQ[4]       ; Missing drive strength ;
+; DRAM_DQ[3]       ; Missing drive strength ;
+; DRAM_DQ[2]       ; Missing drive strength ;
+; DRAM_DQ[1]       ; Missing drive strength ;
+; DRAM_DQ[0]       ; Missing drive strength ;
+; GPIO_1[31]       ; Missing drive strength ;
+; GPIO_1[30]       ; Missing drive strength ;
+; GPIO_1[29]       ; Missing drive strength ;
+; GPIO_1[28]       ; Missing drive strength ;
+; GPIO_1[27]       ; Missing drive strength ;
+; GPIO_1[26]       ; Missing drive strength ;
+; GPIO_1[25]       ; Missing drive strength ;
+; GPIO_1[24]       ; Missing drive strength ;
+; GPIO_1[23]       ; Missing drive strength ;
+; GPIO_1[22]       ; Missing drive strength ;
+; GPIO_1[21]       ; Missing drive strength ;
+; GPIO_1[20]       ; Missing drive strength ;
+; GPIO_1[19]       ; Missing drive strength ;
+; GPIO_1[18]       ; Missing drive strength ;
+; GPIO_1[17]       ; Missing drive strength ;
+; GPIO_1[16]       ; Missing drive strength ;
+; GPIO_1[15]       ; Missing drive strength ;
+; GPIO_1[14]       ; Missing drive strength ;
+; GPIO_1[13]       ; Missing drive strength ;
+; GPIO_1[12]       ; Missing drive strength ;
+; GPIO_1[11]       ; Missing drive strength ;
+; GPIO_1[10]       ; Missing drive strength ;
+; GPIO_1[9]        ; Missing drive strength ;
+; GPIO_1[8]        ; Missing drive strength ;
+; GPIO_1[7]        ; Missing drive strength ;
+; GPIO_1[6]        ; Missing drive strength ;
+; GPIO_1[5]        ; Missing drive strength ;
+; GPIO_1[4]        ; Missing drive strength ;
+; GPIO_1[3]        ; Missing drive strength ;
+; GPIO_1[2]        ; Missing drive strength ;
+; GPIO_1[1]        ; Missing drive strength ;
+; GPIO_1[0]        ; Missing drive strength ;
++------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                    ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+; Name                ; Ignored Entity ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+; Location            ;                ;              ; CLOCK_50_2      ; PIN_B12       ; QSF Assignment ;
+; Location            ;                ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location            ;                ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location            ;                ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location            ;                ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location            ;                ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; Location            ;                ;              ; PS2_CLK         ; PIN_R21       ; QSF Assignment ;
+; Location            ;                ;              ; PS2_DAT         ; PIN_R22       ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_DATA       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_FVAL       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_LVAL       ; ON            ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_ADCDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_ADCLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_BCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_DACDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_DACLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_XCK         ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; CLOCK_50_2      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[32]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[33]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[34]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[35]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; I2C_SCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; I2C_SDAT        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; KEY[3]          ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_CLK         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_DAT         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                      ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Placement (by node) ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 2644 ) ; 0.00 % ( 0 / 2644 )        ; 0.00 % ( 0 / 2644 )      ;
+;     -- Achieved     ; 0.00 % ( 0 / 2644 ) ; 0.00 % ( 0 / 2644 )        ; 0.00 % ( 0 / 2644 )      ;
+;                     ;                     ;                            ;                          ;
+; Routing (by net)    ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+---------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 2633 )   ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 11 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pin.
+
+
++-------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                           ;
++---------------------------------------------+---------------------------+
+; Resource                                    ; Usage                     ;
++---------------------------------------------+---------------------------+
+; Total logic elements                        ; 1,467 / 15,408 ( 10 % )   ;
+;     -- Combinational with no register       ; 437                       ;
+;     -- Register only                        ; 269                       ;
+;     -- Combinational with a register        ; 761                       ;
+;                                             ;                           ;
+; Logic element usage by number of LUT inputs ;                           ;
+;     -- 4 input functions                    ; 544                       ;
+;     -- 3 input functions                    ; 261                       ;
+;     -- <=2 input functions                  ; 393                       ;
+;     -- Register only                        ; 269                       ;
+;                                             ;                           ;
+; Logic elements by mode                      ;                           ;
+;     -- normal mode                          ; 886                       ;
+;     -- arithmetic mode                      ; 312                       ;
+;                                             ;                           ;
+; Total registers*                            ; 1,030 / 17,068 ( 6 % )    ;
+;     -- Dedicated logic registers            ; 1,030 / 15,408 ( 7 % )    ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )         ;
+;                                             ;                           ;
+; Total LABs:  partially or completely used   ; 123 / 963 ( 13 % )        ;
+; Virtual pins                                ; 0                         ;
+; I/O pins                                    ; 141 / 347 ( 41 % )        ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )            ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )             ;
+;                                             ;                           ;
+; Global signals                              ; 9                         ;
+; M9Ks                                        ; 10 / 56 ( 18 % )          ;
+; Total block memory bits                     ; 53,200 / 516,096 ( 10 % ) ;
+; Total block memory implementation bits      ; 92,160 / 516,096 ( 18 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )           ;
+; PLLs                                        ; 1 / 4 ( 25 % )            ;
+; Global clocks                               ; 9 / 20 ( 45 % )           ;
+; JTAGs                                       ; 0 / 1 ( 0 % )             ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )             ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )             ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )             ;
+; Average interconnect usage (total/H/V)      ; 2% / 2% / 2%              ;
+; Peak interconnect usage (total/H/V)         ; 7% / 7% / 7%              ;
+; Maximum fan-out                             ; 505                       ;
+; Highest non-global fan-out                  ; 53                        ;
+; Total fan-out                               ; 7900                      ;
+; Average fan-out                             ; 2.85                      ;
++---------------------------------------------+---------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 1467 / 15408 ( 10 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 437                   ; 0                              ;
+;     -- Register only                        ; 269                   ; 0                              ;
+;     -- Combinational with a register        ; 761                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 544                   ; 0                              ;
+;     -- 3 input functions                    ; 261                   ; 0                              ;
+;     -- <=2 input functions                  ; 393                   ; 0                              ;
+;     -- Register only                        ; 269                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 886                   ; 0                              ;
+;     -- arithmetic mode                      ; 312                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1030                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1030 / 15408 ( 7 % )  ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 123 / 963 ( 13 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 141                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 53200                 ; 0                              ;
+; Total RAM block bits                        ; 92160                 ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 10 / 56 ( 17 % )      ; 0 / 56 ( 0 % )                 ;
+; Clock control block                         ; 7 / 24 ( 29 % )       ; 2 / 24 ( 8 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 554                   ; 1                              ;
+;     -- Registered Input Connections         ; 505                   ; 0                              ;
+;     -- Output Connections                   ; 49                    ; 506                            ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 7976                  ; 514                            ;
+;     -- Registered Connections               ; 3805                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 96                    ; 507                            ;
+;     -- hard_block:auto_generated_inst       ; 507                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 16                    ; 1                              ;
+;     -- Output Ports                         ; 77                    ; 2                              ;
+;     -- Bidir Ports                          ; 48                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                           ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name            ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLOCK_50        ; G21   ; 6        ; 41           ; 15           ; 0            ; 97                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[0] ; AB11  ; 3        ; 21           ; 0            ; 14           ; 254                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[1] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[0]          ; H2    ; 1        ; 0            ; 21           ; 7            ; 35                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[1]          ; G3    ; 1        ; 0            ; 23           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[2]          ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]           ; J6    ; 1        ; 0            ; 24           ; 0            ; 21                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]           ; H5    ; 1        ; 0            ; 27           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]           ; H6    ; 1        ; 0            ; 25           ; 21           ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]           ; G4    ; 1        ; 0            ; 23           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]           ; G5    ; 1        ; 0            ; 27           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]           ; J7    ; 1        ; 0            ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]           ; H7    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]           ; E3    ; 1        ; 0            ; 26           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]           ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]           ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name             ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DRAM_ADDR[0]     ; C4    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[10]    ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[11]    ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[1]     ; A3    ; 8        ; 3            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[2]     ; B3    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[3]     ; C3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[4]     ; A5    ; 8        ; 7            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[5]     ; C6    ; 8        ; 5            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[6]     ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[7]     ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[8]     ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[9]     ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_0        ; B5    ; 8        ; 7            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_1        ; A4    ; 8        ; 5            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CAS_N       ; G8    ; 8        ; 5            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CKE         ; E6    ; 8        ; 1            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CLK         ; E5    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CS_N        ; G7    ; 8        ; 1            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_LDQM        ; E7    ; 8        ; 3            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_RAS_N       ; F7    ; 8        ; 1            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_UDQM        ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_WE_N        ; D6    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[0] ; R16   ; 4        ; 37           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[1] ; T16   ; 4        ; 37           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[0]          ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[1]          ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[2]          ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[3]          ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[4]          ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[5]          ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[6]          ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[0]          ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[1]          ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[2]          ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[3]          ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[4]          ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[5]          ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[6]          ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[0]          ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[1]          ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[2]          ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[3]          ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[4]          ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[5]          ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[6]          ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[0]          ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[1]          ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[2]          ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[3]          ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[4]          ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[5]          ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[6]          ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]          ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]          ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]          ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]          ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]          ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]          ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]          ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]          ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]          ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]          ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[0]         ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]         ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]         ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]         ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK          ; U14   ; 4        ; 39           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]         ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]         ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]         ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]         ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS           ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]         ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]         ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]         ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]         ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_VS           ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                               ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; DRAM_DQ[0]  ; D10   ; 8        ; 16           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[10] ; A9    ; 8        ; 16           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[11] ; C10   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[12] ; B10   ; 8        ; 16           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[13] ; A10   ; 8        ; 16           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[14] ; E10   ; 8        ; 16           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[15] ; F10   ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[1]  ; G10   ; 8        ; 9            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[2]  ; H10   ; 8        ; 9            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[3]  ; E9    ; 8        ; 11           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[4]  ; F9    ; 8        ; 7            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[5]  ; G9    ; 8        ; 9            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[6]  ; H9    ; 8        ; 7            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[7]  ; F8    ; 8        ; 5            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[8]  ; A8    ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[9]  ; B9    ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; GPIO_1[0]   ; AA20  ; 4        ; 37           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[10]  ; U15   ; 4        ; 39           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[11]  ; T15   ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[12]  ; W15   ; 4        ; 32           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[13]  ; V15   ; 4        ; 32           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[14]  ; AB9   ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[15]  ; AA9   ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[16]  ; AA7   ; 3        ; 11           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[17]  ; AB7   ; 3        ; 11           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[18]  ; T14   ; 4        ; 32           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[19]  ; R14   ; 4        ; 39           ; 0            ; 14           ; 4                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO               ; -                   ;
+; GPIO_1[1]   ; AB20  ; 4        ; 37           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[20]  ; U12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[21]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[22]  ; R11   ; 3        ; 3            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[23]  ; R12   ; 3        ; 5            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[24]  ; U10   ; 3        ; 14           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[25]  ; T10   ; 3        ; 14           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[26]  ; U9    ; 3        ; 9            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[27]  ; T9    ; 3        ; 1            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[28]  ; Y7    ; 3        ; 9            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[29]  ; U8    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[2]   ; AA19  ; 4        ; 35           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[30]  ; V6    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[31]  ; V7    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[3]   ; AB19  ; 4        ; 35           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[4]   ; AB18  ; 4        ; 32           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[5]   ; AA18  ; 4        ; 35           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[6]   ; AA17  ; 4        ; 28           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[7]   ; AB17  ; 4        ; 28           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[8]   ; Y17   ; 4        ; 35           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[9]   ; W17   ; 4        ; 35           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                       ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                       ; Use as regular IO        ; HEX3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                       ; Use as regular IO        ; HEX2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                       ; Use as regular IO        ; HEX2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                       ; Use as regular IO        ; HEX1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; HEX0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; HEX1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; HEX1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; HEX1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; HEX1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; HEX1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; HEX1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; HEX0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; HEX0[1]                 ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; DRAM_DQ[12]             ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; DRAM_DQ[10]             ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; DRAM_DQ[9]              ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; DRAM_DQ[8]              ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; DRAM_UDQM               ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO        ; DRAM_ADDR[11]           ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO        ; DRAM_ADDR[9]            ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T10n, PADD19                      ; Use as regular IO        ; DRAM_ADDR[7]            ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T10p, DATA15                      ; Use as regular IO        ; DRAM_ADDR[6]            ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                       ; Use as regular IO        ; DRAM_ADDR[8]            ; Dual Purpose Pin          ;
+; A5       ; DATA5                                    ; Use as regular IO        ; DRAM_ADDR[4]            ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T6p, DATA6                        ; Use as regular IO        ; DRAM_DQ[15]             ; Dual Purpose Pin          ;
+; C6       ; DATA7                                    ; Use as regular IO        ; DRAM_ADDR[5]            ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; DRAM_ADDR[10]           ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T4n, DATA9                        ; Use as regular IO        ; DRAM_DQ[7]              ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T3n, DATA10                       ; Use as regular IO        ; DRAM_ADDR[1]            ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T3p, DATA11                       ; Use as regular IO        ; DRAM_ADDR[2]            ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO        ; DRAM_ADDR[0]            ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 3.3V          ; --           ;
+; 3        ; 16 / 46 ( 35 % ) ; 3.3V          ; --           ;
+; 4        ; 21 / 41 ( 51 % ) ; 3.3V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 28 / 47 ( 60 % ) ; 3.3V          ; --           ;
+; 8        ; 38 / 43 ( 88 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; DRAM_ADDR[1]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 350        ; 8        ; DRAM_BA_1                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 345        ; 8        ; DRAM_ADDR[4]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 336        ; 8        ; DRAM_ADDR[7]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; DRAM_ADDR[11]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 332        ; 8        ; DRAM_DQ[8]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; DRAM_DQ[10]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; DRAM_DQ[13]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; HEX1[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; HEX1[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; HEX1[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; HEX2[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; HEX2[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; HEX3[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; GPIO_1[16]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; GPIO_1[15]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GPIO_1_CLKIN[1]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; GPIO_1[6]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; GPIO_1[5]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 164        ; 4        ; GPIO_1[2]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 169        ; 4        ; GPIO_1[0]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; GPIO_1[17]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; GPIO_1[14]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GPIO_1_CLKIN[0]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; GPIO_1[7]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; GPIO_1[4]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 165        ; 4        ; GPIO_1[3]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 170        ; 4        ; GPIO_1[1]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; DRAM_ADDR[2]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 351        ; 8        ; DRAM_ADDR[10]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; DRAM_BA_0                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 337        ; 8        ; DRAM_ADDR[6]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; DRAM_ADDR[9]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 333        ; 8        ; DRAM_UDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; DRAM_DQ[9]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; DRAM_DQ[12]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; HEX1[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; HEX1[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; HEX2[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; HEX2[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; HEX3[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; HEX3[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; DRAM_ADDR[3]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 359        ; 8        ; DRAM_ADDR[0]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; DRAM_ADDR[5]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 340        ; 8        ; DRAM_ADDR[8]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; DRAM_DQ[11]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; HEX1[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; HEX3[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; DRAM_WE_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; DRAM_DQ[0]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; HEX2[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; HEX3[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; DRAM_CLK                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 362        ; 8        ; DRAM_CKE                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 357        ; 8        ; DRAM_LDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; DRAM_DQ[3]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; DRAM_DQ[14]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; HEX0[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; HEX1[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; HEX2[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; KEY[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; DRAM_RAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 352        ; 8        ; DRAM_DQ[7]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 347        ; 8        ; DRAM_DQ[4]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 348        ; 8        ; DRAM_DQ[15]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 318        ; 7        ; HEX0[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; HEX2[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; HEX3[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; KEY[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; DRAM_CS_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 353        ; 8        ; DRAM_CAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 342        ; 8        ; DRAM_DQ[5]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 341        ; 8        ; DRAM_DQ[1]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; HEX3[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; KEY[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; DRAM_DQ[6]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H10      ; 343        ; 8        ; DRAM_DQ[2]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; GPIO_1[22]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 98         ; 3        ; GPIO_1[23]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; GPIO_1[19]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; GPIO_1_CLKOUT[0]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; GPIO_1[27]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 121        ; 3        ; GPIO_1[25]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; GPIO_1[21]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; GPIO_1[18]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 161        ; 4        ; GPIO_1[11]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ; 171        ; 4        ; GPIO_1_CLKOUT[1]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; GPIO_1[29]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 112        ; 3        ; GPIO_1[26]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 122        ; 3        ; GPIO_1[24]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; GPIO_1[20]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; VGA_CLK                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
+; U15      ; 173        ; 4        ; GPIO_1[10]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; GPIO_1[30]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 105        ; 3        ; GPIO_1[31]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; GPIO_1[13]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; GPIO_1[12]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; GPIO_1[9]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; GPIO_1[28]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; GPIO_1[8]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                       ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; Name                          ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; SDC pin name                  ; inst|u6|altpll_component|auto_generated|pll1                                      ;
+; PLL mode                      ; Normal                                                                            ;
+; Compensate clock              ; clock0                                                                            ;
+; Compensated input/output pins ; --                                                                                ;
+; Switchover type               ; --                                                                                ;
+; Input frequency 0             ; 50.0 MHz                                                                          ;
+; Input frequency 1             ; --                                                                                ;
+; Nominal PFD frequency         ; 25.0 MHz                                                                          ;
+; Nominal VCO frequency         ; 625.0 MHz                                                                         ;
+; VCO post scale K counter      ; 2                                                                                 ;
+; VCO frequency control         ; Auto                                                                              ;
+; VCO phase shift step          ; 200 ps                                                                            ;
+; VCO multiply                  ; --                                                                                ;
+; VCO divide                    ; --                                                                                ;
+; Freq min lock                 ; 24.0 MHz                                                                          ;
+; Freq max lock                 ; 52.02 MHz                                                                         ;
+; M VCO Tap                     ; 5                                                                                 ;
+; M Initial                     ; 2                                                                                 ;
+; M value                       ; 25                                                                                ;
+; N value                       ; 2                                                                                 ;
+; Charge pump current           ; setting 1                                                                         ;
+; Loop filter resistance        ; setting 24                                                                        ;
+; Loop filter capacitance       ; setting 0                                                                         ;
+; Bandwidth                     ; 450 kHz to 980 kHz                                                                ;
+; Bandwidth type                ; Medium                                                                            ;
+; Real time reconfigurable      ; Off                                                                               ;
+; Scan chain MIF file           ; --                                                                                ;
+; Preserve PLL counter order    ; Off                                                                               ;
+; PLL location                  ; PLL_2                                                                             ;
+; Inclk0 signal                 ; CLOCK_50                                                                          ;
+; Inclk1 signal                 ; --                                                                                ;
+; Inclk0 signal type            ; Dedicated Pin                                                                     ;
+; Inclk1 signal type            ; --                                                                                ;
++-------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                             ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                        ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0       ; 5    ; 2   ; 125.0 MHz        ; 0 (0 ps)        ; 9.00 (200 ps)    ; 50/50      ; C0      ; 5             ; 3/2 Odd    ; --            ; 2       ; 5       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1       ; 5    ; 2   ; 125.0 MHz        ; -117 (-2600 ps) ; 9.00 (200 ps)    ; 50/50      ; C1      ; 5             ; 3/2 Odd    ; --            ; 1       ; 0       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                          ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                        ; Library Name ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_CAMERA                                         ; 1467 (2)    ; 1030 (0)                  ; 0 (0)         ; 53200       ; 10   ; 0            ; 0       ; 0         ; 141  ; 0            ; 437 (2)      ; 269 (0)           ; 761 (0)          ; |TOP_CAMERA                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                   ; 1465 (15)   ; 1030 (15)                 ; 0 (0)         ; 53200       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 435 (0)      ; 269 (14)          ; 761 (1)          ; |TOP_CAMERA|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                              ; 68 (68)     ; 58 (58)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 2 (2)             ; 56 (56)          ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                           ; 252 (173)   ; 132 (94)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 120 (79)     ; 15 (5)            ; 117 (89)         ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                        ; 79 (79)     ; 38 (38)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 10 (10)           ; 28 (28)          ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                  ; 93 (77)     ; 66 (55)                   ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 27 (22)      ; 9 (9)             ; 57 (46)          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                           ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component| ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|      ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                  ; 16 (13)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 11 (11)          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|               ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                              ; 50 (50)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 35 (35)          ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |SEG7_LUT_8:u5|                               ; 28 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5                                                                                                                                     ; work         ;
+;          |SEG7_LUT:u0|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                         ; work         ;
+;          |SEG7_LUT:u1|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                         ; work         ;
+;          |SEG7_LUT:u2|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                         ; work         ;
+;          |SEG7_LUT:u3|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                         ; work         ;
+;       |Sdram_Control_4Port:u7|                      ; 897 (228)   ; 697 (130)                 ; 0 (0)         ; 22528       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 200 (92)     ; 229 (16)          ; 468 (120)        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                    ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 129 (35)    ; 116 (30)                  ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (1)       ; 47 (15)           ; 69 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 4 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                    ; 135 (0)     ; 116 (0)                   ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (0)       ; 53 (0)            ; 63 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 135 (0)     ; 116 (0)                   ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (0)       ; 53 (0)            ; 63 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 135 (40)    ; 116 (30)                  ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (7)       ; 53 (19)           ; 63 (8)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (0)            ; 3 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (17)           ; 3 (3)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                   ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 39 (0)            ; 77 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 39 (0)            ; 77 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 129 (40)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (3)       ; 39 (16)           ; 77 (13)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (0)             ; 12 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 12 (12)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                   ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (0)       ; 57 (0)            ; 59 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (0)       ; 57 (0)            ; 59 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 141 (42)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (10)      ; 57 (24)           ; 59 (5)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 4 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                         ; 63 (63)     ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 3 (3)             ; 46 (46)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|               ; 79 (79)     ; 55 (55)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (24)      ; 14 (14)           ; 41 (41)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                           ; 62 (62)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 35 (35)      ; 0 (0)             ; 27 (27)          ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                              ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name             ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; DRAM_LDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[7]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[6]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[5]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[4]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[3]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_UDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_1        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_0        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CKE         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CS_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_RAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_WE_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CLK         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_CLK          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[15]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[14]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[13]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[12]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[11]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[10]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[9]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[8]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[7]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[6]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[5]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[4]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[3]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[2]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[1]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[0]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[31]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[30]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[29]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[28]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[27]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[26]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[25]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[24]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[23]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[22]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[21]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[20]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[19]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[18]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[17]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[16]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[15]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[14]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[13]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[12]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[11]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[10]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[9]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[8]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[7]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[6]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[5]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[4]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[3]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[2]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[1]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[0]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; CLOCK_50         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[0]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; KEY[2]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; KEY[1]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[2]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[1]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[0]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                    ;
++---------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                 ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------+-------------------+---------+
+; GPIO_1_CLKIN[1]                                                     ;                   ;         ;
+; SW[9]                                                               ;                   ;         ;
+; SW[8]                                                               ;                   ;         ;
+; SW[7]                                                               ;                   ;         ;
+; SW[6]                                                               ;                   ;         ;
+; SW[5]                                                               ;                   ;         ;
+; SW[4]                                                               ;                   ;         ;
+; SW[3]                                                               ;                   ;         ;
+; DRAM_DQ[15]                                                         ;                   ;         ;
+; DRAM_DQ[14]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]~feeder      ; 1                 ; 6       ;
+; DRAM_DQ[13]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder      ; 0                 ; 6       ;
+; DRAM_DQ[12]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]~feeder      ; 1                 ; 6       ;
+; DRAM_DQ[11]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder      ; 0                 ; 6       ;
+; DRAM_DQ[10]                                                         ;                   ;         ;
+; DRAM_DQ[9]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]~feeder       ; 1                 ; 6       ;
+; DRAM_DQ[8]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]              ; 0                 ; 6       ;
+; DRAM_DQ[7]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]~feeder       ; 1                 ; 6       ;
+; DRAM_DQ[6]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]              ; 0                 ; 6       ;
+; DRAM_DQ[5]                                                          ;                   ;         ;
+; DRAM_DQ[4]                                                          ;                   ;         ;
+; DRAM_DQ[3]                                                          ;                   ;         ;
+; DRAM_DQ[2]                                                          ;                   ;         ;
+; DRAM_DQ[1]                                                          ;                   ;         ;
+; DRAM_DQ[0]                                                          ;                   ;         ;
+; GPIO_1[31]                                                          ;                   ;         ;
+; GPIO_1[30]                                                          ;                   ;         ;
+; GPIO_1[29]                                                          ;                   ;         ;
+; GPIO_1[28]                                                          ;                   ;         ;
+; GPIO_1[27]                                                          ;                   ;         ;
+; GPIO_1[26]                                                          ;                   ;         ;
+; GPIO_1[25]                                                          ;                   ;         ;
+; GPIO_1[24]                                                          ;                   ;         ;
+; GPIO_1[23]                                                          ;                   ;         ;
+; GPIO_1[22]                                                          ;                   ;         ;
+; GPIO_1[21]                                                          ;                   ;         ;
+; GPIO_1[20]                                                          ;                   ;         ;
+; GPIO_1[19]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9      ; 1                 ; 6       ;
+; GPIO_1[18]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_FVAL                                       ; 1                 ; 6       ;
+; GPIO_1[17]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_LVAL                                       ; 1                 ; 6       ;
+; GPIO_1[16]                                                          ;                   ;         ;
+; GPIO_1[15]                                                          ;                   ;         ;
+; GPIO_1[14]                                                          ;                   ;         ;
+; GPIO_1[13]                                                          ;                   ;         ;
+; GPIO_1[12]                                                          ;                   ;         ;
+; GPIO_1[11]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[0]                                    ; 0                 ; 6       ;
+; GPIO_1[10]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[1]~feeder                             ; 1                 ; 6       ;
+; GPIO_1[9]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[2]~feeder                             ; 1                 ; 6       ;
+; GPIO_1[8]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[3]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[7]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[4]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[6]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[5]                                    ; 0                 ; 6       ;
+; GPIO_1[5]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[6]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[4]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[7]                                    ; 1                 ; 6       ;
+; GPIO_1[3]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[8]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[2]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[9]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[1]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[10]                                   ; 1                 ; 6       ;
+; GPIO_1[0]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[11]~feeder                            ; 0                 ; 6       ;
+; CLOCK_50                                                            ;                   ;         ;
+; GPIO_1_CLKIN[0]                                                     ;                   ;         ;
+; KEY[0]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_2                           ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_0                           ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[0]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[1]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[2]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[3]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[4]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[5]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[6]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[7]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[8]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[9]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[10]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[11]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[12]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[13]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[14]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[15]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[16]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[17]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[18]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[19]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[20]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[21]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[22]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[23]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[24]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[25]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[26]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[27]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[28]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[29]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[30]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[31]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_1                           ; 0                 ; 6       ;
+; KEY[2]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                         ; 1                 ; 6       ;
+; KEY[1]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                         ; 0                 ; 6       ;
+; SW[2]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~3                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~0                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~15                      ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                      ; 0                 ; 6       ;
+; SW[1]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]~feeder ; 0                 ; 6       ;
+; SW[0]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]           ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~25        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~28        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46         ; 1                 ; 6       ;
+;      - SW[0]~_wirecell                                              ; 1                 ; 6       ;
++---------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                  ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 4       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 94      ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~40                                                                                             ; LCCOMB_X1_Y23_N4   ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~41                                                                                             ; LCCOMB_X1_Y23_N2   ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]~30                                                                                              ; LCCOMB_X1_Y23_N26  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|always2~0                                                                                                 ; LCCOMB_X21_Y23_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                 ; FF_X21_Y23_N7      ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                     ; LCCOMB_X17_Y12_N0  ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                             ; LCCOMB_X15_Y13_N18 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]~1                                                                      ; LCCOMB_X14_Y13_N20 ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                           ; FF_X11_Y13_N21     ; 36      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                           ; FF_X11_Y13_N25     ; 35      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                         ; LCCOMB_X11_Y13_N14 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                            ; LCCOMB_X16_Y14_N24 ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                            ; LCCOMB_X11_Y13_N2  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; LCCOMB_X15_Y11_N4  ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                              ; LCCOMB_X15_Y11_N8  ; 43      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                 ; FF_X15_Y11_N17     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                          ; FF_X12_Y14_N17     ; 72      ; Clock                      ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                        ; LCCOMB_X15_Y13_N24 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~31                                                                                 ; LCCOMB_X11_Y11_N16 ; 14      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X20_Y13_N26 ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]~36                                                                                                  ; LCCOMB_X16_Y15_N4  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                 ; LCCOMB_X14_Y24_N0  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; FF_X19_Y26_N1      ; 468     ; Async. clear               ; yes    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; FF_X14_Y24_N21     ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK17           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; FF_X14_Y24_N9      ; 128     ; Async. clear               ; yes    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]~0                                                                                          ; LCCOMB_X19_Y26_N16 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                     ; LCCOMB_X19_Y26_N6  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                      ; LCCOMB_X19_Y23_N8  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y22_N0  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X26_Y23_N8  ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y17_N8  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X22_Y17_N28 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X14_Y20_N16 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X10_Y19_N14 ; 18      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X14_Y17_N30 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X14_Y18_N12 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]~2                                                                                      ; LCCOMB_X19_Y23_N18 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                               ; FF_X15_Y27_N11     ; 16      ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~1                                                                    ; LCCOMB_X17_Y27_N0  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                               ; FF_X17_Y23_N25     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                            ; LCCOMB_X17_Y23_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                              ; LCCOMB_X19_Y27_N4  ; 16      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~45                                                                                  ; LCCOMB_X20_Y23_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46                                                                                  ; LCCOMB_X19_Y23_N4  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46                                                                                  ; LCCOMB_X17_Y26_N0  ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47                                                                                  ; LCCOMB_X19_Y26_N26 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~45                                                                                  ; LCCOMB_X21_Y26_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46                                                                                  ; LCCOMB_X19_Y26_N12 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46                                                                                  ; LCCOMB_X24_Y26_N30 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47                                                                                  ; LCCOMB_X19_Y26_N30 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                               ; LCCOMB_X39_Y18_N14 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                            ; LCCOMB_X38_Y18_N2  ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                            ; LCCOMB_X40_Y18_N30 ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                                                                  ; FF_X40_Y15_N23     ; 117     ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0]                                                   ; PLL_2              ; 505     ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                                                                       ; PIN_AB11           ; 254     ; Clock                      ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; KEY[0]                                                                                                                                ; PIN_H2             ; 35      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                 ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                            ; PIN_G21        ; 94      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                        ; FF_X12_Y14_N17 ; 72      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                  ; FF_X19_Y26_N1  ; 468     ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                  ; FF_X14_Y24_N21 ; 55      ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                  ; FF_X14_Y24_N9  ; 128     ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                ; FF_X40_Y15_N23 ; 117     ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2          ; 505     ; 283                                  ; Global Clock         ; GCLK8            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2          ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                     ; PIN_AB11       ; 254     ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                                                                      ; Fan-Out ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; ~GND                                                                                                                                                                      ; 53      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                                                                  ; 43      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1]                                                                                                                               ; 37      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                                                               ; 36      ;
+; KEY[0]~input                                                                                                                                                              ; 35      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]                                                                                                                               ; 35      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                                                               ; 35      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                                                     ; 32      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3]                                                                                                                               ; 32      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; 31      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                                                     ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                                                                   ; 26      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                                                            ; 24      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                                                                 ; 24      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0                                                                                                                                 ; 23      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]~0                                                                                                                           ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                                            ; 22      ;
+; SW[0]~input                                                                                                                                                               ; 21      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada                                                                                                             ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                                            ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]                                                                                                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0                                                                                                                              ; 18      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; 18      ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                                                         ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                                                                ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                                            ; 17      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                                                                   ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~41                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~40                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                                                                ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                                                         ; 15      ;
+; DE0_D5M:inst|CCD_Capture:u3|always2~0                                                                                                                                     ; 15      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                                                                  ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~31                                                                                                                     ; 14      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~0                                                                                                                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10]                             ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0]                              ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                                            ; 13      ;
+; DE0_D5M:inst|rCCD_LVAL                                                                                                                                                    ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                                                                   ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|always0~1                                                                                                                                  ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                                                                ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                                            ; 12      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1                                                                                                            ; 12      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                                                                ; 12      ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0                                                                                                                                   ; 12      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual                                     ; 11      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6]                                                                                                            ; 11      ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]~36                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5                                                                                                            ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~2                                                                                                                               ; 10      ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                                                        ; 10      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]~30                                                                                                                                  ; 10      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO                                                                                                                                    ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0                                                                                                                               ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[0]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; 9       ;
+; SW[2]~input                                                                                                                                                               ; 8       ;
+; SW[0]~_wirecell                                                                                                                                                           ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~3                                                                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[15]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[14]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[13]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[12]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[11]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[10]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[9]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[8]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[7]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[6]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[5]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[4]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[3]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[2]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[1]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9]                                                                                              ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~4                                                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                                                                ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]~1                                                                                                          ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0                                                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2]                                                                                              ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15]                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14]                                                                                             ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]~2                                                                                                                            ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                               ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1                                                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8]                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6]                                                                                              ; 5       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                                                      ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7]                                                                                                                                  ; 5       ;
+; GPIO_1[19]~input                                                                                                                                                          ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~3                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~2                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010                                                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~1                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~9                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mSTART                                                                                                                                        ; 4       ;
+; DE0_D5M:inst|rCCD_FVAL                                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20]                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13]                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5]                                                                                                                                  ; 4       ;
+; CLOCK_50~input                                                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~11                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~0                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDVAL                                                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]~2                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~7                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ; 3       ;
+; DE0_D5M:inst|CCD_Capture:u3|Pre_FVAL                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2                                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~0                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|rClk[0]                                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                                                                                                                        ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1]                             ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0]                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1]                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10]                                                                                                                                 ; 3       ;
+; SW[1]~input                                                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~1                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~0                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000                                                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1                                                                                                                 ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~4                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~1                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16                                                                                                                  ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~4                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~3                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal7~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|LessThan2~0                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N~0                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal4~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~14                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal2~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~1                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oRequest                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~1                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM~0                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~1                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_V_SYNC                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[13]                            ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[12]                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[12]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[11]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[10]                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[10]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[9]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[14]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[13]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[11]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0]                                                                                                                                  ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4]                                                                                                                                  ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[9]                                                                                                                                     ; 2       ;
+; KEY[1]~input                                                                                                                                                              ; 1       ;
+; KEY[2]~input                                                                                                                                                              ; 1       ;
+; GPIO_1[0]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[1]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[2]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[3]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[4]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[5]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[6]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[7]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[8]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[9]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[10]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[11]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[17]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[18]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[6]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[7]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[8]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[9]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[11]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[12]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[13]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[14]~input                                                                                                                                                         ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell            ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell            ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|rClk[0]~0                                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux6~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux6~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux5~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux5~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~16                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~15                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~6                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~10                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~4                                                                                                                   ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~9                                                                                                      ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~3                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~4                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~7                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~6                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Selector0~2                                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Selector1~2                                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH~2                                                                                                  ; 1       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0~2                                                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read~3                                                                                                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~8                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~7                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~6                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~6                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~5                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~5                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~6                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~6                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~4                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~4                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46                                                                                                                      ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~30                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~1                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~29                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~28                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~27                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~0                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~26                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~25                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Selector1~0                                                                                                                                ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector3~0                                                                                                              ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~0                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~11                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[0]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~10                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[1]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~9                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[2]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~8                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[3]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~7                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[4]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~6                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[5]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~5                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[6]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~4                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[7]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~3                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[8]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~2                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[9]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~1                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[10]                                                                                                                                                ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~2            ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~1            ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~0            ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~0                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[11]                                                                                                                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~9                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~9                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~3                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~3                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux3~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux2~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux2~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux0~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux21~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~14                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux21~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~13                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~12                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~11                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux17~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~10                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux17~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~9                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux9~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~8                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux4~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux4~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux11~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux11~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~2                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]~8                                                                                                                             ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Selector2~0                                                                                                                                ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~12                                                                                                                               ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END~0                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector0~2                                                                                                              ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector0~1                                                                                                              ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[0]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[1]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[2]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[3]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[4]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[5]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[6]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[7]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[8]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[9]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[10]                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[11]                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~4                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~0                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 1       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; Name                                                                                                                                              ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278         ; 24           ; 1278         ; 24           ; yes                    ; no                      ; yes                    ; yes                     ; 30672 ; 1278                        ; 24                          ; 1278                        ; 24                          ; 30672               ; 6    ; None ; M9K_X25_Y13_N0, M9K_X25_Y12_N0, M9K_X25_Y11_N0, M9K_X13_Y13_N0, M9K_X13_Y12_N0, M9K_X13_Y11_N0 ; Old data             ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 8                           ; 512                         ; 8                           ; 4096                ; 1    ; None ; M9K_X25_Y23_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 4                           ; 512                         ; 4                           ; 2048                ; 1    ; None ; M9K_X25_Y17_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y20_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y17_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 1,681 / 47,787 ( 4 % ) ;
+; C16 interconnects     ; 32 / 1,804 ( 2 % )     ;
+; C4 interconnects      ; 699 / 31,272 ( 2 % )   ;
+; Direct links          ; 381 / 47,787 ( < 1 % ) ;
+; Global clocks         ; 9 / 20 ( 45 % )        ;
+; Local interconnects   ; 926 / 15,408 ( 6 % )   ;
+; R24 interconnects     ; 37 / 1,775 ( 2 % )     ;
+; R4 interconnects      ; 1,028 / 41,310 ( 2 % ) ;
++-----------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 11.93) ; Number of LABs  (Total = 123) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 12                            ;
+; 2                                           ; 2                             ;
+; 3                                           ; 1                             ;
+; 4                                           ; 5                             ;
+; 5                                           ; 2                             ;
+; 6                                           ; 5                             ;
+; 7                                           ; 7                             ;
+; 8                                           ; 1                             ;
+; 9                                           ; 1                             ;
+; 10                                          ; 1                             ;
+; 11                                          ; 0                             ;
+; 12                                          ; 4                             ;
+; 13                                          ; 4                             ;
+; 14                                          ; 13                            ;
+; 15                                          ; 10                            ;
+; 16                                          ; 55                            ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.85) ; Number of LABs  (Total = 123) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 72                            ;
+; 1 Clock                            ; 100                           ;
+; 1 Clock enable                     ; 37                            ;
+; 1 Sync. clear                      ; 5                             ;
+; 1 Sync. load                       ; 2                             ;
+; 2 Clock enables                    ; 1                             ;
+; 2 Clocks                           ; 11                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 19.33) ; Number of LABs  (Total = 123) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 7                             ;
+; 2                                            ; 5                             ;
+; 3                                            ; 3                             ;
+; 4                                            ; 1                             ;
+; 5                                            ; 1                             ;
+; 6                                            ; 1                             ;
+; 7                                            ; 7                             ;
+; 8                                            ; 2                             ;
+; 9                                            ; 0                             ;
+; 10                                           ; 3                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 1                             ;
+; 13                                           ; 0                             ;
+; 14                                           ; 1                             ;
+; 15                                           ; 3                             ;
+; 16                                           ; 1                             ;
+; 17                                           ; 8                             ;
+; 18                                           ; 4                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 4                             ;
+; 21                                           ; 8                             ;
+; 22                                           ; 4                             ;
+; 23                                           ; 2                             ;
+; 24                                           ; 5                             ;
+; 25                                           ; 3                             ;
+; 26                                           ; 4                             ;
+; 27                                           ; 7                             ;
+; 28                                           ; 5                             ;
+; 29                                           ; 6                             ;
+; 30                                           ; 8                             ;
+; 31                                           ; 9                             ;
+; 32                                           ; 6                             ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 7.69) ; Number of LABs  (Total = 123) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 0                             ;
+; 1                                               ; 21                            ;
+; 2                                               ; 6                             ;
+; 3                                               ; 5                             ;
+; 4                                               ; 4                             ;
+; 5                                               ; 6                             ;
+; 6                                               ; 8                             ;
+; 7                                               ; 13                            ;
+; 8                                               ; 8                             ;
+; 9                                               ; 9                             ;
+; 10                                              ; 7                             ;
+; 11                                              ; 6                             ;
+; 12                                              ; 3                             ;
+; 13                                              ; 10                            ;
+; 14                                              ; 3                             ;
+; 15                                              ; 6                             ;
+; 16                                              ; 7                             ;
+; 17                                              ; 0                             ;
+; 18                                              ; 0                             ;
+; 19                                              ; 0                             ;
+; 20                                              ; 0                             ;
+; 21                                              ; 0                             ;
+; 22                                              ; 1                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 11.10) ; Number of LABs  (Total = 123) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 1                             ;
+; 2                                            ; 5                             ;
+; 3                                            ; 6                             ;
+; 4                                            ; 20                            ;
+; 5                                            ; 7                             ;
+; 6                                            ; 6                             ;
+; 7                                            ; 4                             ;
+; 8                                            ; 8                             ;
+; 9                                            ; 5                             ;
+; 10                                           ; 7                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 8                             ;
+; 13                                           ; 7                             ;
+; 14                                           ; 5                             ;
+; 15                                           ; 4                             ;
+; 16                                           ; 2                             ;
+; 17                                           ; 2                             ;
+; 18                                           ; 6                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 0                             ;
+; 21                                           ; 1                             ;
+; 22                                           ; 0                             ;
+; 23                                           ; 1                             ;
+; 24                                           ; 2                             ;
+; 25                                           ; 5                             ;
+; 26                                           ; 1                             ;
+; 27                                           ; 1                             ;
+; 28                                           ; 0                             ;
+; 29                                           ; 0                             ;
+; 30                                           ; 0                             ;
+; 31                                           ; 1                             ;
+; 32                                           ; 2                             ;
+; 33                                           ; 1                             ;
+; 34                                           ; 0                             ;
+; 35                                           ; 0                             ;
+; 36                                           ; 0                             ;
+; 37                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 140          ; 0            ; 140          ; 0            ; 0            ; 141       ; 140          ; 0            ; 141       ; 141       ; 0            ; 0            ; 0            ; 0            ; 64           ; 0            ; 0            ; 64           ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 141       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 1            ; 141          ; 1            ; 141          ; 141          ; 0         ; 1            ; 141          ; 0         ; 0         ; 141          ; 141          ; 141          ; 141          ; 77           ; 141          ; 141          ; 77           ; 141          ; 141          ; 112          ; 141          ; 141          ; 141          ; 141          ; 141          ; 141          ; 0         ; 141          ; 141          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DRAM_LDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[1]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_UDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_1          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_0          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CKE           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CS_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_RAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_WE_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CLK           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[11]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[10]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[9]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[8]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[7]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[6]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[5]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[4]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[3]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[2]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[1]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[0]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[1]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[0]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[15]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[14]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[13]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[12]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[11]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[10]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[9]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[8]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[7]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[6]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[5]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[4]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[3]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[2]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[1]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[0]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[31]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[30]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[29]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[28]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[27]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[26]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[25]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[24]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[23]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[22]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[21]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[20]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[19]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[18]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[17]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[16]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[15]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[14]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[13]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[12]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[11]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[10]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[9]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[8]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[7]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[0]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                                                 ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; Source Clock(s)                                     ; Destination Clock(s)                                ; Delay Added in ns ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.5               ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                     ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                      ; Destination Register                                                                                                                                                   ; Delay Added in ns ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.207             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                   ; 0.016             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]              ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                   ; 0.013             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]              ; 0.011             ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 12 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 141 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 3 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1]
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]~0
+        Info (176357): Destination node GPIO_1_CLKOUT[0]~output
+        Info (176357): Destination node VGA_CLK~output
+Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_2 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_2~0
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node GPIO_1[14]~output
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available
+Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 2% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 6% of the available device resources in the region that extends from location X10_Y20 to location X20_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 1.79 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 64 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10
+    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10
+    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10
+    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10
+    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10
+    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9
+    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9
+    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8
+    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8
+    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9
+    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9
+    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9
+    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9
+    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10
+    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10
+    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10
+    Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7
+    Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6
+    Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8
+    Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7
+    Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9
+    Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9
+    Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10
+    Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10
+    Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12
+    Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11
+    Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12
+    Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12
+    Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14
+    Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14
+    Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7
+    Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7
+    Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9
+    Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9
+    Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15
+    Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15
+    Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15
+    Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15
+    Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17
+    Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17
+    Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17
+    Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17
+    Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18
+    Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18
+    Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19
+    Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19
+    Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20
+    Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11
+    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1
+    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin GPIO_1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[20] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[15] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[14] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 22 warnings
+    Info: Peak virtual memory: 1195 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:38 2014
+    Info: Elapsed time: 00:00:15
+    Info: Total CPU time (on all processors): 00:00:17
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.fit.smsg.
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary
new file mode 100644
index 0000000..c5deba6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Mon Mar 17 10:02:37 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_CAMERA
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 1,467 / 15,408 ( 10 % )
+    Total combinational functions : 1,198 / 15,408 ( 8 % )
+    Dedicated logic registers : 1,030 / 15,408 ( 7 % )
+Total registers : 1030
+Total pins : 141 / 347 ( 41 % )
+Total virtual pins : 0
+Total memory bits : 53,200 / 516,096 ( 10 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt
new file mode 100644
index 0000000..c6e71e5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt
@@ -0,0 +1,124 @@
+Flow report for DE0_D5M
+Mon Mar 17 10:02:50 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Mon Mar 17 10:02:44 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 1,467 / 15,408 ( 10 % )                     ;
+;     Total combinational functions  ; 1,198 / 15,408 ( 8 % )                      ;
+;     Dedicated logic registers      ; 1,030 / 15,408 ( 7 % )                      ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200 / 516,096 ( 10 % )                   ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/17/2014 10:02:15 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; DE0_D5M             ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                              ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                        ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 135308249136.139505053504416 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 14622752                     ; --            ; TOP_CAMERA  ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING        ; --            ; TOP_CAMERA  ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                       ; --            ; TOP_CAMERA  ; Top        ;
+; SMART_RECOMPILE                     ; On                           ; Off           ; --          ; --         ;
+; TOP_LEVEL_ENTITY                    ; TOP_CAMERA                   ; DE0_D5M       ; --          ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                          ; --            ; --          ; eda_palace ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:07     ; 1.0                     ; 534 MB              ; 00:00:05                           ;
+; Fitter                    ; 00:00:14     ; 1.4                     ; 1195 MB             ; 00:00:16                           ;
+; Assembler                 ; 00:00:05     ; 1.0                     ; 450 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 549 MB              ; 00:00:03                           ;
+; Total                     ; 00:00:29     ; --                      ; --                  ; 00:00:25                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_sta DE0_D5M -c DE0_D5M
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi
new file mode 100644
index 0000000..a949362
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="ca1109bd0682f003d2ee"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="DE0_D5M.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt
new file mode 100644
index 0000000..187778f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt
@@ -0,0 +1,2506 @@
+Analysis & Synthesis report for DE0_D5M
+Mon Mar 17 10:02:21 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+ 11. Registers Removed During Synthesis
+ 12. Removed Registers Triggering Further Register Optimizations
+ 13. General Register Statistics
+ 14. Inverted Register Statistics
+ 15. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 16. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+ 17. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 69. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1
+ 70. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3
+ 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+ 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+ 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7
+ 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+ 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+ 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+ 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8
+ 82. altshift_taps Parameter Settings by Entity Instance
+ 83. altpll Parameter Settings by Entity Instance
+ 84. dcfifo Parameter Settings by Entity Instance
+ 85. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"
+ 86. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"
+ 87. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"
+ 88. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"
+ 89. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+ 90. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+ 91. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+ 92. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"
+ 93. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5"
+ 94. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+ 95. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"
+ 96. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"
+ 97. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"
+ 98. Elapsed Time Per Partition
+ 99. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Mon Mar 17 10:02:21 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Total logic elements               ; 1,569                                       ;
+;     Total combinational functions  ; 1,198                                       ;
+;     Dedicated logic registers      ; 1,030                                       ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141                                         ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200                                      ;
+; Embedded Multiplier 9-bit elements ; 0                                           ;
+; Total PLLs                         ; 1                                           ;
++------------------------------------+---------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; TOP_CAMERA         ; DE0_D5M            ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; On                 ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                               ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path          ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                            ; Library ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Params.h        ;         ;
+; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/command.v             ;         ;
+; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/control_interface.v   ;         ;
+; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/sdr_data_path.v       ;         ;
+; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Control_4Port.v ;         ;
+; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v          ;         ;
+; V/VGA_Param.h                             ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Param.h                             ;         ;
+; V/CCD_Capture.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/CCD_Capture.v                           ;         ;
+; V/I2C_CCD_Config.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_CCD_Config.v                        ;         ;
+; V/I2C_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_Controller.v                        ;         ;
+; V/Line_Buffer.v                           ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v                           ;         ;
+; V/RAW2RGB.v                               ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/RAW2RGB.v                               ;         ;
+; V/Reset_Delay.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Reset_Delay.v                           ;         ;
+; V/sdram_pll.v                             ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v                             ;         ;
+; V/SEG7_LUT.v                              ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT.v                              ;         ;
+; V/SEG7_LUT_8.v                            ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT_8.v                            ;         ;
+; V/VGA_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Controller.v                        ;         ;
+; DE0_D5M.v                                 ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.v                                 ;         ;
+; TOP_CAMERA.bdf                            ; yes             ; User Block Diagram/Schematic File  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/TOP_CAMERA.bdf                            ;         ;
+; altshift_taps.tdf                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf                                        ;         ;
+; altdpram.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc                                             ;         ;
+; lpm_counter.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc                                          ;         ;
+; lpm_compare.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc                                          ;         ;
+; lpm_constant.inc                          ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc                                         ;         ;
+; db/shift_taps_rnn.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/shift_taps_rnn.tdf                     ;         ;
+; db/altsyncram_lp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_lp81.tdf                    ;         ;
+; db/cntr_cuf.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cntr_cuf.tdf                           ;         ;
+; db/cmpr_vgc.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_vgc.tdf                           ;         ;
+; altpll.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altpll.tdf                                               ;         ;
+; aglobal131.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc                                           ;         ;
+; stratix_pll.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc                                          ;         ;
+; stratixii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc                                        ;         ;
+; cycloneii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                        ;         ;
+; db/altpll_9ee2.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altpll_9ee2.tdf                        ;         ;
+; dcfifo.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf                                               ;         ;
+; lpm_add_sub.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                          ;         ;
+; a_graycounter.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc                                        ;         ;
+; a_fefifo.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc                                             ;         ;
+; a_gray2bin.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc                                           ;         ;
+; dffpipe.inc                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc                                              ;         ;
+; alt_sync_fifo.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc                                        ;         ;
+; altsyncram_fifo.inc                       ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc                                      ;         ;
+; db/dcfifo_v5o1.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dcfifo_v5o1.tdf                        ;         ;
+; db/a_gray2bin_tgb.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_gray2bin_tgb.tdf                     ;         ;
+; db/a_graycounter_s57.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_s57.tdf                  ;         ;
+; db/a_graycounter_ojc.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_ojc.tdf                  ;         ;
+; db/altsyncram_de51.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_de51.tdf                    ;         ;
+; db/dffpipe_oe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_oe9.tdf                        ;         ;
+; db/alt_synch_pipe_qld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_qld.tdf                 ;         ;
+; db/dffpipe_pe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_pe9.tdf                        ;         ;
+; db/alt_synch_pipe_rld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_rld.tdf                 ;         ;
+; db/dffpipe_qe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_qe9.tdf                        ;         ;
+; db/cmpr_e66.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_e66.tdf                           ;         ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                       ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                               ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 1,569                                                                               ;
+;                                             ;                                                                                     ;
+; Total combinational functions               ; 1198                                                                                ;
+; Logic element usage by number of LUT inputs ;                                                                                     ;
+;     -- 4 input functions                    ; 544                                                                                 ;
+;     -- 3 input functions                    ; 261                                                                                 ;
+;     -- <=2 input functions                  ; 393                                                                                 ;
+;                                             ;                                                                                     ;
+; Logic elements by mode                      ;                                                                                     ;
+;     -- normal mode                          ; 886                                                                                 ;
+;     -- arithmetic mode                      ; 312                                                                                 ;
+;                                             ;                                                                                     ;
+; Total registers                             ; 1030                                                                                ;
+;     -- Dedicated logic registers            ; 1030                                                                                ;
+;     -- I/O registers                        ; 0                                                                                   ;
+;                                             ;                                                                                     ;
+; I/O pins                                    ; 141                                                                                 ;
+; Total memory bits                           ; 53200                                                                               ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                   ;
+; Total PLLs                                  ; 1                                                                                   ;
+;     -- PLLs                                 ; 1                                                                                   ;
+;                                             ;                                                                                     ;
+; Maximum fan-out node                        ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ;
+; Maximum fan-out                             ; 547                                                                                 ;
+; Total fan-out                               ; 8862                                                                                ;
+; Average fan-out                             ; 3.37                                                                                ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                         ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                          ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                        ; Library Name ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_CAMERA                                         ; 1198 (2)          ; 1030 (0)     ; 53200       ; 0            ; 0       ; 0         ; 141  ; 0            ; |TOP_CAMERA                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                   ; 1196 (1)          ; 1030 (15)    ; 53200       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                              ; 66 (66)           ; 58 (58)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                           ; 237 (168)         ; 132 (94)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                        ; 69 (69)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                  ; 84 (68)           ; 66 (55)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component| ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|     ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                  ; 16 (13)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|               ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                              ; 50 (50)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |SEG7_LUT_8:u5|                               ; 28 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5                                                                                                                                     ; work         ;
+;          |SEG7_LUT:u0|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                         ; work         ;
+;          |SEG7_LUT:u1|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                         ; work         ;
+;          |SEG7_LUT:u2|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                         ; work         ;
+;          |SEG7_LUT:u3|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                         ; work         ;
+;       |Sdram_Control_4Port:u7|                      ; 668 (212)         ; 697 (130)    ; 22528       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                    ; 82 (0)            ; 116 (0)      ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 82 (0)            ; 116 (0)      ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 82 (15)           ; 116 (30)     ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                    ; 82 (0)            ; 116 (0)      ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 82 (0)            ; 116 (0)      ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 82 (15)           ; 116 (30)     ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                   ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                   ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                         ; 60 (60)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|               ; 64 (64)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                           ; 62 (62)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|            ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672 ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                 ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+; Vendor ; IP Core Name               ; Version ; Release Date ; License Type ; Entity Instance                                                        ; IP Include File                                                                                ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+; Altera ; Shift register (RAM-based) ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                     ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v                  ;
+; Altera ; ALTPLL                     ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v                    ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++----------------------------------------------------------------------+
+; State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ;
++----------------+----------------+----------------+-------------------+
+; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001    ;
++----------------+----------------+----------------+-------------------+
+; mSetup_ST.0000 ; 0              ; 0              ; 0                 ;
+; mSetup_ST.0001 ; 1              ; 0              ; 1                 ;
+; mSetup_ST.0010 ; 1              ; 1              ; 0                 ;
++----------------+----------------+----------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; Register name                                                                                                                               ; Reason for Removal                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0..5,10,15]                                                                                    ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE                                                                                    ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                 ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                           ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                          ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6]                                                                                             ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                            ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                  ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2]                                                                                         ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                                                                                              ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|rClk[1]                                                                                                                        ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                                                                                              ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9                                                                                                  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10                                                                                                 ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[16..31]                                                                                              ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[10..15]                                                                                                  ; Lost fanout                                                                         ;
+; Total Number of Removed Registers = 154                                                                                                     ;                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                     ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register                                   ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7],                          ;
+;                                                          ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7],                            ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                           ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1030  ;
+; Number of registers using Synchronous Clear  ; 129   ;
+; Number of registers using Synchronous Load   ; 81    ;
+; Number of registers using Asynchronous Clear ; 723   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 393   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                   ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                    ; Fan out ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                   ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                       ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                       ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                       ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                       ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                       ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; Total number of inverted registers = 30                                                                                                              ;         ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                          ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]                                       ;
+; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[9]                                       ;
+; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]              ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8] ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]   ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                      ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                  ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]                                   ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                       ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]        ;
+; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]                           ;
+; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]                            ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                              ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                          ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                          ;
+; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                               ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                      ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ;
++----------------+-------+----------------------------------------------------+
+; Parameter Name ; Value ; Type                                               ;
++----------------+-------+----------------------------------------------------+
+; H_SYNC_CYC     ; 96    ; Signed Integer                                     ;
+; H_SYNC_BACK    ; 48    ; Signed Integer                                     ;
+; H_SYNC_ACT     ; 640   ; Signed Integer                                     ;
+; H_SYNC_FRONT   ; 16    ; Signed Integer                                     ;
+; H_SYNC_TOTAL   ; 800   ; Signed Integer                                     ;
+; V_SYNC_CYC     ; 2     ; Signed Integer                                     ;
+; V_SYNC_BACK    ; 33    ; Signed Integer                                     ;
+; V_SYNC_ACT     ; 480   ; Signed Integer                                     ;
+; V_SYNC_FRONT   ; 10    ; Signed Integer                                     ;
+; V_SYNC_TOTAL   ; 525   ; Signed Integer                                     ;
+; X_START        ; 144   ; Signed Integer                                     ;
+; Y_START        ; 35    ; Signed Integer                                     ;
++----------------+-------+----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; COLUMN_WIDTH   ; 1280  ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; Parameter Name ; Value          ; Type                                                                                    ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                 ;
+; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                                          ;
+; TAP_DISTANCE   ; 1280           ; Signed Integer                                                                          ;
+; WIDTH          ; 12             ; Signed Integer                                                                          ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                 ;
+; CBXI_PARAMETER ; shift_taps_rnn ; Untyped                                                                                 ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
++-------------------------------+-------------------+--------------------------------------------+
+; Parameter Name                ; Value             ; Type                                       ;
++-------------------------------+-------------------+--------------------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                                    ;
+; PLL_TYPE                      ; AUTO              ; Untyped                                    ;
+; LPM_HINT                      ; UNUSED            ; Untyped                                    ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                    ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                    ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                                    ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                    ;
+; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                             ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                    ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                    ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                    ;
+; LOCK_HIGH                     ; 1                 ; Untyped                                    ;
+; LOCK_LOW                      ; 1                 ; Untyped                                    ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                    ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                    ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                    ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                    ;
+; SKIP_VCO                      ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                    ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                    ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                    ;
+; BANDWIDTH                     ; 0                 ; Untyped                                    ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                    ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                                    ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                                    ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                    ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                                    ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK1_PHASE_SHIFT              ; -2600             ; Untyped                                    ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                                    ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                                    ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                                    ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                                    ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                    ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; VCO_MIN                       ; 0                 ; Untyped                                    ;
+; VCO_MAX                       ; 0                 ; Untyped                                    ;
+; VCO_CENTER                    ; 0                 ; Untyped                                    ;
+; PFD_MIN                       ; 0                 ; Untyped                                    ;
+; PFD_MAX                       ; 0                 ; Untyped                                    ;
+; M_INITIAL                     ; 0                 ; Untyped                                    ;
+; M                             ; 0                 ; Untyped                                    ;
+; N                             ; 1                 ; Untyped                                    ;
+; M2                            ; 1                 ; Untyped                                    ;
+; N2                            ; 1                 ; Untyped                                    ;
+; SS                            ; 1                 ; Untyped                                    ;
+; C0_HIGH                       ; 0                 ; Untyped                                    ;
+; C1_HIGH                       ; 0                 ; Untyped                                    ;
+; C2_HIGH                       ; 0                 ; Untyped                                    ;
+; C3_HIGH                       ; 0                 ; Untyped                                    ;
+; C4_HIGH                       ; 0                 ; Untyped                                    ;
+; C5_HIGH                       ; 0                 ; Untyped                                    ;
+; C6_HIGH                       ; 0                 ; Untyped                                    ;
+; C7_HIGH                       ; 0                 ; Untyped                                    ;
+; C8_HIGH                       ; 0                 ; Untyped                                    ;
+; C9_HIGH                       ; 0                 ; Untyped                                    ;
+; C0_LOW                        ; 0                 ; Untyped                                    ;
+; C1_LOW                        ; 0                 ; Untyped                                    ;
+; C2_LOW                        ; 0                 ; Untyped                                    ;
+; C3_LOW                        ; 0                 ; Untyped                                    ;
+; C4_LOW                        ; 0                 ; Untyped                                    ;
+; C5_LOW                        ; 0                 ; Untyped                                    ;
+; C6_LOW                        ; 0                 ; Untyped                                    ;
+; C7_LOW                        ; 0                 ; Untyped                                    ;
+; C8_LOW                        ; 0                 ; Untyped                                    ;
+; C9_LOW                        ; 0                 ; Untyped                                    ;
+; C0_INITIAL                    ; 0                 ; Untyped                                    ;
+; C1_INITIAL                    ; 0                 ; Untyped                                    ;
+; C2_INITIAL                    ; 0                 ; Untyped                                    ;
+; C3_INITIAL                    ; 0                 ; Untyped                                    ;
+; C4_INITIAL                    ; 0                 ; Untyped                                    ;
+; C5_INITIAL                    ; 0                 ; Untyped                                    ;
+; C6_INITIAL                    ; 0                 ; Untyped                                    ;
+; C7_INITIAL                    ; 0                 ; Untyped                                    ;
+; C8_INITIAL                    ; 0                 ; Untyped                                    ;
+; C9_INITIAL                    ; 0                 ; Untyped                                    ;
+; C0_MODE                       ; BYPASS            ; Untyped                                    ;
+; C1_MODE                       ; BYPASS            ; Untyped                                    ;
+; C2_MODE                       ; BYPASS            ; Untyped                                    ;
+; C3_MODE                       ; BYPASS            ; Untyped                                    ;
+; C4_MODE                       ; BYPASS            ; Untyped                                    ;
+; C5_MODE                       ; BYPASS            ; Untyped                                    ;
+; C6_MODE                       ; BYPASS            ; Untyped                                    ;
+; C7_MODE                       ; BYPASS            ; Untyped                                    ;
+; C8_MODE                       ; BYPASS            ; Untyped                                    ;
+; C9_MODE                       ; BYPASS            ; Untyped                                    ;
+; C0_PH                         ; 0                 ; Untyped                                    ;
+; C1_PH                         ; 0                 ; Untyped                                    ;
+; C2_PH                         ; 0                 ; Untyped                                    ;
+; C3_PH                         ; 0                 ; Untyped                                    ;
+; C4_PH                         ; 0                 ; Untyped                                    ;
+; C5_PH                         ; 0                 ; Untyped                                    ;
+; C6_PH                         ; 0                 ; Untyped                                    ;
+; C7_PH                         ; 0                 ; Untyped                                    ;
+; C8_PH                         ; 0                 ; Untyped                                    ;
+; C9_PH                         ; 0                 ; Untyped                                    ;
+; L0_HIGH                       ; 1                 ; Untyped                                    ;
+; L1_HIGH                       ; 1                 ; Untyped                                    ;
+; G0_HIGH                       ; 1                 ; Untyped                                    ;
+; G1_HIGH                       ; 1                 ; Untyped                                    ;
+; G2_HIGH                       ; 1                 ; Untyped                                    ;
+; G3_HIGH                       ; 1                 ; Untyped                                    ;
+; E0_HIGH                       ; 1                 ; Untyped                                    ;
+; E1_HIGH                       ; 1                 ; Untyped                                    ;
+; E2_HIGH                       ; 1                 ; Untyped                                    ;
+; E3_HIGH                       ; 1                 ; Untyped                                    ;
+; L0_LOW                        ; 1                 ; Untyped                                    ;
+; L1_LOW                        ; 1                 ; Untyped                                    ;
+; G0_LOW                        ; 1                 ; Untyped                                    ;
+; G1_LOW                        ; 1                 ; Untyped                                    ;
+; G2_LOW                        ; 1                 ; Untyped                                    ;
+; G3_LOW                        ; 1                 ; Untyped                                    ;
+; E0_LOW                        ; 1                 ; Untyped                                    ;
+; E1_LOW                        ; 1                 ; Untyped                                    ;
+; E2_LOW                        ; 1                 ; Untyped                                    ;
+; E3_LOW                        ; 1                 ; Untyped                                    ;
+; L0_INITIAL                    ; 1                 ; Untyped                                    ;
+; L1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G0_INITIAL                    ; 1                 ; Untyped                                    ;
+; G1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G2_INITIAL                    ; 1                 ; Untyped                                    ;
+; G3_INITIAL                    ; 1                 ; Untyped                                    ;
+; E0_INITIAL                    ; 1                 ; Untyped                                    ;
+; E1_INITIAL                    ; 1                 ; Untyped                                    ;
+; E2_INITIAL                    ; 1                 ; Untyped                                    ;
+; E3_INITIAL                    ; 1                 ; Untyped                                    ;
+; L0_MODE                       ; BYPASS            ; Untyped                                    ;
+; L1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G0_MODE                       ; BYPASS            ; Untyped                                    ;
+; G1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G2_MODE                       ; BYPASS            ; Untyped                                    ;
+; G3_MODE                       ; BYPASS            ; Untyped                                    ;
+; E0_MODE                       ; BYPASS            ; Untyped                                    ;
+; E1_MODE                       ; BYPASS            ; Untyped                                    ;
+; E2_MODE                       ; BYPASS            ; Untyped                                    ;
+; E3_MODE                       ; BYPASS            ; Untyped                                    ;
+; L0_PH                         ; 0                 ; Untyped                                    ;
+; L1_PH                         ; 0                 ; Untyped                                    ;
+; G0_PH                         ; 0                 ; Untyped                                    ;
+; G1_PH                         ; 0                 ; Untyped                                    ;
+; G2_PH                         ; 0                 ; Untyped                                    ;
+; G3_PH                         ; 0                 ; Untyped                                    ;
+; E0_PH                         ; 0                 ; Untyped                                    ;
+; E1_PH                         ; 0                 ; Untyped                                    ;
+; E2_PH                         ; 0                 ; Untyped                                    ;
+; E3_PH                         ; 0                 ; Untyped                                    ;
+; M_PH                          ; 0                 ; Untyped                                    ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; CLK0_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK1_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK2_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK3_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK4_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK5_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK6_COUNTER                  ; E0                ; Untyped                                    ;
+; CLK7_COUNTER                  ; E1                ; Untyped                                    ;
+; CLK8_COUNTER                  ; E2                ; Untyped                                    ;
+; CLK9_COUNTER                  ; E3                ; Untyped                                    ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                                    ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                                    ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                                    ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                                    ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                                    ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                    ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                    ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                                    ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                                    ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                                    ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK1                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                                    ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                                    ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                                    ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; CBXI_PARAMETER                ; altpll_9ee2       ; Untyped                                    ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                                    ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                                    ;
+; WIDTH_CLOCK                   ; 5                 ; Signed Integer                             ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                                    ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                                    ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                                    ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                                    ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                                    ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                             ;
++-------------------------------+-------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                          ;
+; REF_PER        ; 1024  ; Signed Integer                                          ;
+; SC_CL          ; 3     ; Signed Integer                                          ;
+; SC_RCD         ; 3     ; Signed Integer                                          ;
+; SC_RRD         ; 7     ; Signed Integer                                          ;
+; SC_PM          ; 1     ; Signed Integer                                          ;
+; SC_BL          ; 1     ; Signed Integer                                          ;
+; SDR_BL         ; 111   ; Unsigned Binary                                         ;
+; SDR_BT         ; 0     ; Unsigned Binary                                         ;
+; SDR_CL         ; 011   ; Unsigned Binary                                         ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ;
++----------------+-------+------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                               ;
++----------------+-------+------------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                     ;
+; REF_PER        ; 1024  ; Signed Integer                                                                     ;
+; SC_CL          ; 3     ; Signed Integer                                                                     ;
+; SC_RCD         ; 3     ; Signed Integer                                                                     ;
+; SC_RRD         ; 7     ; Signed Integer                                                                     ;
+; SC_PM          ; 1     ; Signed Integer                                                                     ;
+; SC_BL          ; 1     ; Signed Integer                                                                     ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                    ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                    ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                    ;
++----------------+-------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                           ;
+; REF_PER        ; 1024  ; Signed Integer                                                           ;
+; SC_CL          ; 3     ; Signed Integer                                                           ;
+; SC_RCD         ; 3     ; Signed Integer                                                           ;
+; SC_RRD         ; 7     ; Signed Integer                                                           ;
+; SC_PM          ; 1     ; Signed Integer                                                           ;
+; SC_BL          ; 1     ; Signed Integer                                                           ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                          ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                          ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                          ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
++----------------+-------+----------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                             ;
++----------------+-------+----------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                   ;
+; REF_PER        ; 1024  ; Signed Integer                                                                   ;
+; SC_CL          ; 3     ; Signed Integer                                                                   ;
+; SC_RCD         ; 3     ; Signed Integer                                                                   ;
+; SC_RRD         ; 7     ; Signed Integer                                                                   ;
+; SC_PM          ; 1     ; Signed Integer                                                                   ;
+; SC_BL          ; 1     ; Signed Integer                                                                   ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                  ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                  ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                  ;
++----------------+-------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ;
++-----------------------+------------------+----------------------------------+
+; Parameter Name        ; Value            ; Type                             ;
++-----------------------+------------------+----------------------------------+
+; default_exposure      ; 0000011111000000 ; Unsigned Binary                  ;
+; exposure_change_value ; 0000000011001000 ; Unsigned Binary                  ;
+; CLK_Freq              ; 50000000         ; Signed Integer                   ;
+; I2C_Freq              ; 20000            ; Signed Integer                   ;
+; LUT_SIZE              ; 25               ; Signed Integer                   ;
++-----------------------+------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; altshift_taps Parameter Settings by Entity Instance                                                       ;
++----------------------------+------------------------------------------------------------------------------+
+; Name                       ; Value                                                                        ;
++----------------------------+------------------------------------------------------------------------------+
+; Number of entity instances ; 1                                                                            ;
+; Entity Instance            ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+;     -- NUMBER_OF_TAPS      ; 2                                                                            ;
+;     -- TAP_DISTANCE        ; 1280                                                                         ;
+;     -- WIDTH               ; 12                                                                           ;
++----------------------------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                      ;
++-------------------------------+---------------------------------------------------+
+; Name                          ; Value                                             ;
++-------------------------------+---------------------------------------------------+
+; Number of entity instances    ; 1                                                 ;
+; Entity Instance               ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                            ;
+;     -- PLL_TYPE               ; AUTO                                              ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                            ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                             ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                                 ;
+;     -- VCO_MULTIPLY_BY        ; 0                                                 ;
+;     -- VCO_DIVIDE_BY          ; 0                                                 ;
++-------------------------------+---------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                                    ;
++----------------------------+------------------------------------------------------------------------------------+
+; Name                       ; Value                                                                              ;
++----------------------------+------------------------------------------------------------------------------------+
+; Number of entity instances ; 4                                                                                  ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
++----------------------------+------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"                                                                                                                   ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port       ; Type  ; Severity ; Details                                                                                                                                      ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; iUART_CTRL ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; DM   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; DQM  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"                                                                                 ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port     ; Type  ; Severity ; Details                                                                                                                                      ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; CMD      ; Input ; Warning  ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives.  Extra input bit(s) "CMD[2..2]" will be connected to GND.  ;
+; INIT_ACK ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"                                                                                                                                                               ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port                 ; Type   ; Severity ; Details                                                                                                                                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; RESET_N              ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND.                               ;
+; WR2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND.                               ;
+; RD2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; CS_N                 ; Output ; Warning  ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ;
++-------+--------+----------+----------------------------+
+; Port  ; Type   ; Severity ; Details                    ;
++-------+--------+----------+----------------------------+
+; oSEG4 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG5 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG6 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG7 ; Output ; Info     ; Explicitly unconnected     ;
++-------+--------+----------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"                                                                      ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                                                  ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; shiftout ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"                                                                                                                                                                   ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                            ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; oRed[1..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oGreen[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oBlue[1..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; iX_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; iY_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"                                                                   ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port            ; Type   ; Severity ; Details                                                                             ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; oX_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; oY_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"                                                                                  ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                  ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; oVGA_R[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_G[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_B[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_SYNC    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_BLANK   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_CLOCK   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:02     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:13 2014
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v
+    Info (12023): Found entity 1: command
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v
+    Info (12023): Found entity 1: control_interface
+Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v
+    Info (12023): Found entity 1: sdr_data_path
+Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v
+    Info (12023): Found entity 1: Sdram_Control_4Port
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v
+    Info (12023): Found entity 1: Sdram_FIFO
+Warning (12019): Can't analyze file -- file V/async_receiver.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v
+    Info (12023): Found entity 1: CCD_Capture
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v
+    Info (12023): Found entity 1: I2C_CCD_Config
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v
+    Info (12023): Found entity 1: I2C_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v
+    Info (12023): Found entity 1: Line_Buffer
+Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v
+    Info (12023): Found entity 1: RAW2RGB
+Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v
+    Info (12023): Found entity 1: Reset_Delay
+Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v
+    Info (12023): Found entity 1: sdram_pll
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v
+    Info (12023): Found entity 1: SEG7_LUT
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v
+    Info (12023): Found entity 1: SEG7_LUT_8
+Warning (12019): Can't analyze file -- file V/uart_crtl.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v
+    Info (12023): Found entity 1: VGA_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v
+    Info (12023): Found entity 1: DE0_D5M
+Info (12021): Found 1 design units, including 1 entities, in source file top_camera.bdf
+    Info (12023): Found entity 1: TOP_CAMERA
+Info (12127): Elaborating entity "TOP_CAMERA" for the top level hierarchy
+Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst"
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(188): truncated value with size 16 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(193): truncated value with size 32 to match size of target (2)
+Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(122) has no driver
+Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1"
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(47): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(50): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(53): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(84): truncated value with size 32 to match size of target (12)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (12)
+Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2"
+Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3"
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)
+Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4"
+Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter:
+    Info (12134): Parameter "lpm_type" = "altshift_taps"
+    Info (12134): Parameter "number_of_taps" = "2"
+    Info (12134): Parameter "tap_distance" = "1280"
+    Info (12134): Parameter "width" = "12"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf
+    Info (12023): Found entity 1: shift_taps_rnn
+Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf
+    Info (12023): Found entity 1: altsyncram_lp81
+Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf
+    Info (12023): Found entity 1: cntr_cuf
+Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf
+    Info (12023): Found entity 1: cmpr_vgc
+Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4"
+Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5"
+Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0"
+Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6"
+Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "2"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "5"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "2"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "5"
+    Info (12134): Parameter "clk1_phase_shift" = "-2600"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone III"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf
+    Info (12023): Found entity 1: altpll_9ee2
+Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated"
+Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7"
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
+Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
+Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
+Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (272007): Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter:
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
+    Info (12134): Parameter "intended_device_family" = "Cyclone"
+    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K"
+    Info (12134): Parameter "lpm_numwords" = "512"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "dcfifo"
+    Info (12134): Parameter "lpm_width" = "16"
+    Info (12134): Parameter "lpm_widthu" = "9"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf
+    Info (12023): Found entity 1: dcfifo_v5o1
+Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info (12023): Found entity 1: a_gray2bin_tgb
+Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info (12023): Found entity 1: a_graycounter_s57
+Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info (12023): Found entity 1: a_graycounter_ojc
+Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf
+    Info (12023): Found entity 1: altsyncram_de51
+Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info (12023): Found entity 1: dffpipe_oe9
+Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_qld
+Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info (12023): Found entity 1: dffpipe_pe9
+Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_rld
+Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info (12023): Found entity 1: dffpipe_qe9
+Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
+    Info (12023): Found entity 1: cmpr_e66
+Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp"
+Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8"
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)
+Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver.
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver.
+Warning (13039): The following bidir pins have no drivers
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "GPIO_1[15]" is fed by VCC
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13009): TRI or OPNDRN buffers permanently enabled
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
+    Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 41 registers lost all their fanouts during netlist optimizations.
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 8 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+    Warning (15610): No output dependent on input pin "SW[7]"
+    Warning (15610): No output dependent on input pin "SW[6]"
+    Warning (15610): No output dependent on input pin "SW[5]"
+    Warning (15610): No output dependent on input pin "SW[4]"
+    Warning (15610): No output dependent on input pin "SW[3]"
+Info (21057): Implemented 1806 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 77 output pins
+    Info (21060): Implemented 48 bidirectional pins
+    Info (21061): Implemented 1596 logic cells
+    Info (21064): Implemented 68 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 119 warnings
+    Info: Peak virtual memory: 534 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:21 2014
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary
new file mode 100644
index 0000000..385ec7e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Mon Mar 17 10:02:21 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_CAMERA
+Family : Cyclone III
+Total logic elements : 1,569
+    Total combinational functions : 1,198
+    Dedicated logic registers : 1,030
+Total registers : 1030
+Total pins : 141
+Total virtual pins : 0
+Total memory bits : 53,200
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin
new file mode 100644
index 0000000..3d3a943
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+CHIP  "DE0_D5M"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+DRAM_ADDR[1]                 : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_1                    : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[4]                 : A5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[7]                 : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[11]                : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[8]                   : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[10]                  : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[13]                  : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+HEX1[0]                      : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[3]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[6]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[1]                      : A16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[4]                      : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+HEX3[2]                      : A19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+GPIO_1[16]                   : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+GPIO_1[15]                   : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[1]              : AA11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+GPIO_1[6]                    : AA17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[5]                    : AA18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[2]                    : AA19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[0]                    : AA20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+GPIO_1[17]                   : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+GPIO_1[14]                   : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[0]              : AB11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+GPIO_1[7]                    : AB17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[4]                    : AB18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[3]                    : AB19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[1]                    : AB20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 3.3V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[2]                 : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[10]                : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_0                    : B5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[6]                 : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[9]                 : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_UDQM                    : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[9]                   : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[12]                  : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+HEX1[1]                      : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[4]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+HEX2[2]                      : B16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[5]                      : B17       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[0]                      : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[3]                      : B19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[3]                 : C3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[0]                 : C4        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+DRAM_ADDR[5]                 : C6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[8]                 : C7        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+DRAM_DQ[11]                  : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+HEX1[2]                      : C13       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+HEX3[4]                      : C19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+DRAM_WE_N                    : D6        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[0]                   : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+HEX2[0]                      : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+HEX3[5]                      : D19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_CLK                     : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CKE                     : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_LDQM                    : E7        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[3]                   : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[14]                  : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[0]                      : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+HEX1[5]                      : E14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[3]                      : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+KEY[2]                       : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+DRAM_RAS_N                   : F7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[7]                   : F8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[4]                   : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[15]                  : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[1]                      : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[5]                      : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[6]                      : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[6]                      : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[1]                      : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+KEY[1]                       : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+DRAM_CS_N                    : G7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CAS_N                   : G8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[5]                   : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[1]                   : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0[4]                      : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+HEX3[6]                      : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+KEY[0]                       : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+DRAM_DQ[6]                   : H9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[2]                   : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0[2]                      : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[3]                      : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+GPIO_1[22]                   : R11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[23]                   : R12       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+GPIO_1[19]                   : R14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+GPIO_1_CLKOUT[0]             : R16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+GPIO_1[27]                   : T9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[25]                   : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+GPIO_1[21]                   : T12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+GPIO_1[18]                   : T14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[11]                   : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_CLKOUT[1]             : T16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+GPIO_1[29]                   : U8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[26]                   : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[24]                   : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+GPIO_1[20]                   : U12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+VGA_CLK                      : U14       : output : 3.3-V LVTTL       :         : 4         : N              
+GPIO_1[10]                   : U15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+GPIO_1[30]                   : V6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[31]                   : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+GPIO_1[13]                   : V15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+GPIO_1[12]                   : W15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 3.3V    : 4         :                
+GPIO_1[9]                    : W17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+GPIO_1[28]                   : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 3.3V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+GPIO_1[8]                    : Y17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof
new file mode 100644
index 0000000..77147af
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf
new file mode 100644
index 0000000..6eb86c4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "14:14:24  April 30, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_D5M"
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf
new file mode 100644
index 0000000..15d8d33
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf
@@ -0,0 +1,557 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_CAMERA
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name BDF_FILE TOP_CAMERA.bdf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak
new file mode 100644
index 0000000..cc80243
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak
@@ -0,0 +1,586 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_D5M
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_0[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_0[16]
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[35]
+set_location_assignment PIN_V6 -to GPIO_1[34]
+set_location_assignment PIN_U8 -to GPIO_1[33]
+set_location_assignment PIN_Y7 -to GPIO_1[32]
+set_location_assignment PIN_T9 -to GPIO_1[31]
+set_location_assignment PIN_U9 -to GPIO_1[30]
+set_location_assignment PIN_T10 -to GPIO_1[29]
+set_location_assignment PIN_U10 -to GPIO_1[28]
+set_location_assignment PIN_R12 -to GPIO_1[27]
+set_location_assignment PIN_R11 -to GPIO_1[26]
+set_location_assignment PIN_T12 -to GPIO_1[25]
+set_location_assignment PIN_U12 -to GPIO_1[24]
+set_location_assignment PIN_R14 -to GPIO_1[23]
+set_location_assignment PIN_T14 -to GPIO_1[22]
+set_location_assignment PIN_AB7 -to GPIO_1[21]
+set_location_assignment PIN_AA7 -to GPIO_1[20]
+set_location_assignment PIN_AA9 -to GPIO_1[19]
+set_location_assignment PIN_T16 -to GPIO_1[18]
+set_location_assignment PIN_AB9 -to GPIO_1[17]
+set_location_assignment PIN_R16 -to GPIO_1[16]
+set_location_assignment PIN_V15 -to GPIO_1[15]
+set_location_assignment PIN_W15 -to GPIO_1[14]
+set_location_assignment PIN_T15 -to GPIO_1[13]
+set_location_assignment PIN_U15 -to GPIO_1[12]
+set_location_assignment PIN_W17 -to GPIO_1[11]
+set_location_assignment PIN_Y17 -to GPIO_1[10]
+set_location_assignment PIN_AB17 -to GPIO_1[9]
+set_location_assignment PIN_AA17 -to GPIO_1[8]
+set_location_assignment PIN_AA18 -to GPIO_1[7]
+set_location_assignment PIN_AB18 -to GPIO_1[6]
+set_location_assignment PIN_AB19 -to GPIO_1[5]
+set_location_assignment PIN_AA19 -to GPIO_1[4]
+set_location_assignment PIN_AB20 -to GPIO_1[3]
+set_location_assignment PIN_AA11 -to GPIO_1[2]
+set_location_assignment PIN_AA20 -to GPIO_1[1]
+set_location_assignment PIN_AB11 -to GPIO_1[0]
+
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+
+
+
+
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws
new file mode 100644
index 0000000..91d2f2b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc
new file mode 100644
index 0000000..6a9d418
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc
@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 10.0 Build 218 06/27/2010 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_50" -period 20ns [get_ports {CLOCK_50}] -waveform {0.000ns 10.000ns}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof
new file mode 100644
index 0000000..76fca82
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt
new file mode 100644
index 0000000..760d753
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt
@@ -0,0 +1,10106 @@
+TimeQuest Timing Analyzer report for DE0_D5M
+Mon Mar 17 10:02:50 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1200mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1200mV 85C Model Setup Summary
+  9. Slow 1200mV 85C Model Hold Summary
+ 10. Slow 1200mV 85C Model Recovery Summary
+ 11. Slow 1200mV 85C Model Removal Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 16. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
+ 19. Slow 1200mV 85C Model Removal: 'CLOCK_50'
+ 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 23. Setup Times
+ 24. Hold Times
+ 25. Clock to Output Times
+ 26. Minimum Clock to Output Times
+ 27. Output Enable Times
+ 28. Minimum Output Enable Times
+ 29. Output Disable Times
+ 30. Minimum Output Disable Times
+ 31. MTBF Summary
+ 32. Synchronizer Summary
+ 33. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+ 34. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+ 35. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+ 36. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+ 37. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+ 38. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+ 39. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+ 40. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+ 41. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+ 42. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+ 43. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+ 44. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+ 45. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+ 46. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+ 47. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+ 48. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+ 49. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+ 50. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+ 51. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+ 52. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+ 53. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+ 54. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+ 55. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+ 56. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+ 57. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+ 58. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+ 59. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+ 60. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+ 61. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+ 62. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+ 63. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+ 64. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+ 65. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+ 66. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+ 67. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+ 68. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+ 69. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+ 70. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+ 71. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+ 72. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+ 73. Slow 1200mV 0C Model Fmax Summary
+ 74. Slow 1200mV 0C Model Setup Summary
+ 75. Slow 1200mV 0C Model Hold Summary
+ 76. Slow 1200mV 0C Model Recovery Summary
+ 77. Slow 1200mV 0C Model Removal Summary
+ 78. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 79. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 80. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 81. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 82. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 83. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 84. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
+ 85. Slow 1200mV 0C Model Removal: 'CLOCK_50'
+ 86. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 87. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 88. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 89. Setup Times
+ 90. Hold Times
+ 91. Clock to Output Times
+ 92. Minimum Clock to Output Times
+ 93. Output Enable Times
+ 94. Minimum Output Enable Times
+ 95. Output Disable Times
+ 96. Minimum Output Disable Times
+ 97. MTBF Summary
+ 98. Synchronizer Summary
+ 99. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+100. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+101. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+102. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+103. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+104. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+105. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+106. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+107. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+108. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+109. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+110. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+111. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+112. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+113. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+114. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+115. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+116. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+117. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+118. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+119. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+120. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+121. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+122. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+123. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+124. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+125. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+126. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+127. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+128. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+129. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+130. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+131. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+132. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+133. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+134. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+135. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+136. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+137. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+138. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+139. Fast 1200mV 0C Model Setup Summary
+140. Fast 1200mV 0C Model Hold Summary
+141. Fast 1200mV 0C Model Recovery Summary
+142. Fast 1200mV 0C Model Removal Summary
+143. Fast 1200mV 0C Model Minimum Pulse Width Summary
+144. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+145. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+146. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+147. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+148. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+149. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
+150. Fast 1200mV 0C Model Removal: 'CLOCK_50'
+151. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+152. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+153. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+154. Setup Times
+155. Hold Times
+156. Clock to Output Times
+157. Minimum Clock to Output Times
+158. Output Enable Times
+159. Minimum Output Enable Times
+160. Output Disable Times
+161. Minimum Output Disable Times
+162. MTBF Summary
+163. Synchronizer Summary
+164. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+165. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+166. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+167. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+168. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+169. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+170. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+171. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+172. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+173. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+174. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+175. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+176. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+177. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+178. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+179. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+180. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+181. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+182. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+183. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+184. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+185. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+186. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+187. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+188. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+189. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+190. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+191. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+192. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+193. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+194. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+195. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+196. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+197. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+198. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+199. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+200. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+201. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+202. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+203. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+204. Multicorner Timing Analysis Summary
+205. Setup Times
+206. Hold Times
+207. Clock to Output Times
+208. Minimum Clock to Output Times
+209. Board Trace Model Assignments
+210. Input Transition Times
+211. Slow Corner Signal Integrity Metrics
+212. Fast Corner Signal Integrity Metrics
+213. Setup Transfers
+214. Hold Transfers
+215. Recovery Transfers
+216. Removal Transfers
+217. Report TCCS
+218. Report RSKM
+219. Unconstrained Paths
+220. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                        ;
++--------------------+-----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name      ; DE0_D5M                                             ;
+; Device Family      ; Cyclone III                                         ;
+; Device Name        ; EP3C16F484C6                                        ;
+; Timing Models      ; Final                                               ;
+; Delay Model        ; Combined                                            ;
+; Rise/Fall Delays   ; Enabled                                             ;
++--------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; DE0_D5M.sdc   ; OK     ; Mon Mar 17 10:02:47 2014 ;
++---------------+--------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; Clock Name                                          ; Type      ; Period ; Frequency ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                 ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; CLOCK_50                                            ; Base      ; 20.000 ; 50.0 MHz  ; 0.000  ; 10.000 ;            ;           ;             ;        ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                            ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000  ; 125.0 MHz ; 0.000  ; 4.000  ; 50.00      ; 2         ; 5           ;        ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000  ; 125.0 MHz ; -2.600 ; 1.400  ; 50.00      ; 2         ; 5           ; -117.0 ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                        ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 174.7 MHz  ; 174.7 MHz       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 207.04 MHz ; 207.04 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                          ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454 ; -22.246       ;
+; CLOCK_50                                            ; 15.170 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                          ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.214 ; 0.000         ;
+; CLOCK_50                                            ; 0.358 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                       ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.497 ; -338.162      ;
+; CLOCK_50                                            ; 14.980 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                       ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.616 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.132 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.736 ; 0.000         ;
+; CLOCK_50                                            ; 9.580 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.250      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; 2.276  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.653      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.340  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.278      ; 5.953      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.360  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.569      ;
+; 2.365  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.564      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                          ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.170 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.782      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.384 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.568      ;
+; 15.400 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.567      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.409 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.558      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.474 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.478      ;
+; 15.477 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.475      ;
+; 15.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.462      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.214 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.799      ;
+; 0.230 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.815      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.910      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.911      ;
+; 0.334 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.902      ;
+; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.380      ; 0.910      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.380      ; 0.912      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.591      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.592      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.592      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.594      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.943      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.943      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.591      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.590      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.591      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.608      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.381 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.600      ;
+; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.385 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.609      ;
+; 0.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.609      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.736      ;
+; 0.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.743      ;
+; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.769      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.778      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.778      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.781      ;
+; 0.568 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.792      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.794      ;
+; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.799      ;
+; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.800      ;
+; 0.585 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.804      ;
+; 0.586 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.805      ;
+; 0.606 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.825      ;
+; 0.700 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.919      ;
+; 0.702 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.921      ;
+; 0.710 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.929      ;
+; 0.825 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.043      ;
+; 0.831 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.050      ;
+; 0.832 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.050      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.285     ; 3.200      ;
+; -1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.277     ; 3.204      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.546     ; 2.792      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.546     ; 2.792      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                    ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.980 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 5.101      ;
+; 14.989 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 5.092      ;
+; 15.085 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 4.996      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.144 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.926      ;
+; 15.223 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 4.858      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.287 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.783      ;
+; 15.290 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.780      ;
+; 15.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.773      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.384 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.686      ;
+; 15.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.678      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                   ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.228      ; 2.081      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.838 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.228      ; 2.223      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.238      ; 2.909      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.135 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.613      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.687     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.615      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.615      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                      ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                  ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0  ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0   ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg        ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0  ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0   ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg        ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                           ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0]                                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                            ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                         ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                            ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[20]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[22]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM[0]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                     ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                     ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                     ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                           ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.632 ; 9.816        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.742 ; 9.742        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|rClk[0]|clk                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.252 ; 3.792 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.228 ; 4.804 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.088 ; 4.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.985 ; 4.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.971 ; 4.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.720 ; 4.223 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.722 ; 4.235 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.708 ; 4.219 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.516 ; -2.017 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.569 ; -2.104 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.516 ; -2.017 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -3.030 ; -3.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.758 ; -4.336 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.529 ; -4.083 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -3.407 ; -3.896 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -3.296 ; -3.778 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -3.282 ; -3.768 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -3.041 ; -3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -3.044 ; -3.537 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.030 ; -3.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.882  ; 6.755  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.291  ; 5.346  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.733  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.700  ; 3.596  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.732  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.589  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.733  ; 3.638  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.576  ; 3.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.527  ; 3.439  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.575  ; 3.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.357  ; 3.274  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.532  ; 3.433  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.594  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.515  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.381  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.540  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.624  ; 3.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.569  ; 3.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.853  ; 5.686  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.923  ; 5.772  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.841  ; 5.703  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.747  ; 5.603  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.667  ; 5.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 6.210  ; 6.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.690  ; 5.589  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.631  ; 5.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.178  ; 5.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.631  ; 5.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.436  ; 5.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.663  ; 5.519  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.466  ; 5.409  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 6.063  ; 5.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.624  ; 5.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.597  ; 3.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.733  ; 3.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.431  ; 3.340  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.576  ; 5.291  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.575 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.703 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.707  ; 6.581  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.825  ; 6.882  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.707  ; 6.581  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.856  ; 4.807  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.856  ; 4.807  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.175  ; 5.233  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.922  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.251  ; 3.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.283  ; 3.195  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.146  ; 3.077  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.283  ; 3.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.133  ; 3.064  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.085  ; 2.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.132  ; 3.029  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.922  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.090  ; 2.989  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.150  ; 3.048  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.074  ; 2.982  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.945  ; 2.861  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.098  ; 3.006  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.179  ; 3.087  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.125  ; 3.044  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.236  ; 3.132  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.781  ; 3.692  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.426  ; 4.325  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.302  ; 4.232  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.235  ; 4.172  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.143  ; 5.835  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.933  ; 4.852  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.418  ; 4.365  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.586  ; 4.522  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.454  ; 4.407  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.187  ; 4.101  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.369  ; 4.307  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.773  ; 4.673  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.165  ; 4.074  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.781  ; 3.692  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.341  ; 4.260  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.381  ; 4.264  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.156  ; 4.070  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.153  ; 3.092  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.282  ; 3.197  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.994  ; 2.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.132  ; 4.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.948 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.075 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.674 ; 3.674 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.461 ; 3.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.863 ; 3.863 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.883 ; 3.883 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.847 ; 3.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.170 ; 3.170 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.170 ; 3.170 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.178 ; 3.178 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.160 ; 3.160 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.168 ; 3.168 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.178 ; 3.178 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.863 ; 3.863 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.935 ; 2.935 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.945 ; 2.945 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.739 ; 2.739 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.935 ; 2.935 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.146 ; 3.146 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.111 ; 3.111 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.461 ; 2.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.461 ; 2.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.469 ; 2.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.451 ; 2.451 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.459 ; 2.459 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.469 ; 2.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.605     ; 3.707     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.615     ; 3.717     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.406     ; 3.508     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.802     ; 3.904     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.605     ; 3.707     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.822     ; 3.924     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.796     ; 3.898     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.104     ; 3.206     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.104     ; 3.206     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.105     ; 3.207     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.094     ; 3.196     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.095     ; 3.197     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.105     ; 3.207     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.802     ; 3.904     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.976     ; 3.072     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.986     ; 3.082     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.785     ; 2.881     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.165     ; 3.261     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.976     ; 3.072     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.185     ; 3.281     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.159     ; 3.255     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.496     ; 2.592     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.496     ; 2.592     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.497     ; 2.593     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.486     ; 2.582     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.487     ; 2.583     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.497     ; 2.593     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.165     ; 3.261     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.051 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.051                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 3.802        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.254                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 6.970        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.284        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.326                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.074        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.397                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.292        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.434                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.899        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.535        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.441                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.336        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.471                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.219        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.502                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.253        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.552                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 6.898        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.654        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.107        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.470        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.605                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.500        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.628                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.103        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.525        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.632                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.382        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.636                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.531        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.670                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.417        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.684                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.578        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.709                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.901        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.808        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.717                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 6.902        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.815        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.748                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.109        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.639        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.765                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.513        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.790                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.773        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.017        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.795                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.104        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.691        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.838                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.985        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.853        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.840                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.984        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.856        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.862                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.905        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.957        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.886                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.108        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.778        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.896                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.645        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.906                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.662        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.244        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.918                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.667        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.991                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 6.902        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.089        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.005                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.740        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.055                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.805        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.215                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.964        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.246                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 4.993        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.358                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.254        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.104        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.397                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.292        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.525                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.274        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.641                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.388        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.733                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.267        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.466        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.873                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.126        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.747        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                         ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 193.87 MHz ; 193.87 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 231.32 MHz ; 231.32 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.053  ; 0.000         ;
+; CLOCK_50                                            ; 15.677 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.190 ; 0.000         ;
+; CLOCK_50                                            ; 0.312 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.843 ; -150.984      ;
+; CLOCK_50                                            ; 15.539 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.477 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.638 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.741 ; 0.000         ;
+; CLOCK_50                                            ; 9.561 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.080 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.893     ; 2.042      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 2.842 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.097      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.914 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.025      ;
+; 2.919 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.020      ;
+; 2.931 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.256      ; 5.340      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.677 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.285      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.875 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.087      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.910 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.065      ;
+; 15.919 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.056      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.951 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.011      ;
+; 15.952 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.010      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.999 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.976      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.717      ;
+; 0.205 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.732      ;
+; 0.295 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.822      ;
+; 0.296 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.823      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.530      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
+; 0.324 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.535      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.537      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.387      ; 0.857      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.387      ; 0.857      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.537      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.341      ; 0.841      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.529      ;
+; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.543      ;
+; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|WRITEA                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.535      ;
+; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.536      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.340      ; 0.847      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.548      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
+; 0.333 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.341 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.346 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.545      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.466 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.665      ;
+; 0.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.671      ;
+; 0.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.694      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.699      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.700      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.700      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.705      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.704      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.716      ;
+; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.716      ;
+; 0.521 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.719      ;
+; 0.525 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.724      ;
+; 0.525 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.723      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.725      ;
+; 0.540 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.739      ;
+; 0.638 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.837      ;
+; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.838      ;
+; 0.640 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.839      ;
+; 0.741 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.939      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.943      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.942      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.942      ;
+; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
+; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.982     ; 2.857      ;
+; -0.796 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.860      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.539 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.558      ;
+; 15.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.549      ;
+; 15.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.469      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.396      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.755 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.342      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.270      ;
+; 15.818 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.267      ;
+; 15.824 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.261      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.190      ;
+; 15.902 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.183      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.534 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.222      ; 1.900      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.632 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.222      ; 1.998      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.262 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.235      ; 2.641      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.342      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.345      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.450     ; 2.343      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                         ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.561 ; 9.745        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.721 ; 9.721        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|rClk[0]|clk                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 3.589 ; 4.163 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 3.589 ; 4.163 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 2.854 ; 3.325 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.848 ; 4.345 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.848 ; 4.345 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.647 ; 4.124 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.508 ; 3.941 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.418 ; 3.842 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.402 ; 3.831 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.177 ; 3.607 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.182 ; 3.617 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.163 ; 3.604 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.293 ; -1.708 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.317 ; -1.789 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.293 ; -1.708 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.565 ; -2.993 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.235 ; -3.721 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.030 ; -3.492 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.908 ; -3.334 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.811 ; -3.222 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.795 ; -3.211 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -2.579 ; -2.996 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.584 ; -3.006 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.565 ; -2.993 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.617  ; 6.571  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.617  ; 6.571  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.491  ; 6.343  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.764  ; 4.656  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.764  ; 4.656  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.013  ; 5.130  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.730  ; 3.594  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.702  ; 3.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.727  ; 3.594  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.587  ; 3.487  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.730  ; 3.586  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.574  ; 3.450  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.533  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.580  ; 3.438  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.373  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.536  ; 3.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.591  ; 3.458  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.526  ; 3.393  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.389  ; 3.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.546  ; 3.427  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.618  ; 3.475  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.558  ; 3.446  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.526  ; 7.148  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.603  ; 5.452  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.676  ; 5.541  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.607  ; 5.466  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.526  ; 7.148  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.522  ; 5.349  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.454  ; 5.296  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.944  ; 5.827  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.487  ; 5.303  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.446  ; 5.300  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.017  ; 4.898  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.452  ; 5.289  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.233  ; 5.055  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.444  ; 5.305  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.296  ; 5.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 5.806  ; 5.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.414  ; 5.226  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.587  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.721  ; 3.601  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.442  ; 3.301  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.583  ; 5.252  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.336  ; 6.187  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.455  ; 6.406  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.336  ; 6.187  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.676  ; 4.567  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.676  ; 4.567  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 4.910  ; 5.026  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.989  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.304  ; 3.159  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.329  ; 3.197  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.194  ; 3.093  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.330  ; 3.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.182  ; 3.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.141  ; 3.032  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.187  ; 3.046  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.989  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.144  ; 2.999  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.198  ; 3.065  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.135  ; 3.003  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.004  ; 2.888  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.155  ; 3.036  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.225  ; 3.082  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.166  ; 3.053  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.286  ; 3.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.770  ; 3.622  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.360  ; 4.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.249  ; 4.128  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.187  ; 4.056  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.096  ; 5.728  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.828  ; 4.689  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.355  ; 4.245  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.512  ; 4.404  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.402  ; 4.261  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.140  ; 3.977  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.300  ; 4.168  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.675  ; 4.504  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.112  ; 3.961  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.770  ; 3.622  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.276  ; 4.132  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.316  ; 4.129  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.112  ; 3.947  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.193  ; 3.098  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.321  ; 3.201  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.055  ; 2.915  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.190  ; 4.858  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.777 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.922 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.119 ; 3.106 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.121 ; 3.108 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.591 ; 3.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.601 ; 3.588 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.404 ; 3.391 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.777 ; 3.764 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.591 ; 3.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.797 ; 3.784 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.766 ; 3.753 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.129 ; 3.116 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.129 ; 3.116 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.141 ; 3.128 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.119 ; 3.106 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.131 ; 3.118 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.141 ; 3.128 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.121 ; 3.108 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.777 ; 3.764 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.251 ; 2.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.252 ; 2.252 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.704 ; 2.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.714 ; 2.714 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.525 ; 2.525 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.882 ; 2.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.704 ; 2.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.902 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.872 ; 2.872 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.261 ; 2.261 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.261 ; 2.261 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.272 ; 2.272 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.251 ; 2.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.262 ; 2.262 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.272 ; 2.272 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.252 ; 2.252 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.882 ; 2.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.591     ; 3.591     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.601     ; 3.601     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.413     ; 3.413     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.769     ; 3.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.591     ; 3.591     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.789     ; 3.789     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.763     ; 3.763     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.140     ; 3.140     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.140     ; 3.140     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.146     ; 3.146     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.130     ; 3.130     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.136     ; 3.136     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.146     ; 3.146     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.769     ; 3.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.714     ; 2.902     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.533     ; 2.721     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.875     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.895     ; 3.083     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.869     ; 3.057     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.272     ; 2.460     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.272     ; 2.460     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.277     ; 2.465     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.262     ; 2.450     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.267     ; 2.455     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.277     ; 2.465     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.875     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.581 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.581                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.335        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.246        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.772                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.080        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.692        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.831                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.493        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.874                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.676        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.896                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.022        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.874        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.906                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.708        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.975                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.335        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.640        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.978                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.021        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.957        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.643        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.986                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.199        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.787        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.061                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.863        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.083                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.196        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.887        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.090                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.892        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.119                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.781        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.133                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.935        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.134                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.018        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.116        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.135                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.019        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.116        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.148                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.809        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.187                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.201        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.986        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.217                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.878        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.247                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.050        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.261                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.920        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.341        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.263                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.022        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.241        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.279                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.100        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.179        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.286                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.200        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.086        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.291                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.097        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.194        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.324                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.808        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.516        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.345                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.008        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.347                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.010        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.358                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.019        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.339        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.445                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.095        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.146        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.587                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.250        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.646                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.307        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.740                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.340        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.400        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.768                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.570        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.901                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.564        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.643        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.070                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.352        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.718        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.198                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.222        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.976        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.424  ; 0.000         ;
+; CLOCK_50                                            ; 17.244 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.116 ; 0.000         ;
+; CLOCK_50                                            ; 0.187 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.773  ; 0.000         ;
+; CLOCK_50                                            ; 17.090 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 0.904 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.414 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.748 ; 0.000         ;
+; CLOCK_50                                            ; 9.265 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 1.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.313     ; 1.270      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 4.705 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.258      ;
+; 4.712 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.150      ; 3.445      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.750 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.213      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.757 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.206      ;
+; 4.764 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.199      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.244 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.729      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.340 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.640      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.343 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.637      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.382 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.591      ;
+; 17.405 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.575      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.432 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.541      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.116 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.433      ;
+; 0.123 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.440      ;
+; 0.162 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.487      ;
+; 0.164 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.481      ;
+; 0.165 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.482      ;
+; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.496      ;
+; 0.173 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.497      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.500      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.500      ;
+; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.316      ;
+; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.316      ;
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.507      ;
+; 0.192 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.319      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.187 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.195 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.314      ;
+; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.319      ;
+; 0.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.208 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.268 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.388      ;
+; 0.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.391      ;
+; 0.294 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.413      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.428      ;
+; 0.310 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.430      ;
+; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.431      ;
+; 0.313 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.433      ;
+; 0.314 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.434      ;
+; 0.325 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.445      ;
+; 0.369 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.489      ;
+; 0.370 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.490      ;
+; 0.377 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.497      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.809 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.860      ;
+; 0.811 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.864      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.978      ;
+; 17.093 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.975      ;
+; 17.155 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.913      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.204 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.856      ;
+; 17.228 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.840      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.285 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.775      ;
+; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.772      ;
+; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.772      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.348 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.712      ;
+; 17.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.710      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.933 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.157      ; 1.174      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 1.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.157      ; 1.256      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.379 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.165      ; 1.628      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.165      ; 1.790      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.006     ; 1.495      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.495      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.751 ; 3.981        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.279 ; 9.463        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.357 ; 9.541        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.441 ; 9.441        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 2.203 ; 3.113 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 2.203 ; 3.113 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 1.819 ; 2.590 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.569 ; 3.369 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.569 ; 3.369 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.420 ; 3.241 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.344 ; 3.086 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.289 ; 3.048 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.279 ; 3.037 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.147 ; 2.890 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.153 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.137 ; 2.886 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.859 ; -1.656 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.164 ; -2.955 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.015 ; -2.819 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.949 ; -2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.891 ; -2.635 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.881 ; -2.624 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.754 ; -2.483 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.760 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.186  ; 4.306  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.186  ; 4.306  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.118  ; 4.091  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.959  ; 2.978  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.959  ; 2.978  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.218  ; 3.178  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.268  ; 2.285  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.233  ; 2.237  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.268  ; 2.285  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.192  ; 2.204  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.244  ; 2.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.168  ; 2.172  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.145  ; 2.152  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.161  ; 2.163  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.060  ; 2.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.125  ; 2.133  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.167  ; 2.176  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.142  ; 2.137  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.057  ; 2.060  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.156  ; 2.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.183  ; 2.200  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.140  ; 2.153  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.205  ; 2.203  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 5.019  ; 4.759  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.533  ; 3.460  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.588  ; 3.529  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.549  ; 3.512  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.019  ; 4.759  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 3.466  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.426  ; 3.430  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.769  ; 3.755  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 3.438  ; 3.426  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.339  ; 3.455  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.129  ; 3.157  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.327  ; 3.428  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.279  ; 3.193  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.442  ; 3.391  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 3.224  ; 3.315  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.656  ; 3.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.402  ; 3.371  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.164  ; 2.170  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.250  ; 2.268  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.082  ; 2.069  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.681  ; 3.498  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.313 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.366 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.082  ; 4.194  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.148  ; 3.113  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.967  ; 1.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.000  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.929  ; 1.937  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.977  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.904  ; 1.905  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.882  ; 1.886  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.897  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.802  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.862  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.903  ; 1.908  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.880  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.892  ; 1.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.918  ; 1.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.876  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.938  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.617  ; 2.649  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.573  ; 2.625  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.537  ; 2.592  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.994  ; 3.818  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.916  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.630  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.743  ; 2.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.644  ; 2.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.505  ; 2.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.610  ; 2.654  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.815  ; 2.798  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.486  ; 2.520  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.582  ; 2.618  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.580  ; 2.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.469  ; 2.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.900  ; 1.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.982  ; 1.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.822  ; 1.806  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.418  ; 3.230  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.878 ; 2.859 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.888 ; 2.869 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.774 ; 2.755 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.984 ; 2.965 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.878 ; 2.859 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.004 ; 2.985 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.981 ; 2.962 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.605 ; 2.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.605 ; 2.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.608 ; 2.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.595 ; 2.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.598 ; 2.579 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.608 ; 2.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.984 ; 2.965 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.746 ; 1.746 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.756 ; 1.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.646 ; 1.646 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.848 ; 1.848 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.746 ; 1.746 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.868 ; 1.868 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.845 ; 1.845 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.486 ; 1.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.486 ; 1.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.488 ; 1.488 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.476 ; 1.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.478 ; 1.478 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.488 ; 1.488 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.848 ; 1.848 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.966     ; 2.966     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.976     ; 2.976     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.841     ; 2.841     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.081     ; 3.081     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.966     ; 2.966     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.101     ; 3.101     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.083     ; 3.083     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.651     ; 2.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.651     ; 2.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.652     ; 2.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.641     ; 2.641     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.642     ; 2.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.652     ; 2.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.081     ; 3.081     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.831     ; 1.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.841     ; 1.973     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.711     ; 1.843     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.941     ; 2.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.831     ; 1.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.961     ; 2.093     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.943     ; 2.075     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.529     ; 1.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.529     ; 1.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.530     ; 1.662     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.519     ; 1.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.520     ; 1.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.530     ; 1.662     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.941     ; 2.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 13.232 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.232                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.589        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.643        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.350                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.443        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.907        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.383                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.790        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.435                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.400        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.035        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.440                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.916        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.456                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.932        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.588        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.895        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.493                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.902        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.503                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.102        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.535                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.009        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.536                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.011        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.176        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.581                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.991        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.585                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.183        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.594                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.522        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.072        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.596                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.003        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.602                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.077        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.615                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.088        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.626                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.102        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.653                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.451        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.202        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.659                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.067        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.664                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.404        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.260        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.672                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.325        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.347        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.689                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.166        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.691                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.164        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.702                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.450        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.252        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.721                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.472        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.734                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.142        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.735                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.145        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.736                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.334        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.793                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.194        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.821                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.230        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.899                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.308        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.926                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.333        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.971                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.378        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.024                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.497        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.082                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.490        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.127                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.535        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.191                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.600        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.591        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.273                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.747        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Clock                                                ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack                                     ; -0.454  ; 0.116 ; -1.497   ; 0.904   ; 3.736               ;
+;  CLOCK_50                                            ; 15.170  ; 0.187 ; 14.980   ; 0.904   ; 9.265               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454  ; 0.116 ; -1.497   ; 2.414   ; 3.736               ;
+; Design-wide TNS                                      ; -22.246 ; 0.0   ; -338.162 ; 0.0     ; 0.0                 ;
+;  CLOCK_50                                            ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -22.246 ; 0.000 ; -338.162 ; 0.000   ; 0.000               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.252 ; 3.792 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.228 ; 4.804 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.088 ; 4.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.985 ; 4.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.971 ; 4.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.720 ; 4.223 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.722 ; 4.235 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.708 ; 4.219 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.859 ; -1.656 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.164 ; -2.955 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.015 ; -2.819 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.949 ; -2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.891 ; -2.635 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.881 ; -2.624 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.754 ; -2.483 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.760 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.882  ; 6.755  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.291  ; 5.346  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.733  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.702  ; 3.596  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.732  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.589  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.733  ; 3.638  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.576  ; 3.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.533  ; 3.439  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.580  ; 3.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.373  ; 3.274  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.536  ; 3.433  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.594  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.526  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.389  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.546  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.624  ; 3.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.569  ; 3.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.853  ; 5.686  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.923  ; 5.772  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.841  ; 5.703  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.747  ; 5.603  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.667  ; 5.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 6.210  ; 6.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.690  ; 5.589  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.631  ; 5.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.178  ; 5.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.631  ; 5.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.436  ; 5.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.663  ; 5.519  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.466  ; 5.409  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 6.063  ; 5.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.624  ; 5.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.597  ; 3.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.733  ; 3.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.442  ; 3.340  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.583  ; 5.291  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.082  ; 4.194  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.148  ; 3.113  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.967  ; 1.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.000  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.929  ; 1.937  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.977  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.904  ; 1.905  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.882  ; 1.886  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.897  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.802  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.862  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.903  ; 1.908  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.880  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.892  ; 1.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.918  ; 1.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.876  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.938  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.617  ; 2.649  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.573  ; 2.625  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.537  ; 2.592  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.994  ; 3.818  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.916  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.630  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.743  ; 2.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.644  ; 2.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.505  ; 2.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.610  ; 2.654  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.815  ; 2.798  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.486  ; 2.520  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.582  ; 2.618  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.580  ; 2.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.469  ; 2.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.900  ; 1.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.982  ; 1.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.822  ; 1.806  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.418  ; 3.230  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                       ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin              ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; GPIO_1_CLKIN[1]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[15]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[14]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[13]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[12]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[11]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[10]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[9]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[8]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[31]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[30]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[29]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[28]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[27]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[26]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[25]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[24]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[23]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[22]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[21]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[20]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[19]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[18]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[17]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[16]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[15]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[14]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[13]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[12]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[11]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1_CLKIN[0]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                       ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3186     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3186     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                           ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                            ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 3     ; 3    ;
+; Unconstrained Input Ports       ; 29    ; 29   ;
+; Unconstrained Input Port Paths  ; 102   ; 102  ;
+; Unconstrained Output Ports      ; 94    ; 94   ;
+; Unconstrained Output Port Paths ; 472   ; 472  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:46 2014
+Info: Command: quartus_sta DE0_D5M -c DE0_D5M
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.454
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.454             -22.246 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.170               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.214
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.214               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.358               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -1.497
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.497            -338.162 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.980               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.616
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.616               0.000 CLOCK_50 
+    Info (332119):     4.132               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.736
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.736               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.580               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.051 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 0.053
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.053               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.677               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.190
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.190               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.312               0.000 CLOCK_50 
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case recovery slack is -0.843
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.843            -150.984 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.539               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.477
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.477               0.000 CLOCK_50 
+    Info (332119):     3.638               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.741
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.741               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.561               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.581 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Fast 1200mV 0C Model
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 1.424
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.424               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.244               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.116
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.116               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.187               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is 0.773
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.773               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.090               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 0.904
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.904               0.000 CLOCK_50 
+    Info (332119):     2.414               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.748
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.748               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.265               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 13.232 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 23 warnings
+    Info: Peak virtual memory: 549 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:50 2014
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary
new file mode 100644
index 0000000..4fbf355
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary
@@ -0,0 +1,125 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.454
+TNS   : -22.246
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : 15.170
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.214
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.497
+TNS   : -338.162
+
+Type  : Slow 1200mV 85C Model Recovery 'CLOCK_50'
+Slack : 14.980
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'CLOCK_50'
+Slack : 1.616
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.132
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.736
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.580
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.053
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 15.677
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.190
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.843
+TNS   : -150.984
+
+Type  : Slow 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 15.539
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 1.477
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.638
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.741
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.561
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.424
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 17.244
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.116
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.187
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.773
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 17.090
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 0.904
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 2.414
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.748
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.265
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..8a35815
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v
new file mode 100644
index 0000000..91386f2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v
@@ -0,0 +1,353 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[3:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[3:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[3:0]		VGA_B;   				//	VGA Blue[9:0]
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; //GPIO_1[0];
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:6];
+assign	VGA_G		=	oVGA_G[9:6];
+assign	VGA_B		=	oVGA_B[9:6];
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak
new file mode 100644
index 0000000..1ff6dd3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak
@@ -0,0 +1,435 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE1 D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module DE1_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_24,						//	24 MHz
+		CLOCK_27,						//	27 MHz
+		CLOCK_50,						//	50 MHz
+		EXT_CLOCK,						//	External Clock
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[3:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[7:0]
+		LEDR,								//	LED Red[9:0]
+		////////////////////////	UART	////////////////////////
+		UART_TXD,						//	UART Transmitter
+		UART_RXD,						//	UART Receiver
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	Flash Interface		////////////////
+		FL_DQ,							//	FLASH Data bus 8 Bits
+		FL_ADDR,							//	FLASH Address bus 22 Bits
+		FL_WE_N,							//	FLASH Write Enable
+		FL_RST_N,						//	FLASH Reset
+		FL_OE_N,							//	FLASH Output Enable
+		FL_CE_N,							//	FLASH Chip Enable
+		////////////////////	SRAM Interface		////////////////
+		SRAM_DQ,							//	SRAM Data bus 16 Bits
+		SRAM_ADDR,						//	SRAM Address bus 18 Bits
+		SRAM_UB_N,						//	SRAM High-byte Data Mask 
+		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
+		SRAM_WE_N,						//	SRAM Write Enable
+		SRAM_CE_N,						//	SRAM Chip Enable
+		SRAM_OE_N,						//	SRAM Output Enable
+		////////////////////	SD_Card Interface	////////////////
+		SD_DAT,							//	SD Card Data
+		SD_DAT3,							//	SD Card Data 3
+		SD_CMD,							//	SD Card Command Signal
+		SD_CLK,							//	SD Card Clock
+		////////////////////	USB JTAG link	////////////////////
+		TDI,  							// CPLD -> FPGA (data in)
+		TCK,  							// CPLD -> FPGA (clk)
+		TCS,  							// CPLD -> FPGA (CS)
+	    TDO,  							// FPGA -> CPLD (data out)
+		////////////////////	I2C		////////////////////////////
+		I2C_SDAT,						//	I2C Data
+		I2C_SCLK,						//	I2C Clock
+		////////////////////	PS2		////////////////////////////
+		PS2_DAT,							//	PS2 Data
+		PS2_CLK,							//	PS2 Clock
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		////////////////	Audio CODEC		////////////////////////
+		AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
+		AUD_ADCDAT,						//	Audio CODEC ADC Data
+		AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
+		AUD_DACDAT,						//	Audio CODEC DAC Data
+		AUD_BCLK,						//	Audio CODEC Bit-Stream Clock
+		AUD_XCK,							//	Audio CODEC Chip Clock
+		////////////////////	GPIO	////////////////////////////
+		GPIO_0,							//	GPIO Connection 0
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input	[1:0]	CLOCK_24;				//	24 MHz
+input	[1:0]	CLOCK_27;				//	27 MHz
+input			CLOCK_50;				//	50 MHz
+input			EXT_CLOCK;				//	External Clock
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+////////////////////////////	LED		////////////////////////////
+output	[7:0]	LEDG;					//	LED Green[7:0]
+output	[9:0]	LEDR;					//	LED Red[9:0]
+////////////////////////////	UART	////////////////////////////
+output			UART_TXD;			//	UART Transmitter
+input				UART_RXD;			//	UART Receiver
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	Flash Interface	////////////////////////
+inout	[7:0]		FL_DQ;				//	FLASH Data bus 8 Bits
+output[21:0]	FL_ADDR;				//	FLASH Address bus 22 Bits
+output			FL_WE_N;				//	FLASH Write Enable
+output			FL_RST_N;			//	FLASH Reset
+output			FL_OE_N;				//	FLASH Output Enable
+output			FL_CE_N;				//	FLASH Chip Enable
+////////////////////////	SRAM Interface	////////////////////////
+inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
+output[17:0]	SRAM_ADDR;			//	SRAM Address bus 18 Bits
+output			SRAM_UB_N;			//	SRAM High-byte Data Mask 
+output			SRAM_LB_N;			//	SRAM Low-byte Data Mask 
+output			SRAM_WE_N;			// SRAM Write Enable
+output			SRAM_CE_N;			//	SRAM Chip Enable
+output			SRAM_OE_N;			//	SRAM Output Enable
+////////////////////	SD Card Interface	////////////////////////
+inout				SD_DAT;				//	SD Card Data
+inout				SD_DAT3;				//	SD Card Data 3
+inout				SD_CMD;				//	SD Card Command Signal
+output			SD_CLK;				//	SD Card Clock
+////////////////////////	I2C		////////////////////////////////
+inout				I2C_SDAT;			//	I2C Data
+output			I2C_SCLK;			//	I2C Clock
+////////////////////////	PS2		////////////////////////////////
+input		 		PS2_DAT;				//	PS2 Data
+input				PS2_CLK;				//	PS2 Clock
+////////////////////	USB JTAG link	////////////////////////////
+input  			TDI;					// CPLD -> FPGA (data in)
+input  			TCK;					// CPLD -> FPGA (clk)
+input  			TCS;					// CPLD -> FPGA (CS)
+output 			TDO;					// FPGA -> CPLD (data out)
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+////////////////////	Audio CODEC		////////////////////////////
+inout				AUD_ADCLRCK;		//	Audio CODEC ADC LR Clock
+input				AUD_ADCDAT;			//	Audio CODEC ADC Data
+inout				AUD_DACLRCK;		//	Audio CODEC DAC LR Clock
+output			AUD_DACDAT;			//	Audio CODEC DAC Data
+inout				AUD_BCLK;			//	Audio CODEC Bit-Stream Clock
+output			AUD_XCK;				//	Audio CODEC Chip Clock
+////////////////////////	GPIO	////////////////////////////////
+inout	[31:0]	GPIO_0;				//	GPIO Connection 0
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[3:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[3:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[3:0]		VGA_B;   				//	VGA Blue[9:0]
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[13];
+assign	CCD_DATA[1]	=	GPIO_1[12];
+assign	CCD_DATA[2]	=	GPIO_1[11];
+assign	CCD_DATA[3]	=	GPIO_1[10];
+assign	CCD_DATA[4]	=	GPIO_1[9];
+assign	CCD_DATA[5]	=	GPIO_1[8];
+assign	CCD_DATA[6]	=	GPIO_1[7];
+assign	CCD_DATA[7]	=	GPIO_1[6];
+assign	CCD_DATA[8]	=	GPIO_1[5];
+assign	CCD_DATA[9]	=	GPIO_1[4];
+assign	CCD_DATA[10]=	GPIO_1[3];
+assign	CCD_DATA[11]=	GPIO_1[1];
+assign	GPIO_1[16]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[22];
+assign	CCD_LVAL	   =	GPIO_1[21];
+assign	CCD_PIXCLK	=	GPIO_1[0];
+assign	GPIO_1[19]	=	1'b1;  // tRIGGER
+assign	GPIO_1[17]	=	DLY_RST_1;
+
+assign	LEDR		   =	SW;
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:6];
+assign	VGA_G		=	oVGA_G[9:6];
+assign	VGA_B		=	oVGA_B[9:6];
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!SW[3]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+assign	UART_TXD = UART_RXD;
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[8]),
+								 .iEXPOSURE_ADJ  (KEY[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[24]),
+								 .I2C_SDAT		  (GPIO_1[23])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf
new file mode 100644
index 0000000..cdf6850
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf
@@ -0,0 +1,642 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Internal Build 220 05/13/2009 Service Pack 2 SJ Full Version
+# Date created = 19:24:48  May 26, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS Off
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -value OFF
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION -value OFF
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v
new file mode 100644
index 0000000..22e2411
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v
@@ -0,0 +1,567 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Sdram_Control_4Port
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module Sdram_Control_4Port(
+		//	HOST Side
+        REF_CLK,
+        RESET_N,
+		CLK,
+		//	FIFO Write Side 1
+        WR1_DATA,
+		WR1,
+		WR1_ADDR,
+		WR1_MAX_ADDR,
+		WR1_LENGTH,
+		WR1_LOAD,
+		WR1_CLK,
+		//	FIFO Write Side 2
+        WR2_DATA,
+		WR2,
+		WR2_ADDR,
+		WR2_MAX_ADDR,
+		WR2_LENGTH,
+		WR2_LOAD,
+		WR2_CLK,
+		//	FIFO Read Side 1
+        RD1_DATA,
+		RD1,
+		RD1_ADDR,
+		RD1_MAX_ADDR,
+		RD1_LENGTH,
+		RD1_LOAD,	
+		RD1_CLK,
+		//	FIFO Read Side 2
+        RD2_DATA,
+		RD2,
+		RD2_ADDR,
+		RD2_MAX_ADDR,
+		RD2_LENGTH,
+		RD2_LOAD,
+		RD2_CLK,
+		//	SDRAM Side
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N,
+        DQ,
+        DQM,
+        );
+
+
+`include        "Sdram_Params.h"
+//	HOST Side
+input                           REF_CLK;                //System Clock
+input                           RESET_N;                //System Reset
+input 							CLK;
+//	FIFO Write Side 1
+input   [`DSIZE-1:0]            WR1_DATA;               //Data input
+input							WR1;					//Write Request
+input	[`ASIZE-1:0]			WR1_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR1_MAX_ADDR;			//Write max address
+input	[8:0]					WR1_LENGTH;				//Write length
+input							WR1_LOAD;				//Write register load & fifo clear
+input							WR1_CLK;				//Write fifo clock
+
+//	FIFO Write Side 2
+input   [`DSIZE-1:0]            WR2_DATA;               //Data input
+input							WR2;					//Write Request
+input	[`ASIZE-1:0]			WR2_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR2_MAX_ADDR;			//Write max address
+input	[8:0]					WR2_LENGTH;				//Write length
+input							WR2_LOAD;				//Write register load & fifo clear
+input							WR2_CLK;				//Write fifo clock
+
+//	FIFO Read Side 1
+output  [`DSIZE-1:0]            RD1_DATA;               //Data output
+input							RD1;					//Read Request
+input	[`ASIZE-1:0]			RD1_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD1_MAX_ADDR;			//Read max address
+input	[8:0]					RD1_LENGTH;				//Read length
+input							RD1_LOAD;				//Read register load & fifo clear
+input							RD1_CLK;				//Read fifo clock
+
+//	FIFO Read Side 2
+output  [`DSIZE-1:0]            RD2_DATA;               //Data output
+input							RD2;					//Read Request
+input	[`ASIZE-1:0]			RD2_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD2_MAX_ADDR;			//Read max address
+input	[8:0]					RD2_LENGTH;				//Read length
+input							RD2_LOAD;				//Read register load & fifo clear
+input							RD2_CLK;				//Read fifo clock
+
+//	SDRAM Side
+output  [11:0]                  SA;                     //SDRAM address output
+output  [1:0]                   BA;                     //SDRAM bank address
+output  [1:0]                   CS_N;                   //SDRAM Chip Selects
+output                          CKE;                    //SDRAM clock enable
+output                          RAS_N;                  //SDRAM Row address Strobe
+output                          CAS_N;                  //SDRAM Column address Strobe
+output                          WE_N;                   //SDRAM write enable
+inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
+output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+
+//	Internal Registers/Wires
+//	Controller
+reg		[`ASIZE-1:0]			mADDR;					//Internal address
+reg		[8:0]					mLENGTH;				//Internal length
+reg		[`ASIZE-1:0]			rWR1_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR1_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR1_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rWR2_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR2_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR2_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rRD1_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD1_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD1_LENGTH;			//Register read length
+reg		[`ASIZE-1:0]			rRD2_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD2_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD2_LENGTH;			//Register read length
+reg		[1:0]					WR_MASK;				//Write port active mask
+reg		[1:0]					RD_MASK;				//Read port active mask
+reg								mWR_DONE;				//Flag write done, 1 pulse SDR_CLK
+reg								mRD_DONE;				//Flag read done, 1 pulse SDR_CLK
+reg								mWR,Pre_WR;				//Internal WR edge capture
+reg								mRD,Pre_RD;				//Internal RD edge capture
+reg 	[9:0] 					ST;						//Controller status
+reg		[1:0] 					CMD;					//Controller command
+reg								PM_STOP;				//Flag page mode stop
+reg								PM_DONE;				//Flag page mode done
+reg								Read;					//Flag read active
+reg								Write;					//Flag write active
+reg	    [`DSIZE-1:0]           	mDATAOUT;               //Controller Data output
+wire    [`DSIZE-1:0]           	mDATAIN;                //Controller Data input
+wire    [`DSIZE-1:0]           	mDATAIN1;                //Controller Data input 1
+wire    [`DSIZE-1:0]           	mDATAIN2;                //Controller Data input 2
+wire                          	CMDACK;                 //Controller command acknowledgement
+//	DRAM Control
+reg  	[`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+reg     [11:0]                  SA;                     //SDRAM address output
+reg     [1:0]                   BA;                     //SDRAM bank address
+reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
+reg                             CKE;                    //SDRAM clock enable
+reg                             RAS_N;                  //SDRAM Row address Strobe
+reg                             CAS_N;                  //SDRAM Column address Strobe
+reg                             WE_N;                   //SDRAM write enable
+wire    [`DSIZE-1:0]            DQOUT;					//SDRAM data out link
+wire  	[`DSIZE/8-1:0]          IDQM;                   //SDRAM data mask lines
+wire    [11:0]                  ISA;                    //SDRAM address output
+wire    [1:0]                   IBA;                    //SDRAM bank address
+wire    [1:0]                   ICS_N;                  //SDRAM Chip Selects
+wire                            ICKE;                   //SDRAM clock enable
+wire                            IRAS_N;                 //SDRAM Row address Strobe
+wire                            ICAS_N;                 //SDRAM Column address Strobe
+wire                            IWE_N;                  //SDRAM write enable
+//	FIFO Control
+reg								OUT_VALID;				//Output data request to read side fifo
+reg								IN_REQ;					//Input	data request to write side fifo
+wire	[8:0]					write_side_fifo_rusedw1;
+wire	[8:0]					read_side_fifo_wusedw1;
+wire	[8:0]					write_side_fifo_rusedw2;
+wire	[8:0]					read_side_fifo_wusedw2;
+//	DRAM Internal Control
+wire    [`ASIZE-1:0]            saddr;
+wire                            load_mode;
+wire                            nop;
+wire                            reada;
+wire                            writea;
+wire                            refresh;
+wire                            precharge;
+wire                            oe;
+wire							ref_ack;
+wire							ref_req;
+wire							init_req;
+wire							cm_ack;
+wire							active;
+wire                            CLK;
+wire							CCD_CLK;
+
+control_interface control1 (
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .CMD(CMD),
+                .ADDR(mADDR),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+                .PRECHARGE(precharge),
+                .LOAD_MODE(load_mode),
+                .SADDR(saddr),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .CMD_ACK(CMDACK)
+                );
+
+command command1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .SADDR(saddr),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+				.LOAD_MODE(load_mode),
+                .PRECHARGE(precharge),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .OE(oe),
+				.PM_STOP(PM_STOP),
+				.PM_DONE(PM_DONE),
+                .SA(ISA),
+                .BA(IBA),
+                .CS_N(ICS_N),
+                .CKE(ICKE),
+                .RAS_N(IRAS_N),
+                .CAS_N(ICAS_N),
+                .WE_N(IWE_N)
+                );
+                
+sdr_data_path data_path1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .DATAIN(mDATAIN),
+                .DM(2'b00),
+                .DQOUT(DQOUT),
+                .DQM(IDQM)
+                );
+
+Sdram_FIFO 	write_fifo1(
+				.data(WR1_DATA),
+				.wrreq(WR1),
+				.wrclk(WR1_CLK),
+				.aclr(WR1_LOAD),
+				.rdreq(IN_REQ&WR_MASK[0]),
+				.rdclk(CLK),
+				.q(mDATAIN1),
+				.rdusedw(write_side_fifo_rusedw1)
+				);
+
+Sdram_FIFO 	write_fifo2(
+				.data(WR2_DATA),
+				.wrreq(WR2),
+				.wrclk(WR2_CLK),
+				.aclr(WR2_LOAD),
+				.rdreq(IN_REQ&WR_MASK[1]),
+				.rdclk(CLK),
+				.q(mDATAIN2),
+				.rdusedw(write_side_fifo_rusedw2)
+				);
+				
+assign	mDATAIN	=	(WR_MASK[0])	?	mDATAIN1	:
+										mDATAIN2	;
+
+Sdram_FIFO 	read_fifo1(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[0]),
+				.wrclk(CLK),
+				.aclr(RD1_LOAD),
+				.rdreq(RD1),
+				.rdclk(RD1_CLK),
+				.q(RD1_DATA),
+				.wrusedw(read_side_fifo_wusedw1)
+				);
+				
+Sdram_FIFO 	read_fifo2(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[1]),
+				.wrclk(CLK),
+				.aclr(RD2_LOAD),
+				.rdreq(RD2),
+				.rdclk(RD2_CLK),
+				.q(RD2_DATA),
+				.wrusedw(read_side_fifo_wusedw2)
+				);
+
+always @(posedge CLK)
+begin
+	SA      <= (ST==SC_CL+mLENGTH)			?	12'h200	:	ISA;
+    BA      <= IBA;
+    CS_N    <= ICS_N;
+    CKE     <= ICKE;
+    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
+    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
+    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
+	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
+	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
+	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
+	mDATAOUT<= DQ;
+end
+
+assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
+assign	active	=	Read | Write;
+
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(RESET_N==0)
+	begin
+		CMD			<=  0;
+		ST			<=  0;
+		Pre_RD		<=  0;
+		Pre_WR		<=  0;
+		Read		<=	0;
+		Write		<=	0;
+		OUT_VALID	<=	0;
+		IN_REQ		<=	0;
+		mWR_DONE	<=	0;
+		mRD_DONE	<=	0;
+	end
+	else
+	begin
+		Pre_RD	<=	mRD;
+		Pre_WR	<=	mWR;
+		case(ST)
+		0:	begin
+				if({Pre_RD,mRD}==2'b01)
+				begin
+					Read	<=	1;
+					Write	<=	0;
+					CMD		<=	2'b01;
+					ST		<=	1;
+				end
+				else if({Pre_WR,mWR}==2'b01)
+				begin
+					Read	<=	0;
+					Write	<=	1;
+					CMD		<=	2'b10;
+					ST		<=	1;
+				end
+			end
+		1:	begin
+				if(CMDACK==1)
+				begin
+					CMD<=2'b00;
+					ST<=2;
+				end
+			end
+		default:	
+			begin	
+				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
+				ST<=ST+1;
+				else
+				ST<=0;
+			end
+		endcase
+	
+		if(Read)
+		begin
+			if(ST==SC_CL+SC_RCD+1)
+			OUT_VALID	<=	1;
+			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
+			begin
+				OUT_VALID	<=	0;
+				Read		<=	0;
+				mRD_DONE	<=	1;
+			end
+		end
+		else
+		mRD_DONE	<=	0;
+		
+		if(Write)
+		begin
+			if(ST==SC_CL-1)
+			IN_REQ	<=	1;
+			else if(ST==SC_CL+mLENGTH-1)
+			IN_REQ	<=	0;
+			else if(ST==SC_CL+SC_RCD+mLENGTH)
+			begin
+				Write	<=	0;
+				mWR_DONE<=	1;
+			end
+		end
+		else
+		mWR_DONE<=	0;
+
+	end
+end
+//	Internal Address & Length Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		rWR1_ADDR		<=	0;
+		rWR2_ADDR		<=	22'h100000;
+		rRD1_ADDR		<=	0;
+		rRD2_ADDR		<=	22'h100000;
+		rWR1_MAX_ADDR	<=	640*480;
+		rWR2_MAX_ADDR	<=	22'h100000+640*480;
+		rRD1_MAX_ADDR	<=	640*480;
+		rRD2_MAX_ADDR	<=	22'h100000+640*480;
+		rWR1_LENGTH		<=	256;
+		rWR2_LENGTH		<=	256;
+		rRD1_LENGTH		<=	256;
+		rRD2_LENGTH		<=	256;
+	end
+	else
+	begin
+		//	Write Side 1
+		if(WR1_LOAD)
+		begin
+			rWR1_ADDR	<=	WR1_ADDR;
+			rWR1_LENGTH	<=	WR1_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[0])
+		begin
+			if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
+				rWR1_ADDR	<=	rWR1_ADDR+rWR1_LENGTH;
+			else
+				rWR1_ADDR	<=	WR1_ADDR;
+		end
+		//	Write Side 2
+		if(WR2_LOAD)
+		begin
+			rWR2_ADDR	<=	WR2_ADDR;
+			rWR2_LENGTH	<=	WR2_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[1])
+		begin
+			if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
+				rWR2_ADDR	<=	rWR2_ADDR+rWR2_LENGTH;
+			else
+				rWR2_ADDR	<=	WR2_ADDR;
+		end
+		//	Read Side 1
+		if(RD1_LOAD)
+		begin
+			rRD1_ADDR	<=	RD1_ADDR;
+			rRD1_LENGTH	<=	RD1_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[0])
+		begin
+			if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
+				rRD1_ADDR	<=	rRD1_ADDR+rRD1_LENGTH;
+			else
+				rRD1_ADDR	<=	RD1_ADDR;
+		end
+		//	Read Side 2
+		if(RD2_LOAD)
+		begin
+			rRD2_ADDR	<=	RD2_ADDR;
+			rRD2_LENGTH	<=	RD2_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[1])
+		begin
+			if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
+				rRD2_ADDR	<=	rRD2_ADDR+rRD2_LENGTH;
+			else
+				rRD2_ADDR	<=	RD2_ADDR;
+		end
+	end
+end
+//	Auto Read/Write Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		mWR		<=	0;
+		mRD		<=	0;
+		mADDR	<=	0;
+		mLENGTH	<=	0;
+	end
+	else
+	begin
+		if( (mWR==0) && (mRD==0) && (ST==0) &&
+			(WR_MASK==0)	&&	(RD_MASK==0) &&
+			(WR1_LOAD==0)	&&	(RD1_LOAD==0) &&
+			(WR2_LOAD==0)	&&	(RD2_LOAD==0) )
+		begin
+			//	Write Side 1
+			if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR1_ADDR;
+				mLENGTH	<=	rWR1_LENGTH;
+				WR_MASK	<=	2'b01;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Write Side 2
+			else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR2_ADDR;
+				mLENGTH	<=	rWR2_LENGTH;
+				WR_MASK	<=	2'b10;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Read Side 1
+			else if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
+			begin
+				mADDR	<=	rRD1_ADDR;
+				mLENGTH	<=	rRD1_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b01;
+				mWR		<=	0;
+				mRD		<=	1;				
+			end
+			//	Read Side 2
+			else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
+			begin
+				mADDR	<=	rRD2_ADDR;
+				mLENGTH	<=	rRD2_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b10;
+				mWR		<=	0;
+				mRD		<=	1;
+			end
+		end
+		if(mWR_DONE)
+		begin
+			WR_MASK	<=	0;
+			mWR		<=	0;
+		end
+		if(mRD_DONE)
+		begin
+			RD_MASK	<=	0;
+			mRD		<=	0;
+		end
+	end
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip
new file mode 100644
index 0000000..ceca5c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_FIFO.v"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v
new file mode 100644
index 0000000..af2662b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: Sdram_FIFO.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Sdram_FIFO (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[8:0]  rdusedw;
+	output	  wrfull;
+	output	[8:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [15:0] sub_wire1;
+	wire  sub_wire2;
+	wire [8:0] sub_wire3;
+	wire [8:0] sub_wire4;
+	wire  wrfull = sub_wire0;
+	wire [15:0] q = sub_wire1[15:0];
+	wire  rdempty = sub_wire2;
+	wire [8:0] wrusedw = sub_wire3[8:0];
+	wire [8:0] rdusedw = sub_wire4[8:0];
+
+	dcfifo	dcfifo_component (
+				.rdclk (rdclk),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.aclr (aclr),
+				.data (data),
+				.rdreq (rdreq),
+				.wrfull (sub_wire0),
+				.q (sub_wire1),
+				.rdempty (sub_wire2),
+				.wrusedw (sub_wire3),
+				.rdusedw (sub_wire4),
+				.rdfull (),
+				.wrempty ());
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+ 	
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v
new file mode 100644
index 0000000..8b37dff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v
@@ -0,0 +1,482 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	command
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module command(
+        CLK,
+        RESET_N,
+        SADDR,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        REF_REQ,
+		INIT_REQ,
+		PM_STOP,
+		PM_DONE,
+        REF_ACK,
+        CM_ACK,
+        OE,
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`ASIZE-1:0]            SADDR;                  // Address
+input                           NOP;                    // Decoded NOP command
+input                           READA;                  // Decoded READA command
+input                           WRITEA;                 // Decoded WRITEA command
+input                           REFRESH;                // Decoded REFRESH command
+input                           PRECHARGE;              // Decoded PRECHARGE command
+input                           LOAD_MODE;              // Decoded LOAD_MODE command
+input                           REF_REQ;                // Hidden refresh request
+input							INIT_REQ;				// Hidden initial request
+input							PM_STOP;				// Page mode stop
+input							PM_DONE;				// Page mode done
+output                          REF_ACK;                // Refresh request acknowledge
+output                          CM_ACK;                 // Command acknowledge
+output                          OE;                     // OE signal for data path module
+output  [11:0]                  SA;                     // SDRAM address
+output  [1:0]                   BA;                     // SDRAM bank address
+output  [1:0]                   CS_N;                   // SDRAM chip selects
+output                          CKE;                    // SDRAM clock enable
+output                          RAS_N;                  // SDRAM RAS
+output                          CAS_N;                  // SDRAM CAS
+output                          WE_N;                   // SDRAM WE_N
+            
+reg                             CM_ACK;
+reg                             REF_ACK;
+reg                             OE;
+reg     [11:0]                  SA;
+reg     [1:0]                   BA;
+reg     [1:0]                   CS_N;
+reg                             CKE;
+reg                             RAS_N;
+reg                             CAS_N;
+reg                             WE_N;
+
+// Internal signals
+reg                             do_reada;
+reg                             do_writea;
+reg                             do_refresh;
+reg                             do_precharge;
+reg                             do_load_mode;
+reg								do_initial;
+reg                             command_done;
+reg     [7:0]                   command_delay;
+reg     [1:0]                   rw_shift;
+reg                             do_act;
+reg                             rw_flag;
+reg                             do_rw;
+reg     [6:0]                   oe_shift;
+reg                             oe1;
+reg                             oe2;
+reg                             oe3;
+reg                             oe4;
+reg     [3:0]                   rp_shift;
+reg                             rp_done;
+reg								ex_read;
+reg								ex_write;
+
+wire    [`ROWSIZE - 1:0]        rowaddr;
+wire    [`COLSIZE - 1:0]        coladdr;
+wire    [`BANKSIZE - 1:0]       bankaddr;
+
+assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
+assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
+assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
+
+// This always block monitors the individual command lines and issues a command
+// to the next stage if there currently another command already running.
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 0;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+        end
+        
+        else
+        begin
+
+//  Issue the appropriate command if the sdram is not currently busy
+			if( INIT_REQ == 1 )
+			begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 1;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+			end
+			else
+			begin
+				do_initial		<= 0;
+				
+                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
+                        & do_reada == 0 & do_writea == 0)
+                        do_refresh <= 1;         
+                else
+                        do_refresh <= 0;
+
+                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
+                begin
+				        do_reada <= 1;
+						ex_read <= 1;
+				end
+                else
+                        do_reada <= 0;
+                    
+                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
+                begin
+				        do_writea <= 1;
+						ex_write <= 1;
+				end
+                else
+                        do_writea <= 0;
+
+                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))	// PRECHARGE
+                        do_precharge <= 1;
+                else
+                        do_precharge <= 0;
+ 
+                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))	// LOADMODE
+                        do_load_mode <= 1;
+                else
+                        do_load_mode <= 0;
+                                               
+// set command_delay shift register and command_done flag
+// The command delay shift register is a timer that is used to ensure that
+// the SDRAM devices have had sufficient time to finish the last command.
+
+                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
+                     | (do_load_mode == 1))
+                begin
+                        command_delay <= 8'b11111111;
+                        command_done  <= 1;
+                        rw_flag <= do_reada;                                                  
+                end
+                
+                else
+                begin
+                        command_done        <= command_delay[0];                // the command_delay shift operation
+                        command_delay		<= (command_delay>>1);
+                end 
+                
+ 
+ // start additional timer that is used for the refresh, writea, reada commands               
+                if (command_delay[0] == 0 & command_done == 1)
+                begin
+                	rp_shift <= 4'b1111;
+                	rp_done <= 1;
+                end
+                else
+                begin						
+					if(SC_PM == 0)
+					begin
+						rp_shift	<= (rp_shift>>1);
+                    	rp_done		<= rp_shift[0];
+					end
+					else
+					begin
+						if( (ex_read == 0) && (ex_write == 0) )
+						begin
+							rp_shift	<= (rp_shift>>1);
+        	            	rp_done		<= rp_shift[0];
+						end
+						else
+						begin
+							if( PM_STOP==1 )
+							begin
+								rp_shift	<= (rp_shift>>1);
+        	      		      	rp_done     <= rp_shift[0];
+								ex_read		<= 1'b0;
+								ex_write	<= 1'b0;
+							end					
+						end
+					end
+                end
+			end
+        end
+end
+
+
+// logic that generates the OE signal for the data path module
+// For normal burst write he duration of OE is dependent on the configured burst length.
+// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
+// and is left on until a PRECHARGE(page burst terminate) is detected.
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                oe_shift <= 0;
+                oe1      <= 0;
+                oe2      <= 0;
+                OE       <= 0;
+        end
+        else
+        begin
+                if (SC_PM == 0)
+                begin
+                        if (do_writea == 1)
+                        begin
+                                if (SC_BL == 1)				//  Set the shift register to the appropriate
+                                        oe_shift <= 0;		// value based on burst length.
+                                else if (SC_BL == 2)
+                                        oe_shift <= 1;
+                                else if (SC_BL == 4)
+                                        oe_shift <= 7;
+                                else if (SC_BL == 8)
+                                        oe_shift <= 127;
+                                oe1 <= 1;
+                        end
+                        else 
+                        begin
+                                oe_shift <= (oe_shift>>1);
+                                oe1  <= oe_shift[0];
+                                oe2  <= oe1;
+                                oe3  <= oe2;
+                                oe4  <= oe3;
+                                if (SC_RCD == 2)
+                                        OE <= oe3;
+                                else
+                                        OE <= oe4;
+                        end
+                end
+                else
+                begin
+                        if (do_writea == 1)					 // OE generation for page mode accesses
+                                oe4   <= 1;
+                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
+                                oe4   <= 0;
+                        OE <= oe4;
+                end
+                               
+        end
+end
+
+
+
+
+// This always block tracks the time between the activate command and the
+// subsequent WRITEA or READA command, RC.  The shift register is set using
+// the configuration register setting SC_RCD. The shift register is loaded with
+// a single '1' with the position within the register dependent on SC_RCD.
+// When the '1' is shifted out of the register it sets so_rw which triggers
+// a writea or reada command
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                rw_shift <= 0;
+                do_rw    <= 0;
+        end
+        
+        else
+        begin
+                
+                if ((do_reada == 1) | (do_writea == 1))
+                begin
+                        if (SC_RCD == 1)                          // Set the shift register
+                                do_rw <= 1;
+                        else if (SC_RCD == 2)
+                                rw_shift <= 1;
+                        else if (SC_RCD == 3)
+                                rw_shift <= 2;
+                end
+                else
+                begin
+                        rw_shift <= (rw_shift>>1);
+                        do_rw    <= rw_shift[0];
+                end 
+        end
+end              
+
+// This always block generates the command acknowledge, CM_ACK, signal.
+// It also generates the acknowledge signal, REF_ACK, that acknowledges
+// a refresh request that was generated by the internal refresh timer circuit.
+always @(posedge CLK or negedge RESET_N) 
+begin
+
+        if (RESET_N == 0) 
+        begin
+                CM_ACK   <= 0;
+                REF_ACK  <= 0;
+        end
+        
+        else
+        begin
+                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
+                        REF_ACK <= 1;
+                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
+                         | (do_load_mode))
+                        CM_ACK <= 1;
+                else
+                begin
+                        REF_ACK <= 0;
+                        CM_ACK  <= 0;
+                end
+        end
+end 
+                    
+
+
+
+
+
+
+// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
+// 
+always @(posedge CLK ) begin
+        if (RESET_N==0) begin
+                SA    <= 0;
+                BA    <= 0;
+                CS_N  <= 1;
+                RAS_N <= 1;
+                CAS_N <= 1;
+                WE_N  <= 1;
+                CKE   <= 0;
+        end
+        else begin
+                CKE <= 1;
+
+// Generate SA 	
+                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
+                        SA <= rowaddr;
+                else
+                        SA <= coladdr;                 // else alway present column address
+                if ((do_rw==1) | (do_precharge))
+                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
+                                                       // don't set it if the controller is in page mode.           
+                if (do_precharge==1 | do_load_mode==1)
+                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
+                else
+                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
+		
+                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
+                        CS_N <= 0;                                    // Select both chip selects if performing
+                else                                                  // refresh, precharge(all) or load_mode
+                begin
+                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
+                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
+                end
+				
+				if(do_load_mode==1)
+				SA	  <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
+
+
+//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
+//depending on the issued command.
+//		
+                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 1;
+                end
+                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 0;
+                end
+                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
+                        RAS_N <= 1;
+                        CAS_N <= 0;
+                        WE_N  <= rw_flag;
+                end
+				else if (do_initial ==1) begin
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;				
+				end
+                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+        end 
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v
new file mode 100644
index 0000000..d7930e2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v
@@ -0,0 +1,240 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	control_interface
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module control_interface(
+        CLK,
+        RESET_N,
+        CMD,
+        ADDR,
+        REF_ACK,
+		INIT_ACK,
+        CM_ACK,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        SADDR,
+        REF_REQ,
+		INIT_REQ,
+        CMD_ACK
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [2:0]                   CMD;                    // Command input
+input   [`ASIZE-1:0]            ADDR;                   // Address
+input                           REF_ACK;                // Refresh request acknowledge
+input							INIT_ACK;				// Initial request acknowledge
+input                           CM_ACK;                 // Command acknowledge
+output                          NOP;                    // Decoded NOP command
+output                          READA;                  // Decoded READA command
+output                          WRITEA;                 // Decoded WRITEA command
+output                          REFRESH;                // Decoded REFRESH command
+output                          PRECHARGE;              // Decoded PRECHARGE command
+output                          LOAD_MODE;              // Decoded LOAD_MODE command
+output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
+output                          REF_REQ;                // Hidden refresh request
+output                          INIT_REQ;               // Hidden initial request
+output                          CMD_ACK;                // Command acknowledge
+
+
+            
+reg                             NOP;
+reg                             READA;
+reg                             WRITEA;
+reg                             REFRESH;
+reg                             PRECHARGE;
+reg                             LOAD_MODE;
+reg     [`ASIZE-1:0]            SADDR;
+reg                             REF_REQ;
+reg                             INIT_REQ;
+reg                             CMD_ACK;
+
+// Internal signals
+reg     [15:0]                  timer;
+reg		[15:0]					init_timer;
+
+
+
+// Command decode and ADDR register
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                NOP             <= 0;
+                READA           <= 0;
+                WRITEA          <= 0;
+                SADDR           <= 0;
+        end
+        
+        else
+        begin
+        
+                SADDR <= ADDR;                                  // register the address to keep proper
+                                                                // alignment with the command
+                                                             
+                if (CMD == 3'b000)                              // NOP command
+                        NOP <= 1;
+                else
+                        NOP <= 0;
+                        
+                if (CMD == 3'b001)                              // READA command
+                        READA <= 1;
+                else
+                        READA <= 0;
+                 
+                if (CMD == 3'b010)                              // WRITEA command
+                        WRITEA <= 1;
+                else
+                        WRITEA <= 0;
+                        
+        end
+end
+
+
+//  Generate CMD_ACK
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+                CMD_ACK <= 0;
+        else
+                if ((CM_ACK == 1) & (CMD_ACK == 0))
+                        CMD_ACK <= 1;
+                else
+                        CMD_ACK <= 0;
+end
+
+
+// refresh timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                timer           <= 0;
+                REF_REQ         <= 0;
+        end        
+        else 
+        begin
+                if (REF_ACK == 1)
+				begin
+                	timer <= REF_PER;
+					REF_REQ	<=0;
+				end
+				else if (INIT_REQ == 1)
+				begin
+                	timer <= REF_PER+200;
+					REF_REQ	<=0;					
+				end
+                else
+                	timer <= timer - 1'b1;
+
+                if (timer==0)
+                    REF_REQ    <= 1;
+
+        end
+end
+
+// initial timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                init_timer      <= 0;
+				REFRESH         <= 0;
+                PRECHARGE      	<= 0; 
+				LOAD_MODE		<= 0;
+				INIT_REQ		<= 0;
+        end        
+        else 
+        begin
+                if (init_timer < (INIT_PER+201))
+					init_timer 	<= init_timer+1;
+					
+				if (init_timer < INIT_PER)
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=1;
+				end
+				else if(init_timer == (INIT_PER+20))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=1;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if( 	(init_timer == (INIT_PER+40))	||
+							(init_timer == (INIT_PER+60))	||
+							(init_timer == (INIT_PER+80))	||
+							(init_timer == (INIT_PER+100))	||
+							(init_timer == (INIT_PER+120))	||
+							(init_timer == (INIT_PER+140))	||
+							(init_timer == (INIT_PER+160))	||
+							(init_timer == (INIT_PER+180))	)
+				begin
+					REFRESH		<=1;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if(init_timer == (INIT_PER+200))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=1;
+					INIT_REQ	<=0;				
+				end
+				else
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;									
+				end
+        end
+end
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v
new file mode 100644
index 0000000..b064bbe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v
@@ -0,0 +1,76 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	sdr_data_path
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module sdr_data_path(
+        CLK,
+        RESET_N,
+        DATAIN,
+        DM,
+        DQOUT,
+        DQM
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`DSIZE-1:0]            DATAIN;                 // Data input from the host
+input   [`DSIZE/8-1:0]          DM;                     // byte data masks
+output  [`DSIZE-1:0]            DQOUT;
+output  [`DSIZE/8-1:0]          DQM;                    // SDRAM data mask ouputs
+reg     [`DSIZE/8-1:0]          DQM;
+            
+
+
+// Allign the input and output data to the SDRAM control path
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+		DQM		<= `DSIZE/8-1'hF;
+        else
+ 		DQM		<=	DM;                 
+end
+
+assign DQOUT = DATAIN;
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf
new file mode 100644
index 0000000..f33dd49
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf
@@ -0,0 +1,875 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 328 160 496 176)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 128 320 192 336))
+)
+(pin
+	(input)
+	(rect 416 192 584 208)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 288 224 344 240))
+)
+(pin
+	(input)
+	(rect 384 208 608 224)
+	(text "INPUT" (rect 180 6 208 16)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKIN[1..0]" (rect 6 4 109 16)(font "Arial" ))
+	(pt 224 8)
+	(drawing
+		(line (pt 139 4)(pt 164 4))
+		(line (pt 139 12)(pt 164 12))
+		(line (pt 168 8)(pt 223 8))
+		(line (pt 139 4)(pt 139 12))
+		(line (pt 164 12)(pt 168 8))
+		(line (pt 164 4)(pt 168 8))
+	)
+	(flipx)
+	(text "VCC" (rect 183 -1 203 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 504 280 560 296))
+)
+(pin
+	(input)
+	(rect 328 176 496 192)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "KEY[2..0]" (rect 5 0 53 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 176 432 232 448))
+)
+(pin
+	(output)
+	(rect 1064 160 1240 176)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "LEDG[9..0]" (rect 116 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 656 264 720 280))
+)
+(pin
+	(output)
+	(rect 1064 224 1240 240)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX3[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1032 336 1096 352))
+)
+(pin
+	(output)
+	(rect 1064 208 1240 224)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX2[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1256 216 1320 232))
+)
+(pin
+	(output)
+	(rect 1064 192 1240 208)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX1[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1272 176 1336 192))
+)
+(pin
+	(output)
+	(rect 1064 176 1240 192)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX0[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1016 352 1080 368))
+)
+(pin
+	(output)
+	(rect 1024 272 1200 288)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_LDQM" (rect 103 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1376 808 1440 824))
+)
+(pin
+	(output)
+	(rect 1024 288 1200 304)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_UDQM" (rect 101 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 704 1784 720))
+)
+(pin
+	(output)
+	(rect 1024 384 1200 400)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_1" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 800 1784 816))
+)
+(pin
+	(output)
+	(rect 1024 368 1200 384)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_0" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1376 776 1440 792))
+)
+(pin
+	(output)
+	(rect 1024 320 1200 336)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 736 1792 752))
+)
+(pin
+	(output)
+	(rect 1024 416 1200 432)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CKE" (rect 110 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 832 1792 848))
+)
+(pin
+	(output)
+	(rect 1024 352 1200 368)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CS_N" (rect 103 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 768 1784 784))
+)
+(pin
+	(output)
+	(rect 1024 336 1200 352)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_RAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 752 1784 768))
+)
+(pin
+	(output)
+	(rect 1024 304 1200 320)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_WE_N" (rect 101 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 720 1784 736))
+)
+(pin
+	(output)
+	(rect 1024 400 1200 416)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CLK" (rect 111 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 464 1200 528 1216))
+)
+(pin
+	(output)
+	(rect 1024 256 1233 272)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_ADDR[11..0] " (rect 98 0 203 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1664 656 1728 672))
+)
+(pin
+	(output)
+	(rect 1024 528 1234 544)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKOUT[1..0]" (rect 90 0 204 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1448 552 1504 568))
+)
+(pin
+	(output)
+	(rect 960 752 1136 768)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 37 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 768 1192 784))
+)
+(pin
+	(output)
+	(rect 960 704 1136 720)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_HS" (rect 43 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 720 1192 736))
+)
+(pin
+	(output)
+	(rect 960 720 1136 736)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_VS" (rect 44 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 736 1192 752))
+)
+(pin
+	(output)
+	(rect 960 656 1136 672)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_R[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 672 1192 688))
+)
+(pin
+	(output)
+	(rect 960 672 1136 688)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 688 1192 704))
+)
+(pin
+	(output)
+	(rect 960 688 1136 704)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_B[3..0]" (rect 5 0 66 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 704 1192 720))
+)
+(pin
+	(bidir)
+	(rect 1024 240 1208 256)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "DRAM_DQ[15..0] " (rect 90 0 179 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1816 608 1880 624))
+)
+(pin
+	(bidir)
+	(rect 1024 544 1200 560)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1[31..0]" (rect 90 0 160 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1400 632 1456 648))
+)
+(symbol
+	(rect 640 136 928 600)
+	(text "DE0_D5M" (rect 5 0 54 12)(font "Arial" ))
+	(text "inst" (rect 8 448 25 460)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 55 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 76 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 48 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 69 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 64 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 103 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 124 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 221 27 276 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 276 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 223 59 276 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 276 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 276 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 101 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 182 123 283 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 210 139 278 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 70 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 208 155 278 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 69 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 209 171 278 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 205 187 279 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 205 203 279 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 211 219 278 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 214 235 277 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 214 251 277 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 218 267 277 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 60 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 217 283 277 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_HS" (rect 231 299 274 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_VS" (rect 232 315 274 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[3..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_R[3..0]" (rect 215 331 277 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[3..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_G[3..0]" (rect 215 347 277 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[3..0]" (rect 0 0 61 12)(font "Arial" ))
+		(text "VGA_B[3..0]" (rect 216 363 277 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 226 379 275 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 114 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 395 285 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 278 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 411 282 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 448))
+	)
+)
+(connector
+	(pt 608 216)
+	(pt 640 216)
+	(bus)
+)
+(connector
+	(pt 584 200)
+	(pt 640 200)
+	(bus)
+)
+(connector
+	(text "KEY[2..0]" (rect 506 168 554 180)(font "Arial" ))
+	(pt 496 184)
+	(pt 640 184)
+	(bus)
+)
+(connector
+	(text "CLOCK_50" (rect 506 152 561 164)(font "Arial" ))
+	(pt 496 168)
+	(pt 640 168)
+)
+(connector
+	(pt 928 168)
+	(pt 1064 168)
+	(bus)
+)
+(connector
+	(pt 928 232)
+	(pt 1064 232)
+	(bus)
+)
+(connector
+	(pt 928 216)
+	(pt 1064 216)
+	(bus)
+)
+(connector
+	(pt 928 200)
+	(pt 1064 200)
+	(bus)
+)
+(connector
+	(pt 928 184)
+	(pt 1064 184)
+	(bus)
+)
+(connector
+	(pt 928 248)
+	(pt 1024 248)
+	(bus)
+)
+(connector
+	(pt 928 264)
+	(pt 1024 264)
+	(bus)
+)
+(connector
+	(pt 928 280)
+	(pt 1024 280)
+)
+(connector
+	(pt 928 296)
+	(pt 1024 296)
+)
+(connector
+	(pt 928 312)
+	(pt 1024 312)
+)
+(connector
+	(pt 928 328)
+	(pt 1024 328)
+)
+(connector
+	(pt 928 344)
+	(pt 1024 344)
+)
+(connector
+	(pt 928 360)
+	(pt 1024 360)
+)
+(connector
+	(pt 928 376)
+	(pt 1024 376)
+)
+(connector
+	(pt 928 392)
+	(pt 1024 392)
+)
+(connector
+	(pt 928 408)
+	(pt 1024 408)
+)
+(connector
+	(pt 928 424)
+	(pt 1024 424)
+)
+(connector
+	(text "VGA_HS" (rect 938 424 981 436)(font "Arial" ))
+	(pt 928 440)
+	(pt 1008 440)
+)
+(connector
+	(text "VGA_VS" (rect 938 440 980 452)(font "Arial" ))
+	(pt 928 456)
+	(pt 1008 456)
+)
+(connector
+	(text "VGA_CLK" (rect 938 504 987 516)(font "Arial" ))
+	(pt 928 520)
+	(pt 1112 520)
+)
+(connector
+	(pt 928 536)
+	(pt 1024 536)
+	(bus)
+)
+(connector
+	(pt 928 552)
+	(pt 1024 552)
+	(bus)
+)
+(connector
+	(text "VGA_R[3..0]" (rect 938 456 1000 468)(font "Arial" ))
+	(pt 928 472)
+	(pt 1136 472)
+	(bus)
+)
+(connector
+	(text "VGA_G[3..0]" (rect 938 472 1000 484)(font "Arial" ))
+	(pt 928 488)
+	(pt 1136 488)
+	(bus)
+)
+(connector
+	(text "VGA_B[3..0]" (rect 938 488 999 500)(font "Arial" ))
+	(pt 928 504)
+	(pt 1136 504)
+	(bus)
+)
+(text "CLOCK_50" (rect 506 152 561 164)(font "Arial" ))
+(text "KEY[2..0]" (rect 506 168 554 180)(font "Arial" ))
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v
new file mode 100644
index 0000000..338ae75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v
@@ -0,0 +1,186 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	D5M CCD_Capture
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module CCD_Capture(	oDATA,
+					oDVAL,
+					oX_Cont,
+					oY_Cont,
+					oFrame_Cont,
+					iDATA,
+					iFVAL,
+					iLVAL,
+					iSTART,
+					iEND,
+					iCLK,
+					iRST
+					);
+					
+input	[11:0]	iDATA;
+input			iFVAL;
+input			iLVAL;
+input			iSTART;
+input			iEND;
+input			iCLK;
+input			iRST;
+output	[11:0]	oDATA;
+output	[15:0]	oX_Cont;
+output	[15:0]	oY_Cont;
+output	[31:0]	oFrame_Cont;
+output			oDVAL;
+reg				Pre_FVAL;
+reg				mCCD_FVAL;
+reg				mCCD_LVAL;
+reg		[11:0]	mCCD_DATA;
+reg		[15:0]	X_Cont;
+reg		[15:0]	Y_Cont;
+reg		[31:0]	Frame_Cont;
+reg				mSTART;
+
+parameter COLUMN_WIDTH = 1280;
+
+assign	oX_Cont		=	X_Cont;
+assign	oY_Cont		=	Y_Cont;
+assign	oFrame_Cont	=	Frame_Cont;
+assign	oDATA		=	mCCD_DATA;
+assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	mSTART	<=	0;
+	else
+	begin
+		if(iSTART)
+		mSTART	<=	1;
+		if(iEND)
+		mSTART	<=	0;		
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Pre_FVAL	<=	0;
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	0;
+
+		X_Cont		<=	0;
+		Y_Cont		<=	0;
+	end
+	else
+	begin
+		Pre_FVAL	<=	iFVAL;
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		mCCD_FVAL	<=	1;
+		else if({Pre_FVAL,iFVAL}==2'b10)
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	iLVAL;
+		if(mCCD_FVAL)
+		begin
+			if(mCCD_LVAL)
+			begin
+				if(X_Cont<(COLUMN_WIDTH-1))
+				X_Cont	<=	X_Cont+1;
+				else
+				begin
+					X_Cont	<=	0;
+					Y_Cont	<=	Y_Cont+1;
+				end
+			end
+		end
+		else
+		begin
+			X_Cont	<=	0;
+			Y_Cont	<=	0;
+		end
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	Frame_Cont	<=	0;
+	else
+	begin
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		Frame_Cont	<=	Frame_Cont+1;
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		mCCD_DATA	<=	0;
+	else if (iLVAL)
+		mCCD_DATA	<=	iDATA;
+	else
+		mCCD_DATA	<=	0;	
+end			
+
+reg	ifval_dealy;
+
+wire ifval_fedge;	
+reg	[15:0]	y_cnt_d;
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		y_cnt_d	<=	0;
+	else
+		y_cnt_d	<=	Y_Cont;	
+end
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		ifval_dealy	<=	0;
+	else
+		ifval_dealy	<=	iFVAL;	
+end
+
+assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  
+
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v
new file mode 100644
index 0000000..11d3a70
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v
@@ -0,0 +1,287 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| CCD config, spelling
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+
+// `define 	ENABLE_TEST_PATTERN 1
+
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	sensor_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			sensor_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((sensor_exposure < exposure_change_value)||
+							(sensor_exposure == 16'h0))
+							sensor_exposure <= 0;
+						else	
+							sensor_exposure <= sensor_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -sensor_exposure) <exposure_change_value)||
+							(sensor_exposure == 16'hffff))
+							sensor_exposure <= 16'hffff;
+						else
+							sensor_exposure <= sensor_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,sensor_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..81810a8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak
@@ -0,0 +1,282 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	senosr_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			senosr_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((senosr_exposure < exposure_change_value)||
+							(senosr_exposure == 16'h0))
+							senosr_exposure <= 0;
+						else	
+							senosr_exposure <= senosr_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -senosr_exposure) <exposure_change_value)||
+							(senosr_exposure == 16'hffff))
+							senosr_exposure <= 16'hffff;
+						else
+							senosr_exposure <= senosr_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,senosr_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v
new file mode 100644
index 0000000..3740541
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v
@@ -0,0 +1,150 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altrea Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL or Verilog source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Joe Yang          :| 05/07/10  :|      Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+	CLOCK,
+	I2C_SCLK,//I2C CLOCK
+ 	I2C_SDAT,//I2C DATA
+	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+	GO,      //GO transfor
+	END,     //END transfor 
+
+	ACK,      //ACK
+	RESET
+);
+	input  CLOCK;
+	input  [31:0]I2C_DATA;	
+	input  GO;
+	input  RESET;	
+ 	inout  I2C_SDAT;	
+	output I2C_SCLK;
+	output END;	
+	output ACK;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [31:0]SD;
+reg [6:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3,ACK4;
+wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0) 
+	SD_COUNTER=0;
+	else 
+	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
+end
+end
+//----
+
+always @(negedge RESET or  posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
+else
+case (SD_COUNTER)
+	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
+	//start
+	6'd1  : begin SD=I2C_DATA;SDO=0;end
+	6'd2  : SCLK=0;
+	//SLAVE ADDR
+	6'd3  : SDO=SD[31];
+	6'd4  : SDO=SD[30];
+	6'd5  : SDO=SD[29];
+	6'd6  : SDO=SD[28];
+	6'd7  : SDO=SD[27];
+	6'd8  : SDO=SD[26];
+	6'd9  : SDO=SD[25];
+	6'd10 : SDO=SD[24];	
+	6'd11 : SDO=1'b1;//ACK
+
+	//SUB ADDR
+	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
+	6'd13  : SDO=SD[22];
+	6'd14  : SDO=SD[21];
+	6'd15  : SDO=SD[20];
+	6'd16  : SDO=SD[19];
+	6'd17  : SDO=SD[18];
+	6'd18  : SDO=SD[17];
+	6'd19  : SDO=SD[16];
+	6'd20  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
+	6'd22  : SDO=SD[14];
+	6'd23  : SDO=SD[13];
+	6'd24  : SDO=SD[12];
+	6'd25  : SDO=SD[11];
+	6'd26  : SDO=SD[10];
+	6'd27  : SDO=SD[9];
+	6'd28  : SDO=SD[8];
+	6'd29  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
+	6'd31  : SDO=SD[6];
+	6'd32  : SDO=SD[5];
+	6'd33  : SDO=SD[4];
+	6'd34  : SDO=SD[3];
+	6'd35  : SDO=SD[2];
+	6'd36  : SDO=SD[1];
+	6'd37  : SDO=SD[0];
+	6'd38  : SDO=1'b1;//ACK
+
+	
+	//stop
+    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
+    6'd40 : SCLK=1'b1; 
+    6'd41 : begin SDO=1'b1; END=1; end 
+
+endcase
+end
+
+
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf
new file mode 100644
index 0000000..b7b5b56
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf
@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 184 128)
+	(text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 184 40)
+		(output)
+		(text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8)))
+		(line (pt 184 40)(pt 168 40)(line_width 3))
+	)
+	(port
+		(pt 184 56)
+		(output)
+		(text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps1x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8)))
+		(line (pt 184 56)(pt 168 56)(line_width 3))
+	)
+	(port
+		(pt 184 72)
+		(output)
+		(text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps0x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8)))
+		(line (pt 184 72)(pt 168 72)(line_width 3))
+	)
+	(drawing
+		(text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8)))
+		(text "Number of taps 2" (rect 19 90 93 102)(font "Arial" ))
+		(text "Tap distance 1280" (rect 19 100 95 112)(font "Arial" ))
+		(line (pt 16 16)(pt 168 16)(line_width 1))
+		(line (pt 168 16)(pt 168 112)(line_width 1))
+		(line (pt 168 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v
new file mode 100644
index 0000000..09482ce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %Shift register (RAM-based)%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altshift_taps 
+
+// ============================================================
+// File Name: Line_Buffer.v
+// Megafunction Name(s):
+// 			altshift_taps
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Line_Buffer (
+	clken,
+	clock,
+	shiftin,
+	shiftout,
+	taps0x,
+	taps1x);
+
+	input	  clken;
+	input	  clock;
+	input	[11:0]  shiftin;
+	output	[11:0]  shiftout;
+	output	[11:0]  taps0x;
+	output	[11:0]  taps1x;
+
+	wire [23:0] sub_wire0;
+	wire [11:0] sub_wire3;
+	wire [23:12] sub_wire1 = sub_wire0[23:12];
+	wire [11:0] sub_wire2 = sub_wire0[11:0];
+	wire [11:0] taps1x = sub_wire1[23:12];
+	wire [11:0] taps0x = sub_wire2[11:0];
+	wire [11:0] shiftout = sub_wire3[11:0];
+
+	altshift_taps	altshift_taps_component (
+				.clken (clken),
+				.clock (clock),
+				.shiftin (shiftin),
+				.taps (sub_wire0),
+				.shiftout (sub_wire3));
+	defparam
+		altshift_taps_component.lpm_type = "altshift_taps",
+		altshift_taps_component.number_of_taps = 2,
+		altshift_taps_component.tap_distance = 1280,
+		altshift_taps_component.width = 12;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
+// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
+// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
+// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
+// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
+// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
+// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
+// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
+// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v
new file mode 100644
index 0000000..16493c7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v
@@ -0,0 +1,128 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	RAW2RGB
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module RAW2RGB(	oRed,
+				oGreen,
+				oBlue,
+				oDVAL,
+				iX_Cont,
+				iY_Cont,
+				iDATA,
+				iDVAL,
+				iCLK,
+				iRST
+				);
+
+input	[10:0]	iX_Cont;
+input	[10:0]	iY_Cont;
+input	[11:0]	iDATA;
+input			iDVAL;
+input			iCLK;
+input			iRST;
+output	[11:0]	oRed;
+output	[11:0]	oGreen;
+output	[11:0]	oBlue;
+output			oDVAL;
+wire	[11:0]	mDATA_0;
+wire	[11:0]	mDATA_1;
+reg		[11:0]	mDATAd_0;
+reg		[11:0]	mDATAd_1;
+reg		[11:0]	mCCD_R;
+reg		[12:0]	mCCD_G;
+reg		[11:0]	mCCD_B;
+reg				mDVAL;
+
+assign	oRed	=	mCCD_R[11:0];
+assign	oGreen	=	mCCD_G[12:1];
+assign	oBlue	=	mCCD_B[11:0];
+assign	oDVAL	=	mDVAL;
+
+Line_Buffer 	u0	(	.clken(iDVAL),
+						.clock(iCLK),
+						.shiftin(iDATA),
+						.taps0x(mDATA_1),
+						.taps1x(mDATA_0)	);
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		mCCD_R	<=	0;
+		mCCD_G	<=	0;
+		mCCD_B	<=	0;
+		mDATAd_0<=	0;
+		mDATAd_1<=	0;
+		mDVAL	<=	0;
+	end
+	else
+	begin
+		mDATAd_0	<=	mDATA_0;
+		mDATAd_1	<=	mDATA_1;
+		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
+		if({iY_Cont[0],iX_Cont[0]}==2'b10)
+		begin
+			mCCD_R	<=	mDATA_0;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATAd_1;
+		end	
+		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
+		begin
+			mCCD_R	<=	mDATAd_0;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATA_1;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
+		begin
+			mCCD_R	<=	mDATA_1;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATAd_0;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
+		begin
+			mCCD_R	<=	mDATAd_1;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATA_0;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v
new file mode 100644
index 0000000..578a964
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v
@@ -0,0 +1,74 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Reset_Delay
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
+input		iCLK;
+input		iRST;
+output reg	oRST_0;
+output reg	oRST_1;
+output reg	oRST_2;
+
+reg	[31:0]	Cont;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Cont	<=	0;
+		oRST_0	<=	0;
+		oRST_1	<=	0;
+		oRST_2	<=	0;
+	end
+	else
+	begin
+		if(Cont!=32'h11FFFFF)
+		Cont	<=	Cont+1;
+		if(Cont>=32'h1FFFFF)
+		oRST_0	<=	1;
+		if(Cont>=32'h2FFFFF)
+		oRST_1	<=	1;
+		if(Cont>=32'h11FFFFF)
+		oRST_2	<=	1;
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v
new file mode 100644
index 0000000..2756db0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT	(	oSEG,iDIG	);
+input	[3:0]	iDIG;
+output	[6:0]	oSEG;
+reg		[6:0]	oSEG;
+
+always @(iDIG)
+begin
+		case(iDIG)
+		4'h1: oSEG = 7'b1111001;	// ---t----
+		4'h2: oSEG = 7'b0100100; 	// |	  |
+		4'h3: oSEG = 7'b0110000; 	// lt	 rt
+		4'h4: oSEG = 7'b0011001; 	// |	  |
+		4'h5: oSEG = 7'b0010010; 	// ---m----
+		4'h6: oSEG = 7'b0000010; 	// |	  |
+		4'h7: oSEG = 7'b1111000; 	// lb	 rb
+		4'h8: oSEG = 7'b0000000; 	// |	  |
+		4'h9: oSEG = 7'b0011000; 	// ---b----
+		4'ha: oSEG = 7'b0001000;
+		4'hb: oSEG = 7'b0000011;
+		4'hc: oSEG = 7'b1000110;
+		4'hd: oSEG = 7'b0100001;
+		4'he: oSEG = 7'b0000110;
+		4'hf: oSEG = 7'b0001110;
+		4'h0: oSEG = 7'b1000000;
+		endcase
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v
new file mode 100644
index 0000000..e84af4e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT_8
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input	[31:0]	iDIG;
+output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
+SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
+SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
+SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
+SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
+SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
+SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
+SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v
new file mode 100644
index 0000000..c9c3537
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v
@@ -0,0 +1,122 @@
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		H_Cont	<=	H_Cont+1;
+		else
+		H_Cont	<=	0;
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+		oVGA_H_SYNC	<=	0;
+		else
+		oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h
new file mode 100644
index 0000000..9d0fd32
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h
@@ -0,0 +1,16 @@
+//	Horizontal Parameter	( Pixel )
+parameter	H_SYNC_CYC	=	96;
+parameter	H_SYNC_BACK	=	48;
+parameter	H_SYNC_ACT	=	640;	
+parameter	H_SYNC_FRONT=	16;
+parameter	H_SYNC_TOTAL=	800;
+
+//	Virtical Parameter		( Line )
+parameter	V_SYNC_CYC	=	2;
+parameter	V_SYNC_BACK	=	33;
+parameter	V_SYNC_ACT	=	480;	
+parameter	V_SYNC_FRONT=	10;
+parameter	V_SYNC_TOTAL=	525;
+//	Start Offset
+parameter	X_START		=	H_SYNC_CYC+H_SYNC_BACK;
+parameter	Y_START		=	V_SYNC_CYC+V_SYNC_BACK;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf
new file mode 100644
index 0000000..a895305
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf
@@ -0,0 +1,81 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 240 168)
+	(text "sdram_pll" (rect 92 0 158 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 240 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 240 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 178 152 401 315)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "5/2" (rect 77 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "5/2" (rect 77 121 165 253)(font "Arial" ))
+		(text "-117.00" (rect 98 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(line (pt 0 0)(pt 241 0))
+		(line (pt 241 0)(pt 241 169))
+		(line (pt 0 169)(pt 241 169))
+		(line (pt 0 0)(pt 0 169))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 91)(pt 48 132))
+		(line (pt 69 91)(pt 69 132)(line_width 3))
+		(line (pt 95 91)(pt 95 132)(line_width 3))
+		(line (pt 129 91)(pt 129 132)(line_width 3))
+		(line (pt 163 91)(pt 163 132))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 151))
+		(line (pt 40 151)(pt 207 151))
+		(line (pt 40 48)(pt 40 151))
+		(line (pt 239 64)(pt 207 64))
+		(line (pt 239 80)(pt 207 80))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf
new file mode 100644
index 0000000..a4a0f2e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="sdram_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip
new file mode 100644
index 0000000..7440d58
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v
new file mode 100644
index 0000000..6b4189b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-2600",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.60000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2600"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak
new file mode 100644
index 0000000..7fd74a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg
new file mode 100644
index 0000000..a48389a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html
new file mode 100644
index 0000000..2d27f12
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for sdram_pll.v </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file sdram_pll.v </CENTER></h2>
+<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
+<CENTER><img src=sdram_pll_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat
new file mode 100644
index 0000000..c3a3f44
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat
@@ -0,0 +1,17 @@
+%QUARTUS_ROOTDIR%\\bin\\quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;DE1_D5M.sof"
+@ set SOPC_BUILDER_PATH_71=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_71%
+@ set SOPC_BUILDER_PATH_72=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_72%
+@ set SOPC_BUILDER_PATH_80=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_80%
+@ set SOPC_BUILDER_PATH_81=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_81%
+@ set SOPC_BUILDER_PATH_90=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_90%
+@ set SOPC_BUILDER_PATH_91=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_91%
+@ set SOPC_BUILDER_PATH_92=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_92%
+@ set SOPC_BUILDER_PATH_100=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_100%
+@ set SOPC_BUILDER_PATH_101=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_101%
+@ set SOPC_BUILDER_PATH_102=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_102%
+@ set SOPC_BUILDER_PATH_110=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_110%
+@ set SOPC_BUILDER_PATH_111=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_111%
+@ set SOPC_BUILDER_PATH_112=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_112%
+@ set SOPC_BUILDER_PATH_120=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_120%
+@ set SOPC_BUILDER_PATH_121=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_121%
+@ set SOPC_BUILDER_PATH_122=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_122%
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof
new file mode 100644
index 0000000..9832b19
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..9ca2d87
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt
@@ -0,0 +1,63 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=2
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=5
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=2
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=5
+CLK1_PHASE_SHIFT=-2600
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
+INTENDED_DEVICE_FAMILY="Cyclone III"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_UNUSED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_UNUSED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone III"
+CBX_AUTO_BLACKBOX=ALL
+inclk
+inclk
+clk
+clk
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt
new file mode 100644
index 0000000..1097973
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt
@@ -0,0 +1,28 @@
+
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:44:47>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:45:47>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:45:55>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt
new file mode 100644
index 0000000..584be9e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt
@@ -0,0 +1,130 @@
+Assembler report for DE0_D5M
+Tue Mar 01 17:41:22 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
+  6. Assembler Device Options: C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Mar 01 17:41:22 2016 ;
+; Revision Name         ; DE0_D5M                               ;
+; Top-level Entity Name ; TOP_DE0_CAMERA_MOUSE                  ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; On       ; Off           ;
+; Use configuration device                                                    ; On       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++----------------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                          ;
++----------------------------------------------------------------------------------------------------+
+; File Name                                                                                          ;
++----------------------------------------------------------------------------------------------------+
+; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof ;
+; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof ;
++----------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof ;
++----------------+-------------------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                                     ;
++----------------+-------------------------------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                                                ;
+; JTAG usercode  ; 0x002190A7                                                                                                  ;
+; Checksum       ; 0x002190A7                                                                                                  ;
++----------------+-------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof ;
++--------------------+---------------------------------------------------------------------------------------------------------+
+; Option             ; Setting                                                                                                 ;
++--------------------+---------------------------------------------------------------------------------------------------------+
+; Device             ; EPCS4                                                                                                   ;
+; JTAG usercode      ; 0x00000000                                                                                              ;
+; Checksum           ; 0x05B0F54D                                                                                              ;
+; Compression Ratio  ; 3                                                                                                       ;
++--------------------+---------------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 17:41:20 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 427 megabytes
+    Info: Processing ended: Tue Mar 01 17:41:22 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf
new file mode 100644
index 0000000..94a0cff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf
@@ -0,0 +1,253 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 512)
+	(text "DE0_D5M" (rect 5 0 49 12)(font "Arial" ))
+	(text "inst" (rect 8 480 20 492)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 49 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 36 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 47 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 220 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 267 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 224 59 267 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 267 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 267 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 177 123 267 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 66 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 201 139 267 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 200 155 267 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160)(line_width 1))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 199 171 267 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176)(line_width 1))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 71 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 196 187 267 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192)(line_width 1))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 73 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 194 203 267 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208)(line_width 1))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 204 219 267 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224)(line_width 1))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 62 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 205 235 267 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240)(line_width 1))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 61 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 206 251 267 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256)(line_width 1))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 57 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 210 267 267 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272)(line_width 1))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 208 283 267 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288)(line_width 1))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_HS" (rect 225 299 267 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304)(line_width 1))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_VS" (rect 224 315 267 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320)(line_width 1))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[9..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_R[9..0]" (rect 210 331 267 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[9..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "VGA_G[9..0]" (rect 211 347 267 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "VGA_B[9..0]" (rect 212 363 267 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 218 379 267 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384)(line_width 1))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "VGA_X[11..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_X[11..0]" (rect 210 395 267 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(output)
+		(text "VGA_Y[11..0]" (rect 0 0 59 12)(font "Arial" ))
+		(text "VGA_Y[11..0]" (rect 208 411 267 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(port
+		(pt 288 432)
+		(output)
+		(text "VGA_ACTIVE" (rect 0 0 68 12)(font "Arial" ))
+		(text "VGA_ACTIVE" (rect 199 427 267 439)(font "Arial" ))
+		(line (pt 288 432)(pt 272 432)(line_width 1))
+	)
+	(port
+		(pt 288 448)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 443 267 455)(font "Arial" ))
+		(line (pt 288 448)(pt 272 448)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 267 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 464)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 459 267 471)(font "Arial" ))
+		(line (pt 288 464)(pt 272 464)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 480)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf
new file mode 100644
index 0000000..f8e4340
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/") File("DE0_D5M.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done
new file mode 100644
index 0000000..5eba180
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done
@@ -0,0 +1 @@
+Tue Mar 01 17:42:15 2016
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt
new file mode 100644
index 0000000..897fbbf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt
@@ -0,0 +1,4095 @@
+Fitter report for DE0_D5M
+Tue Mar 01 17:41:19 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Non-Global High Fan-Out Signals
+ 27. Fitter RAM Summary
+ 28. Other Routing Usage Summary
+ 29. LAB Logic Elements
+ 30. LAB-wide Signals
+ 31. LAB Signals Sourced
+ 32. LAB Signals Sourced Out
+ 33. LAB Distinct Inputs
+ 34. I/O Rules Summary
+ 35. I/O Rules Details
+ 36. I/O Rules Matrix
+ 37. Fitter Device Options
+ 38. Operating Settings and Conditions
+ 39. Estimated Delay Added for Hold Timing Summary
+ 40. Estimated Delay Added for Hold Timing Details
+ 41. Fitter Messages
+ 42. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Mar 01 17:41:19 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                          ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                             ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 2,322 / 15,408 ( 15 % )                          ;
+;     Total combinational functions  ; 1,910 / 15,408 ( 12 % )                          ;
+;     Dedicated logic registers      ; 1,326 / 15,408 ( 9 % )                           ;
+; Total registers                    ; 1326                                             ;
+; Total pins                         ; 143 / 347 ( 41 % )                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 134,236 / 516,096 ( 26 % )                       ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                                   ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Use smart compilation                                                      ; On                                    ; Off                                   ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.43        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  14.3%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------+
+; I/O Assignment Warnings                   ;
++------------------+------------------------+
+; Pin Name         ; Reason                 ;
++------------------+------------------------+
+; DRAM_LDQM        ; Missing drive strength ;
+; DRAM_UDQM        ; Missing drive strength ;
+; DRAM_BA_1        ; Missing drive strength ;
+; DRAM_BA_0        ; Missing drive strength ;
+; DRAM_CAS_N       ; Missing drive strength ;
+; DRAM_CKE         ; Missing drive strength ;
+; DRAM_CS_N        ; Missing drive strength ;
+; DRAM_RAS_N       ; Missing drive strength ;
+; DRAM_WE_N        ; Missing drive strength ;
+; DRAM_CLK         ; Missing drive strength ;
+; VGA_CLK          ; Missing drive strength ;
+; VGA_HS           ; Missing drive strength ;
+; VGA_VS           ; Missing drive strength ;
+; DRAM_ADDR[11]    ; Missing drive strength ;
+; DRAM_ADDR[10]    ; Missing drive strength ;
+; DRAM_ADDR[9]     ; Missing drive strength ;
+; DRAM_ADDR[8]     ; Missing drive strength ;
+; DRAM_ADDR[7]     ; Missing drive strength ;
+; DRAM_ADDR[6]     ; Missing drive strength ;
+; DRAM_ADDR[5]     ; Missing drive strength ;
+; DRAM_ADDR[4]     ; Missing drive strength ;
+; DRAM_ADDR[3]     ; Missing drive strength ;
+; DRAM_ADDR[2]     ; Missing drive strength ;
+; DRAM_ADDR[1]     ; Missing drive strength ;
+; DRAM_ADDR[0]     ; Missing drive strength ;
+; GPIO_1_CLKOUT[1] ; Missing drive strength ;
+; GPIO_1_CLKOUT[0] ; Missing drive strength ;
+; HEX0[6]          ; Missing drive strength ;
+; HEX0[5]          ; Missing drive strength ;
+; HEX0[4]          ; Missing drive strength ;
+; HEX0[3]          ; Missing drive strength ;
+; HEX0[2]          ; Missing drive strength ;
+; HEX0[1]          ; Missing drive strength ;
+; HEX0[0]          ; Missing drive strength ;
+; HEX1[6]          ; Missing drive strength ;
+; HEX1[5]          ; Missing drive strength ;
+; HEX1[4]          ; Missing drive strength ;
+; HEX1[3]          ; Missing drive strength ;
+; HEX1[2]          ; Missing drive strength ;
+; HEX1[1]          ; Missing drive strength ;
+; HEX1[0]          ; Missing drive strength ;
+; HEX2[6]          ; Missing drive strength ;
+; HEX2[5]          ; Missing drive strength ;
+; HEX2[4]          ; Missing drive strength ;
+; HEX2[3]          ; Missing drive strength ;
+; HEX2[2]          ; Missing drive strength ;
+; HEX2[1]          ; Missing drive strength ;
+; HEX2[0]          ; Missing drive strength ;
+; HEX3[6]          ; Missing drive strength ;
+; HEX3[5]          ; Missing drive strength ;
+; HEX3[4]          ; Missing drive strength ;
+; HEX3[3]          ; Missing drive strength ;
+; HEX3[2]          ; Missing drive strength ;
+; HEX3[1]          ; Missing drive strength ;
+; HEX3[0]          ; Missing drive strength ;
+; LEDG[9]          ; Missing drive strength ;
+; LEDG[8]          ; Missing drive strength ;
+; LEDG[7]          ; Missing drive strength ;
+; LEDG[6]          ; Missing drive strength ;
+; LEDG[5]          ; Missing drive strength ;
+; LEDG[4]          ; Missing drive strength ;
+; LEDG[3]          ; Missing drive strength ;
+; LEDG[2]          ; Missing drive strength ;
+; LEDG[1]          ; Missing drive strength ;
+; LEDG[0]          ; Missing drive strength ;
+; VGA_B[3]         ; Missing drive strength ;
+; VGA_B[2]         ; Missing drive strength ;
+; VGA_B[1]         ; Missing drive strength ;
+; VGA_B[0]         ; Missing drive strength ;
+; VGA_G[3]         ; Missing drive strength ;
+; VGA_G[2]         ; Missing drive strength ;
+; VGA_G[1]         ; Missing drive strength ;
+; VGA_G[0]         ; Missing drive strength ;
+; VGA_R[3]         ; Missing drive strength ;
+; VGA_R[2]         ; Missing drive strength ;
+; VGA_R[1]         ; Missing drive strength ;
+; VGA_R[0]         ; Missing drive strength ;
+; DRAM_DQ[15]      ; Missing drive strength ;
+; DRAM_DQ[14]      ; Missing drive strength ;
+; DRAM_DQ[13]      ; Missing drive strength ;
+; DRAM_DQ[12]      ; Missing drive strength ;
+; DRAM_DQ[11]      ; Missing drive strength ;
+; DRAM_DQ[10]      ; Missing drive strength ;
+; DRAM_DQ[9]       ; Missing drive strength ;
+; DRAM_DQ[8]       ; Missing drive strength ;
+; DRAM_DQ[7]       ; Missing drive strength ;
+; DRAM_DQ[6]       ; Missing drive strength ;
+; DRAM_DQ[5]       ; Missing drive strength ;
+; DRAM_DQ[4]       ; Missing drive strength ;
+; DRAM_DQ[3]       ; Missing drive strength ;
+; DRAM_DQ[2]       ; Missing drive strength ;
+; DRAM_DQ[1]       ; Missing drive strength ;
+; DRAM_DQ[0]       ; Missing drive strength ;
+; GPIO_1[31]       ; Missing drive strength ;
+; GPIO_1[30]       ; Missing drive strength ;
+; GPIO_1[29]       ; Missing drive strength ;
+; GPIO_1[28]       ; Missing drive strength ;
+; GPIO_1[27]       ; Missing drive strength ;
+; GPIO_1[26]       ; Missing drive strength ;
+; GPIO_1[25]       ; Missing drive strength ;
+; GPIO_1[24]       ; Missing drive strength ;
+; GPIO_1[23]       ; Missing drive strength ;
+; GPIO_1[22]       ; Missing drive strength ;
+; GPIO_1[21]       ; Missing drive strength ;
+; GPIO_1[20]       ; Missing drive strength ;
+; GPIO_1[19]       ; Missing drive strength ;
+; GPIO_1[18]       ; Missing drive strength ;
+; GPIO_1[17]       ; Missing drive strength ;
+; GPIO_1[16]       ; Missing drive strength ;
+; GPIO_1[15]       ; Missing drive strength ;
+; GPIO_1[14]       ; Missing drive strength ;
+; GPIO_1[13]       ; Missing drive strength ;
+; GPIO_1[12]       ; Missing drive strength ;
+; GPIO_1[11]       ; Missing drive strength ;
+; GPIO_1[10]       ; Missing drive strength ;
+; GPIO_1[9]        ; Missing drive strength ;
+; GPIO_1[8]        ; Missing drive strength ;
+; GPIO_1[7]        ; Missing drive strength ;
+; GPIO_1[6]        ; Missing drive strength ;
+; GPIO_1[5]        ; Missing drive strength ;
+; GPIO_1[4]        ; Missing drive strength ;
+; GPIO_1[3]        ; Missing drive strength ;
+; GPIO_1[2]        ; Missing drive strength ;
+; GPIO_1[1]        ; Missing drive strength ;
+; GPIO_1[0]        ; Missing drive strength ;
+; PS2_DAT          ; Missing drive strength ;
+; PS2_CLK          ; Missing drive strength ;
++------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                          ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+; Name                ; Ignored Entity       ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+; Location            ;                      ;              ; CLOCK_50_2      ; PIN_B12       ; QSF Assignment ;
+; Location            ;                      ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location            ;                      ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_ADCDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_ADCLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_BCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_DACDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_DACLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; AUD_XCK         ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; BUTTON[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; BUTTON[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; BUTTON[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; CLOCK_50_2      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[32]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[33]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[34]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; GPIO_1[35]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX0_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; I2C_SCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; I2C_SDAT        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; KEY[3]          ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ;                      ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_DATA       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_FVAL       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_LVAL       ; ON            ; QSF Assignment ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 3768 ( 0.00 % )    ;
+;     -- Achieved     ; 0 / 3768 ( 0.00 % )    ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 3757    ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 11      ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin.
+
+
++--------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                            ;
++---------------------------------------------+----------------------------+
+; Resource                                    ; Usage                      ;
++---------------------------------------------+----------------------------+
+; Total logic elements                        ; 2,322 / 15,408 ( 15 % )    ;
+;     -- Combinational with no register       ; 996                        ;
+;     -- Register only                        ; 412                        ;
+;     -- Combinational with a register        ; 914                        ;
+;                                             ;                            ;
+; Logic element usage by number of LUT inputs ;                            ;
+;     -- 4 input functions                    ; 595                        ;
+;     -- 3 input functions                    ; 744                        ;
+;     -- <=2 input functions                  ; 571                        ;
+;     -- Register only                        ; 412                        ;
+;                                             ;                            ;
+; Logic elements by mode                      ;                            ;
+;     -- normal mode                          ; 1073                       ;
+;     -- arithmetic mode                      ; 837                        ;
+;                                             ;                            ;
+; Total registers*                            ; 1,326 / 17,068 ( 8 % )     ;
+;     -- Dedicated logic registers            ; 1,326 / 15,408 ( 9 % )     ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )          ;
+;                                             ;                            ;
+; Total LABs:  partially or completely used   ; 200 / 963 ( 21 % )         ;
+; Virtual pins                                ; 0                          ;
+; I/O pins                                    ; 143 / 347 ( 41 % )         ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )             ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )              ;
+;                                             ;                            ;
+; Global signals                              ; 11                         ;
+; M9Ks                                        ; 20 / 56 ( 36 % )           ;
+; Total block memory bits                     ; 134,236 / 516,096 ( 26 % ) ;
+; Total block memory implementation bits      ; 184,320 / 516,096 ( 36 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )            ;
+; PLLs                                        ; 1 / 4 ( 25 % )             ;
+; Global clocks                               ; 11 / 20 ( 55 % )           ;
+; JTAGs                                       ; 0 / 1 ( 0 % )              ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )              ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )              ;
+; Average interconnect usage (total/H/V)      ; 4% / 4% / 4%               ;
+; Peak interconnect usage (total/H/V)         ; 12% / 12% / 14%            ;
+; Maximum fan-out                             ; 512                        ;
+; Highest non-global fan-out                  ; 262                        ;
+; Total fan-out                               ; 10938                      ;
+; Average fan-out                             ; 2.80                       ;
++---------------------------------------------+----------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 2322 / 15408 ( 15 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 996                   ; 0                              ;
+;     -- Register only                        ; 412                   ; 0                              ;
+;     -- Combinational with a register        ; 914                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 595                   ; 0                              ;
+;     -- 3 input functions                    ; 744                   ; 0                              ;
+;     -- <=2 input functions                  ; 571                   ; 0                              ;
+;     -- Register only                        ; 412                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 1073                  ; 0                              ;
+;     -- arithmetic mode                      ; 837                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1326                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1326 / 15408 ( 9 % )  ; 0 / 15408 ( 0 % )              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 200 / 963 ( 21 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 143                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 134236                ; 0                              ;
+; Total RAM block bits                        ; 184320                ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 20 / 56 ( 35 % )      ; 0 / 56 ( 0 % )                 ;
+; Clock control block                         ; 9 / 24 ( 37 % )       ; 2 / 24 ( 8 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 563                   ; 1                              ;
+;     -- Registered Input Connections         ; 512                   ; 0                              ;
+;     -- Output Connections                   ; 51                    ; 513                            ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 11168                 ; 521                            ;
+;     -- Registered Connections               ; 4988                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 100                   ; 514                            ;
+;     -- hard_block:auto_generated_inst       ; 514                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 16                    ; 1                              ;
+;     -- Output Ports                         ; 77                    ; 2                              ;
+;     -- Bidir Ports                          ; 50                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                           ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name            ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLOCK_50        ; G21   ; 6        ; 41           ; 15           ; 0            ; 106                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[0] ; AB11  ; 3        ; 21           ; 0            ; 14           ; 229                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[1] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[0]          ; H2    ; 1        ; 0            ; 21           ; 7            ; 262                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[1]          ; G3    ; 1        ; 0            ; 23           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[2]          ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]           ; J6    ; 1        ; 0            ; 24           ; 0            ; 25                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]           ; H5    ; 1        ; 0            ; 27           ; 0            ; 6                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]           ; H6    ; 1        ; 0            ; 25           ; 21           ; 15                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]           ; G4    ; 1        ; 0            ; 23           ; 7            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]           ; G5    ; 1        ; 0            ; 27           ; 21           ; 22                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]           ; J7    ; 1        ; 0            ; 22           ; 14           ; 22                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]           ; H7    ; 1        ; 0            ; 25           ; 14           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]           ; E3    ; 1        ; 0            ; 26           ; 7            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]           ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]           ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name             ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DRAM_ADDR[0]     ; C4    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[10]    ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[11]    ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[1]     ; A3    ; 8        ; 3            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[2]     ; B3    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[3]     ; C3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[4]     ; A5    ; 8        ; 7            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[5]     ; C6    ; 8        ; 5            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[6]     ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[7]     ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[8]     ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[9]     ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_0        ; B5    ; 8        ; 7            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_1        ; A4    ; 8        ; 5            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CAS_N       ; G8    ; 8        ; 5            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CKE         ; E6    ; 8        ; 1            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CLK         ; E5    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CS_N        ; G7    ; 8        ; 1            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_LDQM        ; E7    ; 8        ; 3            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_RAS_N       ; F7    ; 8        ; 1            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_UDQM        ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_WE_N        ; D6    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[0] ; R16   ; 4        ; 37           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[1] ; T16   ; 4        ; 37           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[0]          ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[1]          ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[2]          ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[3]          ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[4]          ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[5]          ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[6]          ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[0]          ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[1]          ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[2]          ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[3]          ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[4]          ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[5]          ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[6]          ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[0]          ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[1]          ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[2]          ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[3]          ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[4]          ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[5]          ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[6]          ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[0]          ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[1]          ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[2]          ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[3]          ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[4]          ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[5]          ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[6]          ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]          ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]          ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]          ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]          ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]          ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]          ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]          ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]          ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]          ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]          ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[0]         ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]         ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]         ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]         ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK          ; AB13  ; 4        ; 23           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]         ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]         ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]         ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]         ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS           ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]         ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]         ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]         ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]         ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_VS           ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                               ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; DRAM_DQ[0]  ; D10   ; 8        ; 16           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[10] ; A9    ; 8        ; 16           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[11] ; C10   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[12] ; B10   ; 8        ; 16           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[13] ; A10   ; 8        ; 16           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[14] ; E10   ; 8        ; 16           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[15] ; F10   ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[1]  ; G10   ; 8        ; 9            ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[2]  ; H10   ; 8        ; 9            ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[3]  ; E9    ; 8        ; 11           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[4]  ; F9    ; 8        ; 7            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[5]  ; G9    ; 8        ; 9            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[6]  ; H9    ; 8        ; 7            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[7]  ; F8    ; 8        ; 5            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[8]  ; A8    ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[9]  ; B9    ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; GPIO_1[0]   ; AA20  ; 4        ; 37           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[10]  ; U15   ; 4        ; 39           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[11]  ; T15   ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[12]  ; W15   ; 4        ; 32           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[13]  ; V15   ; 4        ; 32           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[14]  ; AB9   ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[15]  ; AA9   ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[16]  ; AA7   ; 3        ; 11           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[17]  ; AB7   ; 3        ; 11           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[18]  ; T14   ; 4        ; 32           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[19]  ; R14   ; 4        ; 39           ; 0            ; 14           ; 4                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO               ; -                   ;
+; GPIO_1[1]   ; AB20  ; 4        ; 37           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[20]  ; U12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[21]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[22]  ; R11   ; 3        ; 3            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[23]  ; R12   ; 3        ; 5            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[24]  ; U10   ; 3        ; 14           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[25]  ; T10   ; 3        ; 14           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[26]  ; U9    ; 3        ; 9            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[27]  ; T9    ; 3        ; 1            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[28]  ; Y7    ; 3        ; 9            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[29]  ; U8    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[2]   ; AA19  ; 4        ; 35           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[30]  ; V6    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[31]  ; V7    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[3]   ; AB19  ; 4        ; 35           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[4]   ; AB18  ; 4        ; 32           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[5]   ; AA18  ; 4        ; 35           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[6]   ; AA17  ; 4        ; 28           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[7]   ; AB17  ; 4        ; 28           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[8]   ; Y17   ; 4        ; 35           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[9]   ; W17   ; 4        ; 35           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; PS2_CLK     ; P22   ; 5        ; 41           ; 11           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; ps2:inst6|ce~0 (inverted)                                          ; -                   ;
+; PS2_DAT     ; P21   ; 5        ; 41           ; 12           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; ps2:inst6|de~0 (inverted)                                          ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                       ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                       ; Use as regular IO        ; HEX3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                       ; Use as regular IO        ; HEX2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                       ; Use as regular IO        ; HEX2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                       ; Use as regular IO        ; HEX1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; HEX0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; HEX1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; HEX1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; HEX1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; HEX1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; HEX1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; HEX1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; HEX0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; HEX0[1]                 ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; DRAM_DQ[12]             ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; DRAM_DQ[10]             ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; DRAM_DQ[9]              ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; DRAM_DQ[8]              ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; DRAM_UDQM               ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO        ; DRAM_ADDR[11]           ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO        ; DRAM_ADDR[9]            ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T10n, PADD19                      ; Use as regular IO        ; DRAM_ADDR[7]            ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T10p, DATA15                      ; Use as regular IO        ; DRAM_ADDR[6]            ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                       ; Use as regular IO        ; DRAM_ADDR[8]            ; Dual Purpose Pin          ;
+; A5       ; DATA5                                    ; Use as regular IO        ; DRAM_ADDR[4]            ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T6p, DATA6                        ; Use as regular IO        ; DRAM_DQ[15]             ; Dual Purpose Pin          ;
+; C6       ; DATA7                                    ; Use as regular IO        ; DRAM_ADDR[5]            ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; DRAM_ADDR[10]           ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T4n, DATA9                        ; Use as regular IO        ; DRAM_DQ[7]              ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T3n, DATA10                       ; Use as regular IO        ; DRAM_ADDR[1]            ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T3p, DATA11                       ; Use as regular IO        ; DRAM_ADDR[2]            ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO        ; DRAM_ADDR[0]            ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 3.3V          ; --           ;
+; 3        ; 16 / 46 ( 35 % ) ; 3.3V          ; --           ;
+; 4        ; 21 / 41 ( 51 % ) ; 3.3V          ; --           ;
+; 5        ; 2 / 46 ( 4 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 28 / 47 ( 60 % ) ; 3.3V          ; --           ;
+; 8        ; 38 / 43 ( 88 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; DRAM_ADDR[1]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 350        ; 8        ; DRAM_BA_1                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 345        ; 8        ; DRAM_ADDR[4]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 336        ; 8        ; DRAM_ADDR[7]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; DRAM_ADDR[11]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 332        ; 8        ; DRAM_DQ[8]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; DRAM_DQ[10]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; DRAM_DQ[13]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; HEX1[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; HEX1[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; HEX1[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; HEX2[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; HEX2[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; HEX3[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; GPIO_1[16]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; GPIO_1[15]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GPIO_1_CLKIN[1]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; GPIO_1[6]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; GPIO_1[5]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 164        ; 4        ; GPIO_1[2]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 169        ; 4        ; GPIO_1[0]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; GPIO_1[17]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; GPIO_1[14]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GPIO_1_CLKIN[0]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; VGA_CLK                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; GPIO_1[7]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; GPIO_1[4]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 165        ; 4        ; GPIO_1[3]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 170        ; 4        ; GPIO_1[1]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; DRAM_ADDR[2]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 351        ; 8        ; DRAM_ADDR[10]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; DRAM_BA_0                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 337        ; 8        ; DRAM_ADDR[6]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; DRAM_ADDR[9]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 333        ; 8        ; DRAM_UDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; DRAM_DQ[9]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; DRAM_DQ[12]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; HEX1[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; HEX1[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; HEX2[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; HEX2[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; HEX3[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; HEX3[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; DRAM_ADDR[3]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 359        ; 8        ; DRAM_ADDR[0]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; DRAM_ADDR[5]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 340        ; 8        ; DRAM_ADDR[8]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; DRAM_DQ[11]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; HEX1[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; HEX3[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; DRAM_WE_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; DRAM_DQ[0]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; HEX2[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; HEX3[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; DRAM_CLK                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 362        ; 8        ; DRAM_CKE                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 357        ; 8        ; DRAM_LDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; DRAM_DQ[3]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; DRAM_DQ[14]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; HEX0[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; HEX1[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; HEX2[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; KEY[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; DRAM_RAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 352        ; 8        ; DRAM_DQ[7]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 347        ; 8        ; DRAM_DQ[4]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 348        ; 8        ; DRAM_DQ[15]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 318        ; 7        ; HEX0[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; HEX2[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; HEX3[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; KEY[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; DRAM_CS_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 353        ; 8        ; DRAM_CAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 342        ; 8        ; DRAM_DQ[5]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 341        ; 8        ; DRAM_DQ[1]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; HEX3[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; KEY[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; DRAM_DQ[6]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H10      ; 343        ; 8        ; DRAM_DQ[2]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; PS2_DAT                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P22      ; 210        ; 5        ; PS2_CLK                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; GPIO_1[22]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 98         ; 3        ; GPIO_1[23]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; GPIO_1[19]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; GPIO_1_CLKOUT[0]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; GPIO_1[27]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 121        ; 3        ; GPIO_1[25]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; GPIO_1[21]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; GPIO_1[18]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 161        ; 4        ; GPIO_1[11]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ; 171        ; 4        ; GPIO_1_CLKOUT[1]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; GPIO_1[29]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 112        ; 3        ; GPIO_1[26]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 122        ; 3        ; GPIO_1[24]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; GPIO_1[20]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; GPIO_1[10]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; GPIO_1[30]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 105        ; 3        ; GPIO_1[31]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; GPIO_1[13]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; GPIO_1[12]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; GPIO_1[9]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; GPIO_1[28]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; GPIO_1[8]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                       ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; Name                          ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; SDC pin name                  ; inst|u6|altpll_component|auto_generated|pll1                                      ;
+; PLL mode                      ; Normal                                                                            ;
+; Compensate clock              ; clock0                                                                            ;
+; Compensated input/output pins ; --                                                                                ;
+; Switchover type               ; --                                                                                ;
+; Input frequency 0             ; 50.0 MHz                                                                          ;
+; Input frequency 1             ; --                                                                                ;
+; Nominal PFD frequency         ; 25.0 MHz                                                                          ;
+; Nominal VCO frequency         ; 625.0 MHz                                                                         ;
+; VCO post scale K counter      ; 2                                                                                 ;
+; VCO frequency control         ; Auto                                                                              ;
+; VCO phase shift step          ; 200 ps                                                                            ;
+; VCO multiply                  ; --                                                                                ;
+; VCO divide                    ; --                                                                                ;
+; Freq min lock                 ; 24.0 MHz                                                                          ;
+; Freq max lock                 ; 52.02 MHz                                                                         ;
+; M VCO Tap                     ; 5                                                                                 ;
+; M Initial                     ; 2                                                                                 ;
+; M value                       ; 25                                                                                ;
+; N value                       ; 2                                                                                 ;
+; Charge pump current           ; setting 1                                                                         ;
+; Loop filter resistance        ; setting 24                                                                        ;
+; Loop filter capacitance       ; setting 0                                                                         ;
+; Bandwidth                     ; 450 kHz to 980 kHz                                                                ;
+; Bandwidth type                ; Medium                                                                            ;
+; Real time reconfigurable      ; Off                                                                               ;
+; Scan chain MIF file           ; --                                                                                ;
+; Preserve PLL counter order    ; Off                                                                               ;
+; PLL location                  ; PLL_2                                                                             ;
+; Inclk0 signal                 ; CLOCK_50                                                                          ;
+; Inclk1 signal                 ; --                                                                                ;
+; Inclk0 signal type            ; Dedicated Pin                                                                     ;
+; Inclk1 signal type            ; --                                                                                ;
++-------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                             ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                        ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0       ; 5    ; 2   ; 125.0 MHz        ; 0 (0 ps)        ; 9.00 (200 ps)    ; 50/50      ; C0      ; 5             ; 3/2 Odd    ; --            ; 2       ; 5       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1       ; 5    ; 2   ; 125.0 MHz        ; -117 (-2600 ps) ; 9.00 (200 ps)    ; 50/50      ; C1      ; 5             ; 3/2 Odd    ; --            ; 1       ; 0       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                               ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_DE0_CAMERA_MOUSE                                    ; 2322 (2)    ; 1326 (0)                  ; 0 (0)         ; 134236      ; 20   ; 0            ; 0       ; 0         ; 143  ; 0            ; 996 (2)      ; 412 (0)           ; 914 (0)          ; |TOP_DE0_CAMERA_MOUSE                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                        ; 1458 (15)   ; 1013 (15)                 ; 0 (0)         ; 62416       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 443 (0)      ; 295 (14)          ; 720 (1)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                                   ; 42 (42)     ; 33 (33)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (9)        ; 2 (2)             ; 31 (31)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                                ; 253 (174)   ; 132 (94)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 121 (80)     ; 15 (6)            ; 117 (89)         ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                             ; 79 (79)     ; 38 (38)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 9 (9)             ; 29 (29)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                       ; 93 (77)     ; 66 (55)                   ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 27 (22)      ; 9 (9)             ; 57 (46)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                                ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component|      ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|           ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                       ; 16 (13)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 11 (11)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|                    ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                                   ; 50 (50)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 35 (35)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |Sdram_Control_4Port:u7|                           ; 931 (237)   ; 704 (137)                 ; 0 (0)         ; 31744       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 227 (99)     ; 254 (22)          ; 450 (116)        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                         ; 142 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 26 (0)       ; 60 (0)            ; 56 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 142 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 26 (0)       ; 60 (0)            ; 56 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 142 (41)    ; 116 (30)                  ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 26 (11)      ; 60 (22)           ; 56 (4)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 15 (15)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 20 (0)            ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 20 (20)           ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 3 (3)             ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                         ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 50 (0)            ; 66 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 50 (0)            ; 66 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 139 (42)    ; 116 (30)                  ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (11)      ; 50 (18)           ; 66 (9)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 18 (18)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 15 (15)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 6 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 2 (2)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                        ; 131 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 131 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 131 (39)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (4)       ; 47 (20)           ; 69 (11)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 17 (17)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 6 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                        ; 140 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 56 (0)            ; 60 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 140 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 56 (0)            ; 60 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 140 (43)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (9)       ; 56 (23)           ; 60 (6)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (0)            ; 1 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 19 (19)           ; 1 (1)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (0)            ; 8 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 12 (12)           ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                              ; 63 (63)     ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 3 (3)             ; 45 (45)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|                    ; 80 (80)     ; 55 (55)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (25)      ; 16 (16)           ; 39 (39)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                                ; 81 (81)     ; 28 (28)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 44 (44)      ; 1 (1)             ; 36 (36)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
+;    |altshift_taps:fifo_inst2|                            ; 15 (0)      ; 10 (0)                    ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 10 (0)           ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2                                                                                                                                       ; work         ;
+;       |shift_taps_lpm:auto_generated|                    ; 15 (0)      ; 10 (0)                    ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 10 (0)           ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated                                                                                                         ; work         ;
+;          |altsyncram_vp81:altsyncram2|                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2                                                                             ; work         ;
+;          |cntr_1tf:cntr1|                                ; 15 (12)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 10 (10)          ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1                                                                                          ; work         ;
+;             |cmpr_ugc:cmpr4|                             ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4                                                                           ; work         ;
+;    |mean_vga:vga_blur_catapult_inst|                     ; 588 (0)     ; 192 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 396 (0)      ; 80 (0)            ; 112 (0)          ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst                                                                                                                                ; work         ;
+;       |mean_vga_core:mean_vga_core_inst|                 ; 588 (573)   ; 192 (192)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 396 (381)    ; 80 (80)           ; 112 (112)        ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst                                                                                               ; work         ;
+;          |lpm_mult:Mult0|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult1|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult2|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core                                                             ; work         ;
+;    |ps2:inst6|                                           ; 139 (111)   ; 99 (99)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (12)      ; 37 (37)           ; 62 (62)          ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6                                                                                                                                                      ; work         ;
+;       |SEG7_LUT:U1|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U2|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U3|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U4|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4                                                                                                                                          ; work         ;
+;    |vga_mouse_square:vga_mouse_catapult_inst|            ; 101 (0)     ; 12 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 89 (0)       ; 0 (0)             ; 12 (0)           ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst                                                                                                                       ; work         ;
+;       |vga_mouse_square_core:vga_mouse_square_core_inst| ; 101 (101)   ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 89 (89)      ; 0 (0)             ; 12 (12)          ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst                                                                      ; work         ;
+;    |vga_mux:inst10|                                      ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (0)       ; 0 (0)             ; 3 (0)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                                                                                                                                 ; work         ;
+;       |lpm_mux:LPM_MUX_component|                        ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (0)       ; 0 (0)             ; 3 (0)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component                                                                                                                       ; work         ;
+;          |mux_u7e:auto_generated|                        ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (21)      ; 0 (0)             ; 3 (3)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated                                                                                                ; work         ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                              ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name             ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; DRAM_LDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_UDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_1        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_0        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CKE         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CS_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_RAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_WE_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CLK         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_CLK          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[15]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[14]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[13]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[12]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[11]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[10]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[9]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[8]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[7]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[6]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[5]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[4]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[3]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[2]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[1]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[0]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[31]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[30]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[29]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[28]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[27]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[26]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[25]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[24]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[23]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[22]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[21]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[20]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[19]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[18]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[17]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[16]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[15]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[14]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[13]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[12]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[11]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[10]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[9]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[8]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[7]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[6]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[5]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[4]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[3]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[2]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[1]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[0]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; PS2_DAT          ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; PS2_CLK          ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[4]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[5]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; CLOCK_50         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[0]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[7]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[6]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[3]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[2]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[1]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[0]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; KEY[1]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[2]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                                             ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                                                          ; Pad To Core Index ; Setting ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; GPIO_1_CLKIN[1]                                                                                                                              ;                   ;         ;
+; SW[9]                                                                                                                                        ;                   ;         ;
+; SW[8]                                                                                                                                        ;                   ;         ;
+; DRAM_DQ[15]                                                                                                                                  ;                   ;         ;
+; DRAM_DQ[14]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[13]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder                                                                               ; 1                 ; 6       ;
+; DRAM_DQ[12]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[11]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[10]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]~feeder                                                                               ; 1                 ; 6       ;
+; DRAM_DQ[9]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[8]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[7]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                       ; 1                 ; 6       ;
+; DRAM_DQ[6]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]~feeder                                                                                ; 1                 ; 6       ;
+; DRAM_DQ[5]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                       ; 1                 ; 6       ;
+; DRAM_DQ[4]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[3]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]~feeder                                                                                ; 1                 ; 6       ;
+; DRAM_DQ[2]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2]~feeder                                                                                ; 1                 ; 6       ;
+; DRAM_DQ[1]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[0]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]~feeder                                                                                ; 0                 ; 6       ;
+; GPIO_1[31]                                                                                                                                   ;                   ;         ;
+; GPIO_1[30]                                                                                                                                   ;                   ;         ;
+; GPIO_1[29]                                                                                                                                   ;                   ;         ;
+; GPIO_1[28]                                                                                                                                   ;                   ;         ;
+; GPIO_1[27]                                                                                                                                   ;                   ;         ;
+; GPIO_1[26]                                                                                                                                   ;                   ;         ;
+; GPIO_1[25]                                                                                                                                   ;                   ;         ;
+; GPIO_1[24]                                                                                                                                   ;                   ;         ;
+; GPIO_1[23]                                                                                                                                   ;                   ;         ;
+; GPIO_1[22]                                                                                                                                   ;                   ;         ;
+; GPIO_1[21]                                                                                                                                   ;                   ;         ;
+; GPIO_1[20]                                                                                                                                   ;                   ;         ;
+; GPIO_1[19]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9                                                                               ; 1                 ; 6       ;
+; GPIO_1[18]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_FVAL~feeder                                                                                                         ; 1                 ; 6       ;
+; GPIO_1[17]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_LVAL                                                                                                                ; 1                 ; 6       ;
+; GPIO_1[16]                                                                                                                                   ;                   ;         ;
+; GPIO_1[15]                                                                                                                                   ;                   ;         ;
+; GPIO_1[14]                                                                                                                                   ;                   ;         ;
+; GPIO_1[13]                                                                                                                                   ;                   ;         ;
+; GPIO_1[12]                                                                                                                                   ;                   ;         ;
+; GPIO_1[11]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[0]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[10]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[1]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[9]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[2]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[8]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[3]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[7]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[4]                                                                                                             ; 0                 ; 6       ;
+; GPIO_1[6]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[5]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[5]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[6]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[4]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[7]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[3]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[8]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[2]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[9]                                                                                                             ; 0                 ; 6       ;
+; GPIO_1[1]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[10]~feeder                                                                                                     ; 0                 ; 6       ;
+; GPIO_1[0]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[11]~feeder                                                                                                     ; 1                 ; 6       ;
+; PS2_DAT                                                                                                                                      ;                   ;         ;
+;      - ps2:inst6|ps2_dat_syn0~0                                                                                                              ; 1                 ; 6       ;
+; PS2_CLK                                                                                                                                      ;                   ;         ;
+;      - ps2:inst6|ps2_clk_syn0~0                                                                                                              ; 1                 ; 6       ;
+; SW[4]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~9                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~9                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~9                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~9                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~1                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~5                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8                                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~9                                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~13                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~17                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~21                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22                                                    ; 0                 ; 6       ;
+; SW[5]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~11                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~11                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~11                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~11                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~3                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~7                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8                                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~11                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~15                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~19                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~23                                                    ; 0                 ; 6       ;
+; CLOCK_50                                                                                                                                     ;                   ;         ;
+; KEY[0]                                                                                                                                       ;                   ;         ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|midlatch                                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|riglatch                                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|leflatch                                                                                                                    ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[6]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[7]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[8]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[9]   ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[0]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[1]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[2]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[3]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[4]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[5]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[6]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[7]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[0]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[1]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[2]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[3]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[4]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[5]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[6]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[7]                                                                                                                  ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[9]                                 ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[8]                                 ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[7]                                 ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[6]                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[1]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[2]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[3]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[4]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[5]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[6]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[7]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[8]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[9]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[10]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[11]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[12]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[13]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[14]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[15]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[16]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[17]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[18]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[19]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[25]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[26]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[27]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[28]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[29]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[30]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[31]                                                                                                  ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[75]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[74]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[73]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[72]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[71]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[70]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[15]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[45]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[14]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[44]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[13]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[43]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[12]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[42]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[11]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[41]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[10]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[40]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[78]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[77]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[76]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[18]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[48]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[17]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[47]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[16]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[46]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[79]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[19]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[49]                                          ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[65]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[64]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[63]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[62]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[61]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[60]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[5]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[35]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[4]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[34]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[3]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[33]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[2]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[32]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[1]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[31]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[0]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[30]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[68]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[67]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[66]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[8]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[38]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[7]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[37]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[6]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[36]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[69]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[9]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[39]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[5]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[85]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[4]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[84]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[3]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[83]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[2]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[82]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[1]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[81]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[0]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[80]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[25]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[55]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[24]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[54]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[23]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[53]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[22]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[52]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[21]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[51]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[20]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[50]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[8]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[88]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[7]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[87]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[6]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[86]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[28]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[58]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[27]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[57]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[26]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[56]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[9]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[89]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[29]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[59]                                          ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                   ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.listen                                                                                                            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.pullclk                                                                                                           ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.trans                                                                                                             ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.pulldat                                                                                                           ; 1                 ; 6       ;
+; SW[7]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~15                                     ; 0                 ; 6       ;
+; SW[6]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~13                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~13                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~13                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~13                                     ; 0                 ; 6       ;
+; SW[3]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~7                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~7                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~7                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~7                                      ; 0                 ; 6       ;
+; SW[2]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~5                                      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~19                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~4                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~23                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~25                                                                                               ; 1                 ; 6       ;
+; SW[1]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~3                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~3                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~3                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~3                                      ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]~feeder                                                                          ; 0                 ; 6       ;
+; SW[0]                                                                                                                                        ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                    ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                     ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17                                                                                  ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~1                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~1                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~1                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~1                                      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~25                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~28                                                                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46                                                                                  ; 1                 ; 6       ;
+;      - SW[0]~_wirecell                                                                                                                       ; 1                 ; 6       ;
+; KEY[1]                                                                                                                                       ;                   ;         ;
+;      - ps2:inst6|Selector1~0                                                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                                                                                                  ; 0                 ; 6       ;
+; GPIO_1_CLKIN[0]                                                                                                                              ;                   ;         ;
+; KEY[2]                                                                                                                                       ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                                                                                                  ; 0                 ; 6       ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                  ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 5       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 102     ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~18                                                                                             ; LCCOMB_X12_Y14_N30 ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~19                                                                                             ; LCCOMB_X12_Y14_N28 ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[14]~3                                                                                              ; LCCOMB_X12_Y14_N22 ; 1       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                 ; FF_X12_Y14_N7      ; 7       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                     ; LCCOMB_X12_Y14_N16 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                             ; LCCOMB_X32_Y13_N0  ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]~1                                                                      ; LCCOMB_X31_Y12_N26 ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                           ; FF_X31_Y14_N9      ; 34      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                           ; FF_X31_Y14_N13     ; 36      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                         ; LCCOMB_X31_Y15_N24 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                            ; LCCOMB_X29_Y15_N8  ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                            ; LCCOMB_X31_Y15_N0  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; LCCOMB_X26_Y15_N4  ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                              ; LCCOMB_X26_Y15_N26 ; 43      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                 ; FF_X26_Y15_N11     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                          ; FF_X40_Y15_N3      ; 72      ; Clock                      ; yes    ; Global Clock         ; GCLK5            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                        ; LCCOMB_X31_Y15_N18 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31                                                                                 ; LCCOMB_X29_Y14_N2  ; 14      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X14_Y16_N26 ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]~36                                                                                                  ; LCCOMB_X11_Y17_N26 ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                 ; LCCOMB_X20_Y21_N30 ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; FF_X19_Y28_N3      ; 468     ; Async. clear               ; yes    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; FF_X20_Y21_N5      ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK16           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; FF_X21_Y21_N1      ; 106     ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0                                                                                          ; LCCOMB_X19_Y27_N6  ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                     ; LCCOMB_X19_Y28_N12 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                      ; LCCOMB_X19_Y28_N10 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X27_Y22_N30 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X29_Y22_N22 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y24_N4  ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X24_Y23_N22 ; 18      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X10_Y23_N2  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X10_Y24_N24 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X16_Y24_N12 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X14_Y25_N26 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                               ; FF_X10_Y27_N5      ; 16      ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1                                                                    ; LCCOMB_X16_Y27_N6  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                               ; FF_X10_Y26_N17     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                            ; LCCOMB_X10_Y26_N30 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                              ; LCCOMB_X11_Y27_N16 ; 16      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR~3                                                                                             ; LCCOMB_X19_Y27_N18 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~45                                                                                  ; LCCOMB_X19_Y28_N6  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46                                                                                  ; LCCOMB_X20_Y28_N0  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~45                                                                                  ; LCCOMB_X14_Y28_N0  ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46                                                                                  ; LCCOMB_X19_Y28_N26 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~45                                                                                  ; LCCOMB_X21_Y28_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46                                                                                  ; LCCOMB_X19_Y28_N16 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46                                                                                  ; LCCOMB_X19_Y26_N30 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47                                                                                  ; LCCOMB_X19_Y28_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                               ; LCCOMB_X22_Y21_N22 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                            ; LCCOMB_X20_Y19_N10 ; 13      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                            ; LCCOMB_X17_Y22_N26 ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|active                                                                                                 ; FF_X20_Y19_N9      ; 20      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                                                                  ; FF_X40_Y15_N31     ; 342     ; Clock                      ; yes    ; Global Clock         ; GCLK18           ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0]                                                   ; PLL_2              ; 512     ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                                                                       ; PIN_AB11           ; 229     ; Clock                      ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; KEY[0]                                                                                                                                ; PIN_H2             ; 262     ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cout_actual                                                     ; LCCOMB_X14_Y18_N2  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|Equal2~0                                                                                                                    ; LCCOMB_X31_Y19_N4  ; 8       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|Equal3~2                                                                                                                    ; LCCOMB_X31_Y23_N28 ; 6       ; Async. clear               ; yes    ; Global Clock         ; GCLK10           ; --                        ;
+; ps2:inst6|always5~1                                                                                                                   ; LCCOMB_X31_Y23_N24 ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|clk_div[8]                                                                                                                  ; FF_X40_Y15_N21     ; 38      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; ps2:inst6|clk_div[8]                                                                                                                  ; FF_X40_Y15_N21     ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|cur_state.listen                                                                                                            ; FF_X39_Y15_N7      ; 38      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|cur_state.trans                                                                                                             ; FF_X39_Y15_N23     ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|de~0                                                                                                                        ; LCCOMB_X39_Y15_N16 ; 1       ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|ps2_clk_in                                                                                                                  ; FF_X39_Y15_N11     ; 51      ; Clock                      ; yes    ; Global Clock         ; GCLK11           ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                     ;
++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                ; Location           ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                            ; PIN_G21            ; 102     ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                        ; FF_X40_Y15_N3      ; 72      ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                  ; FF_X19_Y28_N3      ; 468     ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                  ; FF_X20_Y21_N5      ; 55      ; 0                                    ; Global Clock         ; GCLK16           ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                ; FF_X40_Y15_N31     ; 342     ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2              ; 512     ; 186                                  ; Global Clock         ; GCLK8            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2              ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                     ; PIN_AB11           ; 229     ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
+; ps2:inst6|Equal3~2                                                                  ; LCCOMB_X31_Y23_N28 ; 6       ; 0                                    ; Global Clock         ; GCLK10           ; --                        ;
+; ps2:inst6|clk_div[8]                                                                ; FF_X40_Y15_N21     ; 38      ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; ps2:inst6|ps2_clk_in                                                                ; FF_X39_Y15_N11     ; 51      ; 0                                    ; Global Clock         ; GCLK11           ; --                        ;
++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                                                                      ; Fan-Out ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; KEY[0]~input                                                                                                                                                              ; 262     ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                                                        ; 106     ;
+; ~GND                                                                                                                                                                      ; 63      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                                                                  ; 43      ;
+; DE0_D5M:inst|VGA_Controller:u1|always0~1                                                                                                                                  ; 39      ;
+; ps2:inst6|cur_state.listen                                                                                                                                                ; 38      ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0                                                                                                                                   ; 38      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1]                                                                                                                               ; 37      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                                                               ; 36      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]                                                                                                                               ; 34      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                                                               ; 34      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3]                                                                                                                               ; 33      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0]                                                                                                                                     ; 33      ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                                                     ; 32      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; 31      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                                                     ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                                                                   ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0                                                                                                                                 ; 26      ;
+; SW[0]~input                                                                                                                                                               ; 25      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                                                            ; 24      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                                                                 ; 24      ;
+; SW[5]~input                                                                                                                                                               ; 22      ;
+; SW[4]~input                                                                                                                                                               ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                                            ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[9]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[8]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[7]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[6]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[5]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[4]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[3]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[2]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[1]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[0]                                                                                  ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada                                                                                                             ; 20      ;
+; DE0_D5M:inst|VGA_Controller:u1|active                                                                                                                                     ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]~0                                                                                                                           ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                                            ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 19      ;
+; ps2:inst6|always5~1                                                                                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]                                                                                                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0                                                                                                                              ; 18      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; 18      ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                                                         ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                                                                ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                                            ; 17      ;
+; ps2:inst6|cur_state.trans                                                                                                                                                 ; 17      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~19                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~18                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                                                                   ; 16      ;
+; SW[2]~input                                                                                                                                                               ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                                                                ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                                                         ; 15      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                                                                  ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31                                                                                                                     ; 14      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~1                                                                                                                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10]                             ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0]                              ; 14      ;
+; DE0_D5M:inst|rCCD_LVAL                                                                                                                                                    ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                                            ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                                                                ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                                                                   ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                                                                ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                                            ; 12      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1                                                                                                            ; 12      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual                                     ; 11      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6]                                                                                                            ; 11      ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]~36                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5                                                                                                            ; 10      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cout_actual                                                                                         ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~2                                                                                                                               ; 10      ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                                                        ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 10      ;
+; ps2:inst6|y_latch[7]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[6]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[5]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[4]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[3]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[2]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[1]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[0]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[7]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[6]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[5]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[4]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[3]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[2]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[1]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[0]                                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO                                                                                                                                    ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0                                                                                                                               ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; 9       ;
+; SW[0]~_wirecell                                                                                                                                                           ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; ps2:inst6|cur_state.pullclk                                                                                                                                               ; 8       ;
+; ps2:inst6|Equal2~0                                                                                                                                                        ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~3                                                                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|or_itm~0                                                                        ; 8       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[9]~18                                                                                 ; 8       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[9]~18                                                                              ; 8       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[9]~18                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9]                                                                                              ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[10]~20                                                                                ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[10]~20                                                                             ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[10]~20                                                                             ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7]                                                                                                                                  ; 7       ;
+; SW[1]~input                                                                                                                                                               ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7                                                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                                                                ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]~1                                                                                                          ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0                                                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2]                                                                                              ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15]                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14]                                                                                             ; 6       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[11]~22                                                                                ; 6       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[11]~22                                                                             ; 6       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[11]~22                                                                             ; 6       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6]                                                                                                                                  ; 6       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5]                                                                                                                                  ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[3]~2                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~5                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; ps2:inst6|delay[0]                                                                                                                                                        ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; ps2:inst6|byte_cnt[0]                                                                                                                                                     ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                               ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8]                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16                                                      ; 5       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                                                      ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_15_sdt[1]~2                                                                                       ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_19_sdt[1]~2                                                                                       ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_29_sdt[1]~2                                                                                       ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2]                                                                                                                                  ; 5       ;
+; SW[3]~input                                                                                                                                                               ; 4       ;
+; SW[6]~input                                                                                                                                                               ; 4       ;
+; SW[7]~input                                                                                                                                                               ; 4       ;
+; CLOCK_50~input                                                                                                                                                            ; 4       ;
+; GPIO_1[19]~input                                                                                                                                                          ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010                                                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; 4       ;
+; ps2:inst6|delay[1]                                                                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~8                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|oRequest                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1                                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20]                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13]                                                                                             ; 4       ;
+; ps2:inst6|byte_cnt[1]                                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                                                      ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add56~8                                                                                                  ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add11~10                                                                                                 ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_15_sdt[2]~4                                                                                       ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add15~8                                                                                                  ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add50~10                                                                                                 ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_19_sdt[2]~4                                                                                       ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add22~8                                                                                                  ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add37~10                                                                                                 ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_29_sdt[2]~4                                                                                       ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[56]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[57]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[58]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[37]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[38]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[39]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[46]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[47]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[48]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[49]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[59]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[36]                                                                                ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell                                                                                                    ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~0                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0                                                                                                ; 3       ;
+; ps2:inst6|delay[2]                                                                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR~3                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ; 3       ;
+; ps2:inst6|Equal3~0                                                                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2                                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0                                                                                                                              ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[6]~3                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[7]~2                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[8]~1                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[9]~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~0                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|rClk[0]                                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                                                                                                                        ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1]                             ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0]                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1]                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ; 3       ;
+; ps2:inst6|byte_cnt[2]                                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add57~14                                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add7~0                                                                                                   ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[12]~24                                                                                ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add52~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[8]~16                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[7]~14                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[6]~12                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[26]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[27]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[28]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[29]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[20]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[22]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[23]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[24]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[25]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[50]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[51]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[21]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[53]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[54]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[55]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[52]                                                                                ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add16~14                                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add46~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[12]~24                                                                             ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add51~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[8]~16                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[7]~14                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[6]~12                                                                              ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[1]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[2]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[3]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[4]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[5]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[0]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[31]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[32]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[33]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[34]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[30]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[7]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[8]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[9]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[19]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[35]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[6]                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add23~14                                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add33~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[12]~24                                                                             ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add38~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[8]~16                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[7]~14                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[6]~12                                                                              ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[11]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[12]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[16]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[17]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[18]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[10]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[14]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[15]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[40]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[41]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[42]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[13]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[44]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[45]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[43]                                                                                ; 3       ;
+; ps2:inst6|cnt[7]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[6]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[5]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[0]                                                                                                                                                          ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10]                                                                                                                                 ; 3       ;
+; KEY[1]~input                                                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~26                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~11                                                                                                                         ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~9                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000                                                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|mSTART                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|rCCD_FVAL                                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1                                                                                                                 ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~4                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~1                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0                                                                                                                              ; 2       ;
+; ps2:inst6|nex_state.pulldat~0                                                                                                                                             ; 2       ;
+; ps2:inst6|delay[3]                                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16                                                                                                                  ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDVAL                                                                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]                                                                                                                          ; 2       ;
+; ps2:inst6|Selector1~0                                                                                                                                                     ; 2       ;
+; ps2:inst6|Selector0~0                                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~9                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~4                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~3                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal7~0                                                                                                                              ; 2       ;
+; ps2:inst6|Equal3~1                                                                                                                                                        ; 2       ;
+; ps2:inst6|ct[0]                                                                                                                                                           ; 2       ;
+; ps2:inst6|ps2_dat_in                                                                                                                                                      ; 2       ;
+; ps2:inst6|clk_div[0]                                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|LessThan2~0                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~6                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~1                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N~0                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal4~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~14                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal2~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~1                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~5                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~0                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[59]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[29]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[89]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[56]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[26]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[57]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[27]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[58]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[28]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[86]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[87]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[88]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[50]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[20]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[51]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[21]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[52]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[22]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[53]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[23]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[54]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[24]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[55]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[25]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[80]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[81]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[82]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[83]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[84]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[85]                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[39]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[9]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[69]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[36]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[6]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[37]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[7]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[38]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[8]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[66]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[67]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[68]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[30]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[0]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[31]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[1]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[32]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[2]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[33]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[3]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[34]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[4]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[35]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[5]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[60]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[61]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[62]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[63]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[64]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[65]                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[49]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[19]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[79]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[46]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[16]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[47]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[17]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[48]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[18]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[76]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[77]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[78]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[40]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[10]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[41]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[11]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[42]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[12]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[43]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[13]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[44]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[14]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[45]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[15]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[70]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[71]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[72]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[73]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[74]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[75]                                                                              ; 2       ;
+; ps2:inst6|shift_reg[2]                                                                                                                                                    ; 2       ;
+; ps2:inst6|shift_reg[3]                                                                                                                                                    ; 2       ;
+; ps2:inst6|shift_reg[30]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[29]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[28]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[27]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[26]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[25]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[24]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[23]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[19]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[18]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[17]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[16]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[15]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[14]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[13]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[12]                                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~1                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM~0                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~1                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[6]~4                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[7]~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[8]~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[9]~1                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[6]~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[7]~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[8]~1                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[9]~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_V_SYNC                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[10]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[9]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[14]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[13]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[11]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[13]                            ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[12]                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[12]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[11]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[10]                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                                                                                                                              ; 2       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+
+; Name                                                                                                                                              ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size   ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278         ; 24           ; 1278         ; 24           ; yes                    ; no                      ; yes                    ; yes                     ; 30672  ; 1278                        ; 24                          ; 1278                        ; 24                          ; 30672               ; 6    ; None ; M9K_X13_Y12_N0, M9K_X13_Y15_N0, M9K_X13_Y13_N0, M9K_X13_Y14_N0, M9K_X13_Y16_N0, M9K_X13_Y17_N0                                                                 ; Old data             ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 15                          ; 512                         ; 15                          ; 7680                ; 1    ; None ; M9K_X25_Y22_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 15                          ; 512                         ; 15                          ; 7680                ; 1    ; None ; M9K_X25_Y23_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y23_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y24_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; Single Clock ; 798          ; 150          ; 798          ; 150          ; yes                    ; no                      ; yes                    ; yes                     ; 119700 ; 798                         ; 90                          ; 798                         ; 90                          ; 71820               ; 10   ; None ; M9K_X25_Y16_N0, M9K_X13_Y19_N0, M9K_X25_Y19_N0, M9K_X25_Y20_N0, M9K_X25_Y15_N0, M9K_X25_Y13_N0, M9K_X25_Y14_N0, M9K_X25_Y17_N0, M9K_X25_Y18_N0, M9K_X13_Y18_N0 ; Old data             ; Old data        ; Old data        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++------------------------------------------------------+
+; Other Routing Usage Summary                          ;
++-----------------------------+------------------------+
+; Other Routing Resource Type ; Usage                  ;
++-----------------------------+------------------------+
+; Block interconnects         ; 3,012 / 47,787 ( 6 % ) ;
+; C16 interconnects           ; 47 / 1,804 ( 3 % )     ;
+; C4 interconnects            ; 1,374 / 31,272 ( 4 % ) ;
+; Direct links                ; 618 / 47,787 ( 1 % )   ;
+; Global clocks               ; 11 / 20 ( 55 % )       ;
+; Local interconnects         ; 1,196 / 15,408 ( 8 % ) ;
+; R24 interconnects           ; 77 / 1,775 ( 4 % )     ;
+; R4 interconnects            ; 1,624 / 41,310 ( 4 % ) ;
++-----------------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 11.61) ; Number of LABs  (Total = 200) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 29                            ;
+; 2                                           ; 5                             ;
+; 3                                           ; 2                             ;
+; 4                                           ; 2                             ;
+; 5                                           ; 2                             ;
+; 6                                           ; 1                             ;
+; 7                                           ; 5                             ;
+; 8                                           ; 5                             ;
+; 9                                           ; 4                             ;
+; 10                                          ; 4                             ;
+; 11                                          ; 5                             ;
+; 12                                          ; 9                             ;
+; 13                                          ; 11                            ;
+; 14                                          ; 21                            ;
+; 15                                          ; 18                            ;
+; 16                                          ; 77                            ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.54) ; Number of LABs  (Total = 200) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 98                            ;
+; 1 Clock                            ; 133                           ;
+; 1 Clock enable                     ; 41                            ;
+; 1 Sync. clear                      ; 9                             ;
+; 1 Sync. load                       ; 3                             ;
+; 2 Async. clears                    ; 1                             ;
+; 2 Clock enables                    ; 4                             ;
+; 2 Clocks                           ; 20                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 17.07) ; Number of LABs  (Total = 200) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 17                            ;
+; 2                                            ; 13                            ;
+; 3                                            ; 2                             ;
+; 4                                            ; 5                             ;
+; 5                                            ; 1                             ;
+; 6                                            ; 3                             ;
+; 7                                            ; 6                             ;
+; 8                                            ; 0                             ;
+; 9                                            ; 3                             ;
+; 10                                           ; 4                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 13                            ;
+; 13                                           ; 9                             ;
+; 14                                           ; 4                             ;
+; 15                                           ; 6                             ;
+; 16                                           ; 6                             ;
+; 17                                           ; 4                             ;
+; 18                                           ; 7                             ;
+; 19                                           ; 4                             ;
+; 20                                           ; 5                             ;
+; 21                                           ; 4                             ;
+; 22                                           ; 7                             ;
+; 23                                           ; 7                             ;
+; 24                                           ; 7                             ;
+; 25                                           ; 6                             ;
+; 26                                           ; 6                             ;
+; 27                                           ; 5                             ;
+; 28                                           ; 9                             ;
+; 29                                           ; 11                            ;
+; 30                                           ; 6                             ;
+; 31                                           ; 9                             ;
+; 32                                           ; 8                             ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 8.11) ; Number of LABs  (Total = 200) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 0                             ;
+; 1                                               ; 34                            ;
+; 2                                               ; 12                            ;
+; 3                                               ; 8                             ;
+; 4                                               ; 11                            ;
+; 5                                               ; 12                            ;
+; 6                                               ; 9                             ;
+; 7                                               ; 12                            ;
+; 8                                               ; 11                            ;
+; 9                                               ; 6                             ;
+; 10                                              ; 11                            ;
+; 11                                              ; 10                            ;
+; 12                                              ; 13                            ;
+; 13                                              ; 19                            ;
+; 14                                              ; 8                             ;
+; 15                                              ; 7                             ;
+; 16                                              ; 8                             ;
+; 17                                              ; 3                             ;
+; 18                                              ; 0                             ;
+; 19                                              ; 2                             ;
+; 20                                              ; 1                             ;
+; 21                                              ; 0                             ;
+; 22                                              ; 0                             ;
+; 23                                              ; 0                             ;
+; 24                                              ; 0                             ;
+; 25                                              ; 0                             ;
+; 26                                              ; 2                             ;
+; 27                                              ; 1                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 12.40) ; Number of LABs  (Total = 200) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 2                             ;
+; 2                                            ; 18                            ;
+; 3                                            ; 17                            ;
+; 4                                            ; 15                            ;
+; 5                                            ; 8                             ;
+; 6                                            ; 6                             ;
+; 7                                            ; 8                             ;
+; 8                                            ; 8                             ;
+; 9                                            ; 7                             ;
+; 10                                           ; 3                             ;
+; 11                                           ; 16                            ;
+; 12                                           ; 9                             ;
+; 13                                           ; 5                             ;
+; 14                                           ; 3                             ;
+; 15                                           ; 7                             ;
+; 16                                           ; 2                             ;
+; 17                                           ; 3                             ;
+; 18                                           ; 2                             ;
+; 19                                           ; 3                             ;
+; 20                                           ; 4                             ;
+; 21                                           ; 6                             ;
+; 22                                           ; 11                            ;
+; 23                                           ; 10                            ;
+; 24                                           ; 8                             ;
+; 25                                           ; 6                             ;
+; 26                                           ; 3                             ;
+; 27                                           ; 1                             ;
+; 28                                           ; 4                             ;
+; 29                                           ; 0                             ;
+; 30                                           ; 0                             ;
+; 31                                           ; 1                             ;
+; 32                                           ; 1                             ;
+; 33                                           ; 1                             ;
+; 34                                           ; 0                             ;
+; 35                                           ; 0                             ;
+; 36                                           ; 0                             ;
+; 37                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 142          ; 0            ; 142          ; 0            ; 0            ; 143       ; 142          ; 0            ; 143       ; 143       ; 0            ; 0            ; 0            ; 0            ; 66           ; 0            ; 0            ; 66           ; 0            ; 0            ; 30           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 143       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 1            ; 143          ; 1            ; 143          ; 143          ; 0         ; 1            ; 143          ; 0         ; 0         ; 143          ; 143          ; 143          ; 143          ; 77           ; 143          ; 143          ; 77           ; 143          ; 143          ; 113          ; 143          ; 143          ; 143          ; 143          ; 143          ; 143          ; 0         ; 143          ; 143          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DRAM_LDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[1]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_UDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_1          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_0          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CKE           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CS_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_RAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_WE_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CLK           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[11]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[10]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[9]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[8]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[7]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[6]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[5]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[4]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[3]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[2]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[1]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[0]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[1]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[0]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[15]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[14]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[13]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[12]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[11]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[10]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[9]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[8]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[7]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[6]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[5]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[4]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[3]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[2]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[1]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[0]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[31]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[30]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[29]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[28]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[27]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[26]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[25]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[24]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[23]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[22]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[21]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[20]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[19]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[18]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[17]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[16]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[15]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[14]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[13]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[12]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[11]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[10]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[9]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[8]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[7]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_DAT            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_CLK            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[0]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                                                 ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; Source Clock(s)                                     ; Destination Clock(s)                                ; Delay Added in ns ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.3               ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                       ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                      ; Destination Register                                                                                                                                                     ; Delay Added in ns ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.110             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.108             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                     ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                               ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                               ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                     ; 0.011             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 0.011             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 0.011             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 0.010             ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 11 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 143 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 3 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1]
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]
+        Info (176357): Destination node ps2:inst6|clk_div[8]
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]~0
+        Info (176357): Destination node GPIO_1_CLKOUT[0]~output
+        Info (176357): Destination node VGA_CLK~output
+Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0
+Info (176353): Automatically promoted node ps2:inst6|ps2_clk_in 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node ps2:inst6|Equal2~0
+Info (176353): Automatically promoted node ps2:inst6|clk_div[8] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node ps2:inst6|clk_div[8]~22
+        Info (176357): Destination node ps2:inst6|ps2_clk_in
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~45
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node GPIO_1[14]~output
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1
+Info (176353): Automatically promoted node ps2:inst6|Equal3~2 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available
+Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning (15709): Ignored I/O standard assignments to the following nodes
+    Warning (15710): Ignored I/O standard assignment to node "AUD_ADCDAT"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_ADCLRCK"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_BCLK"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_DACDAT"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_DACLRCK"
+    Warning (15710): Ignored I/O standard assignment to node "AUD_XCK"
+    Warning (15710): Ignored I/O standard assignment to node "BUTTON[0]"
+    Warning (15710): Ignored I/O standard assignment to node "BUTTON[1]"
+    Warning (15710): Ignored I/O standard assignment to node "BUTTON[2]"
+    Warning (15710): Ignored I/O standard assignment to node "CLOCK_50_2"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_BYTE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_CE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ15_AM1"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_OE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RST_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RY"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[32]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[33]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[34]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO_1[35]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "I2C_SCLK"
+    Warning (15710): Ignored I/O standard assignment to node "I2C_SDAT"
+    Warning (15710): Ignored I/O standard assignment to node "KEY[3]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_BLON"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[0]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[1]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[2]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[3]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[4]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[5]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[6]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[7]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_EN"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RS"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RW"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBCLK"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBDAT"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CLK"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CMD"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT0"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT3"
+    Warning (15710): Ignored I/O standard assignment to node "SD_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "UART_CTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RXD"
+    Warning (15710): Ignored I/O standard assignment to node "UART_TXD"
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 4% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 2.03 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10
+    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10
+    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10
+    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10
+    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10
+    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9
+    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9
+    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8
+    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8
+    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9
+    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9
+    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9
+    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9
+    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10
+    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10
+    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10
+    Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7
+    Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6
+    Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8
+    Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7
+    Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9
+    Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9
+    Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10
+    Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10
+    Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12
+    Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11
+    Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12
+    Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12
+    Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14
+    Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14
+    Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7
+    Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7
+    Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9
+    Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9
+    Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15
+    Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15
+    Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15
+    Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15
+    Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17
+    Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17
+    Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17
+    Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17
+    Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18
+    Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18
+    Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19
+    Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19
+    Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20
+    Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20
+    Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21
+    Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11
+    Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1
+Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin GPIO_1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[20] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[15] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[14] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 149 warnings
+    Info: Peak virtual memory: 1149 megabytes
+    Info: Processing ended: Tue Mar 01 17:41:20 2016
+    Info: Elapsed time: 00:00:15
+    Info: Total CPU time (on all processors): 00:00:17
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg.
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary
new file mode 100644
index 0000000..b512015
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Mar 01 17:41:19 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_DE0_CAMERA_MOUSE
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 2,322 / 15,408 ( 15 % )
+    Total combinational functions : 1,910 / 15,408 ( 12 % )
+    Dedicated logic registers : 1,326 / 15,408 ( 9 % )
+Total registers : 1326
+Total pins : 143 / 347 ( 41 % )
+Total virtual pins : 0
+Total memory bits : 134,236 / 516,096 ( 26 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt
new file mode 100644
index 0000000..b7ef44f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt
@@ -0,0 +1,130 @@
+Flow report for DE0_D5M
+Tue Mar 01 17:41:26 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Mar 01 17:41:22 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                          ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                             ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 2,322 / 15,408 ( 15 % )                          ;
+;     Total combinational functions  ; 1,910 / 15,408 ( 12 % )                          ;
+;     Dedicated logic registers      ; 1,326 / 15,408 ( 9 % )                           ;
+; Total registers                    ; 1326                                             ;
+; Total pins                         ; 143 / 347 ( 41 % )                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 134,236 / 516,096 ( 26 % )                       ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                                   ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/01/2016 17:40:57 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; DE0_D5M             ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name          ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+; COMPILER_SIGNATURE_ID               ; 260248564268246.145685405708876       ; --            ; --                   ; --         ;
+; IP_TOOL_NAME                        ; LPM_MUX                               ; --            ; --                   ; --         ;
+; IP_TOOL_VERSION                     ; 13.1                                  ; --            ; --                   ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --                   ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --                   ; --         ;
+; MISC_FILE                           ; vga_mux.bsf                           ; --            ; --                   ; --         ;
+; MISC_FILE                           ; vga_mux.cmp                           ; --            ; --                   ; --         ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --                   ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --                   ; --         ;
+; SMART_RECOMPILE                     ; On                                    ; Off           ; --                   ; --         ;
+; TOP_LEVEL_ENTITY                    ; TOP_DE0_CAMERA_MOUSE                  ; DE0_D5M       ; --                   ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                                   ; --            ; --                   ; eda_palace ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:07     ; 1.0                     ; 558 MB              ; 00:00:07                           ;
+; Fitter                    ; 00:00:14     ; 1.4                     ; 1149 MB             ; 00:00:17                           ;
+; Assembler                 ; 00:00:02     ; 1.0                     ; 427 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 525 MB              ; 00:00:03                           ;
+; Total                     ; 00:00:26     ; --                      ; --                  ; 00:00:28                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_sta DE0_D5M -c DE0_D5M
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi
new file mode 100644
index 0000000..28e919f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="721c6f50753b6e030ba6"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="DE0_D5M.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt
new file mode 100644
index 0000000..43893f3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt
@@ -0,0 +1,3023 @@
+Analysis & Synthesis report for DE0_D5M
+Tue Mar 01 17:41:04 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state
+ 11. State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 17. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+ 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 69. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 70. Source assignments for altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2
+ 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1
+ 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3
+ 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+ 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+ 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7
+ 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+ 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+ 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+ 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 82. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 83. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8
+ 84. Parameter Settings for User Entity Instance: ps2:inst6
+ 85. Parameter Settings for User Entity Instance: vga_mux:inst10|LPM_MUX:LPM_MUX_component
+ 86. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire
+ 87. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire
+ 88. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire
+ 89. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire
+ 90. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg
+ 91. Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire
+ 92. Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+ 93. Parameter Settings for User Entity Instance: altshift_taps:fifo_inst2
+ 94. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1
+ 95. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0
+ 96. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2
+ 97. altshift_taps Parameter Settings by Entity Instance
+ 98. altpll Parameter Settings by Entity Instance
+ 99. dcfifo Parameter Settings by Entity Instance
+100. lpm_mult Parameter Settings by Entity Instance
+101. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"
+102. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"
+103. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"
+104. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"
+105. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+106. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+107. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+108. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"
+109. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5"
+110. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+111. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"
+112. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"
+113. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"
+114. Elapsed Time Per Partition
+115. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Mar 01 17:41:04 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                          ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                             ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 2,505                                            ;
+;     Total combinational functions  ; 1,910                                            ;
+;     Dedicated logic registers      ; 1,326                                            ;
+; Total registers                    ; 1326                                             ;
+; Total pins                         ; 143                                              ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 134,236                                          ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 1                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                          ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+; Option                                                                     ; Setting              ; Default Value      ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6         ;                    ;
+; Top-level entity name                                                      ; TOP_DE0_CAMERA_MOUSE ; DE0_D5M            ;
+; Family name                                                                ; Cyclone III          ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; On                   ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                   ; On                 ;
+; Enable compact report table                                                ; Off                  ; Off                ;
+; Restructure Multiplexers                                                   ; Auto                 ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                  ; Off                ;
+; Preserve fewer node names                                                  ; On                   ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                  ; Off                ;
+; Verilog Version                                                            ; Verilog_2001         ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993            ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto                 ; Auto               ;
+; Safe State Machine                                                         ; Off                  ; Off                ;
+; Extract Verilog State Machines                                             ; On                   ; On                 ;
+; Extract VHDL State Machines                                                ; On                   ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                  ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000                 ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                  ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                   ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                   ; On                 ;
+; Parallel Synthesis                                                         ; On                   ; On                 ;
+; DSP Block Balancing                                                        ; Auto                 ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                   ; On                 ;
+; Power-Up Don't Care                                                        ; On                   ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                  ; Off                ;
+; Remove Duplicate Registers                                                 ; On                   ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                  ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                  ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                  ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                  ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                  ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                   ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                  ; Off                ;
+; Optimization Technique                                                     ; Balanced             ; Balanced           ;
+; Carry Chain Length                                                         ; 70                   ; 70                 ;
+; Auto Carry Chains                                                          ; On                   ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                   ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                  ; Off                ;
+; Auto ROM Replacement                                                       ; On                   ; On                 ;
+; Auto RAM Replacement                                                       ; On                   ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                   ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto                 ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto                 ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                   ; On                 ;
+; Strict RAM Replacement                                                     ; Off                  ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                   ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                  ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                   ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                  ; Off                ;
+; Auto Resource Sharing                                                      ; Off                  ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                  ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                  ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                  ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                   ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                  ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                   ; On                 ;
+; Report Parameter Settings                                                  ; On                   ; On                 ;
+; Report Source Assignments                                                  ; On                   ; On                 ;
+; Report Connectivity Checks                                                 ; On                   ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                  ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                    ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation   ; Normal compilation ;
+; HDL message level                                                          ; Level2               ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                  ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000                 ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                 ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                  ; 100                ;
+; Clock MUX Protection                                                       ; On                   ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                  ; Off                ;
+; Block Design Naming                                                        ; Auto                 ; Auto               ;
+; SDC constraint protection                                                  ; Off                  ; Off                ;
+; Synthesis Effort                                                           ; Auto                 ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                   ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                  ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium               ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto                 ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                   ; On                 ;
+; Synthesis Seed                                                             ; 1                    ; 1                  ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                                                        ;
++-------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path          ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                                                     ; Library ;
++-------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------+
+; catapult_ip/blur3x3/rtl.v                 ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v                 ;         ;
+; V/ps2.v                                   ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v                                   ;         ;
+; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User Unspecified File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h        ;         ;
+; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v             ;         ;
+; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v   ;         ;
+; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v       ;         ;
+; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v ;         ;
+; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Wizard-Generated File         ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v          ;         ;
+; V/VGA_Param.h                             ; yes             ; User Unspecified File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h                             ;         ;
+; V/CCD_Capture.v                           ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v                           ;         ;
+; V/I2C_CCD_Config.v                        ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v                        ;         ;
+; V/I2C_Controller.v                        ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v                        ;         ;
+; V/Line_Buffer.v                           ; yes             ; User Wizard-Generated File         ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v                           ;         ;
+; V/RAW2RGB.v                               ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v                               ;         ;
+; V/Reset_Delay.v                           ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v                           ;         ;
+; V/sdram_pll.v                             ; yes             ; User Wizard-Generated File         ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v                             ;         ;
+; V/SEG7_LUT.v                              ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v                              ;         ;
+; V/SEG7_LUT_8.v                            ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v                            ;         ;
+; V/VGA_Controller.v                        ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v                        ;         ;
+; DE0_D5M.v                                 ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v                                 ;         ;
+; V/TOP_DE0_CAMERA_MOUSE.bdf                ; yes             ; User Block Diagram/Schematic File  ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf                ;         ;
+; vga_mux.vhd                               ; yes             ; User Wizard-Generated File         ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd                               ;         ;
+; catapult_ip/mouse/rtl_mgc_ioport.v        ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v        ;         ;
+; catapult_ip/mouse/rtl.v                   ; yes             ; User Verilog HDL File              ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v                   ;         ;
+; altshift_taps.tdf                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf                                                              ;         ;
+; altdpram.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc                                                                   ;         ;
+; lpm_counter.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc                                                                ;         ;
+; lpm_compare.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc                                                                ;         ;
+; lpm_constant.inc                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc                                                               ;         ;
+; db/shift_taps_rnn.tdf                     ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf                     ;         ;
+; db/altsyncram_lp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf                    ;         ;
+; db/cntr_cuf.tdf                           ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf                           ;         ;
+; db/cmpr_vgc.tdf                           ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf                           ;         ;
+; altpll.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf                                                                     ;         ;
+; aglobal130.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc                                                                 ;         ;
+; stratix_pll.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc                                                                ;         ;
+; stratixii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc                                                              ;         ;
+; cycloneii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc                                                              ;         ;
+; db/altpll_9ee2.tdf                        ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf                        ;         ;
+; dcfifo.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf                                                                     ;         ;
+; lpm_add_sub.inc                           ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc                                                                ;         ;
+; a_graycounter.inc                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_graycounter.inc                                                              ;         ;
+; a_fefifo.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fefifo.inc                                                                   ;         ;
+; a_gray2bin.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_gray2bin.inc                                                                 ;         ;
+; dffpipe.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffpipe.inc                                                                    ;         ;
+; alt_sync_fifo.inc                         ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_sync_fifo.inc                                                              ;         ;
+; altsyncram_fifo.inc                       ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram_fifo.inc                                                            ;         ;
+; db/dcfifo_v5o1.tdf                        ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf                        ;         ;
+; db/a_gray2bin_tgb.tdf                     ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf                     ;         ;
+; db/a_graycounter_s57.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf                  ;         ;
+; db/a_graycounter_ojc.tdf                  ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf                  ;         ;
+; db/altsyncram_de51.tdf                    ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf                    ;         ;
+; db/dffpipe_oe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf                        ;         ;
+; db/alt_synch_pipe_qld.tdf                 ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf                 ;         ;
+; db/dffpipe_pe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf                        ;         ;
+; db/alt_synch_pipe_rld.tdf                 ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf                 ;         ;
+; db/dffpipe_qe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf                        ;         ;
+; db/cmpr_e66.tdf                           ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf                           ;         ;
+; lpm_mux.tdf                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf                                                                    ;         ;
+; muxlut.inc                                ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muxlut.inc                                                                     ;         ;
+; bypassff.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc                                                                   ;         ;
+; altshift.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc                                                                   ;         ;
+; db/mux_u7e.tdf                            ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf                            ;         ;
+; db/shift_taps_lpm.tdf                     ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf                     ;         ;
+; db/altsyncram_vp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf                    ;         ;
+; db/cntr_1tf.tdf                           ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf                           ;         ;
+; db/cmpr_ugc.tdf                           ; yes             ; Auto-Generated Megafunction        ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf                           ;         ;
+; lpm_mult.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf                                                                   ;         ;
+; multcore.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.inc                                                                   ;         ;
+; multcore.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf                                                                   ;         ;
+; csa_add.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/csa_add.inc                                                                    ;         ;
+; mpar_add.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.inc                                                                   ;         ;
+; muleabz.inc                               ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/muleabz.inc                                                                    ;         ;
+; mul_lfrg.inc                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_lfrg.inc                                                                   ;         ;
+; mul_boothc.inc                            ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mul_boothc.inc                                                                 ;         ;
+; alt_ded_mult.inc                          ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult.inc                                                               ;         ;
+; alt_ded_mult_y.inc                        ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_ded_mult_y.inc                                                             ;         ;
+; mpar_add.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf                                                                   ;         ;
+; altshift.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf                                                                   ;         ;
++-------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                       ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                               ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 2,505                                                                               ;
+;                                             ;                                                                                     ;
+; Total combinational functions               ; 1910                                                                                ;
+; Logic element usage by number of LUT inputs ;                                                                                     ;
+;     -- 4 input functions                    ; 595                                                                                 ;
+;     -- 3 input functions                    ; 744                                                                                 ;
+;     -- <=2 input functions                  ; 571                                                                                 ;
+;                                             ;                                                                                     ;
+; Logic elements by mode                      ;                                                                                     ;
+;     -- normal mode                          ; 1073                                                                                ;
+;     -- arithmetic mode                      ; 837                                                                                 ;
+;                                             ;                                                                                     ;
+; Total registers                             ; 1326                                                                                ;
+;     -- Dedicated logic registers            ; 1326                                                                                ;
+;     -- I/O registers                        ; 0                                                                                   ;
+;                                             ;                                                                                     ;
+; I/O pins                                    ; 143                                                                                 ;
+; Total memory bits                           ; 134236                                                                              ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                   ;
+; Total PLLs                                  ; 1                                                                                   ;
+;     -- PLLs                                 ; 1                                                                                   ;
+;                                             ;                                                                                     ;
+; Maximum fan-out node                        ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ;
+; Maximum fan-out                             ; 572                                                                                 ;
+; Total fan-out                               ; 13223                                                                               ;
+; Average fan-out                             ; 3.53                                                                                ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                        ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                               ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_DE0_CAMERA_MOUSE                                    ; 1910 (2)          ; 1326 (0)     ; 134236      ; 0            ; 0       ; 0         ; 143  ; 0            ; |TOP_DE0_CAMERA_MOUSE                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                        ; 1163 (1)          ; 1013 (15)    ; 62416       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                                   ; 40 (40)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                                ; 238 (169)         ; 132 (94)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                             ; 69 (69)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                       ; 84 (68)           ; 66 (55)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                                ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|          ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                       ; 16 (13)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|                    ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                                   ; 50 (50)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |Sdram_Control_4Port:u7|                           ; 670 (214)         ; 704 (137)    ; 31744       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                         ; 82 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 82 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 82 (15)           ; 116 (30)     ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                         ; 83 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 83 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 83 (15)           ; 116 (30)     ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                        ; 83 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 83 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 83 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                        ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                              ; 60 (60)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|                    ; 64 (64)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                                ; 80 (80)           ; 28 (28)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
+;    |altshift_taps:fifo_inst2|                            ; 15 (0)            ; 10 (0)       ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2                                                                                                                                       ; work         ;
+;       |shift_taps_lpm:auto_generated|                    ; 15 (0)            ; 10 (0)       ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated                                                                                                         ; work         ;
+;          |altsyncram_vp81:altsyncram2|                   ; 0 (0)             ; 0 (0)        ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2                                                                             ; work         ;
+;          |cntr_1tf:cntr1|                                ; 15 (12)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1                                                                                          ; work         ;
+;             |cmpr_ugc:cmpr4|                             ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4                                                                           ; work         ;
+;    |mean_vga:vga_blur_catapult_inst|                     ; 507 (0)           ; 192 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst                                                                                                                                ; work         ;
+;       |mean_vga_core:mean_vga_core_inst|                 ; 507 (492)         ; 192 (192)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst                                                                                               ; work         ;
+;          |lpm_mult:Mult0|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult1|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult2|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core                                                             ; work         ;
+;    |ps2:inst6|                                           ; 102 (74)          ; 99 (99)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6                                                                                                                                                      ; work         ;
+;       |SEG7_LUT:U1|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U2|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U3|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U4|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4                                                                                                                                          ; work         ;
+;    |vga_mouse_square:vga_mouse_catapult_inst|            ; 97 (0)            ; 12 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst                                                                                                                       ; work         ;
+;       |vga_mouse_square_core:vga_mouse_square_core_inst| ; 97 (97)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst                                                                      ; work         ;
+;    |vga_mux:inst10|                                      ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                                                                                                                                 ; work         ;
+;       |lpm_mux:LPM_MUX_component|                        ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component                                                                                                                       ; work         ;
+;          |mux_u7e:auto_generated|                        ; 24 (24)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated                                                                                                ; work         ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+; Name                                                                                                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; 798          ; 150          ; 798          ; 150          ; 119700 ; None ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                                    ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+
+; Vendor ; IP Core Name               ; Version ; Release Date ; License Type ; Entity Instance                                                                  ; IP Include File                                                                                                         ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+
+; Altera ; Shift register (RAM-based) ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                     ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v                  ;
+; Altera ; ALTPLL                     ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                  ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v                    ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1  ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2  ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; LPM_MUX                    ; 13.1    ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                             ; C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd                      ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------------+
+; State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state                                      ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+; Name              ; cur_state.trans ; cur_state.pulldat ; cur_state.pullclk ; cur_state.listen ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+; cur_state.listen  ; 0               ; 0                 ; 0                 ; 0                ;
+; cur_state.pullclk ; 0               ; 0                 ; 1                 ; 1                ;
+; cur_state.pulldat ; 0               ; 1                 ; 0                 ; 1                ;
+; cur_state.trans   ; 1               ; 0                 ; 0                 ; 1                ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ;
++----------------+----------------+----------------+-----------------------------+
+; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001              ;
++----------------+----------------+----------------+-----------------------------+
+; mSetup_ST.0000 ; 0              ; 0              ; 0                           ;
+; mSetup_ST.0001 ; 1              ; 0              ; 1                           ;
+; mSetup_ST.0010 ; 1              ; 1              ; 0                           ;
++----------------+----------------+----------------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; Register name                                                                                                                               ; Reason for Removal                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[15]                                                                                            ; Lost fanout                                                                         ;
+; ps2:inst6|dout_reg[9]                                                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE                                                                                    ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                 ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                           ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                          ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6]                                                                                             ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                            ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                  ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2]                                                                                         ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                                                                                              ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|rClk[1]                                                                                                                        ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                                                                                              ; Stuck at VCC due to stuck port data_in                                              ;
+; ps2:inst6|cur_state~4                                                                                                                       ; Lost fanout                                                                         ;
+; ps2:inst6|cur_state~5                                                                                                                       ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9                                                                                                  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10                                                                                                 ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[1..15]                                                                                                   ; Lost fanout                                                                         ;
+; Total Number of Removed Registers = 143                                                                                                     ;                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                     ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register                                   ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7],                          ;
+;                                                          ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7],                            ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                           ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1326  ;
+; Number of registers using Synchronous Clear  ; 131   ;
+; Number of registers using Synchronous Load   ; 91    ;
+; Number of registers using Asynchronous Clear ; 932   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 430   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                   ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                    ; Fan out ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                   ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                       ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                       ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                       ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                       ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                       ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; Total number of inverted registers = 30                                                                                                              ;         ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                              ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[2]              ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9] ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]   ;
+; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]                                       ;
+; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[2]                                       ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                      ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                  ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[14]                                  ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                       ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]        ;
+; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]                           ;
+; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[3]                             ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                              ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                          ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                 ;
+; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                               ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                       ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2 ;
++---------------------------------+--------------------+------+---------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                          ;
++---------------------------------+--------------------+------+---------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                           ;
++---------------------------------+--------------------+------+---------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ;
++----------------+-------+----------------------------------------------------+
+; Parameter Name ; Value ; Type                                               ;
++----------------+-------+----------------------------------------------------+
+; H_SYNC_CYC     ; 96    ; Signed Integer                                     ;
+; H_SYNC_BACK    ; 48    ; Signed Integer                                     ;
+; H_SYNC_ACT     ; 640   ; Signed Integer                                     ;
+; H_SYNC_FRONT   ; 16    ; Signed Integer                                     ;
+; H_SYNC_TOTAL   ; 800   ; Signed Integer                                     ;
+; V_SYNC_CYC     ; 2     ; Signed Integer                                     ;
+; V_SYNC_BACK    ; 33    ; Signed Integer                                     ;
+; V_SYNC_ACT     ; 480   ; Signed Integer                                     ;
+; V_SYNC_FRONT   ; 10    ; Signed Integer                                     ;
+; V_SYNC_TOTAL   ; 525   ; Signed Integer                                     ;
+; X_START        ; 144   ; Signed Integer                                     ;
+; Y_START        ; 35    ; Signed Integer                                     ;
++----------------+-------+----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; COLUMN_WIDTH   ; 1280  ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; Parameter Name ; Value          ; Type                                                                                    ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                 ;
+; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                                          ;
+; TAP_DISTANCE   ; 1280           ; Signed Integer                                                                          ;
+; WIDTH          ; 12             ; Signed Integer                                                                          ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                 ;
+; CBXI_PARAMETER ; shift_taps_rnn ; Untyped                                                                                 ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
++-------------------------------+-------------------+--------------------------------------------+
+; Parameter Name                ; Value             ; Type                                       ;
++-------------------------------+-------------------+--------------------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                                    ;
+; PLL_TYPE                      ; AUTO              ; Untyped                                    ;
+; LPM_HINT                      ; UNUSED            ; Untyped                                    ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                    ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                    ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                                    ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                    ;
+; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                             ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                    ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                    ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                    ;
+; LOCK_HIGH                     ; 1                 ; Untyped                                    ;
+; LOCK_LOW                      ; 1                 ; Untyped                                    ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                    ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                    ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                    ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                    ;
+; SKIP_VCO                      ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                    ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                    ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                    ;
+; BANDWIDTH                     ; 0                 ; Untyped                                    ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                    ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                                    ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                                    ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                    ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                                    ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK1_PHASE_SHIFT              ; -2600             ; Untyped                                    ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                                    ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                                    ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                                    ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                                    ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                    ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; VCO_MIN                       ; 0                 ; Untyped                                    ;
+; VCO_MAX                       ; 0                 ; Untyped                                    ;
+; VCO_CENTER                    ; 0                 ; Untyped                                    ;
+; PFD_MIN                       ; 0                 ; Untyped                                    ;
+; PFD_MAX                       ; 0                 ; Untyped                                    ;
+; M_INITIAL                     ; 0                 ; Untyped                                    ;
+; M                             ; 0                 ; Untyped                                    ;
+; N                             ; 1                 ; Untyped                                    ;
+; M2                            ; 1                 ; Untyped                                    ;
+; N2                            ; 1                 ; Untyped                                    ;
+; SS                            ; 1                 ; Untyped                                    ;
+; C0_HIGH                       ; 0                 ; Untyped                                    ;
+; C1_HIGH                       ; 0                 ; Untyped                                    ;
+; C2_HIGH                       ; 0                 ; Untyped                                    ;
+; C3_HIGH                       ; 0                 ; Untyped                                    ;
+; C4_HIGH                       ; 0                 ; Untyped                                    ;
+; C5_HIGH                       ; 0                 ; Untyped                                    ;
+; C6_HIGH                       ; 0                 ; Untyped                                    ;
+; C7_HIGH                       ; 0                 ; Untyped                                    ;
+; C8_HIGH                       ; 0                 ; Untyped                                    ;
+; C9_HIGH                       ; 0                 ; Untyped                                    ;
+; C0_LOW                        ; 0                 ; Untyped                                    ;
+; C1_LOW                        ; 0                 ; Untyped                                    ;
+; C2_LOW                        ; 0                 ; Untyped                                    ;
+; C3_LOW                        ; 0                 ; Untyped                                    ;
+; C4_LOW                        ; 0                 ; Untyped                                    ;
+; C5_LOW                        ; 0                 ; Untyped                                    ;
+; C6_LOW                        ; 0                 ; Untyped                                    ;
+; C7_LOW                        ; 0                 ; Untyped                                    ;
+; C8_LOW                        ; 0                 ; Untyped                                    ;
+; C9_LOW                        ; 0                 ; Untyped                                    ;
+; C0_INITIAL                    ; 0                 ; Untyped                                    ;
+; C1_INITIAL                    ; 0                 ; Untyped                                    ;
+; C2_INITIAL                    ; 0                 ; Untyped                                    ;
+; C3_INITIAL                    ; 0                 ; Untyped                                    ;
+; C4_INITIAL                    ; 0                 ; Untyped                                    ;
+; C5_INITIAL                    ; 0                 ; Untyped                                    ;
+; C6_INITIAL                    ; 0                 ; Untyped                                    ;
+; C7_INITIAL                    ; 0                 ; Untyped                                    ;
+; C8_INITIAL                    ; 0                 ; Untyped                                    ;
+; C9_INITIAL                    ; 0                 ; Untyped                                    ;
+; C0_MODE                       ; BYPASS            ; Untyped                                    ;
+; C1_MODE                       ; BYPASS            ; Untyped                                    ;
+; C2_MODE                       ; BYPASS            ; Untyped                                    ;
+; C3_MODE                       ; BYPASS            ; Untyped                                    ;
+; C4_MODE                       ; BYPASS            ; Untyped                                    ;
+; C5_MODE                       ; BYPASS            ; Untyped                                    ;
+; C6_MODE                       ; BYPASS            ; Untyped                                    ;
+; C7_MODE                       ; BYPASS            ; Untyped                                    ;
+; C8_MODE                       ; BYPASS            ; Untyped                                    ;
+; C9_MODE                       ; BYPASS            ; Untyped                                    ;
+; C0_PH                         ; 0                 ; Untyped                                    ;
+; C1_PH                         ; 0                 ; Untyped                                    ;
+; C2_PH                         ; 0                 ; Untyped                                    ;
+; C3_PH                         ; 0                 ; Untyped                                    ;
+; C4_PH                         ; 0                 ; Untyped                                    ;
+; C5_PH                         ; 0                 ; Untyped                                    ;
+; C6_PH                         ; 0                 ; Untyped                                    ;
+; C7_PH                         ; 0                 ; Untyped                                    ;
+; C8_PH                         ; 0                 ; Untyped                                    ;
+; C9_PH                         ; 0                 ; Untyped                                    ;
+; L0_HIGH                       ; 1                 ; Untyped                                    ;
+; L1_HIGH                       ; 1                 ; Untyped                                    ;
+; G0_HIGH                       ; 1                 ; Untyped                                    ;
+; G1_HIGH                       ; 1                 ; Untyped                                    ;
+; G2_HIGH                       ; 1                 ; Untyped                                    ;
+; G3_HIGH                       ; 1                 ; Untyped                                    ;
+; E0_HIGH                       ; 1                 ; Untyped                                    ;
+; E1_HIGH                       ; 1                 ; Untyped                                    ;
+; E2_HIGH                       ; 1                 ; Untyped                                    ;
+; E3_HIGH                       ; 1                 ; Untyped                                    ;
+; L0_LOW                        ; 1                 ; Untyped                                    ;
+; L1_LOW                        ; 1                 ; Untyped                                    ;
+; G0_LOW                        ; 1                 ; Untyped                                    ;
+; G1_LOW                        ; 1                 ; Untyped                                    ;
+; G2_LOW                        ; 1                 ; Untyped                                    ;
+; G3_LOW                        ; 1                 ; Untyped                                    ;
+; E0_LOW                        ; 1                 ; Untyped                                    ;
+; E1_LOW                        ; 1                 ; Untyped                                    ;
+; E2_LOW                        ; 1                 ; Untyped                                    ;
+; E3_LOW                        ; 1                 ; Untyped                                    ;
+; L0_INITIAL                    ; 1                 ; Untyped                                    ;
+; L1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G0_INITIAL                    ; 1                 ; Untyped                                    ;
+; G1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G2_INITIAL                    ; 1                 ; Untyped                                    ;
+; G3_INITIAL                    ; 1                 ; Untyped                                    ;
+; E0_INITIAL                    ; 1                 ; Untyped                                    ;
+; E1_INITIAL                    ; 1                 ; Untyped                                    ;
+; E2_INITIAL                    ; 1                 ; Untyped                                    ;
+; E3_INITIAL                    ; 1                 ; Untyped                                    ;
+; L0_MODE                       ; BYPASS            ; Untyped                                    ;
+; L1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G0_MODE                       ; BYPASS            ; Untyped                                    ;
+; G1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G2_MODE                       ; BYPASS            ; Untyped                                    ;
+; G3_MODE                       ; BYPASS            ; Untyped                                    ;
+; E0_MODE                       ; BYPASS            ; Untyped                                    ;
+; E1_MODE                       ; BYPASS            ; Untyped                                    ;
+; E2_MODE                       ; BYPASS            ; Untyped                                    ;
+; E3_MODE                       ; BYPASS            ; Untyped                                    ;
+; L0_PH                         ; 0                 ; Untyped                                    ;
+; L1_PH                         ; 0                 ; Untyped                                    ;
+; G0_PH                         ; 0                 ; Untyped                                    ;
+; G1_PH                         ; 0                 ; Untyped                                    ;
+; G2_PH                         ; 0                 ; Untyped                                    ;
+; G3_PH                         ; 0                 ; Untyped                                    ;
+; E0_PH                         ; 0                 ; Untyped                                    ;
+; E1_PH                         ; 0                 ; Untyped                                    ;
+; E2_PH                         ; 0                 ; Untyped                                    ;
+; E3_PH                         ; 0                 ; Untyped                                    ;
+; M_PH                          ; 0                 ; Untyped                                    ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; CLK0_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK1_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK2_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK3_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK4_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK5_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK6_COUNTER                  ; E0                ; Untyped                                    ;
+; CLK7_COUNTER                  ; E1                ; Untyped                                    ;
+; CLK8_COUNTER                  ; E2                ; Untyped                                    ;
+; CLK9_COUNTER                  ; E3                ; Untyped                                    ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                                    ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                                    ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                                    ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                                    ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                                    ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                    ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                    ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                                    ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                                    ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                                    ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK1                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                                    ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                                    ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                                    ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; CBXI_PARAMETER                ; altpll_9ee2       ; Untyped                                    ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                                    ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                                    ;
+; WIDTH_CLOCK                   ; 5                 ; Signed Integer                             ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                                    ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                                    ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                                    ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                                    ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                                    ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                             ;
++-------------------------------+-------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                          ;
+; REF_PER        ; 1024  ; Signed Integer                                          ;
+; SC_CL          ; 3     ; Signed Integer                                          ;
+; SC_RCD         ; 3     ; Signed Integer                                          ;
+; SC_RRD         ; 7     ; Signed Integer                                          ;
+; SC_PM          ; 1     ; Signed Integer                                          ;
+; SC_BL          ; 1     ; Signed Integer                                          ;
+; SDR_BL         ; 111   ; Unsigned Binary                                         ;
+; SDR_BT         ; 0     ; Unsigned Binary                                         ;
+; SDR_CL         ; 011   ; Unsigned Binary                                         ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ;
++----------------+-------+------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                               ;
++----------------+-------+------------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                     ;
+; REF_PER        ; 1024  ; Signed Integer                                                                     ;
+; SC_CL          ; 3     ; Signed Integer                                                                     ;
+; SC_RCD         ; 3     ; Signed Integer                                                                     ;
+; SC_RRD         ; 7     ; Signed Integer                                                                     ;
+; SC_PM          ; 1     ; Signed Integer                                                                     ;
+; SC_BL          ; 1     ; Signed Integer                                                                     ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                    ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                    ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                    ;
++----------------+-------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                           ;
+; REF_PER        ; 1024  ; Signed Integer                                                           ;
+; SC_CL          ; 3     ; Signed Integer                                                           ;
+; SC_RCD         ; 3     ; Signed Integer                                                           ;
+; SC_RRD         ; 7     ; Signed Integer                                                           ;
+; SC_PM          ; 1     ; Signed Integer                                                           ;
+; SC_BL          ; 1     ; Signed Integer                                                           ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                          ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                          ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                          ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
++----------------+-------+----------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                             ;
++----------------+-------+----------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                   ;
+; REF_PER        ; 1024  ; Signed Integer                                                                   ;
+; SC_CL          ; 3     ; Signed Integer                                                                   ;
+; SC_RCD         ; 3     ; Signed Integer                                                                   ;
+; SC_RRD         ; 7     ; Signed Integer                                                                   ;
+; SC_PM          ; 1     ; Signed Integer                                                                   ;
+; SC_BL          ; 1     ; Signed Integer                                                                   ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                  ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                  ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                  ;
++----------------+-------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ;
++-----------------------+------------------+----------------------------------+
+; Parameter Name        ; Value            ; Type                             ;
++-----------------------+------------------+----------------------------------+
+; default_exposure      ; 0000011111000000 ; Unsigned Binary                  ;
+; exposure_change_value ; 0000000011001000 ; Unsigned Binary                  ;
+; CLK_Freq              ; 50000000         ; Signed Integer                   ;
+; I2C_Freq              ; 20000            ; Signed Integer                   ;
+; LUT_SIZE              ; 25               ; Signed Integer                   ;
++-----------------------+------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------+
+; Parameter Settings for User Entity Instance: ps2:inst6 ;
++----------------+-----------+---------------------------+
+; Parameter Name ; Value     ; Type                      ;
++----------------+-----------+---------------------------+
+; enable_byte    ; 011110100 ; Unsigned Binary           ;
+; listen         ; 00        ; Unsigned Binary           ;
+; pullclk        ; 01        ; Unsigned Binary           ;
+; pulldat        ; 10        ; Unsigned Binary           ;
+; trans          ; 11        ; Unsigned Binary           ;
++----------------+-----------+---------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mux:inst10|LPM_MUX:LPM_MUX_component ;
++------------------------+-------------+------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                           ;
++------------------------+-------------+------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                     ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                   ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                   ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                 ;
+; LPM_WIDTH              ; 30          ; Signed Integer                                 ;
+; LPM_SIZE               ; 4           ; Signed Integer                                 ;
+; LPM_WIDTHS             ; 2           ; Signed Integer                                 ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                 ;
+; CBXI_PARAMETER         ; mux_u7e     ; Untyped                                        ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                        ;
++------------------------+-------------+------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                            ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                                                  ;
+; width          ; 20    ; Signed Integer                                                                                  ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                                                    ;
+; width          ; 20    ; Signed Integer                                                                                    ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                 ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+; rscid          ; 3     ; Signed Integer                                                                                       ;
+; width          ; 8     ; Signed Integer                                                                                       ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; rscid          ; 4     ; Signed Integer                                                                                    ;
+; width          ; 30    ; Signed Integer                                                                                    ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+; rscid          ; 5     ; Signed Integer                                                                                           ;
+; width          ; 30    ; Signed Integer                                                                                           ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire ;
++----------------+-------+-------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                ;
++----------------+-------+-------------------------------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                                      ;
+; width          ; 90    ; Signed Integer                                                                      ;
++----------------+-------+-------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg ;
++----------------+-------+--------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                       ;
++----------------+-------+--------------------------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                                             ;
+; width          ; 30    ; Signed Integer                                                                             ;
++----------------+-------+--------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altshift_taps:fifo_inst2 ;
++----------------+----------------+-------------------------------------+
+; Parameter Name ; Value          ; Type                                ;
++----------------+----------------+-------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                             ;
+; NUMBER_OF_TAPS ; 5              ; Untyped                             ;
+; TAP_DISTANCE   ; 800            ; Untyped                             ;
+; WIDTH          ; 30             ; Untyped                             ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                             ;
+; CBXI_PARAMETER ; shift_taps_lpm ; Untyped                             ;
++----------------+----------------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; altshift_taps Parameter Settings by Entity Instance                                                       ;
++----------------------------+------------------------------------------------------------------------------+
+; Name                       ; Value                                                                        ;
++----------------------------+------------------------------------------------------------------------------+
+; Number of entity instances ; 2                                                                            ;
+; Entity Instance            ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+;     -- NUMBER_OF_TAPS      ; 2                                                                            ;
+;     -- TAP_DISTANCE        ; 1280                                                                         ;
+;     -- WIDTH               ; 12                                                                           ;
+; Entity Instance            ; altshift_taps:fifo_inst2                                                     ;
+;     -- NUMBER_OF_TAPS      ; 5                                                                            ;
+;     -- TAP_DISTANCE        ; 800                                                                          ;
+;     -- WIDTH               ; 30                                                                           ;
++----------------------------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                      ;
++-------------------------------+---------------------------------------------------+
+; Name                          ; Value                                             ;
++-------------------------------+---------------------------------------------------+
+; Number of entity instances    ; 1                                                 ;
+; Entity Instance               ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                            ;
+;     -- PLL_TYPE               ; AUTO                                              ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                            ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                             ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                                 ;
+;     -- VCO_MULTIPLY_BY        ; 0                                                 ;
+;     -- VCO_DIVIDE_BY          ; 0                                                 ;
++-------------------------------+---------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                                    ;
++----------------------------+------------------------------------------------------------------------------------+
+; Name                       ; Value                                                                              ;
++----------------------------+------------------------------------------------------------------------------------+
+; Number of entity instances ; 4                                                                                  ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
++----------------------------+------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                                          ;
++---------------------------------------+---------------------------------------------------------------------------------+
+; Name                                  ; Value                                                                           ;
++---------------------------------------+---------------------------------------------------------------------------------+
+; Number of entity instances            ; 3                                                                               ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1 ;
+;     -- LPM_WIDTHA                     ; 3                                                                               ;
+;     -- LPM_WIDTHB                     ; 6                                                                               ;
+;     -- LPM_WIDTHP                     ; 9                                                                               ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0 ;
+;     -- LPM_WIDTHA                     ; 3                                                                               ;
+;     -- LPM_WIDTHB                     ; 6                                                                               ;
+;     -- LPM_WIDTHP                     ; 9                                                                               ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2 ;
+;     -- LPM_WIDTHA                     ; 3                                                                               ;
+;     -- LPM_WIDTHB                     ; 6                                                                               ;
+;     -- LPM_WIDTHP                     ; 9                                                                               ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
++---------------------------------------+---------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"                                                                                                                   ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port       ; Type  ; Severity ; Details                                                                                                                                      ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; iUART_CTRL ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; DM   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; DQM  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"                                                                                 ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port     ; Type  ; Severity ; Details                                                                                                                                      ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; CMD      ; Input ; Warning  ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives.  Extra input bit(s) "CMD[2..2]" will be connected to GND.  ;
+; INIT_ACK ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"                                                                                                                                                               ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port                 ; Type   ; Severity ; Details                                                                                                                                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; RESET_N              ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND.                               ;
+; WR2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND.                               ;
+; RD2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; CS_N                 ; Output ; Warning  ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ;
++-------+--------+----------+----------------------------+
+; Port  ; Type   ; Severity ; Details                    ;
++-------+--------+----------+----------------------------+
+; oSEG4 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG5 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG6 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG7 ; Output ; Info     ; Explicitly unconnected     ;
++-------+--------+----------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"                                                                      ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                                                  ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; shiftout ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"                                                                                                                                                                   ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                            ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; oRed[1..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oGreen[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oBlue[1..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; iX_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; iY_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"                                                                   ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port            ; Type   ; Severity ; Details                                                                             ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; oX_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; oY_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"                                                                                ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                                                  ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; oVGA_SYNC  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_BLANK ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_CLOCK ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:03     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 17:40:56 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 2 design units, including 2 entities, in source file catapult_ip/blur3x3/rtl.v
+    Info (12023): Found entity 1: mean_vga_core
+    Info (12023): Found entity 2: mean_vga
+Info (12021): Found 1 design units, including 1 entities, in source file v/ps2.v
+    Info (12023): Found entity 1: ps2
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v
+    Info (12023): Found entity 1: command
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v
+    Info (12023): Found entity 1: control_interface
+Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v
+    Info (12023): Found entity 1: sdr_data_path
+Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v
+    Info (12023): Found entity 1: Sdram_Control_4Port
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v
+    Info (12023): Found entity 1: Sdram_FIFO
+Warning (12019): Can't analyze file -- file V/async_receiver.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v
+    Info (12023): Found entity 1: CCD_Capture
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v
+    Info (12023): Found entity 1: I2C_CCD_Config
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v
+    Info (12023): Found entity 1: I2C_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v
+    Info (12023): Found entity 1: Line_Buffer
+Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v
+    Info (12023): Found entity 1: RAW2RGB
+Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v
+    Info (12023): Found entity 1: Reset_Delay
+Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v
+    Info (12023): Found entity 1: sdram_pll
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v
+    Info (12023): Found entity 1: SEG7_LUT
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v
+    Info (12023): Found entity 1: SEG7_LUT_8
+Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v
+    Info (12023): Found entity 1: VGA_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v
+    Info (12023): Found entity 1: DE0_D5M
+Info (12021): Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf
+    Info (12023): Found entity 1: TOP_DE0_CAMERA_MOUSE
+Info (12021): Found 2 design units, including 1 entities, in source file vga_mux.vhd
+    Info (12022): Found design unit 1: vga_mux-SYN
+    Info (12023): Found entity 1: vga_mux
+Info (12021): Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v
+    Info (12023): Found entity 1: mgc_out_reg_pos
+    Info (12023): Found entity 2: mgc_out_reg_neg
+    Info (12023): Found entity 3: mgc_out_reg
+    Info (12023): Found entity 4: mgc_out_buf_wait
+    Info (12023): Found entity 5: mgc_out_fifo_wait
+    Info (12023): Found entity 6: mgc_out_fifo_wait_core
+    Info (12023): Found entity 7: mgc_pipe
+Info (12021): Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v
+    Info (12023): Found entity 1: mgc_in_wire
+    Info (12023): Found entity 2: mgc_in_wire_en
+    Info (12023): Found entity 3: mgc_in_wire_wait
+    Info (12023): Found entity 4: mgc_chan_in
+    Info (12023): Found entity 5: mgc_out_stdreg
+    Info (12023): Found entity 6: mgc_out_stdreg_en
+    Info (12023): Found entity 7: mgc_out_stdreg_wait
+    Info (12023): Found entity 8: mgc_out_prereg_en
+    Info (12023): Found entity 9: mgc_inout_stdreg_en
+    Info (12023): Found entity 10: hid_tribuf
+    Info (12023): Found entity 11: mgc_inout_stdreg_wait
+    Info (12023): Found entity 12: mgc_inout_buf_wait
+    Info (12023): Found entity 13: mgc_inout_fifo_wait
+    Info (12023): Found entity 14: mgc_io_sync
+    Info (12023): Found entity 15: mgc_bsync_rdy
+    Info (12023): Found entity 16: mgc_bsync_vld
+    Info (12023): Found entity 17: mgc_bsync_rv
+    Info (12023): Found entity 18: mgc_sync
+    Info (12023): Found entity 19: funccall_inout
+    Info (12023): Found entity 20: modulario_en_in
+Info (12021): Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v
+    Info (12023): Found entity 1: vga_mouse_square_core
+    Info (12023): Found entity 2: vga_mouse_square
+Info (12127): Elaborating entity "TOP_DE0_CAMERA_MOUSE" for the top level hierarchy
+Warning (275002): No superset bus at connection
+Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port "VGA_R" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(166): see declaration for object "VGA_R"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port "VGA_G" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(167): see declaration for object "VGA_G"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port "VGA_B" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(168): see declaration for object "VGA_B"
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)
+Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(128) has no driver
+Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1"
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)
+Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2"
+Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3"
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)
+Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4"
+Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter:
+    Info (12134): Parameter "lpm_type" = "altshift_taps"
+    Info (12134): Parameter "number_of_taps" = "2"
+    Info (12134): Parameter "tap_distance" = "1280"
+    Info (12134): Parameter "width" = "12"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf
+    Info (12023): Found entity 1: shift_taps_rnn
+Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf
+    Info (12023): Found entity 1: altsyncram_lp81
+Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf
+    Info (12023): Found entity 1: cntr_cuf
+Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf
+    Info (12023): Found entity 1: cmpr_vgc
+Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4"
+Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5"
+Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0"
+Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6"
+Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "2"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "5"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "2"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "5"
+    Info (12134): Parameter "clk1_phase_shift" = "-2600"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone III"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf
+    Info (12023): Found entity 1: altpll_9ee2
+Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated"
+Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7"
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
+Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
+Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
+Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (272007): Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter:
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
+    Info (12134): Parameter "intended_device_family" = "Cyclone"
+    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K"
+    Info (12134): Parameter "lpm_numwords" = "512"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "dcfifo"
+    Info (12134): Parameter "lpm_width" = "16"
+    Info (12134): Parameter "lpm_widthu" = "9"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf
+    Info (12023): Found entity 1: dcfifo_v5o1
+Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info (12023): Found entity 1: a_gray2bin_tgb
+Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info (12023): Found entity 1: a_graycounter_s57
+Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info (12023): Found entity 1: a_graycounter_ojc
+Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf
+    Info (12023): Found entity 1: altsyncram_de51
+Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info (12023): Found entity 1: dffpipe_oe9
+Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_qld
+Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info (12023): Found entity 1: dffpipe_pe9
+Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_rld
+Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info (12023): Found entity 1: dffpipe_qe9
+Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
+    Info (12023): Found entity 1: cmpr_e66
+Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp"
+Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8"
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)
+Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
+Info (12128): Elaborating entity "ps2" for hierarchy "ps2:inst6"
+Warning (10230): Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)
+Warning (10230): Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)
+Warning (10230): Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)
+Info (12128): Elaborating entity "vga_mux" for hierarchy "vga_mux:inst10"
+Info (12128): Elaborating entity "LPM_MUX" for hierarchy "vga_mux:inst10|LPM_MUX:LPM_MUX_component"
+Info (12130): Elaborated megafunction instantiation "vga_mux:inst10|LPM_MUX:LPM_MUX_component"
+Info (12133): Instantiated megafunction "vga_mux:inst10|LPM_MUX:LPM_MUX_component" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTH" = "30"
+    Info (12134): Parameter "LPM_SIZE" = "4"
+    Info (12134): Parameter "LPM_WIDTHS" = "2"
+    Info (12134): Parameter "LPM_PIPELINE" = "0"
+    Info (12134): Parameter "LPM_TYPE" = "LPM_MUX"
+    Info (12134): Parameter "LPM_HINT" = "UNUSED"
+Info (12021): Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf
+    Info (12023): Found entity 1: mux_u7e
+Info (12128): Elaborating entity "mux_u7e" for hierarchy "vga_mux:inst10|LPM_MUX:LPM_MUX_component|mux_u7e:auto_generated"
+Info (12128): Elaborating entity "vga_mouse_square" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "vga_mouse_square_core" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst"
+Info (12128): Elaborating entity "mean_vga" for hierarchy "mean_vga:vga_blur_catapult_inst"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "mean_vga_core" for hierarchy "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst"
+Warning (10230): Verilog HDL assignment warning at rtl.v(153): truncated value with size 11 to match size of target (10)
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "altshift_taps:fifo_inst2"
+Info (12130): Elaborated megafunction instantiation "altshift_taps:fifo_inst2"
+Info (12133): Instantiated megafunction "altshift_taps:fifo_inst2" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "5"
+    Info (12134): Parameter "TAP_DISTANCE" = "800"
+    Info (12134): Parameter "WIDTH" = "30"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_lpm.tdf
+    Info (12023): Found entity 1: shift_taps_lpm
+Info (12128): Elaborating entity "shift_taps_lpm" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_vp81.tdf
+    Info (12023): Found entity 1: altsyncram_vp81
+Info (12128): Elaborating entity "altsyncram_vp81" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf
+    Info (12023): Found entity 1: cntr_1tf
+Info (12128): Elaborating entity "cntr_1tf" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf
+    Info (12023): Found entity 1: cmpr_ugc
+Info (12128): Elaborating entity "cmpr_ugc" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4"
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[120]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[121]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[122]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[123]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[124]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[125]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[126]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[127]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[128]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[129]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[130]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[131]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[132]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[133]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[134]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[135]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[136]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[137]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[138]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[139]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[140]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[141]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[142]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[143]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[144]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[145]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[146]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[147]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[148]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[149]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[90]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[91]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[92]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[93]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[94]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[95]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[96]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[97]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[98]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[99]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[100]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[101]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[102]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[103]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[104]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[105]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[106]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[107]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[108]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[109]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[110]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[111]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[112]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[113]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[114]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[115]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[116]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[117]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[118]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[119]"
+Info (278001): Inferred 3 megafunctions from design logic
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult1"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult0"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult2"
+Info (12130): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1"
+Info (12133): Instantiated megafunction "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "3"
+    Info (12134): Parameter "LPM_WIDTHB" = "6"
+    Info (12134): Parameter "LPM_WIDTHP" = "9"
+    Info (12134): Parameter "LPM_WIDTHR" = "9"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|altshift:external_latency_ffs", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1"
+Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver.
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver.
+Warning (13039): The following bidir pins have no drivers
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "GPIO_1[15]" is fed by VCC
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13009): TRI or OPNDRN buffers permanently enabled
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
+    Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND
+    Warning (13410): Pin "LEDG[9]" is stuck at GND
+    Warning (13410): Pin "LEDG[8]" is stuck at GND
+    Warning (13410): Pin "LEDG[7]" is stuck at GND
+    Warning (13410): Pin "LEDG[6]" is stuck at GND
+    Warning (13410): Pin "LEDG[5]" is stuck at GND
+    Warning (13410): Pin "LEDG[4]" is stuck at GND
+    Warning (13410): Pin "LEDG[3]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 29 registers lost all their fanouts during netlist optimizations.
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 3 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+Info (21057): Implemented 2857 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 77 output pins
+    Info (21060): Implemented 50 bidirectional pins
+    Info (21061): Implemented 2537 logic cells
+    Info (21064): Implemented 176 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 176 warnings
+    Info: Peak virtual memory: 558 megabytes
+    Info: Processing ended: Tue Mar 01 17:41:04 2016
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:08
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary
new file mode 100644
index 0000000..e69a769
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Mar 01 17:41:04 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_DE0_CAMERA_MOUSE
+Family : Cyclone III
+Total logic elements : 2,505
+    Total combinational functions : 1,910
+    Dedicated logic registers : 1,326
+Total registers : 1326
+Total pins : 143
+Total virtual pins : 0
+Total memory bits : 134,236
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin
new file mode 100644
index 0000000..605d7b1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "DE0_D5M"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+DRAM_ADDR[1]                 : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_1                    : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[4]                 : A5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[7]                 : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[11]                : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[8]                   : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[10]                  : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[13]                  : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+HEX1[0]                      : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[3]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[6]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[1]                      : A16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[4]                      : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+HEX3[2]                      : A19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+GPIO_1[16]                   : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+GPIO_1[15]                   : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[1]              : AA11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+GPIO_1[6]                    : AA17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[5]                    : AA18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[2]                    : AA19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[0]                    : AA20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+GPIO_1[17]                   : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+GPIO_1[14]                   : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[0]              : AB11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB12      :        :                   :         : 4         :                
+VGA_CLK                      : AB13      : output : 3.3-V LVTTL       :         : 4         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+GPIO_1[7]                    : AB17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[4]                    : AB18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[3]                    : AB19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[1]                    : AB20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 3.3V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[2]                 : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[10]                : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_0                    : B5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[6]                 : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[9]                 : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_UDQM                    : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[9]                   : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[12]                  : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+HEX1[1]                      : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[4]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+HEX2[2]                      : B16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[5]                      : B17       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[0]                      : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[3]                      : B19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[3]                 : C3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[0]                 : C4        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+DRAM_ADDR[5]                 : C6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[8]                 : C7        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+DRAM_DQ[11]                  : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+HEX1[2]                      : C13       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+HEX3[4]                      : C19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+DRAM_WE_N                    : D6        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[0]                   : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+HEX2[0]                      : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+HEX3[5]                      : D19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_CLK                     : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CKE                     : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_LDQM                    : E7        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[3]                   : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[14]                  : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[0]                      : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+HEX1[5]                      : E14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[3]                      : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+KEY[2]                       : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+DRAM_RAS_N                   : F7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[7]                   : F8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[4]                   : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[15]                  : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[1]                      : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[5]                      : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[6]                      : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[6]                      : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[1]                      : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+KEY[1]                       : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+DRAM_CS_N                    : G7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CAS_N                   : G8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[5]                   : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[1]                   : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0[4]                      : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+HEX3[6]                      : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+KEY[0]                       : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+DRAM_DQ[6]                   : H9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[2]                   : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0[2]                      : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[3]                      : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+PS2_DAT                      : P21       : bidir  : 3.3-V LVTTL       :         : 5         : Y              
+PS2_CLK                      : P22       : bidir  : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+GPIO_1[22]                   : R11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[23]                   : R12       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+GPIO_1[19]                   : R14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+GPIO_1_CLKOUT[0]             : R16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+GPIO_1[27]                   : T9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[25]                   : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+GPIO_1[21]                   : T12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+GPIO_1[18]                   : T14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[11]                   : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_CLKOUT[1]             : T16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+GPIO_1[29]                   : U8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[26]                   : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[24]                   : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+GPIO_1[20]                   : U12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+GPIO_1[10]                   : U15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+GPIO_1[30]                   : V6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[31]                   : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+GPIO_1[13]                   : V15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+GPIO_1[12]                   : W15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 3.3V    : 4         :                
+GPIO_1[9]                    : W17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+GPIO_1[28]                   : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 3.3V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+GPIO_1[8]                    : Y17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
new file mode 100644
index 0000000..bef0d53
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pti_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pti_db_list.ddb
new file mode 100644
index 0000000..81e1a96
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pti_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf
new file mode 100644
index 0000000..fad5fa0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "13.1"
+DATE = "14:14:24  April 30, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_D5M"
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf
new file mode 100644
index 0000000..f975767
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf
@@ -0,0 +1,574 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_DE0_CAMERA_MOUSE
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+# mouse connected as keyboard ...
+set_location_assignment PIN_P22 -to PS2_CLK
+set_location_assignment PIN_P21 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+
+set_global_assignment -name VERILOG_FILE catapult_ip/blur3x3/rtl.v
+set_global_assignment -name VERILOG_FILE V/ps2.v
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name BDF_FILE V/TOP_DE0_CAMERA_MOUSE.bdf
+set_global_assignment -name QIP_FILE vga_mux.qip
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak
new file mode 100644
index 0000000..8404697
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak
@@ -0,0 +1,571 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_DE0_CAMERA_MOUSE
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl.v
+set_global_assignment -name VERILOG_FILE V/ps2.v
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name BDF_FILE V/TOP_DE0_CAMERA_MOUSE.bdf
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws
new file mode 100644
index 0000000..a85b478
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc
new file mode 100644
index 0000000..6a9d418
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc
@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 10.0 Build 218 06/27/2010 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_50" -period 20ns [get_ports {CLOCK_50}] -waveform {0.000ns 10.000ns}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
new file mode 100644
index 0000000..5d36fc0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt
new file mode 100644
index 0000000..bf03c8c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt
@@ -0,0 +1,10440 @@
+TimeQuest Timing Analyzer report for DE0_D5M
+Tue Mar 01 17:41:26 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1200mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1200mV 85C Model Setup Summary
+  9. Slow 1200mV 85C Model Hold Summary
+ 10. Slow 1200mV 85C Model Recovery Summary
+ 11. Slow 1200mV 85C Model Removal Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 16. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
+ 19. Slow 1200mV 85C Model Removal: 'CLOCK_50'
+ 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 23. Setup Times
+ 24. Hold Times
+ 25. Clock to Output Times
+ 26. Minimum Clock to Output Times
+ 27. Propagation Delay
+ 28. Minimum Propagation Delay
+ 29. Output Enable Times
+ 30. Minimum Output Enable Times
+ 31. Output Disable Times
+ 32. Minimum Output Disable Times
+ 33. MTBF Summary
+ 34. Synchronizer Summary
+ 35. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+ 36. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+ 37. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+ 38. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+ 39. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+ 40. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+ 41. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+ 42. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+ 43. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+ 44. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+ 45. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+ 46. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+ 47. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+ 48. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+ 49. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+ 50. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+ 51. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+ 52. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+ 53. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+ 54. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+ 55. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+ 56. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+ 57. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+ 58. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+ 59. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+ 60. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+ 61. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+ 62. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+ 63. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+ 64. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+ 65. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+ 66. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+ 67. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+ 68. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+ 69. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+ 70. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+ 71. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+ 72. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+ 73. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+ 74. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+ 75. Slow 1200mV 0C Model Fmax Summary
+ 76. Slow 1200mV 0C Model Setup Summary
+ 77. Slow 1200mV 0C Model Hold Summary
+ 78. Slow 1200mV 0C Model Recovery Summary
+ 79. Slow 1200mV 0C Model Removal Summary
+ 80. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 81. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 82. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 83. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 84. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 85. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 86. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
+ 87. Slow 1200mV 0C Model Removal: 'CLOCK_50'
+ 88. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 89. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 90. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 91. Setup Times
+ 92. Hold Times
+ 93. Clock to Output Times
+ 94. Minimum Clock to Output Times
+ 95. Propagation Delay
+ 96. Minimum Propagation Delay
+ 97. Output Enable Times
+ 98. Minimum Output Enable Times
+ 99. Output Disable Times
+100. Minimum Output Disable Times
+101. MTBF Summary
+102. Synchronizer Summary
+103. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+104. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+105. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+106. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+107. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+108. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+109. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+110. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+111. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+112. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+113. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+114. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+115. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+116. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+117. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+118. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+119. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+120. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+121. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+122. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+123. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+124. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+125. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+126. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+127. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+128. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+129. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+130. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+131. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+132. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+133. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+134. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+135. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+136. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+137. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+138. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+139. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+140. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+141. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+142. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+143. Fast 1200mV 0C Model Setup Summary
+144. Fast 1200mV 0C Model Hold Summary
+145. Fast 1200mV 0C Model Recovery Summary
+146. Fast 1200mV 0C Model Removal Summary
+147. Fast 1200mV 0C Model Minimum Pulse Width Summary
+148. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+149. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+150. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+151. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+152. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+153. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
+154. Fast 1200mV 0C Model Removal: 'CLOCK_50'
+155. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+156. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+157. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+158. Setup Times
+159. Hold Times
+160. Clock to Output Times
+161. Minimum Clock to Output Times
+162. Propagation Delay
+163. Minimum Propagation Delay
+164. Output Enable Times
+165. Minimum Output Enable Times
+166. Output Disable Times
+167. Minimum Output Disable Times
+168. MTBF Summary
+169. Synchronizer Summary
+170. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+171. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+172. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+173. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+174. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+175. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+176. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+177. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+178. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+179. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+180. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+181. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+182. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+183. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+184. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+185. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+186. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+187. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+188. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+189. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+190. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+191. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+192. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+193. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+194. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+195. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+196. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+197. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+198. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+199. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+200. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+201. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+202. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+203. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+204. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+205. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+206. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+207. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+208. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+209. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+210. Multicorner Timing Analysis Summary
+211. Setup Times
+212. Hold Times
+213. Clock to Output Times
+214. Minimum Clock to Output Times
+215. Progagation Delay
+216. Minimum Progagation Delay
+217. Board Trace Model Assignments
+218. Input Transition Times
+219. Slow Corner Signal Integrity Metrics
+220. Fast Corner Signal Integrity Metrics
+221. Setup Transfers
+222. Hold Transfers
+223. Recovery Transfers
+224. Removal Transfers
+225. Report TCCS
+226. Report RSKM
+227. Unconstrained Paths
+228. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; DE0_D5M                                                            ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; DE0_D5M.sdc   ; OK     ; Tue Mar 01 17:41:24 2016 ;
++---------------+--------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; Clock Name                                          ; Type      ; Period ; Frequency ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                 ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; CLOCK_50                                            ; Base      ; 20.000 ; 50.0 MHz  ; 0.000  ; 10.000 ;            ;           ;             ;        ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                            ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000  ; 125.0 MHz ; 0.000  ; 4.000  ; 50.00      ; 2         ; 5           ;        ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000  ; 125.0 MHz ; -2.600 ; 1.400  ; 50.00      ; 2         ; 5           ; -117.0 ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                        ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 183.28 MHz ; 183.28 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 225.73 MHz ; 225.73 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                          ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.619 ; -28.860       ;
+; CLOCK_50                                            ; 15.570 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                          ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.283 ; 0.000         ;
+; CLOCK_50                                            ; 0.358 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                       ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.405 ; -338.209      ;
+; CLOCK_50                                            ; 14.249 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                       ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.496 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.024 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.735 ; 0.000         ;
+; CLOCK_50                                            ; 9.580 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.619 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.097      ;
+; -0.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.264      ;
+; -0.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.264      ;
+; -0.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.264      ;
+; -0.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.264      ;
+; -0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.227      ;
+; -0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.227      ;
+; -0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.214     ; 2.227      ;
+; -0.385 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.219     ; 2.181      ;
+; -0.385 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.219     ; 2.181      ;
+; -0.385 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.219     ; 2.181      ;
+; -0.385 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.219     ; 2.181      ;
+; -0.385 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.219     ; 2.181      ;
+; -0.385 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.219     ; 2.181      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.164      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.164      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.164      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.164      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.164      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.220     ; 2.082      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.110      ;
+; -0.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.084      ;
+; -0.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.084      ;
+; -0.257 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.188     ; 2.084      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; -0.208 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.008      ;
+; 2.544  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.108     ; 5.363      ;
+; 2.544  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.108     ; 5.363      ;
+; 2.544  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.108     ; 5.363      ;
+; 2.565  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.257      ; 5.707      ;
+; 2.584  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.288      ; 5.719      ;
+; 2.589  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.288      ; 5.714      ;
+; 2.591  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.262      ; 5.686      ;
+; 2.591  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.262      ; 5.686      ;
+; 2.591  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.262      ; 5.686      ;
+; 2.609  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.256      ; 5.662      ;
+; 2.620  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.288      ; 5.683      ;
+; 2.623  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 5.652      ;
+; 2.623  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.108     ; 5.284      ;
+; 2.623  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 5.652      ;
+; 2.623  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.108     ; 5.284      ;
+; 2.623  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 5.652      ;
+; 2.623  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.108     ; 5.284      ;
+; 2.628  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.287      ; 5.674      ;
+; 2.633  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.287      ; 5.669      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                             ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                       ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.627      ;
+; 15.603 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.594      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.539      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.730 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.187      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.739 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.178      ;
+; 15.776 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.421      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.081      ;
+; 15.846 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.351      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.052      ;
+; 15.874 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 4.043      ;
+; 15.883 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.314      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.916 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 4.012      ;
+; 15.971 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.946      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.098     ; 3.944      ;
+; 15.979 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.218      ;
+; 15.998 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]            ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 3.947      ;
+; 16.006 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.818     ; 3.191      ;
+; 16.032 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]            ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.070     ; 3.913      ;
+; 16.051 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.877      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.059 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.869      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
+; 16.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.087     ; 3.866      ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.283 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.382      ; 0.852      ;
+; 0.294 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.382      ; 0.863      ;
+; 0.306 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.382      ; 0.875      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.377      ; 0.877      ;
+; 0.314 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.882      ;
+; 0.315 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.382      ; 0.884      ;
+; 0.316 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.377      ; 0.880      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.377      ; 0.889      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.373      ; 0.888      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.899      ;
+; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.903      ;
+; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.377      ; 0.901      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.906      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.384      ; 0.912      ;
+; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.382      ; 0.913      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.376      ; 0.909      ;
+; 0.350 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.373      ; 0.910      ;
+; 0.357 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.591      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.363 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.377      ; 0.927      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0]                                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.591      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[5]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.591      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.577      ;
+; 0.361 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
+; 0.381 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.600      ;
+; 0.385 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.389 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.609      ;
+; 0.434 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.629      ;
+; 0.509 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.728      ;
+; 0.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.743      ;
+; 0.549 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.769      ;
+; 0.550 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.769      ;
+; 0.551 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.770      ;
+; 0.552 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.771      ;
+; 0.553 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.772      ;
+; 0.555 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.774      ;
+; 0.555 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.774      ;
+; 0.555 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.776      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.777      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.778      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.780      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.780      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.780      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.781      ;
+; 0.562 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.564 ; ps2:inst6|clk_div[1]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.783      ;
+; 0.568 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.788      ;
+; 0.568 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.794      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.794      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.794      ;
+; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.799      ;
+; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.800      ;
+; 0.588 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.807      ;
+; 0.607 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.826      ;
+; 0.698 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.917      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.066      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.395 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.276     ; 3.068      ;
+; -1.345 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.285     ; 3.108      ;
+; -1.335 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.273     ; 3.110      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.713      ;
+; -1.240 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.704      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.239 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.712      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.714      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.715      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.715      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.715      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.715      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.715      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.715      ;
+; -1.238 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.716      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                    ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.249 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.947      ;
+; 14.258 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.938      ;
+; 14.355 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.841      ;
+; 14.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.772      ;
+; 14.492 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.704      ;
+; 14.578 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.629      ;
+; 14.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.626      ;
+; 14.588 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.619      ;
+; 14.675 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.532      ;
+; 14.683 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.524      ;
+; 14.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.393      ;
+; 14.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.392      ;
+; 14.822 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.385      ;
+; 14.823 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.384      ;
+; 14.920 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.287      ;
+; 15.041 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.155      ;
+; 15.050 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.146      ;
+; 15.057 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.808     ; 4.150      ;
+; 15.094 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.102      ;
+; 15.146 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 4.050      ;
+; 15.247 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 3.949      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 3.913      ;
+; 15.355 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 3.841      ;
+; 15.402 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 3.794      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 3.754      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.644 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.307      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.653 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.298      ;
+; 15.725 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.819     ; 3.471      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.201      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.132      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
+; 15.887 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.064      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                   ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.714      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.598 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.816      ;
+; 1.822 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.059      ;
+; 1.822 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.059      ;
+; 1.822 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.059      ;
+; 1.822 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.059      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.341      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.390 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.080      ; 2.627      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.400 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 2.626      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.431 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.650      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
+; 2.610 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.079      ; 2.846      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.024 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.650     ; 2.531      ;
+; 4.051 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.677     ; 2.531      ;
+; 4.051 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.677     ; 2.531      ;
+; 4.051 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.677     ; 2.531      ;
+; 4.051 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.677     ; 2.531      ;
+; 4.051 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.677     ; 2.531      ;
+; 4.051 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.677     ; 2.531      ;
+; 4.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.531      ;
+; 4.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.531      ;
+; 4.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.531      ;
+; 4.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.531      ;
+; 4.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.531      ;
+; 4.057 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.535      ;
+; 4.057 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.535      ;
+; 4.060 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.531      ;
+; 4.060 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.531      ;
+; 4.060 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.531      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.532      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.532      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.066 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.533      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.525      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.699     ; 2.525      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.524      ;
+; 4.067 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.528      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.079 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.533      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.082 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.708     ; 2.531      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.091 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.716     ; 2.532      ;
+; 4.093 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.715     ; 2.535      ;
+; 4.093 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.715     ; 2.535      ;
+; 4.093 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.715     ; 2.535      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                       ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                   ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.735 ; 3.965        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0   ;
+; 3.735 ; 3.965        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0    ;
+; 3.735 ; 3.965        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg         ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0   ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0    ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg         ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                            ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0  ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                           ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                           ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                           ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                           ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                           ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                           ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0  ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM[1]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                            ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]                                                                                                                          ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                                                          ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                          ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                             ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                               ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                   ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ;
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                  ;
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[8]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.827 ; 5.374 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.827 ; 5.374 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 4.037 ; 4.669 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.447 ; 5.058 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.860 ; 4.391 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 4.280 ; 4.851 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 4.267 ; 4.852 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 4.162 ; 4.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 4.418 ; 4.986 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 4.444 ; 5.042 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.340 ; 4.921 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.447 ; 5.058 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.159 ; 4.658 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 4.397 ; 4.991 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.972 ; 4.482 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.930 ; 4.434 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 4.172 ; 4.687 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 4.194 ; 4.685 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 4.146 ; 4.637 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.846 ; -2.409 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -2.241 ; -2.884 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.846 ; -2.409 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -3.175 ; -3.685 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -3.175 ; -3.685 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -3.578 ; -4.127 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -3.566 ; -4.129 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -3.464 ; -3.986 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -3.722 ; -4.279 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -3.748 ; -4.333 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.636 ; -4.195 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.750 ; -4.348 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -3.462 ; -3.943 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -3.703 ; -4.284 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -3.283 ; -3.774 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -3.241 ; -3.728 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -3.475 ; -3.970 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -3.497 ; -3.969 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.450 ; -3.922 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.620  ; 6.470  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.741  ; 5.690  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.620  ; 6.470  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.642  ; 5.675  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.642  ; 5.675  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.517  ; 5.545  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.725  ; 3.635  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.452  ; 3.339  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.624  ; 3.532  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.725  ; 3.635  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.560  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.506  ; 3.410  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.240  ; 3.149  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.048  ; 2.959  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.438  ; 3.381  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.037  ; 2.950  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.356  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.317  ; 3.214  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.329  ; 3.244  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.479  ; 3.388  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.477  ; 3.375  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.203  ; 3.103  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.361  ; 3.263  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.434  ; 7.042  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.245  ; 5.015  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.294  ; 5.160  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.657  ; 5.476  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.434  ; 7.042  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.470  ; 5.368  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.273  ; 5.139  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.443  ; 5.342  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.680  ; 5.593  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.962  ; 4.784  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.766  ; 4.701  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.445  ; 5.324  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.339  ; 5.253  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.447  ; 5.341  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.880  ; 4.786  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.880  ; 4.778  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.572  ; 5.503  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.614  ; 3.575  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.372  ; 3.275  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.280  ; 3.212  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.450  ; 5.118  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.575 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.703 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 5.612  ; 5.557  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.612  ; 5.557  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.457  ; 6.307  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.517  ; 5.544  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.517  ; 5.544  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.392  ; 5.424  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.615  ; 2.526  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.013  ; 2.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.179  ; 3.086  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.276  ; 3.184  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.117  ; 3.047  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.066  ; 2.968  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.809  ; 2.717  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.625  ; 2.535  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.001  ; 2.941  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.615  ; 2.526  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.921  ; 2.836  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.884  ; 2.781  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.895  ; 2.808  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.039  ; 2.947  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.037  ; 2.934  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.774  ; 2.673  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.924  ; 2.826  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.753  ; 3.647  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.855  ; 3.711  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.263  ; 4.176  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.138  ; 4.032  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.930  ; 5.608  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.154  ; 4.045  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.255  ; 4.169  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.300  ; 4.211  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.288  ; 4.227  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.156  ; 4.056  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.947  ; 3.833  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.273  ; 4.212  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.753  ; 3.647  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.388  ; 4.317  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.116  ; 3.971  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.992  ; 3.888  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.266  ; 4.165  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.168  ; 3.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.936  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.849  ; 2.778  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.013  ; 4.680  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.948 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.075 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 8.576 ; 8.521 ; 9.162 ; 9.128 ;
+; SW[4]      ; VGA_B[1]    ; 8.547 ; 8.452 ; 9.114 ; 9.016 ;
+; SW[4]      ; VGA_B[2]    ; 8.461 ; 8.340 ; 9.099 ; 8.992 ;
+; SW[4]      ; VGA_B[3]    ; 8.366 ; 8.284 ; 8.926 ; 8.836 ;
+; SW[4]      ; VGA_G[0]    ; 8.084 ; 7.953 ; 8.640 ; 8.517 ;
+; SW[4]      ; VGA_G[1]    ; 9.132 ; 9.026 ; 9.697 ; 9.584 ;
+; SW[4]      ; VGA_G[2]    ; 8.850 ; 8.727 ; 9.441 ; 9.318 ;
+; SW[4]      ; VGA_G[3]    ; 9.081 ; 8.945 ; 9.681 ; 9.528 ;
+; SW[4]      ; VGA_R[0]    ; 8.613 ; 8.492 ; 9.241 ; 9.111 ;
+; SW[4]      ; VGA_R[1]    ; 8.997 ; 8.886 ; 9.556 ; 9.437 ;
+; SW[4]      ; VGA_R[2]    ; 8.636 ; 8.479 ; 9.283 ; 9.117 ;
+; SW[4]      ; VGA_R[3]    ; 9.087 ; 8.940 ; 9.679 ; 9.532 ;
+; SW[5]      ; VGA_B[0]    ; 8.730 ; 8.666 ; 9.313 ; 9.264 ;
+; SW[5]      ; VGA_B[1]    ; 8.378 ; 8.283 ; 8.983 ; 8.888 ;
+; SW[5]      ; VGA_B[2]    ; 8.351 ; 8.244 ; 8.951 ; 8.844 ;
+; SW[5]      ; VGA_B[3]    ; 8.212 ; 8.126 ; 8.829 ; 8.747 ;
+; SW[5]      ; VGA_G[0]    ; 8.424 ; 8.292 ; 9.020 ; 8.897 ;
+; SW[5]      ; VGA_G[1]    ; 9.125 ; 9.019 ; 9.760 ; 9.654 ;
+; SW[5]      ; VGA_G[2]    ; 8.202 ; 8.079 ; 8.733 ; 8.610 ;
+; SW[5]      ; VGA_G[3]    ; 8.731 ; 8.590 ; 9.286 ; 9.133 ;
+; SW[5]      ; VGA_R[0]    ; 8.231 ; 8.101 ; 8.847 ; 8.717 ;
+; SW[5]      ; VGA_R[1]    ; 8.846 ; 8.731 ; 9.460 ; 9.349 ;
+; SW[5]      ; VGA_R[2]    ; 8.533 ; 8.367 ; 9.135 ; 8.969 ;
+; SW[5]      ; VGA_R[3]    ; 8.860 ; 8.691 ; 9.466 ; 9.319 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 8.280 ; 8.190 ; 8.843 ; 8.753 ;
+; SW[4]      ; VGA_B[1]    ; 7.697 ; 7.603 ; 8.301 ; 8.148 ;
+; SW[4]      ; VGA_B[2]    ; 8.136 ; 8.035 ; 8.726 ; 8.599 ;
+; SW[4]      ; VGA_B[3]    ; 7.744 ; 7.630 ; 8.295 ; 8.172 ;
+; SW[4]      ; VGA_G[0]    ; 7.866 ; 7.740 ; 8.415 ; 8.282 ;
+; SW[4]      ; VGA_G[1]    ; 8.411 ; 8.307 ; 8.995 ; 8.832 ;
+; SW[4]      ; VGA_G[2]    ; 8.488 ; 8.352 ; 9.087 ; 8.891 ;
+; SW[4]      ; VGA_G[3]    ; 7.858 ; 7.784 ; 8.465 ; 8.255 ;
+; SW[4]      ; VGA_R[0]    ; 8.331 ; 8.209 ; 8.906 ; 8.779 ;
+; SW[4]      ; VGA_R[1]    ; 8.350 ; 8.207 ; 8.901 ; 8.749 ;
+; SW[4]      ; VGA_R[2]    ; 8.353 ; 8.196 ; 8.946 ; 8.784 ;
+; SW[4]      ; VGA_R[3]    ; 8.511 ; 8.356 ; 9.099 ; 8.917 ;
+; SW[5]      ; VGA_B[0]    ; 7.831 ; 7.717 ; 8.387 ; 8.305 ;
+; SW[5]      ; VGA_B[1]    ; 8.099 ; 7.993 ; 8.657 ; 8.568 ;
+; SW[5]      ; VGA_B[2]    ; 7.680 ; 7.574 ; 8.287 ; 8.122 ;
+; SW[5]      ; VGA_B[3]    ; 7.991 ; 7.878 ; 8.564 ; 8.451 ;
+; SW[5]      ; VGA_G[0]    ; 7.708 ; 7.571 ; 8.271 ; 8.173 ;
+; SW[5]      ; VGA_G[1]    ; 8.758 ; 8.659 ; 9.399 ; 9.232 ;
+; SW[5]      ; VGA_G[2]    ; 7.447 ; 7.282 ; 7.975 ; 7.801 ;
+; SW[5]      ; VGA_G[3]    ; 8.362 ; 8.276 ; 8.927 ; 8.738 ;
+; SW[5]      ; VGA_R[0]    ; 7.715 ; 7.592 ; 8.283 ; 8.190 ;
+; SW[5]      ; VGA_R[1]    ; 8.599 ; 8.457 ; 9.170 ; 9.028 ;
+; SW[5]      ; VGA_R[2]    ; 8.000 ; 7.842 ; 8.551 ; 8.423 ;
+; SW[5]      ; VGA_R[3]    ; 8.566 ; 8.390 ; 9.125 ; 8.956 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.125 ; 3.125 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.644 ; 3.644 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.377 ; 3.377 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.387 ; 3.387 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.125 ; 3.125 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.344 ; 3.344 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.377 ; 3.377 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.364 ; 3.364 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.606 ; 3.606 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.470 ; 3.470 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.470 ; 3.470 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.460 ; 3.460 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.654 ; 3.654 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.644 ; 3.644 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.344 ; 3.344 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.419 ; 2.419 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.917 ; 2.917 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.661 ; 2.661 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.671 ; 2.671 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.419 ; 2.419 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.629 ; 2.629 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.661 ; 2.661 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.649 ; 2.649 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.880 ; 2.880 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.751 ; 2.751 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.751 ; 2.751 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.937 ; 2.937 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.741 ; 2.741 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.927 ; 2.927 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.937 ; 2.937 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.917 ; 2.917 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.629 ; 2.629 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.058     ; 3.160     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.584     ; 3.686     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.311     ; 3.413     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.321     ; 3.423     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.058     ; 3.160     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.283     ; 3.385     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.311     ; 3.413     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.303     ; 3.405     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.526     ; 3.628     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.419     ; 3.521     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.419     ; 3.521     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.604     ; 3.706     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.409     ; 3.511     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.594     ; 3.696     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.604     ; 3.706     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.584     ; 3.686     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.283     ; 3.385     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.453     ; 2.549     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.957     ; 3.053     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.695     ; 2.791     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.705     ; 2.801     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.453     ; 2.549     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.668     ; 2.764     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.695     ; 2.791     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.688     ; 2.784     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.902     ; 2.998     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.800     ; 2.896     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.800     ; 2.896     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.977     ; 3.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.790     ; 2.886     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.967     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.977     ; 3.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.957     ; 3.053     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.668     ; 2.764     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 10.811 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 10.811                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 6.774        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.037        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 10.891                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.266        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 3.625        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 10.947                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.749        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.198        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.196                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 3.931        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.259                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.006        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.309                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.499        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.810        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.377                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.131        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.246        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.379                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.127        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.421                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 6.421        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.000        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.423                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.844        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.579        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.438                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.173        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.448                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.128        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.320        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.542                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.291        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.634                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.123        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.511        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.639                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.144        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 4.495        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.650                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.266        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.384        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.665                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.181        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.484        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.704                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.033        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.671        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.721                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.456        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.729                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.104        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.625        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.733                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.103        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.630        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.735                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.266        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.469        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.780                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.155        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.625        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.786                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.156        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.630        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.843                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.981        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.862        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.845                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 6.897        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.948        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.923                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.144        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 4.779        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.925                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.153        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.772        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.938                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.673        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.942                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.746        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.196        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.016                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.108        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.908        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.019                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 6.872        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.147        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.062                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.154        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.908        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.133                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 6.995        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.138        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.143                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.110        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.033        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.239                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.149        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.090        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.356                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.267        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.089        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.404                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.143        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.261        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.428                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.121        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.307        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.504                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.178        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.326        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                         ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 205.04 MHz ; 205.04 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 248.94 MHz ; 248.94 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.084 ; -1.260        ;
+; CLOCK_50                                            ; 15.983 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.283 ; 0.000         ;
+; CLOCK_50                                            ; 0.312 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.758 ; -148.233      ;
+; CLOCK_50                                            ; 14.888 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.358 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.530 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.740 ; 0.000         ;
+; CLOCK_50                                            ; 9.562 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                             ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; -0.084 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 1.899      ;
+; 0.064  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 2.038      ;
+; 0.064  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 2.038      ;
+; 0.064  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 2.038      ;
+; 0.064  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 2.038      ;
+; 0.077  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.907     ; 2.031      ;
+; 0.077  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.907     ; 2.031      ;
+; 0.077  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.907     ; 2.031      ;
+; 0.138  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.912     ; 1.965      ;
+; 0.138  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.912     ; 1.965      ;
+; 0.138  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.912     ; 1.965      ;
+; 0.138  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.912     ; 1.965      ;
+; 0.138  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.912     ; 1.965      ;
+; 0.138  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.912     ; 1.965      ;
+; 0.178  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.954      ;
+; 0.178  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.954      ;
+; 0.178  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.954      ;
+; 0.178  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.954      ;
+; 0.178  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.954      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.210  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.916      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.229  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.913     ; 1.873      ;
+; 0.251  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.881      ;
+; 0.251  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.881      ;
+; 0.251  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.883     ; 1.881      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 0.279  ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.828      ;
+; 3.123  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.805      ;
+; 3.123  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.805      ;
+; 3.123  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.805      ;
+; 3.164  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.241      ; 5.092      ;
+; 3.164  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.241      ; 5.092      ;
+; 3.164  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.241      ; 5.092      ;
+; 3.174  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.237      ; 5.078      ;
+; 3.187  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.741      ;
+; 3.187  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.741      ;
+; 3.187  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.741      ;
+; 3.188  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.242      ; 5.069      ;
+; 3.188  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.242      ; 5.069      ;
+; 3.188  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.242      ; 5.069      ;
+; 3.210  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.236      ; 5.041      ;
+; 3.214  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 4.713      ;
+; 3.214  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 4.713      ;
+; 3.214  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 4.713      ;
+; 3.223  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.705      ;
+; 3.223  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.087     ; 4.705      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                              ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                       ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.983 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 3.316      ;
+; 16.012 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 3.287      ;
+; 16.065 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 3.234      ;
+; 16.172 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 3.127      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.742      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.191 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.734      ;
+; 16.241 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 3.058      ;
+; 16.266 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 3.033      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.654      ;
+; 16.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.607      ;
+; 16.326 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.599      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.357 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.579      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.557      ;
+; 16.372 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 2.927      ;
+; 16.395 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.716     ; 2.904      ;
+; 16.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]            ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.550      ;
+; 16.406 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.090     ; 3.519      ;
+; 16.422 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]            ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.532      ;
+; 16.465 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]             ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.061     ; 3.489      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.479 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.457      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.079     ; 3.455      ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.283 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.342      ; 0.794      ;
+; 0.291 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.342      ; 0.802      ;
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.342      ; 0.812      ;
+; 0.305 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.337      ; 0.811      ;
+; 0.307 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.341      ; 0.817      ;
+; 0.309 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.336      ; 0.814      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.342      ; 0.822      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.317 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.333      ; 0.819      ;
+; 0.318 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.337      ; 0.824      ;
+; 0.319 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.341      ; 0.829      ;
+; 0.319 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.519      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.324 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.537      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.341      ; 0.835      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.537      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.329 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.336      ; 0.834      ;
+; 0.330 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.340      ; 0.839      ;
+; 0.330 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.345      ; 0.844      ;
+; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.337      ; 0.841      ;
+; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.342      ; 0.846      ;
+; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0]                                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.536      ;
+; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[5]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.333      ; 0.840      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.539      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.552      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.319 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.519      ;
+; 0.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.538      ;
+; 0.341 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.344 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.544      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.386 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.564      ;
+; 0.468 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.667      ;
+; 0.471 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.671      ;
+; 0.494 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.694      ;
+; 0.495 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.695      ;
+; 0.495 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.694      ;
+; 0.496 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.696      ;
+; 0.497 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.697      ;
+; 0.499 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.699      ;
+; 0.499 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.699      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.704      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.705      ;
+; 0.507 ; ps2:inst6|clk_div[1]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.707      ;
+; 0.507 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.056      ; 0.707      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.520 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.719      ;
+; 0.524 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.723      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.725      ;
+; 0.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.740      ;
+; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.838      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.758 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.985     ; 2.731      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.748 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.973     ; 2.733      ;
+; -0.708 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.983     ; 2.765      ;
+; -0.698 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.971     ; 2.767      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.205     ; 2.408      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.410      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.410      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.598 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.408      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.409      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.404      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.404      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
+; -0.597 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 2.396      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.888 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 4.410      ;
+; 14.896 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 4.402      ;
+; 14.976 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 4.322      ;
+; 15.062 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 4.247      ;
+; 15.103 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 4.195      ;
+; 15.184 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 4.125      ;
+; 15.186 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 4.123      ;
+; 15.193 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 4.116      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 4.046      ;
+; 15.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 4.038      ;
+; 15.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 3.917      ;
+; 15.393 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 3.916      ;
+; 15.400 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 3.909      ;
+; 15.401 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 3.908      ;
+; 15.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 3.828      ;
+; 15.591 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.707      ;
+; 15.597 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.701      ;
+; 15.606 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.692      ;
+; 15.607 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.706     ; 3.702      ;
+; 15.685 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.613      ;
+; 15.713 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.585      ;
+; 15.805 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.493      ;
+; 15.811 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.487      ;
+; 15.920 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 3.396      ;
+; 15.921 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.377      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.836      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.131 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.828      ;
+; 16.171 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.717     ; 3.127      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.211 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.748      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 3.673      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
+; 16.338 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 3.621      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.556      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.422 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.620      ;
+; 1.666 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 1.884      ;
+; 1.666 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 1.884      ;
+; 1.666 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 1.884      ;
+; 1.666 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 1.884      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 1.937 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.145      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.183 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.381      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.073      ; 2.405      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.206 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.412      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 2.579      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.530 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.406     ; 2.268      ;
+; 3.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.432     ; 2.268      ;
+; 3.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.432     ; 2.268      ;
+; 3.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.432     ; 2.268      ;
+; 3.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.432     ; 2.268      ;
+; 3.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.432     ; 2.268      ;
+; 3.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.432     ; 2.268      ;
+; 3.558 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.434     ; 2.268      ;
+; 3.558 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.434     ; 2.268      ;
+; 3.558 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.434     ; 2.268      ;
+; 3.558 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.434     ; 2.268      ;
+; 3.558 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.434     ; 2.268      ;
+; 3.560 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.271      ;
+; 3.560 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.271      ;
+; 3.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.439     ; 2.267      ;
+; 3.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.439     ; 2.267      ;
+; 3.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.439     ; 2.267      ;
+; 3.571 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.268      ;
+; 3.571 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.575 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.268      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.577 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.264      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.261      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.261      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.462     ; 2.260      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.584 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.269      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.461     ; 2.268      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.585 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.270      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.592 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.468     ; 2.268      ;
+; 3.595 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.469     ; 2.270      ;
+; 3.595 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.469     ; 2.270      ;
+; 3.595 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.469     ; 2.270      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                         ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.741 ; 3.971        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.741 ; 3.971        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]                                                                                                                              ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ;
+; 3.747 ; 3.963        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; 3.747 ; 3.963        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; 3.747 ; 3.963        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; 3.747 ; 3.963        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.747 ; 3.963        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.562 ; 9.746        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ;
+; 9.562 ; 9.746        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                  ;
+; 9.562 ; 9.746        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[8]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.279 ; 4.742 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.279 ; 4.742 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.575 ; 4.119 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.844 ; 4.355 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.307 ; 3.753 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.698 ; 4.176 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.677 ; 4.159 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.572 ; 4.039 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.811 ; 4.289 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.841 ; 4.338 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.744 ; 4.228 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.844 ; 4.355 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.581 ; 3.997 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.795 ; 4.287 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.406 ; 3.823 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.363 ; 3.790 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.589 ; 4.015 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.611 ; 4.022 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.567 ; 3.992 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.607 ; -2.074 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.914 ; -2.498 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.607 ; -2.074 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.703 ; -3.135 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -2.703 ; -3.135 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -3.078 ; -3.541 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -3.058 ; -3.525 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -2.957 ; -3.410 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -3.197 ; -3.666 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -3.227 ; -3.713 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.123 ; -3.592 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.230 ; -3.729 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.967 ; -3.371 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -3.183 ; -3.666 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -2.799 ; -3.203 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.757 ; -3.171 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -2.975 ; -3.388 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.995 ; -3.394 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.953 ; -3.365 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.256  ; 6.106  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.456  ; 5.345  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.256  ; 6.106  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.408  ; 5.356  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.408  ; 5.356  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.226  ; 5.308  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.727  ; 3.587  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.465  ; 3.319  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.615  ; 3.474  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.727  ; 3.587  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.569  ; 3.459  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.518  ; 3.379  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.260  ; 3.157  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.085  ; 2.987  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.445  ; 3.348  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.068  ; 2.972  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.375  ; 3.257  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.336  ; 3.204  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.348  ; 3.228  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.493  ; 3.352  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.490  ; 3.350  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.228  ; 3.100  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.379  ; 3.238  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.228  ; 6.811  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.053  ; 4.851  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.113  ; 4.941  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.433  ; 5.208  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.228  ; 6.811  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.263  ; 5.120  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.092  ; 4.924  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.249  ; 5.105  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.451  ; 5.330  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.792  ; 4.617  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.643  ; 4.516  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.256  ; 5.118  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.157  ; 5.032  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.259  ; 5.128  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.750  ; 4.610  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.721  ; 4.581  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.360  ; 5.255  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.610  ; 3.514  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.396  ; 3.252  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.302  ; 3.192  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.466  ; 5.089  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 5.340  ; 5.229  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.340  ; 5.229  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.109  ; 5.959  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.294  ; 5.239  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.294  ; 5.239  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.115  ; 5.198  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.694  ; 2.597  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.075  ; 2.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.221  ; 3.081  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.329  ; 3.190  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.176  ; 3.066  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.128  ; 2.990  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.879  ; 2.774  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.711  ; 2.612  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.059  ; 2.960  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.694  ; 2.597  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.991  ; 2.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.953  ; 2.821  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.964  ; 2.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.103  ; 2.964  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.101  ; 2.961  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.849  ; 2.721  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.992  ; 2.852  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.742  ; 3.583  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.829  ; 3.655  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.209  ; 4.061  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.096  ; 3.926  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.902  ; 5.538  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.097  ; 3.938  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.201  ; 4.056  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.235  ; 4.088  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.232  ; 4.118  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.101  ; 3.944  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.925  ; 3.786  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.216  ; 4.117  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.742  ; 3.583  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.322  ; 4.195  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.079  ; 3.927  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.956  ; 3.804  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.210  ; 4.052  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.216  ; 3.119  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.009  ; 2.867  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.920  ; 2.810  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.078  ; 4.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.777 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.922 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 7.938 ; 7.806 ; 8.429 ; 8.325 ;
+; SW[4]      ; VGA_B[1]    ; 7.895 ; 7.762 ; 8.384 ; 8.237 ;
+; SW[4]      ; VGA_B[2]    ; 7.830 ; 7.649 ; 8.355 ; 8.200 ;
+; SW[4]      ; VGA_B[3]    ; 7.754 ; 7.621 ; 8.245 ; 8.104 ;
+; SW[4]      ; VGA_G[0]    ; 7.509 ; 7.333 ; 7.981 ; 7.805 ;
+; SW[4]      ; VGA_G[1]    ; 8.463 ; 8.279 ; 8.954 ; 8.762 ;
+; SW[4]      ; VGA_G[2]    ; 8.201 ; 8.055 ; 8.689 ; 8.543 ;
+; SW[4]      ; VGA_G[3]    ; 8.400 ; 8.229 ; 8.898 ; 8.707 ;
+; SW[4]      ; VGA_R[0]    ; 7.972 ; 7.826 ; 8.510 ; 8.356 ;
+; SW[4]      ; VGA_R[1]    ; 8.340 ; 8.159 ; 8.829 ; 8.640 ;
+; SW[4]      ; VGA_R[2]    ; 8.001 ; 7.787 ; 8.539 ; 8.317 ;
+; SW[4]      ; VGA_R[3]    ; 8.450 ; 8.261 ; 8.927 ; 8.742 ;
+; SW[5]      ; VGA_B[0]    ; 8.090 ; 7.946 ; 8.578 ; 8.454 ;
+; SW[5]      ; VGA_B[1]    ; 7.768 ; 7.627 ; 8.276 ; 8.143 ;
+; SW[5]      ; VGA_B[2]    ; 7.738 ; 7.576 ; 8.244 ; 8.089 ;
+; SW[5]      ; VGA_B[3]    ; 7.630 ; 7.493 ; 8.144 ; 8.013 ;
+; SW[5]      ; VGA_G[0]    ; 7.816 ; 7.632 ; 8.308 ; 8.132 ;
+; SW[5]      ; VGA_G[1]    ; 8.451 ; 8.286 ; 8.964 ; 8.807 ;
+; SW[5]      ; VGA_G[2]    ; 7.614 ; 7.463 ; 8.072 ; 7.913 ;
+; SW[5]      ; VGA_G[3]    ; 8.073 ; 7.900 ; 8.544 ; 8.353 ;
+; SW[5]      ; VGA_R[0]    ; 7.634 ; 7.486 ; 8.152 ; 7.998 ;
+; SW[5]      ; VGA_R[1]    ; 8.215 ; 8.030 ; 8.728 ; 8.549 ;
+; SW[5]      ; VGA_R[2]    ; 7.914 ; 7.697 ; 8.429 ; 8.207 ;
+; SW[5]      ; VGA_R[3]    ; 8.224 ; 8.016 ; 8.723 ; 8.538 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 7.675 ; 7.528 ; 8.155 ; 8.008 ;
+; SW[4]      ; VGA_B[1]    ; 7.147 ; 7.010 ; 7.656 ; 7.470 ;
+; SW[4]      ; VGA_B[2]    ; 7.541 ; 7.388 ; 8.038 ; 7.858 ;
+; SW[4]      ; VGA_B[3]    ; 7.202 ; 7.042 ; 7.683 ; 7.517 ;
+; SW[4]      ; VGA_G[0]    ; 7.318 ; 7.137 ; 7.773 ; 7.592 ;
+; SW[4]      ; VGA_G[1]    ; 7.801 ; 7.642 ; 8.309 ; 8.101 ;
+; SW[4]      ; VGA_G[2]    ; 7.889 ; 7.725 ; 8.391 ; 8.169 ;
+; SW[4]      ; VGA_G[3]    ; 7.314 ; 7.187 ; 7.827 ; 7.578 ;
+; SW[4]      ; VGA_R[0]    ; 7.721 ; 7.574 ; 8.219 ; 8.066 ;
+; SW[4]      ; VGA_R[1]    ; 7.762 ; 7.556 ; 8.240 ; 8.028 ;
+; SW[4]      ; VGA_R[2]    ; 7.749 ; 7.538 ; 8.246 ; 8.029 ;
+; SW[4]      ; VGA_R[3]    ; 7.928 ; 7.742 ; 8.402 ; 8.187 ;
+; SW[5]      ; VGA_B[0]    ; 7.286 ; 7.112 ; 7.761 ; 7.616 ;
+; SW[5]      ; VGA_B[1]    ; 7.526 ; 7.371 ; 8.003 ; 7.870 ;
+; SW[5]      ; VGA_B[2]    ; 7.140 ; 6.983 ; 7.652 ; 7.446 ;
+; SW[5]      ; VGA_B[3]    ; 7.434 ; 7.276 ; 7.917 ; 7.757 ;
+; SW[5]      ; VGA_G[0]    ; 7.174 ; 6.992 ; 7.638 ; 7.491 ;
+; SW[5]      ; VGA_G[1]    ; 8.141 ; 7.986 ; 8.653 ; 8.438 ;
+; SW[5]      ; VGA_G[2]    ; 6.946 ; 6.759 ; 7.394 ; 7.201 ;
+; SW[5]      ; VGA_G[3]    ; 7.761 ; 7.610 ; 8.248 ; 7.999 ;
+; SW[5]      ; VGA_R[0]    ; 7.177 ; 7.028 ; 7.654 ; 7.533 ;
+; SW[5]      ; VGA_R[1]    ; 7.996 ; 7.792 ; 8.477 ; 8.271 ;
+; SW[5]      ; VGA_R[2]    ; 7.442 ; 7.229 ; 7.912 ; 7.727 ;
+; SW[5]      ; VGA_R[3]    ; 7.962 ; 7.751 ; 8.425 ; 8.220 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.091 ; 3.078 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.570 ; 3.557 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.326 ; 3.313 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.336 ; 3.323 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.091 ; 3.078 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.300 ; 3.287 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.326 ; 3.313 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.320 ; 3.307 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.539 ; 3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.410 ; 3.397 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.410 ; 3.397 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.590 ; 3.577 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.400 ; 3.387 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.580 ; 3.567 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.590 ; 3.577 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.570 ; 3.557 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.300 ; 3.287 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.224 ; 2.224 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.685 ; 2.685 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.450 ; 2.450 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.460 ; 2.460 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.224 ; 2.224 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.425 ; 2.425 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.450 ; 2.450 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.445 ; 2.445 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.654 ; 2.654 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.532 ; 2.532 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.532 ; 2.532 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.705 ; 2.705 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.522 ; 2.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.695 ; 2.695 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.705 ; 2.705 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.685 ; 2.685 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.425 ; 2.425 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.104     ; 3.104     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.570     ; 3.570     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.326     ; 3.326     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.336     ; 3.336     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.104     ; 3.104     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.298     ; 3.298     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.326     ; 3.326     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.318     ; 3.318     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.521     ; 3.521     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.427     ; 3.427     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.427     ; 3.427     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.590     ; 3.590     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.417     ; 3.417     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.580     ; 3.580     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.590     ; 3.590     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.570     ; 3.570     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.298     ; 3.298     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.236     ; 2.424     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.684     ; 2.872     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.450     ; 2.638     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.460     ; 2.648     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.236     ; 2.424     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.423     ; 2.611     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.450     ; 2.638     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.443     ; 2.631     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.637     ; 2.825     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.548     ; 2.736     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.548     ; 2.736     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.538     ; 2.726     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.694     ; 2.882     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.684     ; 2.872     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.423     ; 2.611     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.374 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.374                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 6.913        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.461        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.406                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.056        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.488                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.889        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.599        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.679                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.349        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.330        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.770                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.431        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.822                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.670        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.152        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.871                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.533        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.885                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.233        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.652        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.890                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.540        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.905                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 6.588        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.317        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.911                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.974        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.937        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.936                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.223        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.713        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.012                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.675        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.090                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.213        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.877        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.106                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.242        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 4.864        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.115                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.285        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.830        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.123                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.351        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.772        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.143                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.793        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.159                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.144        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.015        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.177                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.980        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.180                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.196        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.984        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.189                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.839        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.223                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.261        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.962        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.223                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.262        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.961        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.277                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.098        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.179        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.287                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.020        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.267        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.346                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.260        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.086        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.355                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.240        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.115        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.379                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.029        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.387                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.880        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.507        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.432                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.201        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.231        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.445                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.261        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.184        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.460                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 6.998        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.462        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.512                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.207        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.305        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.532                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.099        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.433        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.634                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.245        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.389        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.740                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.351        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.389        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.788                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.240        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.548        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.803                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.212        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.591        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.843                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.282        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.561        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.379  ; 0.000         ;
+; CLOCK_50                                            ; 17.476 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.135 ; 0.000         ;
+; CLOCK_50                                            ; 0.187 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.842  ; 0.000         ;
+; CLOCK_50                                            ; 16.628 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 0.814 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.346 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.746 ; 0.000         ;
+; CLOCK_50                                            ; 9.264 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.379 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.132      ;
+; 1.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.254      ;
+; 1.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.254      ;
+; 1.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.254      ;
+; 1.428 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.254      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.217      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.217      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.217      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.324     ; 1.214      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.324     ; 1.214      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.324     ; 1.214      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.324     ; 1.214      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.324     ; 1.214      ;
+; 1.469 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.324     ; 1.214      ;
+; 1.502 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.198      ;
+; 1.502 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.198      ;
+; 1.502 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.198      ;
+; 1.502 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.198      ;
+; 1.502 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.198      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.174      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.556 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.308     ; 1.143      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.562 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.124      ;
+; 1.565 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.135      ;
+; 1.565 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.135      ;
+; 1.565 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.135      ;
+; 4.835 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.140      ; 3.312      ;
+; 4.847 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.317      ;
+; 4.853 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.140      ; 3.294      ;
+; 4.854 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.310      ;
+; 4.865 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.299      ;
+; 4.866 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.298      ;
+; 4.872 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.292      ;
+; 4.884 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.057     ; 3.066      ;
+; 4.884 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.057     ; 3.066      ;
+; 4.884 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.057     ; 3.066      ;
+; 4.884 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.280      ;
+; 4.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.140      ; 3.249      ;
+; 4.903 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.139      ; 3.243      ;
+; 4.903 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.140      ; 3.244      ;
+; 4.904 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.143      ; 3.246      ;
+; 4.904 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.143      ; 3.246      ;
+; 4.904 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.143      ; 3.246      ;
+; 4.910 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.140      ; 3.237      ;
+; 4.910 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.157      ; 3.254      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                              ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                       ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.476 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 2.024      ;
+; 17.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 2.004      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 2.001      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.401      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.398      ;
+; 17.594 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 1.906      ;
+; 17.604 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 1.896      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.613 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.336      ;
+; 17.615 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.334      ;
+; 17.618 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.331      ;
+; 17.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 1.855      ;
+; 17.667 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 1.833      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.285      ;
+; 17.680 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.269      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.686 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.263      ;
+; 17.700 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK       ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.507     ; 1.800      ;
+; 17.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.218      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.750 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.206      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 2.196      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
+; 17.753 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 2.203      ;
++--------+-------------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.135 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.461      ;
+; 0.142 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.468      ;
+; 0.148 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.472      ;
+; 0.153 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.479      ;
+; 0.155 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.481      ;
+; 0.156 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.217      ; 0.477      ;
+; 0.158 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.482      ;
+; 0.159 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.217      ; 0.480      ;
+; 0.161 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.215      ; 0.480      ;
+; 0.161 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.485      ;
+; 0.164 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.487      ;
+; 0.166 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.217      ; 0.487      ;
+; 0.169 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.217      ; 0.490      ;
+; 0.171 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.215      ; 0.490      ;
+; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.498      ;
+; 0.175 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.215      ; 0.494      ;
+; 0.175 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.499      ;
+; 0.179 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.185 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.217      ; 0.506      ;
+; 0.185 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.313      ;
+; 0.185 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.313      ;
+; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.192 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[5]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.312      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0]                                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[2]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.316      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.315      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.187 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.194 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.314      ;
+; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.319      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.208 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.231 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.337      ;
+; 0.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.382      ;
+; 0.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.391      ;
+; 0.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.413      ;
+; 0.294 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.414      ;
+; 0.295 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
+; 0.295 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.415      ;
+; 0.296 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
+; 0.296 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.416      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.300 ; ps2:inst6|clk_div[1]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.301 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.421      ;
+; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.424      ;
+; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.428      ;
+; 0.311 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.430      ;
+; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.431      ;
+; 0.316 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.435      ;
+; 0.327 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.446      ;
+; 0.370 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.489      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.842 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.773      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.849 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.775      ;
+; 0.878 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.791      ;
+; 0.885 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.351     ; 1.793      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.585      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.500     ; 1.586      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.921 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.583      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.584      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.586      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.586      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.508     ; 1.577      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.508     ; 1.577      ;
+; 0.922 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.508     ; 1.577      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 16.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.871      ;
+; 16.631 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.868      ;
+; 16.693 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.806      ;
+; 16.751 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.755      ;
+; 16.766 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.733      ;
+; 16.830 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.676      ;
+; 16.833 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.673      ;
+; 16.833 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.673      ;
+; 16.893 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.613      ;
+; 16.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.611      ;
+; 16.966 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.540      ;
+; 16.968 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.538      ;
+; 16.969 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.537      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.536      ;
+; 17.033 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.473      ;
+; 17.104 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.501     ; 2.402      ;
+; 17.115 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.384      ;
+; 17.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.380      ;
+; 17.166 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.333      ;
+; 17.180 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.319      ;
+; 17.241 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.258      ;
+; 17.253 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.246      ;
+; 17.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.202      ;
+; 17.320 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 2.179      ;
+; 17.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2           ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.494     ; 2.160      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.471      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.468      ;
+; 17.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.508     ; 1.975      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.564 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.406      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.622 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.030     ; 2.355      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
+; 17.637 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.333      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.814 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.933      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 0.898 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.017      ;
+; 1.029 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.162      ;
+; 1.029 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.162      ;
+; 1.029 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.162      ;
+; 1.029 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.162      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.198 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.046      ; 1.328      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.345 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.464      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.353 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.049      ; 1.486      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.369 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.495      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
+; 1.415 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 1.534      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.346 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -0.990     ; 1.440      ;
+; 2.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.002     ; 1.440      ;
+; 2.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.002     ; 1.440      ;
+; 2.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.002     ; 1.440      ;
+; 2.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.002     ; 1.440      ;
+; 2.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.002     ; 1.440      ;
+; 2.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.002     ; 1.440      ;
+; 2.360 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.440      ;
+; 2.360 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.440      ;
+; 2.360 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.440      ;
+; 2.360 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.440      ;
+; 2.360 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.440      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.442      ;
+; 2.363 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.442      ;
+; 2.364 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.008     ; 1.440      ;
+; 2.364 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.008     ; 1.440      ;
+; 2.364 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.008     ; 1.440      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.439      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.439      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.443      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.434      ;
+; 2.370 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.437      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.371 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.443      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.440      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.377 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.378 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.020     ; 1.442      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.024     ; 1.441      ;
+; 2.383 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.028     ; 1.439      ;
+; 2.383 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.028     ; 1.439      ;
+; 2.383 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.028     ; 1.439      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.751 ; 3.981        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]                                                                                                                             ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]                                                                                                                              ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ;
+; 3.783 ; 3.967        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.264 ; 9.448        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 2.702 ; 3.504 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 2.702 ; 3.504 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 2.297 ; 3.118 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.573 ; 3.382 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.218 ; 2.990 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.472 ; 3.284 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.440 ; 3.268 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.408 ; 3.213 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.527 ; 3.329 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.561 ; 3.371 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.483 ; 3.318 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.573 ; 3.382 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.394 ; 3.166 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.533 ; 3.336 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.288 ; 3.052 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.259 ; 3.019 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.375 ; 3.168 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.412 ; 3.195 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.381 ; 3.155 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.045 ; -1.863 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.241 ; -2.135 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.045 ; -1.863 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.822 ; -2.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -1.822 ; -2.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -2.066 ; -2.862 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -2.035 ; -2.845 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -2.004 ; -2.792 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -2.123 ; -2.915 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -2.157 ; -2.956 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.077 ; -2.894 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.169 ; -2.967 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.992 ; -2.749 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.131 ; -2.924 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -1.890 ; -2.639 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.861 ; -2.607 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.974 ; -2.751 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.009 ; -2.776 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.979 ; -2.738 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.949  ; 3.818  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.430  ; 3.441  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 3.949  ; 3.818  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.352  ; 3.448  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.352  ; 3.448  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.345  ; 3.275  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.258  ; 2.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.090  ; 2.074  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.188  ; 2.201  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.258  ; 2.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.162  ; 2.176  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.132  ; 2.131  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.973  ; 1.956  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.873  ; 1.845  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.112  ; 2.108  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.856  ; 1.830  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.044  ; 2.036  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.020  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.026  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.112  ; 2.103  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.112  ; 2.101  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.939  ; 1.909  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.025  ; 1.999  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 4.805  ; 4.536  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.109  ; 3.025  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.206  ; 3.159  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.405  ; 3.347  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 4.805  ; 4.536  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 3.287  ; 3.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.197  ; 3.154  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.290  ; 3.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 3.441  ; 3.424  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.989  ; 2.899  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.835  ; 2.883  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.321  ; 3.293  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.229  ; 3.210  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.327  ; 3.294  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.898  ; 2.952  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.906  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.341  ; 3.360  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.196  ; 2.209  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.036  ; 2.011  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.010  ; 1.987  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.581  ; 3.368  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.313 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.366 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.356  ; 3.363  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.356  ; 3.363  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 3.854  ; 3.724  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.280  ; 3.369  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.280  ; 3.369  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.271  ; 3.207  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.604  ; 1.576  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.829  ; 1.811  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 1.924  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.991  ; 2.001  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.899  ; 1.909  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.871  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.716  ; 1.697  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.621  ; 1.590  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.851  ; 1.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.604  ; 1.576  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.786  ; 1.775  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.762  ; 1.742  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.769  ; 1.753  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.850  ; 1.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.850  ; 1.837  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.684  ; 1.652  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.765  ; 1.737  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.241  ; 2.243  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.282  ; 2.281  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.530  ; 2.561  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.459  ; 2.485  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.864  ; 3.681  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.459  ; 2.488  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.530  ; 2.573  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.561  ; 2.584  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.567  ; 2.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.481  ; 2.497  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.337  ; 2.288  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.568  ; 2.627  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.241  ; 2.243  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.625  ; 2.659  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.422  ; 2.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.367  ; 2.378  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.501  ; 2.553  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.931  ; 1.940  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.777  ; 1.750  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.753  ; 1.727  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.321  ; 3.106  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 5.004 ; 5.045 ; 5.845 ; 5.886 ;
+; SW[4]      ; VGA_B[1]    ; 5.011 ; 5.005 ; 5.833 ; 5.827 ;
+; SW[4]      ; VGA_B[2]    ; 4.948 ; 4.922 ; 5.823 ; 5.797 ;
+; SW[4]      ; VGA_B[3]    ; 4.902 ; 4.906 ; 5.731 ; 5.735 ;
+; SW[4]      ; VGA_G[0]    ; 4.744 ; 4.736 ; 5.555 ; 5.547 ;
+; SW[4]      ; VGA_G[1]    ; 5.346 ; 5.365 ; 6.174 ; 6.193 ;
+; SW[4]      ; VGA_G[2]    ; 5.161 ; 5.184 ; 6.008 ; 6.031 ;
+; SW[4]      ; VGA_G[3]    ; 5.298 ; 5.274 ; 6.144 ; 6.120 ;
+; SW[4]      ; VGA_R[0]    ; 5.024 ; 5.031 ; 5.906 ; 5.906 ;
+; SW[4]      ; VGA_R[1]    ; 5.255 ; 5.291 ; 6.082 ; 6.118 ;
+; SW[4]      ; VGA_R[2]    ; 5.013 ; 5.030 ; 5.886 ; 5.896 ;
+; SW[4]      ; VGA_R[3]    ; 5.299 ; 5.334 ; 6.133 ; 6.168 ;
+; SW[5]      ; VGA_B[0]    ; 5.094 ; 5.132 ; 5.934 ; 5.975 ;
+; SW[5]      ; VGA_B[1]    ; 4.927 ; 4.921 ; 5.763 ; 5.757 ;
+; SW[5]      ; VGA_B[2]    ; 4.907 ; 4.881 ; 5.742 ; 5.716 ;
+; SW[5]      ; VGA_B[3]    ; 4.829 ; 4.833 ; 5.658 ; 5.662 ;
+; SW[5]      ; VGA_G[0]    ; 4.953 ; 4.945 ; 5.755 ; 5.754 ;
+; SW[5]      ; VGA_G[1]    ; 5.352 ; 5.371 ; 6.201 ; 6.220 ;
+; SW[5]      ; VGA_G[2]    ; 4.805 ; 4.828 ; 5.580 ; 5.603 ;
+; SW[5]      ; VGA_G[3]    ; 5.098 ; 5.074 ; 5.902 ; 5.878 ;
+; SW[5]      ; VGA_R[0]    ; 4.836 ; 4.836 ; 5.665 ; 5.665 ;
+; SW[5]      ; VGA_R[1]    ; 5.181 ; 5.217 ; 6.010 ; 6.046 ;
+; SW[5]      ; VGA_R[2]    ; 4.966 ; 4.976 ; 5.808 ; 5.818 ;
+; SW[5]      ; VGA_R[3]    ; 5.148 ; 5.171 ; 5.983 ; 6.018 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 4.831 ; 4.842 ; 5.644 ; 5.655 ;
+; SW[4]      ; VGA_B[1]    ; 4.527 ; 4.526 ; 5.373 ; 5.335 ;
+; SW[4]      ; VGA_B[2]    ; 4.761 ; 4.742 ; 5.597 ; 5.573 ;
+; SW[4]      ; VGA_B[3]    ; 4.554 ; 4.540 ; 5.382 ; 5.361 ;
+; SW[4]      ; VGA_G[0]    ; 4.592 ; 4.590 ; 5.400 ; 5.398 ;
+; SW[4]      ; VGA_G[1]    ; 4.925 ; 4.948 ; 5.778 ; 5.764 ;
+; SW[4]      ; VGA_G[2]    ; 4.944 ; 4.959 ; 5.793 ; 5.781 ;
+; SW[4]      ; VGA_G[3]    ; 4.604 ; 4.631 ; 5.457 ; 5.405 ;
+; SW[4]      ; VGA_R[0]    ; 4.863 ; 4.867 ; 5.708 ; 5.712 ;
+; SW[4]      ; VGA_R[1]    ; 4.891 ; 4.909 ; 5.716 ; 5.727 ;
+; SW[4]      ; VGA_R[2]    ; 4.851 ; 4.866 ; 5.687 ; 5.702 ;
+; SW[4]      ; VGA_R[3]    ; 4.979 ; 5.001 ; 5.818 ; 5.823 ;
+; SW[5]      ; VGA_B[0]    ; 4.601 ; 4.601 ; 5.408 ; 5.428 ;
+; SW[5]      ; VGA_B[1]    ; 4.752 ; 4.752 ; 5.560 ; 5.560 ;
+; SW[5]      ; VGA_B[2]    ; 4.523 ; 4.503 ; 5.370 ; 5.313 ;
+; SW[5]      ; VGA_B[3]    ; 4.700 ; 4.682 ; 5.501 ; 5.483 ;
+; SW[5]      ; VGA_G[0]    ; 4.542 ; 4.527 ; 5.344 ; 5.352 ;
+; SW[5]      ; VGA_G[1]    ; 5.119 ; 5.143 ; 5.969 ; 5.975 ;
+; SW[5]      ; VGA_G[2]    ; 4.372 ; 4.377 ; 5.148 ; 5.146 ;
+; SW[5]      ; VGA_G[3]    ; 4.847 ; 4.882 ; 5.655 ; 5.650 ;
+; SW[5]      ; VGA_R[0]    ; 4.545 ; 4.545 ; 5.346 ; 5.365 ;
+; SW[5]      ; VGA_R[1]    ; 5.036 ; 5.050 ; 5.837 ; 5.851 ;
+; SW[5]      ; VGA_R[2]    ; 4.670 ; 4.681 ; 5.477 ; 5.507 ;
+; SW[5]      ; VGA_R[3]    ; 4.984 ; 4.996 ; 5.791 ; 5.806 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.572 ; 2.553 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.866 ; 2.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.701 ; 2.682 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.711 ; 2.692 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.572 ; 2.553 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.693 ; 2.674 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.701 ; 2.682 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.713 ; 2.694 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.821 ; 2.802 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.787 ; 2.768 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.787 ; 2.768 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.886 ; 2.867 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.777 ; 2.758 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.876 ; 2.857 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.886 ; 2.867 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.866 ; 2.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.693 ; 2.674 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.453 ; 1.453 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.735 ; 1.735 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.576 ; 1.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.586 ; 1.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.453 ; 1.453 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.569 ; 1.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.576 ; 1.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.589 ; 1.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.692 ; 1.692 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.660 ; 1.660 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.660 ; 1.660 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.755 ; 1.755 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.650 ; 1.650 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.745 ; 1.745 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.755 ; 1.755 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.735 ; 1.735 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.569 ; 1.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.618     ; 2.618     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.944     ; 2.944     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.768     ; 2.768     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.778     ; 2.778     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.618     ; 2.618     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.757     ; 2.757     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.768     ; 2.768     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.777     ; 2.777     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.902     ; 2.902     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.851     ; 2.851     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.851     ; 2.851     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.964     ; 2.964     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.841     ; 2.841     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.954     ; 2.954     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.964     ; 2.964     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.944     ; 2.944     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.757     ; 2.757     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.497     ; 1.629     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.810     ; 1.942     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.641     ; 1.773     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.651     ; 1.783     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.497     ; 1.629     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.630     ; 1.762     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.641     ; 1.773     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.650     ; 1.782     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.770     ; 1.902     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.722     ; 1.854     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.722     ; 1.854     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.830     ; 1.962     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.712     ; 1.844     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.820     ; 1.952     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.830     ; 1.962     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.810     ; 1.942     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.630     ; 1.762     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 13.104 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.104                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.322        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.782        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.122                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.597        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.525        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.180                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.309        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.871        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.292                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.597        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.695        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.351                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.759        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.377                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.156        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.221        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.414                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.517        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.897        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.414                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.325        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.089        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.433                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.841        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.451                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.852        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.460                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.133        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.327        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.465                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.939        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.508                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.917        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.564                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.038        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.572                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.973        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.575                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.534        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.041        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.594                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.545        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.049        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.608                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.009        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.625                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.600        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.025        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.628                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.476        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.152        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.637                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.114        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.639                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.522        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.117        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.658                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.531        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.127        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.662                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.532        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.130        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.682                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.435        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.247        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.686                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.399        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.287        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.718                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.195        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.735                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.136        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.739                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.529        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.210        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.754                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.306        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.448        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.779                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.358        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.421        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.798                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.271        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.813                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.529        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.284        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.852                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.456        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.396        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.888                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.515        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.373        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.898                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.371        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.973                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.374        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.998                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.474        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.029                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.532        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.497        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.071                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.544        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.527        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Clock                                                ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack                                     ; -0.619  ; 0.135 ; -1.405   ; 0.814   ; 3.735               ;
+;  CLOCK_50                                            ; 15.570  ; 0.187 ; 14.249   ; 0.814   ; 9.264               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.619  ; 0.135 ; -1.405   ; 2.346   ; 3.735               ;
+; Design-wide TNS                                      ; -28.86  ; 0.0   ; -338.209 ; 0.0     ; 0.0                 ;
+;  CLOCK_50                                            ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -28.860 ; 0.000 ; -338.209 ; 0.000   ; 0.000               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.827 ; 5.374 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.827 ; 5.374 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 4.037 ; 4.669 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.447 ; 5.058 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.860 ; 4.391 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 4.280 ; 4.851 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 4.267 ; 4.852 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 4.162 ; 4.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 4.418 ; 4.986 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 4.444 ; 5.042 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.340 ; 4.921 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.447 ; 5.058 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.159 ; 4.658 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 4.397 ; 4.991 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.972 ; 4.482 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.930 ; 4.434 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 4.172 ; 4.687 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 4.194 ; 4.685 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 4.146 ; 4.637 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.045 ; -1.863 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.241 ; -2.135 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.045 ; -1.863 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.822 ; -2.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -1.822 ; -2.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -2.066 ; -2.862 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -2.035 ; -2.845 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -2.004 ; -2.792 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -2.123 ; -2.915 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -2.157 ; -2.956 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.077 ; -2.894 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.169 ; -2.967 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.992 ; -2.749 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.131 ; -2.924 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -1.890 ; -2.639 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.861 ; -2.607 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.974 ; -2.751 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.009 ; -2.776 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.979 ; -2.738 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.620  ; 6.470  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.741  ; 5.690  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.620  ; 6.470  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.642  ; 5.675  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.642  ; 5.675  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.517  ; 5.545  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.727  ; 3.635  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.465  ; 3.339  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.624  ; 3.532  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.727  ; 3.635  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.569  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.518  ; 3.410  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.260  ; 3.157  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.085  ; 2.987  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.445  ; 3.381  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.068  ; 2.972  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.375  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.336  ; 3.214  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.348  ; 3.244  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.493  ; 3.388  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.490  ; 3.375  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.228  ; 3.103  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.379  ; 3.263  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.434  ; 7.042  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.245  ; 5.015  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.294  ; 5.160  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.657  ; 5.476  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.434  ; 7.042  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.470  ; 5.368  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.273  ; 5.139  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.443  ; 5.342  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.680  ; 5.593  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.962  ; 4.784  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.766  ; 4.701  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.445  ; 5.324  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.339  ; 5.253  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.447  ; 5.341  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.880  ; 4.786  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.880  ; 4.778  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.572  ; 5.503  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.614  ; 3.575  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.396  ; 3.275  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.302  ; 3.212  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.466  ; 5.118  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.356  ; 3.363  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.356  ; 3.363  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 3.854  ; 3.724  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.280  ; 3.369  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.280  ; 3.369  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.271  ; 3.207  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.604  ; 1.576  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.829  ; 1.811  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 1.924  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.991  ; 2.001  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.899  ; 1.909  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.871  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.716  ; 1.697  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.621  ; 1.590  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.851  ; 1.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.604  ; 1.576  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.786  ; 1.775  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.762  ; 1.742  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.769  ; 1.753  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.850  ; 1.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.850  ; 1.837  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.684  ; 1.652  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.765  ; 1.737  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.241  ; 2.243  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.282  ; 2.281  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.530  ; 2.561  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.459  ; 2.485  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.864  ; 3.681  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.459  ; 2.488  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.530  ; 2.573  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.561  ; 2.584  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.567  ; 2.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.481  ; 2.497  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.337  ; 2.288  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.568  ; 2.627  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.241  ; 2.243  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.625  ; 2.659  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.422  ; 2.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.367  ; 2.378  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.501  ; 2.553  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.931  ; 1.940  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.777  ; 1.750  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.753  ; 1.727  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.321  ; 3.106  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Progagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 8.576 ; 8.521 ; 9.162 ; 9.128 ;
+; SW[4]      ; VGA_B[1]    ; 8.547 ; 8.452 ; 9.114 ; 9.016 ;
+; SW[4]      ; VGA_B[2]    ; 8.461 ; 8.340 ; 9.099 ; 8.992 ;
+; SW[4]      ; VGA_B[3]    ; 8.366 ; 8.284 ; 8.926 ; 8.836 ;
+; SW[4]      ; VGA_G[0]    ; 8.084 ; 7.953 ; 8.640 ; 8.517 ;
+; SW[4]      ; VGA_G[1]    ; 9.132 ; 9.026 ; 9.697 ; 9.584 ;
+; SW[4]      ; VGA_G[2]    ; 8.850 ; 8.727 ; 9.441 ; 9.318 ;
+; SW[4]      ; VGA_G[3]    ; 9.081 ; 8.945 ; 9.681 ; 9.528 ;
+; SW[4]      ; VGA_R[0]    ; 8.613 ; 8.492 ; 9.241 ; 9.111 ;
+; SW[4]      ; VGA_R[1]    ; 8.997 ; 8.886 ; 9.556 ; 9.437 ;
+; SW[4]      ; VGA_R[2]    ; 8.636 ; 8.479 ; 9.283 ; 9.117 ;
+; SW[4]      ; VGA_R[3]    ; 9.087 ; 8.940 ; 9.679 ; 9.532 ;
+; SW[5]      ; VGA_B[0]    ; 8.730 ; 8.666 ; 9.313 ; 9.264 ;
+; SW[5]      ; VGA_B[1]    ; 8.378 ; 8.283 ; 8.983 ; 8.888 ;
+; SW[5]      ; VGA_B[2]    ; 8.351 ; 8.244 ; 8.951 ; 8.844 ;
+; SW[5]      ; VGA_B[3]    ; 8.212 ; 8.126 ; 8.829 ; 8.747 ;
+; SW[5]      ; VGA_G[0]    ; 8.424 ; 8.292 ; 9.020 ; 8.897 ;
+; SW[5]      ; VGA_G[1]    ; 9.125 ; 9.019 ; 9.760 ; 9.654 ;
+; SW[5]      ; VGA_G[2]    ; 8.202 ; 8.079 ; 8.733 ; 8.610 ;
+; SW[5]      ; VGA_G[3]    ; 8.731 ; 8.590 ; 9.286 ; 9.133 ;
+; SW[5]      ; VGA_R[0]    ; 8.231 ; 8.101 ; 8.847 ; 8.717 ;
+; SW[5]      ; VGA_R[1]    ; 8.846 ; 8.731 ; 9.460 ; 9.349 ;
+; SW[5]      ; VGA_R[2]    ; 8.533 ; 8.367 ; 9.135 ; 8.969 ;
+; SW[5]      ; VGA_R[3]    ; 8.860 ; 8.691 ; 9.466 ; 9.319 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Progagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 4.831 ; 4.842 ; 5.644 ; 5.655 ;
+; SW[4]      ; VGA_B[1]    ; 4.527 ; 4.526 ; 5.373 ; 5.335 ;
+; SW[4]      ; VGA_B[2]    ; 4.761 ; 4.742 ; 5.597 ; 5.573 ;
+; SW[4]      ; VGA_B[3]    ; 4.554 ; 4.540 ; 5.382 ; 5.361 ;
+; SW[4]      ; VGA_G[0]    ; 4.592 ; 4.590 ; 5.400 ; 5.398 ;
+; SW[4]      ; VGA_G[1]    ; 4.925 ; 4.948 ; 5.778 ; 5.764 ;
+; SW[4]      ; VGA_G[2]    ; 4.944 ; 4.959 ; 5.793 ; 5.781 ;
+; SW[4]      ; VGA_G[3]    ; 4.604 ; 4.631 ; 5.457 ; 5.405 ;
+; SW[4]      ; VGA_R[0]    ; 4.863 ; 4.867 ; 5.708 ; 5.712 ;
+; SW[4]      ; VGA_R[1]    ; 4.891 ; 4.909 ; 5.716 ; 5.727 ;
+; SW[4]      ; VGA_R[2]    ; 4.851 ; 4.866 ; 5.687 ; 5.702 ;
+; SW[4]      ; VGA_R[3]    ; 4.979 ; 5.001 ; 5.818 ; 5.823 ;
+; SW[5]      ; VGA_B[0]    ; 4.601 ; 4.601 ; 5.408 ; 5.428 ;
+; SW[5]      ; VGA_B[1]    ; 4.752 ; 4.752 ; 5.560 ; 5.560 ;
+; SW[5]      ; VGA_B[2]    ; 4.523 ; 4.503 ; 5.370 ; 5.313 ;
+; SW[5]      ; VGA_B[3]    ; 4.700 ; 4.682 ; 5.501 ; 5.483 ;
+; SW[5]      ; VGA_G[0]    ; 4.542 ; 4.527 ; 5.344 ; 5.352 ;
+; SW[5]      ; VGA_G[1]    ; 5.119 ; 5.143 ; 5.969 ; 5.975 ;
+; SW[5]      ; VGA_G[2]    ; 4.372 ; 4.377 ; 5.148 ; 5.146 ;
+; SW[5]      ; VGA_G[3]    ; 4.847 ; 4.882 ; 5.655 ; 5.650 ;
+; SW[5]      ; VGA_R[0]    ; 4.545 ; 4.545 ; 5.346 ; 5.365 ;
+; SW[5]      ; VGA_R[1]    ; 5.036 ; 5.050 ; 5.837 ; 5.851 ;
+; SW[5]      ; VGA_R[2]    ; 4.670 ; 4.681 ; 5.477 ; 5.507 ;
+; SW[5]      ; VGA_R[3]    ; 4.984 ; 4.996 ; 5.791 ; 5.806 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                       ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin              ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; GPIO_1_CLKIN[1]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[15]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[14]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[13]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[12]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[11]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[10]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[9]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[8]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[31]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[30]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[29]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[28]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[27]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[26]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[25]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[24]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[23]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[22]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[21]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[20]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[19]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[18]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[17]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[16]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[15]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[14]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[13]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[12]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[11]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_DAT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_CLK                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1_CLKIN[0]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                       ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3231     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11645    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3231     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11645    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                           ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                            ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 5     ; 5    ;
+; Unconstrained Input Ports       ; 43    ; 43   ;
+; Unconstrained Input Port Paths  ; 428   ; 428  ;
+; Unconstrained Output Ports      ; 89    ; 89   ;
+; Unconstrained Output Port Paths ; 530   ; 530  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 17:41:23 2016
+Info: Command: quartus_sta DE0_D5M -c DE0_D5M
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.619
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.619       -28.860 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.570         0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.283
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.283         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.358         0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -1.405
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -1.405      -338.209 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.249         0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.496
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     1.496         0.000 CLOCK_50 
+    Info (332119):     4.024         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.735
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.735         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.580         0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 10.811 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.084
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.084        -1.260 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.983         0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.283
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.283         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.312         0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -0.758
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.758      -148.233 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.888         0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.358
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     1.358         0.000 CLOCK_50 
+    Info (332119):     3.530         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.740
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.740         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.562         0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.374 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Fast 1200mV 0C Model
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 1.379
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     1.379         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.476         0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.135
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.135         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.187         0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is 0.842
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.842         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    16.628         0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 0.814
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.814         0.000 CLOCK_50 
+    Info (332119):     2.346         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.746
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     3.746         0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.264         0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 13.104 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings
+    Info: Peak virtual memory: 525 megabytes
+    Info: Processing ended: Tue Mar 01 17:41:26 2016
+    Info: Elapsed time: 00:00:03
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary
new file mode 100644
index 0000000..4a5967c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary
@@ -0,0 +1,125 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.619
+TNS   : -28.860
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : 15.570
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.283
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.405
+TNS   : -338.209
+
+Type  : Slow 1200mV 85C Model Recovery 'CLOCK_50'
+Slack : 14.249
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'CLOCK_50'
+Slack : 1.496
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.024
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.735
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.580
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.084
+TNS   : -1.260
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 15.983
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.283
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.758
+TNS   : -148.233
+
+Type  : Slow 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 14.888
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 1.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.530
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.740
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.562
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.379
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 17.476
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.135
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.187
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.842
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 16.628
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 0.814
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 2.346
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.746
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.264
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..33470dd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
new file mode 100644
index 0000000..278fabe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
@@ -0,0 +1,379 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		VGA_X,							//	VGA X scan coord
+		VGA_Y,							//	VGA Y scan coord
+		VGA_ACTIVE,						//	VGA ACTIVE
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+output	[11:0]		VGA_X;				//	VGA X scan coord
+output	[11:0]		VGA_Y;				//	VGA Y scan coord
+output         VGA_ACTIVE;          // VGA ACTIVE
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[9:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[9:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[9:0]		VGA_B;   				//	VGA Blue[9:0]
+wire	[11:0]		VGA_X;	 				//	VGA X scan 
+wire	[11:0]		VGA_Y;   				//	VGA Y scan
+wire				VGA_ACTIVE;
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:0];
+assign	VGA_G		=	oVGA_G[9:0];
+assign	VGA_B		=	oVGA_B[9:0];
+
+// vga scan coordinates
+wire	[11:0]	oVGA_X;
+wire	[11:0]	oVGA_Y;
+assign	VGA_X		=	oVGA_Y;
+assign	VGA_Y		=	oVGA_X;
+
+// vga output active
+wire 	oVGA_ACTIVE;
+assign VGA_ACTIVE = oVGA_ACTIVE;
+
+
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							// VGA Scan Coordinates
+							.oVGA_X(oVGA_X),
+							.oVGA_Y(oVGA_Y),
+							.oVGA_ACTIVE(oVGA_ACTIVE),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak
new file mode 100644
index 0000000..8059c4c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak
@@ -0,0 +1,369 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		VGA_X,							//	VGA X scan coord
+		VGA_Y,							//	VGA Y scan coord
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+output	[11:0]		VGA_X;				//	VGA X scan coord
+output	[11:0]		VGA_Y;				//	VGA Y scan coord
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[9:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[9:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[9:0]		VGA_B;   				//	VGA Blue[9:0]
+wire	[11:0]		VGA_X;	 				//	VGA X scan 
+wire	[11:0]		VGA_Y;   				//	VGA Y scan
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:0];
+assign	VGA_G		=	oVGA_G[9:0];
+assign	VGA_B		=	oVGA_B[9:0];
+
+
+wire	[11:0]	oVGA_X;
+wire	[11:0]	oVGA_Y;
+assign	VGA_X		=	oVGA_Y;
+assign	VGA_Y		=	oVGA_X;
+
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							// VGA Scan Coordinates
+							.oVGA_X(oVGA_X),
+							.oVGA_Y(oVGA_Y),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v
new file mode 100644
index 0000000..22e2411
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v
@@ -0,0 +1,567 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Sdram_Control_4Port
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module Sdram_Control_4Port(
+		//	HOST Side
+        REF_CLK,
+        RESET_N,
+		CLK,
+		//	FIFO Write Side 1
+        WR1_DATA,
+		WR1,
+		WR1_ADDR,
+		WR1_MAX_ADDR,
+		WR1_LENGTH,
+		WR1_LOAD,
+		WR1_CLK,
+		//	FIFO Write Side 2
+        WR2_DATA,
+		WR2,
+		WR2_ADDR,
+		WR2_MAX_ADDR,
+		WR2_LENGTH,
+		WR2_LOAD,
+		WR2_CLK,
+		//	FIFO Read Side 1
+        RD1_DATA,
+		RD1,
+		RD1_ADDR,
+		RD1_MAX_ADDR,
+		RD1_LENGTH,
+		RD1_LOAD,	
+		RD1_CLK,
+		//	FIFO Read Side 2
+        RD2_DATA,
+		RD2,
+		RD2_ADDR,
+		RD2_MAX_ADDR,
+		RD2_LENGTH,
+		RD2_LOAD,
+		RD2_CLK,
+		//	SDRAM Side
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N,
+        DQ,
+        DQM,
+        );
+
+
+`include        "Sdram_Params.h"
+//	HOST Side
+input                           REF_CLK;                //System Clock
+input                           RESET_N;                //System Reset
+input 							CLK;
+//	FIFO Write Side 1
+input   [`DSIZE-1:0]            WR1_DATA;               //Data input
+input							WR1;					//Write Request
+input	[`ASIZE-1:0]			WR1_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR1_MAX_ADDR;			//Write max address
+input	[8:0]					WR1_LENGTH;				//Write length
+input							WR1_LOAD;				//Write register load & fifo clear
+input							WR1_CLK;				//Write fifo clock
+
+//	FIFO Write Side 2
+input   [`DSIZE-1:0]            WR2_DATA;               //Data input
+input							WR2;					//Write Request
+input	[`ASIZE-1:0]			WR2_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR2_MAX_ADDR;			//Write max address
+input	[8:0]					WR2_LENGTH;				//Write length
+input							WR2_LOAD;				//Write register load & fifo clear
+input							WR2_CLK;				//Write fifo clock
+
+//	FIFO Read Side 1
+output  [`DSIZE-1:0]            RD1_DATA;               //Data output
+input							RD1;					//Read Request
+input	[`ASIZE-1:0]			RD1_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD1_MAX_ADDR;			//Read max address
+input	[8:0]					RD1_LENGTH;				//Read length
+input							RD1_LOAD;				//Read register load & fifo clear
+input							RD1_CLK;				//Read fifo clock
+
+//	FIFO Read Side 2
+output  [`DSIZE-1:0]            RD2_DATA;               //Data output
+input							RD2;					//Read Request
+input	[`ASIZE-1:0]			RD2_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD2_MAX_ADDR;			//Read max address
+input	[8:0]					RD2_LENGTH;				//Read length
+input							RD2_LOAD;				//Read register load & fifo clear
+input							RD2_CLK;				//Read fifo clock
+
+//	SDRAM Side
+output  [11:0]                  SA;                     //SDRAM address output
+output  [1:0]                   BA;                     //SDRAM bank address
+output  [1:0]                   CS_N;                   //SDRAM Chip Selects
+output                          CKE;                    //SDRAM clock enable
+output                          RAS_N;                  //SDRAM Row address Strobe
+output                          CAS_N;                  //SDRAM Column address Strobe
+output                          WE_N;                   //SDRAM write enable
+inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
+output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+
+//	Internal Registers/Wires
+//	Controller
+reg		[`ASIZE-1:0]			mADDR;					//Internal address
+reg		[8:0]					mLENGTH;				//Internal length
+reg		[`ASIZE-1:0]			rWR1_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR1_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR1_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rWR2_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR2_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR2_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rRD1_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD1_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD1_LENGTH;			//Register read length
+reg		[`ASIZE-1:0]			rRD2_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD2_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD2_LENGTH;			//Register read length
+reg		[1:0]					WR_MASK;				//Write port active mask
+reg		[1:0]					RD_MASK;				//Read port active mask
+reg								mWR_DONE;				//Flag write done, 1 pulse SDR_CLK
+reg								mRD_DONE;				//Flag read done, 1 pulse SDR_CLK
+reg								mWR,Pre_WR;				//Internal WR edge capture
+reg								mRD,Pre_RD;				//Internal RD edge capture
+reg 	[9:0] 					ST;						//Controller status
+reg		[1:0] 					CMD;					//Controller command
+reg								PM_STOP;				//Flag page mode stop
+reg								PM_DONE;				//Flag page mode done
+reg								Read;					//Flag read active
+reg								Write;					//Flag write active
+reg	    [`DSIZE-1:0]           	mDATAOUT;               //Controller Data output
+wire    [`DSIZE-1:0]           	mDATAIN;                //Controller Data input
+wire    [`DSIZE-1:0]           	mDATAIN1;                //Controller Data input 1
+wire    [`DSIZE-1:0]           	mDATAIN2;                //Controller Data input 2
+wire                          	CMDACK;                 //Controller command acknowledgement
+//	DRAM Control
+reg  	[`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+reg     [11:0]                  SA;                     //SDRAM address output
+reg     [1:0]                   BA;                     //SDRAM bank address
+reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
+reg                             CKE;                    //SDRAM clock enable
+reg                             RAS_N;                  //SDRAM Row address Strobe
+reg                             CAS_N;                  //SDRAM Column address Strobe
+reg                             WE_N;                   //SDRAM write enable
+wire    [`DSIZE-1:0]            DQOUT;					//SDRAM data out link
+wire  	[`DSIZE/8-1:0]          IDQM;                   //SDRAM data mask lines
+wire    [11:0]                  ISA;                    //SDRAM address output
+wire    [1:0]                   IBA;                    //SDRAM bank address
+wire    [1:0]                   ICS_N;                  //SDRAM Chip Selects
+wire                            ICKE;                   //SDRAM clock enable
+wire                            IRAS_N;                 //SDRAM Row address Strobe
+wire                            ICAS_N;                 //SDRAM Column address Strobe
+wire                            IWE_N;                  //SDRAM write enable
+//	FIFO Control
+reg								OUT_VALID;				//Output data request to read side fifo
+reg								IN_REQ;					//Input	data request to write side fifo
+wire	[8:0]					write_side_fifo_rusedw1;
+wire	[8:0]					read_side_fifo_wusedw1;
+wire	[8:0]					write_side_fifo_rusedw2;
+wire	[8:0]					read_side_fifo_wusedw2;
+//	DRAM Internal Control
+wire    [`ASIZE-1:0]            saddr;
+wire                            load_mode;
+wire                            nop;
+wire                            reada;
+wire                            writea;
+wire                            refresh;
+wire                            precharge;
+wire                            oe;
+wire							ref_ack;
+wire							ref_req;
+wire							init_req;
+wire							cm_ack;
+wire							active;
+wire                            CLK;
+wire							CCD_CLK;
+
+control_interface control1 (
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .CMD(CMD),
+                .ADDR(mADDR),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+                .PRECHARGE(precharge),
+                .LOAD_MODE(load_mode),
+                .SADDR(saddr),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .CMD_ACK(CMDACK)
+                );
+
+command command1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .SADDR(saddr),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+				.LOAD_MODE(load_mode),
+                .PRECHARGE(precharge),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .OE(oe),
+				.PM_STOP(PM_STOP),
+				.PM_DONE(PM_DONE),
+                .SA(ISA),
+                .BA(IBA),
+                .CS_N(ICS_N),
+                .CKE(ICKE),
+                .RAS_N(IRAS_N),
+                .CAS_N(ICAS_N),
+                .WE_N(IWE_N)
+                );
+                
+sdr_data_path data_path1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .DATAIN(mDATAIN),
+                .DM(2'b00),
+                .DQOUT(DQOUT),
+                .DQM(IDQM)
+                );
+
+Sdram_FIFO 	write_fifo1(
+				.data(WR1_DATA),
+				.wrreq(WR1),
+				.wrclk(WR1_CLK),
+				.aclr(WR1_LOAD),
+				.rdreq(IN_REQ&WR_MASK[0]),
+				.rdclk(CLK),
+				.q(mDATAIN1),
+				.rdusedw(write_side_fifo_rusedw1)
+				);
+
+Sdram_FIFO 	write_fifo2(
+				.data(WR2_DATA),
+				.wrreq(WR2),
+				.wrclk(WR2_CLK),
+				.aclr(WR2_LOAD),
+				.rdreq(IN_REQ&WR_MASK[1]),
+				.rdclk(CLK),
+				.q(mDATAIN2),
+				.rdusedw(write_side_fifo_rusedw2)
+				);
+				
+assign	mDATAIN	=	(WR_MASK[0])	?	mDATAIN1	:
+										mDATAIN2	;
+
+Sdram_FIFO 	read_fifo1(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[0]),
+				.wrclk(CLK),
+				.aclr(RD1_LOAD),
+				.rdreq(RD1),
+				.rdclk(RD1_CLK),
+				.q(RD1_DATA),
+				.wrusedw(read_side_fifo_wusedw1)
+				);
+				
+Sdram_FIFO 	read_fifo2(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[1]),
+				.wrclk(CLK),
+				.aclr(RD2_LOAD),
+				.rdreq(RD2),
+				.rdclk(RD2_CLK),
+				.q(RD2_DATA),
+				.wrusedw(read_side_fifo_wusedw2)
+				);
+
+always @(posedge CLK)
+begin
+	SA      <= (ST==SC_CL+mLENGTH)			?	12'h200	:	ISA;
+    BA      <= IBA;
+    CS_N    <= ICS_N;
+    CKE     <= ICKE;
+    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
+    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
+    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
+	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
+	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
+	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
+	mDATAOUT<= DQ;
+end
+
+assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
+assign	active	=	Read | Write;
+
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(RESET_N==0)
+	begin
+		CMD			<=  0;
+		ST			<=  0;
+		Pre_RD		<=  0;
+		Pre_WR		<=  0;
+		Read		<=	0;
+		Write		<=	0;
+		OUT_VALID	<=	0;
+		IN_REQ		<=	0;
+		mWR_DONE	<=	0;
+		mRD_DONE	<=	0;
+	end
+	else
+	begin
+		Pre_RD	<=	mRD;
+		Pre_WR	<=	mWR;
+		case(ST)
+		0:	begin
+				if({Pre_RD,mRD}==2'b01)
+				begin
+					Read	<=	1;
+					Write	<=	0;
+					CMD		<=	2'b01;
+					ST		<=	1;
+				end
+				else if({Pre_WR,mWR}==2'b01)
+				begin
+					Read	<=	0;
+					Write	<=	1;
+					CMD		<=	2'b10;
+					ST		<=	1;
+				end
+			end
+		1:	begin
+				if(CMDACK==1)
+				begin
+					CMD<=2'b00;
+					ST<=2;
+				end
+			end
+		default:	
+			begin	
+				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
+				ST<=ST+1;
+				else
+				ST<=0;
+			end
+		endcase
+	
+		if(Read)
+		begin
+			if(ST==SC_CL+SC_RCD+1)
+			OUT_VALID	<=	1;
+			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
+			begin
+				OUT_VALID	<=	0;
+				Read		<=	0;
+				mRD_DONE	<=	1;
+			end
+		end
+		else
+		mRD_DONE	<=	0;
+		
+		if(Write)
+		begin
+			if(ST==SC_CL-1)
+			IN_REQ	<=	1;
+			else if(ST==SC_CL+mLENGTH-1)
+			IN_REQ	<=	0;
+			else if(ST==SC_CL+SC_RCD+mLENGTH)
+			begin
+				Write	<=	0;
+				mWR_DONE<=	1;
+			end
+		end
+		else
+		mWR_DONE<=	0;
+
+	end
+end
+//	Internal Address & Length Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		rWR1_ADDR		<=	0;
+		rWR2_ADDR		<=	22'h100000;
+		rRD1_ADDR		<=	0;
+		rRD2_ADDR		<=	22'h100000;
+		rWR1_MAX_ADDR	<=	640*480;
+		rWR2_MAX_ADDR	<=	22'h100000+640*480;
+		rRD1_MAX_ADDR	<=	640*480;
+		rRD2_MAX_ADDR	<=	22'h100000+640*480;
+		rWR1_LENGTH		<=	256;
+		rWR2_LENGTH		<=	256;
+		rRD1_LENGTH		<=	256;
+		rRD2_LENGTH		<=	256;
+	end
+	else
+	begin
+		//	Write Side 1
+		if(WR1_LOAD)
+		begin
+			rWR1_ADDR	<=	WR1_ADDR;
+			rWR1_LENGTH	<=	WR1_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[0])
+		begin
+			if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
+				rWR1_ADDR	<=	rWR1_ADDR+rWR1_LENGTH;
+			else
+				rWR1_ADDR	<=	WR1_ADDR;
+		end
+		//	Write Side 2
+		if(WR2_LOAD)
+		begin
+			rWR2_ADDR	<=	WR2_ADDR;
+			rWR2_LENGTH	<=	WR2_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[1])
+		begin
+			if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
+				rWR2_ADDR	<=	rWR2_ADDR+rWR2_LENGTH;
+			else
+				rWR2_ADDR	<=	WR2_ADDR;
+		end
+		//	Read Side 1
+		if(RD1_LOAD)
+		begin
+			rRD1_ADDR	<=	RD1_ADDR;
+			rRD1_LENGTH	<=	RD1_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[0])
+		begin
+			if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
+				rRD1_ADDR	<=	rRD1_ADDR+rRD1_LENGTH;
+			else
+				rRD1_ADDR	<=	RD1_ADDR;
+		end
+		//	Read Side 2
+		if(RD2_LOAD)
+		begin
+			rRD2_ADDR	<=	RD2_ADDR;
+			rRD2_LENGTH	<=	RD2_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[1])
+		begin
+			if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
+				rRD2_ADDR	<=	rRD2_ADDR+rRD2_LENGTH;
+			else
+				rRD2_ADDR	<=	RD2_ADDR;
+		end
+	end
+end
+//	Auto Read/Write Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		mWR		<=	0;
+		mRD		<=	0;
+		mADDR	<=	0;
+		mLENGTH	<=	0;
+	end
+	else
+	begin
+		if( (mWR==0) && (mRD==0) && (ST==0) &&
+			(WR_MASK==0)	&&	(RD_MASK==0) &&
+			(WR1_LOAD==0)	&&	(RD1_LOAD==0) &&
+			(WR2_LOAD==0)	&&	(RD2_LOAD==0) )
+		begin
+			//	Write Side 1
+			if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR1_ADDR;
+				mLENGTH	<=	rWR1_LENGTH;
+				WR_MASK	<=	2'b01;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Write Side 2
+			else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR2_ADDR;
+				mLENGTH	<=	rWR2_LENGTH;
+				WR_MASK	<=	2'b10;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Read Side 1
+			else if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
+			begin
+				mADDR	<=	rRD1_ADDR;
+				mLENGTH	<=	rRD1_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b01;
+				mWR		<=	0;
+				mRD		<=	1;				
+			end
+			//	Read Side 2
+			else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
+			begin
+				mADDR	<=	rRD2_ADDR;
+				mLENGTH	<=	rRD2_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b10;
+				mWR		<=	0;
+				mRD		<=	1;
+			end
+		end
+		if(mWR_DONE)
+		begin
+			WR_MASK	<=	0;
+			mWR		<=	0;
+		end
+		if(mRD_DONE)
+		begin
+			RD_MASK	<=	0;
+			mRD		<=	0;
+		end
+	end
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip
new file mode 100644
index 0000000..ceca5c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_FIFO.v"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v
new file mode 100644
index 0000000..af2662b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: Sdram_FIFO.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Sdram_FIFO (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[8:0]  rdusedw;
+	output	  wrfull;
+	output	[8:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [15:0] sub_wire1;
+	wire  sub_wire2;
+	wire [8:0] sub_wire3;
+	wire [8:0] sub_wire4;
+	wire  wrfull = sub_wire0;
+	wire [15:0] q = sub_wire1[15:0];
+	wire  rdempty = sub_wire2;
+	wire [8:0] wrusedw = sub_wire3[8:0];
+	wire [8:0] rdusedw = sub_wire4[8:0];
+
+	dcfifo	dcfifo_component (
+				.rdclk (rdclk),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.aclr (aclr),
+				.data (data),
+				.rdreq (rdreq),
+				.wrfull (sub_wire0),
+				.q (sub_wire1),
+				.rdempty (sub_wire2),
+				.wrusedw (sub_wire3),
+				.rdusedw (sub_wire4),
+				.rdfull (),
+				.wrempty ());
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+ 	
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v
new file mode 100644
index 0000000..8b37dff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v
@@ -0,0 +1,482 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	command
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module command(
+        CLK,
+        RESET_N,
+        SADDR,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        REF_REQ,
+		INIT_REQ,
+		PM_STOP,
+		PM_DONE,
+        REF_ACK,
+        CM_ACK,
+        OE,
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`ASIZE-1:0]            SADDR;                  // Address
+input                           NOP;                    // Decoded NOP command
+input                           READA;                  // Decoded READA command
+input                           WRITEA;                 // Decoded WRITEA command
+input                           REFRESH;                // Decoded REFRESH command
+input                           PRECHARGE;              // Decoded PRECHARGE command
+input                           LOAD_MODE;              // Decoded LOAD_MODE command
+input                           REF_REQ;                // Hidden refresh request
+input							INIT_REQ;				// Hidden initial request
+input							PM_STOP;				// Page mode stop
+input							PM_DONE;				// Page mode done
+output                          REF_ACK;                // Refresh request acknowledge
+output                          CM_ACK;                 // Command acknowledge
+output                          OE;                     // OE signal for data path module
+output  [11:0]                  SA;                     // SDRAM address
+output  [1:0]                   BA;                     // SDRAM bank address
+output  [1:0]                   CS_N;                   // SDRAM chip selects
+output                          CKE;                    // SDRAM clock enable
+output                          RAS_N;                  // SDRAM RAS
+output                          CAS_N;                  // SDRAM CAS
+output                          WE_N;                   // SDRAM WE_N
+            
+reg                             CM_ACK;
+reg                             REF_ACK;
+reg                             OE;
+reg     [11:0]                  SA;
+reg     [1:0]                   BA;
+reg     [1:0]                   CS_N;
+reg                             CKE;
+reg                             RAS_N;
+reg                             CAS_N;
+reg                             WE_N;
+
+// Internal signals
+reg                             do_reada;
+reg                             do_writea;
+reg                             do_refresh;
+reg                             do_precharge;
+reg                             do_load_mode;
+reg								do_initial;
+reg                             command_done;
+reg     [7:0]                   command_delay;
+reg     [1:0]                   rw_shift;
+reg                             do_act;
+reg                             rw_flag;
+reg                             do_rw;
+reg     [6:0]                   oe_shift;
+reg                             oe1;
+reg                             oe2;
+reg                             oe3;
+reg                             oe4;
+reg     [3:0]                   rp_shift;
+reg                             rp_done;
+reg								ex_read;
+reg								ex_write;
+
+wire    [`ROWSIZE - 1:0]        rowaddr;
+wire    [`COLSIZE - 1:0]        coladdr;
+wire    [`BANKSIZE - 1:0]       bankaddr;
+
+assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
+assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
+assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
+
+// This always block monitors the individual command lines and issues a command
+// to the next stage if there currently another command already running.
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 0;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+        end
+        
+        else
+        begin
+
+//  Issue the appropriate command if the sdram is not currently busy
+			if( INIT_REQ == 1 )
+			begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 1;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+			end
+			else
+			begin
+				do_initial		<= 0;
+				
+                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
+                        & do_reada == 0 & do_writea == 0)
+                        do_refresh <= 1;         
+                else
+                        do_refresh <= 0;
+
+                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
+                begin
+				        do_reada <= 1;
+						ex_read <= 1;
+				end
+                else
+                        do_reada <= 0;
+                    
+                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
+                begin
+				        do_writea <= 1;
+						ex_write <= 1;
+				end
+                else
+                        do_writea <= 0;
+
+                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))	// PRECHARGE
+                        do_precharge <= 1;
+                else
+                        do_precharge <= 0;
+ 
+                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))	// LOADMODE
+                        do_load_mode <= 1;
+                else
+                        do_load_mode <= 0;
+                                               
+// set command_delay shift register and command_done flag
+// The command delay shift register is a timer that is used to ensure that
+// the SDRAM devices have had sufficient time to finish the last command.
+
+                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
+                     | (do_load_mode == 1))
+                begin
+                        command_delay <= 8'b11111111;
+                        command_done  <= 1;
+                        rw_flag <= do_reada;                                                  
+                end
+                
+                else
+                begin
+                        command_done        <= command_delay[0];                // the command_delay shift operation
+                        command_delay		<= (command_delay>>1);
+                end 
+                
+ 
+ // start additional timer that is used for the refresh, writea, reada commands               
+                if (command_delay[0] == 0 & command_done == 1)
+                begin
+                	rp_shift <= 4'b1111;
+                	rp_done <= 1;
+                end
+                else
+                begin						
+					if(SC_PM == 0)
+					begin
+						rp_shift	<= (rp_shift>>1);
+                    	rp_done		<= rp_shift[0];
+					end
+					else
+					begin
+						if( (ex_read == 0) && (ex_write == 0) )
+						begin
+							rp_shift	<= (rp_shift>>1);
+        	            	rp_done		<= rp_shift[0];
+						end
+						else
+						begin
+							if( PM_STOP==1 )
+							begin
+								rp_shift	<= (rp_shift>>1);
+        	      		      	rp_done     <= rp_shift[0];
+								ex_read		<= 1'b0;
+								ex_write	<= 1'b0;
+							end					
+						end
+					end
+                end
+			end
+        end
+end
+
+
+// logic that generates the OE signal for the data path module
+// For normal burst write he duration of OE is dependent on the configured burst length.
+// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
+// and is left on until a PRECHARGE(page burst terminate) is detected.
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                oe_shift <= 0;
+                oe1      <= 0;
+                oe2      <= 0;
+                OE       <= 0;
+        end
+        else
+        begin
+                if (SC_PM == 0)
+                begin
+                        if (do_writea == 1)
+                        begin
+                                if (SC_BL == 1)				//  Set the shift register to the appropriate
+                                        oe_shift <= 0;		// value based on burst length.
+                                else if (SC_BL == 2)
+                                        oe_shift <= 1;
+                                else if (SC_BL == 4)
+                                        oe_shift <= 7;
+                                else if (SC_BL == 8)
+                                        oe_shift <= 127;
+                                oe1 <= 1;
+                        end
+                        else 
+                        begin
+                                oe_shift <= (oe_shift>>1);
+                                oe1  <= oe_shift[0];
+                                oe2  <= oe1;
+                                oe3  <= oe2;
+                                oe4  <= oe3;
+                                if (SC_RCD == 2)
+                                        OE <= oe3;
+                                else
+                                        OE <= oe4;
+                        end
+                end
+                else
+                begin
+                        if (do_writea == 1)					 // OE generation for page mode accesses
+                                oe4   <= 1;
+                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
+                                oe4   <= 0;
+                        OE <= oe4;
+                end
+                               
+        end
+end
+
+
+
+
+// This always block tracks the time between the activate command and the
+// subsequent WRITEA or READA command, RC.  The shift register is set using
+// the configuration register setting SC_RCD. The shift register is loaded with
+// a single '1' with the position within the register dependent on SC_RCD.
+// When the '1' is shifted out of the register it sets so_rw which triggers
+// a writea or reada command
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                rw_shift <= 0;
+                do_rw    <= 0;
+        end
+        
+        else
+        begin
+                
+                if ((do_reada == 1) | (do_writea == 1))
+                begin
+                        if (SC_RCD == 1)                          // Set the shift register
+                                do_rw <= 1;
+                        else if (SC_RCD == 2)
+                                rw_shift <= 1;
+                        else if (SC_RCD == 3)
+                                rw_shift <= 2;
+                end
+                else
+                begin
+                        rw_shift <= (rw_shift>>1);
+                        do_rw    <= rw_shift[0];
+                end 
+        end
+end              
+
+// This always block generates the command acknowledge, CM_ACK, signal.
+// It also generates the acknowledge signal, REF_ACK, that acknowledges
+// a refresh request that was generated by the internal refresh timer circuit.
+always @(posedge CLK or negedge RESET_N) 
+begin
+
+        if (RESET_N == 0) 
+        begin
+                CM_ACK   <= 0;
+                REF_ACK  <= 0;
+        end
+        
+        else
+        begin
+                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
+                        REF_ACK <= 1;
+                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
+                         | (do_load_mode))
+                        CM_ACK <= 1;
+                else
+                begin
+                        REF_ACK <= 0;
+                        CM_ACK  <= 0;
+                end
+        end
+end 
+                    
+
+
+
+
+
+
+// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
+// 
+always @(posedge CLK ) begin
+        if (RESET_N==0) begin
+                SA    <= 0;
+                BA    <= 0;
+                CS_N  <= 1;
+                RAS_N <= 1;
+                CAS_N <= 1;
+                WE_N  <= 1;
+                CKE   <= 0;
+        end
+        else begin
+                CKE <= 1;
+
+// Generate SA 	
+                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
+                        SA <= rowaddr;
+                else
+                        SA <= coladdr;                 // else alway present column address
+                if ((do_rw==1) | (do_precharge))
+                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
+                                                       // don't set it if the controller is in page mode.           
+                if (do_precharge==1 | do_load_mode==1)
+                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
+                else
+                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
+		
+                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
+                        CS_N <= 0;                                    // Select both chip selects if performing
+                else                                                  // refresh, precharge(all) or load_mode
+                begin
+                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
+                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
+                end
+				
+				if(do_load_mode==1)
+				SA	  <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
+
+
+//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
+//depending on the issued command.
+//		
+                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 1;
+                end
+                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 0;
+                end
+                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
+                        RAS_N <= 1;
+                        CAS_N <= 0;
+                        WE_N  <= rw_flag;
+                end
+				else if (do_initial ==1) begin
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;				
+				end
+                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+        end 
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v
new file mode 100644
index 0000000..d7930e2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v
@@ -0,0 +1,240 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	control_interface
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module control_interface(
+        CLK,
+        RESET_N,
+        CMD,
+        ADDR,
+        REF_ACK,
+		INIT_ACK,
+        CM_ACK,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        SADDR,
+        REF_REQ,
+		INIT_REQ,
+        CMD_ACK
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [2:0]                   CMD;                    // Command input
+input   [`ASIZE-1:0]            ADDR;                   // Address
+input                           REF_ACK;                // Refresh request acknowledge
+input							INIT_ACK;				// Initial request acknowledge
+input                           CM_ACK;                 // Command acknowledge
+output                          NOP;                    // Decoded NOP command
+output                          READA;                  // Decoded READA command
+output                          WRITEA;                 // Decoded WRITEA command
+output                          REFRESH;                // Decoded REFRESH command
+output                          PRECHARGE;              // Decoded PRECHARGE command
+output                          LOAD_MODE;              // Decoded LOAD_MODE command
+output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
+output                          REF_REQ;                // Hidden refresh request
+output                          INIT_REQ;               // Hidden initial request
+output                          CMD_ACK;                // Command acknowledge
+
+
+            
+reg                             NOP;
+reg                             READA;
+reg                             WRITEA;
+reg                             REFRESH;
+reg                             PRECHARGE;
+reg                             LOAD_MODE;
+reg     [`ASIZE-1:0]            SADDR;
+reg                             REF_REQ;
+reg                             INIT_REQ;
+reg                             CMD_ACK;
+
+// Internal signals
+reg     [15:0]                  timer;
+reg		[15:0]					init_timer;
+
+
+
+// Command decode and ADDR register
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                NOP             <= 0;
+                READA           <= 0;
+                WRITEA          <= 0;
+                SADDR           <= 0;
+        end
+        
+        else
+        begin
+        
+                SADDR <= ADDR;                                  // register the address to keep proper
+                                                                // alignment with the command
+                                                             
+                if (CMD == 3'b000)                              // NOP command
+                        NOP <= 1;
+                else
+                        NOP <= 0;
+                        
+                if (CMD == 3'b001)                              // READA command
+                        READA <= 1;
+                else
+                        READA <= 0;
+                 
+                if (CMD == 3'b010)                              // WRITEA command
+                        WRITEA <= 1;
+                else
+                        WRITEA <= 0;
+                        
+        end
+end
+
+
+//  Generate CMD_ACK
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+                CMD_ACK <= 0;
+        else
+                if ((CM_ACK == 1) & (CMD_ACK == 0))
+                        CMD_ACK <= 1;
+                else
+                        CMD_ACK <= 0;
+end
+
+
+// refresh timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                timer           <= 0;
+                REF_REQ         <= 0;
+        end        
+        else 
+        begin
+                if (REF_ACK == 1)
+				begin
+                	timer <= REF_PER;
+					REF_REQ	<=0;
+				end
+				else if (INIT_REQ == 1)
+				begin
+                	timer <= REF_PER+200;
+					REF_REQ	<=0;					
+				end
+                else
+                	timer <= timer - 1'b1;
+
+                if (timer==0)
+                    REF_REQ    <= 1;
+
+        end
+end
+
+// initial timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                init_timer      <= 0;
+				REFRESH         <= 0;
+                PRECHARGE      	<= 0; 
+				LOAD_MODE		<= 0;
+				INIT_REQ		<= 0;
+        end        
+        else 
+        begin
+                if (init_timer < (INIT_PER+201))
+					init_timer 	<= init_timer+1;
+					
+				if (init_timer < INIT_PER)
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=1;
+				end
+				else if(init_timer == (INIT_PER+20))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=1;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if( 	(init_timer == (INIT_PER+40))	||
+							(init_timer == (INIT_PER+60))	||
+							(init_timer == (INIT_PER+80))	||
+							(init_timer == (INIT_PER+100))	||
+							(init_timer == (INIT_PER+120))	||
+							(init_timer == (INIT_PER+140))	||
+							(init_timer == (INIT_PER+160))	||
+							(init_timer == (INIT_PER+180))	)
+				begin
+					REFRESH		<=1;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if(init_timer == (INIT_PER+200))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=1;
+					INIT_REQ	<=0;				
+				end
+				else
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;									
+				end
+        end
+end
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v
new file mode 100644
index 0000000..b064bbe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v
@@ -0,0 +1,76 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	sdr_data_path
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module sdr_data_path(
+        CLK,
+        RESET_N,
+        DATAIN,
+        DM,
+        DQOUT,
+        DQM
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`DSIZE-1:0]            DATAIN;                 // Data input from the host
+input   [`DSIZE/8-1:0]          DM;                     // byte data masks
+output  [`DSIZE-1:0]            DQOUT;
+output  [`DSIZE/8-1:0]          DQM;                    // SDRAM data mask ouputs
+reg     [`DSIZE/8-1:0]          DQM;
+            
+
+
+// Allign the input and output data to the SDRAM control path
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+		DQM		<= `DSIZE/8-1'hF;
+        else
+ 		DQM		<=	DM;                 
+end
+
+assign DQOUT = DATAIN;
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v
new file mode 100644
index 0000000..338ae75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v
@@ -0,0 +1,186 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	D5M CCD_Capture
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module CCD_Capture(	oDATA,
+					oDVAL,
+					oX_Cont,
+					oY_Cont,
+					oFrame_Cont,
+					iDATA,
+					iFVAL,
+					iLVAL,
+					iSTART,
+					iEND,
+					iCLK,
+					iRST
+					);
+					
+input	[11:0]	iDATA;
+input			iFVAL;
+input			iLVAL;
+input			iSTART;
+input			iEND;
+input			iCLK;
+input			iRST;
+output	[11:0]	oDATA;
+output	[15:0]	oX_Cont;
+output	[15:0]	oY_Cont;
+output	[31:0]	oFrame_Cont;
+output			oDVAL;
+reg				Pre_FVAL;
+reg				mCCD_FVAL;
+reg				mCCD_LVAL;
+reg		[11:0]	mCCD_DATA;
+reg		[15:0]	X_Cont;
+reg		[15:0]	Y_Cont;
+reg		[31:0]	Frame_Cont;
+reg				mSTART;
+
+parameter COLUMN_WIDTH = 1280;
+
+assign	oX_Cont		=	X_Cont;
+assign	oY_Cont		=	Y_Cont;
+assign	oFrame_Cont	=	Frame_Cont;
+assign	oDATA		=	mCCD_DATA;
+assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	mSTART	<=	0;
+	else
+	begin
+		if(iSTART)
+		mSTART	<=	1;
+		if(iEND)
+		mSTART	<=	0;		
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Pre_FVAL	<=	0;
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	0;
+
+		X_Cont		<=	0;
+		Y_Cont		<=	0;
+	end
+	else
+	begin
+		Pre_FVAL	<=	iFVAL;
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		mCCD_FVAL	<=	1;
+		else if({Pre_FVAL,iFVAL}==2'b10)
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	iLVAL;
+		if(mCCD_FVAL)
+		begin
+			if(mCCD_LVAL)
+			begin
+				if(X_Cont<(COLUMN_WIDTH-1))
+				X_Cont	<=	X_Cont+1;
+				else
+				begin
+					X_Cont	<=	0;
+					Y_Cont	<=	Y_Cont+1;
+				end
+			end
+		end
+		else
+		begin
+			X_Cont	<=	0;
+			Y_Cont	<=	0;
+		end
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	Frame_Cont	<=	0;
+	else
+	begin
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		Frame_Cont	<=	Frame_Cont+1;
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		mCCD_DATA	<=	0;
+	else if (iLVAL)
+		mCCD_DATA	<=	iDATA;
+	else
+		mCCD_DATA	<=	0;	
+end			
+
+reg	ifval_dealy;
+
+wire ifval_fedge;	
+reg	[15:0]	y_cnt_d;
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		y_cnt_d	<=	0;
+	else
+		y_cnt_d	<=	Y_Cont;	
+end
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		ifval_dealy	<=	0;
+	else
+		ifval_dealy	<=	iFVAL;	
+end
+
+assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  
+
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v
new file mode 100644
index 0000000..11d3a70
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v
@@ -0,0 +1,287 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| CCD config, spelling
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+
+// `define 	ENABLE_TEST_PATTERN 1
+
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	sensor_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			sensor_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((sensor_exposure < exposure_change_value)||
+							(sensor_exposure == 16'h0))
+							sensor_exposure <= 0;
+						else	
+							sensor_exposure <= sensor_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -sensor_exposure) <exposure_change_value)||
+							(sensor_exposure == 16'hffff))
+							sensor_exposure <= 16'hffff;
+						else
+							sensor_exposure <= sensor_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,sensor_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..81810a8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak
@@ -0,0 +1,282 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	senosr_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			senosr_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((senosr_exposure < exposure_change_value)||
+							(senosr_exposure == 16'h0))
+							senosr_exposure <= 0;
+						else	
+							senosr_exposure <= senosr_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -senosr_exposure) <exposure_change_value)||
+							(senosr_exposure == 16'hffff))
+							senosr_exposure <= 16'hffff;
+						else
+							senosr_exposure <= senosr_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,senosr_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v
new file mode 100644
index 0000000..3740541
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v
@@ -0,0 +1,150 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altrea Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL or Verilog source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Joe Yang          :| 05/07/10  :|      Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+	CLOCK,
+	I2C_SCLK,//I2C CLOCK
+ 	I2C_SDAT,//I2C DATA
+	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+	GO,      //GO transfor
+	END,     //END transfor 
+
+	ACK,      //ACK
+	RESET
+);
+	input  CLOCK;
+	input  [31:0]I2C_DATA;	
+	input  GO;
+	input  RESET;	
+ 	inout  I2C_SDAT;	
+	output I2C_SCLK;
+	output END;	
+	output ACK;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [31:0]SD;
+reg [6:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3,ACK4;
+wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0) 
+	SD_COUNTER=0;
+	else 
+	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
+end
+end
+//----
+
+always @(negedge RESET or  posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
+else
+case (SD_COUNTER)
+	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
+	//start
+	6'd1  : begin SD=I2C_DATA;SDO=0;end
+	6'd2  : SCLK=0;
+	//SLAVE ADDR
+	6'd3  : SDO=SD[31];
+	6'd4  : SDO=SD[30];
+	6'd5  : SDO=SD[29];
+	6'd6  : SDO=SD[28];
+	6'd7  : SDO=SD[27];
+	6'd8  : SDO=SD[26];
+	6'd9  : SDO=SD[25];
+	6'd10 : SDO=SD[24];	
+	6'd11 : SDO=1'b1;//ACK
+
+	//SUB ADDR
+	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
+	6'd13  : SDO=SD[22];
+	6'd14  : SDO=SD[21];
+	6'd15  : SDO=SD[20];
+	6'd16  : SDO=SD[19];
+	6'd17  : SDO=SD[18];
+	6'd18  : SDO=SD[17];
+	6'd19  : SDO=SD[16];
+	6'd20  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
+	6'd22  : SDO=SD[14];
+	6'd23  : SDO=SD[13];
+	6'd24  : SDO=SD[12];
+	6'd25  : SDO=SD[11];
+	6'd26  : SDO=SD[10];
+	6'd27  : SDO=SD[9];
+	6'd28  : SDO=SD[8];
+	6'd29  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
+	6'd31  : SDO=SD[6];
+	6'd32  : SDO=SD[5];
+	6'd33  : SDO=SD[4];
+	6'd34  : SDO=SD[3];
+	6'd35  : SDO=SD[2];
+	6'd36  : SDO=SD[1];
+	6'd37  : SDO=SD[0];
+	6'd38  : SDO=1'b1;//ACK
+
+	
+	//stop
+    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
+    6'd40 : SCLK=1'b1; 
+    6'd41 : begin SDO=1'b1; END=1; end 
+
+endcase
+end
+
+
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf
new file mode 100644
index 0000000..b7b5b56
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf
@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 184 128)
+	(text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 184 40)
+		(output)
+		(text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8)))
+		(line (pt 184 40)(pt 168 40)(line_width 3))
+	)
+	(port
+		(pt 184 56)
+		(output)
+		(text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps1x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8)))
+		(line (pt 184 56)(pt 168 56)(line_width 3))
+	)
+	(port
+		(pt 184 72)
+		(output)
+		(text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps0x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8)))
+		(line (pt 184 72)(pt 168 72)(line_width 3))
+	)
+	(drawing
+		(text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8)))
+		(text "Number of taps 2" (rect 19 90 93 102)(font "Arial" ))
+		(text "Tap distance 1280" (rect 19 100 95 112)(font "Arial" ))
+		(line (pt 16 16)(pt 168 16)(line_width 1))
+		(line (pt 168 16)(pt 168 112)(line_width 1))
+		(line (pt 168 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v
new file mode 100644
index 0000000..09482ce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %Shift register (RAM-based)%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altshift_taps 
+
+// ============================================================
+// File Name: Line_Buffer.v
+// Megafunction Name(s):
+// 			altshift_taps
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Line_Buffer (
+	clken,
+	clock,
+	shiftin,
+	shiftout,
+	taps0x,
+	taps1x);
+
+	input	  clken;
+	input	  clock;
+	input	[11:0]  shiftin;
+	output	[11:0]  shiftout;
+	output	[11:0]  taps0x;
+	output	[11:0]  taps1x;
+
+	wire [23:0] sub_wire0;
+	wire [11:0] sub_wire3;
+	wire [23:12] sub_wire1 = sub_wire0[23:12];
+	wire [11:0] sub_wire2 = sub_wire0[11:0];
+	wire [11:0] taps1x = sub_wire1[23:12];
+	wire [11:0] taps0x = sub_wire2[11:0];
+	wire [11:0] shiftout = sub_wire3[11:0];
+
+	altshift_taps	altshift_taps_component (
+				.clken (clken),
+				.clock (clock),
+				.shiftin (shiftin),
+				.taps (sub_wire0),
+				.shiftout (sub_wire3));
+	defparam
+		altshift_taps_component.lpm_type = "altshift_taps",
+		altshift_taps_component.number_of_taps = 2,
+		altshift_taps_component.tap_distance = 1280,
+		altshift_taps_component.width = 12;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
+// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
+// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
+// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
+// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
+// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
+// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
+// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
+// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v
new file mode 100644
index 0000000..16493c7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v
@@ -0,0 +1,128 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	RAW2RGB
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module RAW2RGB(	oRed,
+				oGreen,
+				oBlue,
+				oDVAL,
+				iX_Cont,
+				iY_Cont,
+				iDATA,
+				iDVAL,
+				iCLK,
+				iRST
+				);
+
+input	[10:0]	iX_Cont;
+input	[10:0]	iY_Cont;
+input	[11:0]	iDATA;
+input			iDVAL;
+input			iCLK;
+input			iRST;
+output	[11:0]	oRed;
+output	[11:0]	oGreen;
+output	[11:0]	oBlue;
+output			oDVAL;
+wire	[11:0]	mDATA_0;
+wire	[11:0]	mDATA_1;
+reg		[11:0]	mDATAd_0;
+reg		[11:0]	mDATAd_1;
+reg		[11:0]	mCCD_R;
+reg		[12:0]	mCCD_G;
+reg		[11:0]	mCCD_B;
+reg				mDVAL;
+
+assign	oRed	=	mCCD_R[11:0];
+assign	oGreen	=	mCCD_G[12:1];
+assign	oBlue	=	mCCD_B[11:0];
+assign	oDVAL	=	mDVAL;
+
+Line_Buffer 	u0	(	.clken(iDVAL),
+						.clock(iCLK),
+						.shiftin(iDATA),
+						.taps0x(mDATA_1),
+						.taps1x(mDATA_0)	);
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		mCCD_R	<=	0;
+		mCCD_G	<=	0;
+		mCCD_B	<=	0;
+		mDATAd_0<=	0;
+		mDATAd_1<=	0;
+		mDVAL	<=	0;
+	end
+	else
+	begin
+		mDATAd_0	<=	mDATA_0;
+		mDATAd_1	<=	mDATA_1;
+		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
+		if({iY_Cont[0],iX_Cont[0]}==2'b10)
+		begin
+			mCCD_R	<=	mDATA_0;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATAd_1;
+		end	
+		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
+		begin
+			mCCD_R	<=	mDATAd_0;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATA_1;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
+		begin
+			mCCD_R	<=	mDATA_1;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATAd_0;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
+		begin
+			mCCD_R	<=	mDATAd_1;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATA_0;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v
new file mode 100644
index 0000000..578a964
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v
@@ -0,0 +1,74 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Reset_Delay
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
+input		iCLK;
+input		iRST;
+output reg	oRST_0;
+output reg	oRST_1;
+output reg	oRST_2;
+
+reg	[31:0]	Cont;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Cont	<=	0;
+		oRST_0	<=	0;
+		oRST_1	<=	0;
+		oRST_2	<=	0;
+	end
+	else
+	begin
+		if(Cont!=32'h11FFFFF)
+		Cont	<=	Cont+1;
+		if(Cont>=32'h1FFFFF)
+		oRST_0	<=	1;
+		if(Cont>=32'h2FFFFF)
+		oRST_1	<=	1;
+		if(Cont>=32'h11FFFFF)
+		oRST_2	<=	1;
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v
new file mode 100644
index 0000000..2756db0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT	(	oSEG,iDIG	);
+input	[3:0]	iDIG;
+output	[6:0]	oSEG;
+reg		[6:0]	oSEG;
+
+always @(iDIG)
+begin
+		case(iDIG)
+		4'h1: oSEG = 7'b1111001;	// ---t----
+		4'h2: oSEG = 7'b0100100; 	// |	  |
+		4'h3: oSEG = 7'b0110000; 	// lt	 rt
+		4'h4: oSEG = 7'b0011001; 	// |	  |
+		4'h5: oSEG = 7'b0010010; 	// ---m----
+		4'h6: oSEG = 7'b0000010; 	// |	  |
+		4'h7: oSEG = 7'b1111000; 	// lb	 rb
+		4'h8: oSEG = 7'b0000000; 	// |	  |
+		4'h9: oSEG = 7'b0011000; 	// ---b----
+		4'ha: oSEG = 7'b0001000;
+		4'hb: oSEG = 7'b0000011;
+		4'hc: oSEG = 7'b1000110;
+		4'hd: oSEG = 7'b0100001;
+		4'he: oSEG = 7'b0000110;
+		4'hf: oSEG = 7'b0001110;
+		4'h0: oSEG = 7'b1000000;
+		endcase
+end
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v
new file mode 100644
index 0000000..e84af4e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT_8
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input	[31:0]	iDIG;
+output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
+SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
+SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
+SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
+SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
+SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
+SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
+SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf
new file mode 100644
index 0000000..5b1f507
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf
@@ -0,0 +1,1741 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 424 88 592 104)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 288 232 352 248))
+)
+(pin
+	(input)
+	(rect 512 120 680 136)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 448 136 504 152))
+)
+(pin
+	(input)
+	(rect 480 136 704 152)
+	(text "INPUT" (rect 180 6 208 16)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKIN[1..0]" (rect 6 4 109 16)(font "Arial" ))
+	(pt 224 8)
+	(drawing
+		(line (pt 139 4)(pt 164 4))
+		(line (pt 139 12)(pt 164 12))
+		(line (pt 168 8)(pt 223 8))
+		(line (pt 139 4)(pt 139 12))
+		(line (pt 164 12)(pt 168 8))
+		(line (pt 164 4)(pt 168 8))
+	)
+	(flipx)
+	(text "VCC" (rect 183 -1 203 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 664 192 720 208))
+)
+(pin
+	(input)
+	(rect 424 104 592 120)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "KEY[2..0]" (rect 5 0 53 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 336 344 392 360))
+)
+(pin
+	(output)
+	(rect 504 24 680 40)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "LEDG[9..0]" (rect 5 0 60 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 96 168 160 184))
+)
+(pin
+	(output)
+	(rect 1144 200 1320 216)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_LDQM" (rect 103 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1008 296 1072 312))
+)
+(pin
+	(output)
+	(rect 1144 216 1320 232)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_UDQM" (rect 101 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 192 1416 208))
+)
+(pin
+	(output)
+	(rect 1144 312 1320 328)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_1" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 288 1416 304))
+)
+(pin
+	(output)
+	(rect 1144 296 1320 312)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_0" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1008 264 1072 280))
+)
+(pin
+	(output)
+	(rect 1144 248 1320 264)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 224 1424 240))
+)
+(pin
+	(output)
+	(rect 1144 344 1320 360)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CKE" (rect 110 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 320 1424 336))
+)
+(pin
+	(output)
+	(rect 1144 280 1320 296)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CS_N" (rect 103 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 256 1416 272))
+)
+(pin
+	(output)
+	(rect 1144 264 1320 280)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_RAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 240 1416 256))
+)
+(pin
+	(output)
+	(rect 1144 232 1320 248)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_WE_N" (rect 101 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 208 1416 224))
+)
+(pin
+	(output)
+	(rect 1144 328 1320 344)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CLK" (rect 111 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 96 688 160 704))
+)
+(pin
+	(output)
+	(rect 736 1272 912 1288)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 37 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 912 1288 968 1304))
+)
+(pin
+	(output)
+	(rect 736 1224 912 1240)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_HS" (rect 43 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 616 1240 672 1256))
+)
+(pin
+	(output)
+	(rect 736 1240 912 1256)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_VS" (rect 44 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 624 1256 680 1272))
+)
+(pin
+	(output)
+	(rect 736 1176 912 1192)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_R[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 648 1152 704 1168))
+)
+(pin
+	(output)
+	(rect 736 1192 912 1208)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 624 1200 680 1216))
+)
+(pin
+	(output)
+	(rect 736 1208 912 1224)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_B[3..0]" (rect 5 0 66 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 624 1216 680 1232))
+)
+(pin
+	(output)
+	(rect 1144 184 1353 200)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_ADDR[11..0] " (rect 98 0 203 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1296 144 1360 160))
+)
+(pin
+	(output)
+	(rect 504 -64 680 -48)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX3[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 360 -72 424 -56))
+)
+(pin
+	(output)
+	(rect 504 -48 680 -32)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX2[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 416 32 480 48))
+)
+(pin
+	(output)
+	(rect 504 -32 680 -16)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX1[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 208 56 272 72))
+)
+(pin
+	(output)
+	(rect 504 -16 680 0)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX0[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 552 32 616 48))
+)
+(pin
+	(output)
+	(rect 1144 504 1354 520)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKOUT[1..0]" (rect 90 0 204 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1416 504 1472 520))
+)
+(pin
+	(bidir)
+	(rect 1144 168 1328 184)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "DRAM_DQ[15..0] " (rect 90 0 179 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1448 96 1512 112))
+)
+(pin
+	(bidir)
+	(rect 376 576 552 592)
+	(text "BIDIR" (rect 151 6 175 16)(font "Arial" (font_size 6)))
+	(text "PS2_DAT" (rect 5 4 52 16)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 120 12)(pt 98 12))
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 120 4)(pt 98 4))
+		(line (pt 98 12)(pt 94 8))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 120 12)(pt 124 8))
+		(line (pt 124 8)(pt 120 4))
+	)
+	(rotate180)
+	(text "VCC" (rect 152 -1 172 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 120 504 176 520))
+)
+(pin
+	(bidir)
+	(rect 376 600 552 616)
+	(text "BIDIR" (rect 151 6 175 16)(font "Arial" (font_size 6)))
+	(text "PS2_CLK" (rect 5 4 52 16)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 120 12)(pt 98 12))
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 120 4)(pt 98 4))
+		(line (pt 98 12)(pt 94 8))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 120 12)(pt 124 8))
+		(line (pt 124 8)(pt 120 4))
+	)
+	(rotate180)
+	(text "VCC" (rect 152 -1 172 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 504 632 560 648))
+)
+(pin
+	(bidir)
+	(rect 1144 520 1320 536)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1[31..0]" (rect 90 0 160 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1368 584 1424 600))
+)
+(symbol
+	(rect 992 952 1024 984)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst5" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 1496 944 1528 960)
+	(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
+	(text "inst4" (rect 3 5 26 17)(font "Arial" )(invisible))
+	(port
+		(pt 16 16)
+		(output)
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(line (pt 16 16)(pt 16 8))
+	)
+	(drawing
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 760 704 968 944)
+	(text "ps2" (rect 5 0 22 12)(font "Arial" ))
+	(text "inst6" (rect 8 224 31 236)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "iSTART" (rect 0 0 36 12)(font "Arial" ))
+		(text "iSTART" (rect 21 27 57 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "iRST_n" (rect 0 0 35 12)(font "Arial" ))
+		(text "iRST_n" (rect 21 43 56 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "iCLK_50" (rect 0 0 41 12)(font "Arial" ))
+		(text "iCLK_50" (rect 21 59 62 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "oLEFBUT" (rect 0 0 47 12)(font "Arial" ))
+		(text "oLEFBUT" (rect 148 59 195 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "oRIGBUT" (rect 0 0 47 12)(font "Arial" ))
+		(text "oRIGBUT" (rect 148 75 195 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "oMIDBUT" (rect 0 0 47 12)(font "Arial" ))
+		(text "oMIDBUT" (rect 148 91 195 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "oX[7..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "oX[7..0]" (rect 156 107 193 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112)(line_width 3))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "oY[7..0]" (rect 0 0 40 12)(font "Arial" ))
+		(text "oY[7..0]" (rect 154 123 194 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128)(line_width 3))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "oX_MOV1[6..0]" (rect 0 0 73 12)(font "Arial" ))
+		(text "oX_MOV1[6..0]" (rect 126 139 199 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144)(line_width 3))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "oX_MOV2[6..0]" (rect 0 0 73 12)(font "Arial" ))
+		(text "oX_MOV2[6..0]" (rect 126 155 199 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160)(line_width 3))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "oY_MOV1[6..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "oY_MOV1[6..0]" (rect 124 171 199 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "oY_MOV2[6..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "oY_MOV2[6..0]" (rect 124 187 199 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 32)
+		(bidir)
+		(text "PS2_CLK" (rect 0 0 47 12)(font "Arial" ))
+		(text "PS2_CLK" (rect 145 27 192 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32))
+	)
+	(port
+		(pt 208 48)
+		(bidir)
+		(text "PS2_DAT" (rect 0 0 47 12)(font "Arial" ))
+		(text "PS2_DAT" (rect 144 43 191 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48))
+	)
+	(parameter
+		"enable_byte"
+		"011110100"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"listen"
+		"00"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pullclk"
+		"01"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pulldat"
+		"10"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"trans"
+		"11"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(drawing
+		(rectangle (rect 16 16 192 224))
+	)
+	(annotation_block (parameter)(rect 736 616 960 704))
+)
+(symbol
+	(rect 2304 1056 2448 1168)
+	(text "vga_mux" (rect 48 0 108 16)(font "Arial" (font_size 10)))
+	(text "inst10" (rect 8 96 37 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[29..0]" (rect 4 26 78 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[29..0]" (rect 4 42 78 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[29..0]" (rect 4 58 78 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[29..0]" (rect 4 74 78 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 72 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 65 59 79 103)(font "Arial" (font_size 8))(vertical))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
+	)
+	(port
+		(pt 144 64)
+		(output)
+		(text "result[29..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[29..0]" (rect 84 50 151 64)(font "Arial" (font_size 8)))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 104))
+		(line (pt 64 24)(pt 80 32))
+		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 32)(pt 80 96))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
+(symbol
+	(rect 760 64 1048 560)
+	(text "DE0_D5M" (rect 5 0 54 12)(font "Arial" ))
+	(text "inst" (rect 8 480 25 492)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 55 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 76 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 48 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 69 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 64 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 103 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 124 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 221 27 276 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 276 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 223 59 276 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 276 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 276 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 101 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 182 123 283 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 210 139 278 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 70 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 208 155 278 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 69 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 209 171 278 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 205 187 279 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 205 203 279 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 211 219 278 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 214 235 277 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 214 251 277 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 218 267 277 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 60 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 217 283 277 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_HS" (rect 231 299 274 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_VS" (rect 232 315 274 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[9..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_R[9..0]" (rect 215 331 277 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[9..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_G[9..0]" (rect 215 347 277 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[9..0]" (rect 0 0 61 12)(font "Arial" ))
+		(text "VGA_B[9..0]" (rect 216 363 277 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 226 379 275 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "VGA_X[11..0]" (rect 0 0 66 12)(font "Arial" ))
+		(text "VGA_X[11..0]" (rect 212 395 278 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(output)
+		(text "VGA_Y[11..0]" (rect 0 0 68 12)(font "Arial" ))
+		(text "VGA_Y[11..0]" (rect 210 411 278 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(port
+		(pt 288 432)
+		(output)
+		(text "VGA_ACTIVE" (rect 0 0 67 12)(font "Arial" ))
+		(text "VGA_ACTIVE" (rect 211 427 278 439)(font "Arial" ))
+		(line (pt 288 432)(pt 272 432))
+	)
+	(port
+		(pt 288 448)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 114 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 443 285 455)(font "Arial" ))
+		(line (pt 288 448)(pt 272 448)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 278 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 464)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 459 282 471)(font "Arial" ))
+		(line (pt 288 464)(pt 272 464)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 480))
+	)
+)
+(symbol
+	(rect 1800 536 1832 568)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst7" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 1896 456 2040 560)
+	(text "ALTSHIFT_TAPS" (rect 23 1 141 17)(font "Arial" (font_size 10)))
+	(text "fifo_inst2" (rect 8 88 55 100)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "shiftin[WIDTH-1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "shiftin[]" (rect 21 25 62 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "clken" (rect 0 0 25 12)(font "Arial" ))
+		(text "clken" (rect 21 57 50 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 25 12)(font "Arial" ))
+		(text "clock" (rect 21 41 50 55)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "aclr" (rect 24 72 45 86)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 24 72 45 86)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "shiftout[WIDTH-1..0]" (rect -208 0 -105 12)(font "Arial" ))
+		(text "shiftout[]" (rect 82 25 131 39)(font "Arial" (font_size 8)))
+		(line (pt 144 32)(pt 128 32)(line_width 3))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "taps[(WIDTH*NUMBER_OF_TAPS) -1..0]" (rect -208 0 -4 12)(font "Arial" ))
+		(text "taps[]" (rect 97 41 128 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(parameter
+		"NUMBER_OF_TAPS"
+		"5"
+		"Number of output taps, each separated by TAP_DISTANCE clock cycles"
+	)
+	(parameter
+		"TAP_DISTANCE"
+		"800"
+		"Number of shift positions between output taps"
+	)
+	(parameter
+		"WIDTH"
+		"30"
+		"Number of bits for the shiftin input"
+	)
+	(drawing
+		(line (pt 16 56)(pt 24 48))
+		(line (pt 16 40)(pt 24 48))
+		(rectangle (rect 16 16 128 88))
+	)
+	(annotation_block (parameter)(rect 1880 400 2049 456))
+)
+(symbol
+	(rect 1672 848 1960 1024)
+	(text "vga_mouse_square" (rect 5 0 101 12)(font "Arial" ))
+	(text "vga_mouse_catapult_inst" (rect 8 160 134 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vga_xy_rsc_z[19..0]" (rect 0 0 101 12)(font "Arial" ))
+		(text "vga_xy_rsc_z[19..0]" (rect 21 27 122 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "mouse_xy_rsc_z[19..0]" (rect 0 0 115 12)(font "Arial" ))
+		(text "mouse_xy_rsc_z[19..0]" (rect 21 43 136 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "cursor_size_rsc_z[7..0]" (rect 0 0 113 12)(font "Arial" ))
+		(text "cursor_size_rsc_z[7..0]" (rect 21 59 134 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "video_in_rsc_z[29..0]" (rect 0 0 105 12)(font "Arial" ))
+		(text "video_in_rsc_z[29..0]" (rect 21 75 126 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 91 35 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "en" (rect 0 0 11 12)(font "Arial" ))
+		(text "en" (rect 21 107 32 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "arst_n" (rect 0 0 30 12)(font "Arial" ))
+		(text "arst_n" (rect 21 123 51 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "video_out_rsc_z[29..0]" (rect 0 0 112 12)(font "Arial" ))
+		(text "video_out_rsc_z[29..0]" (rect 173 27 285 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 160))
+	)
+)
+(symbol
+	(rect 1704 1080 1944 1192)
+	(text "mean_vga" (rect 5 0 56 12)(font "Arial" ))
+	(text "vga_blur_catapult_inst" (rect 8 96 118 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vin_rsc_z[89..0]" (rect 0 0 79 12)(font "Arial" ))
+		(text "vin_rsc_z[89..0]" (rect 21 27 100 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 11 12)(font "Arial" ))
+		(text "en" (rect 21 59 32 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "arst_n" (rect 0 0 30 12)(font "Arial" ))
+		(text "arst_n" (rect 21 75 51 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 240 32)
+		(output)
+		(text "vout_rsc_z[29..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "vout_rsc_z[29..0]" (rect 147 27 233 39)(font "Arial" ))
+		(line (pt 240 32)(pt 224 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 224 96))
+	)
+)
+(symbol
+	(rect 1528 1128 1560 1144)
+	(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
+	(text "inst8" (rect 3 5 26 17)(font "Arial" )(invisible))
+	(port
+		(pt 16 16)
+		(output)
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(line (pt 16 16)(pt 16 8))
+	)
+	(drawing
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(connector
+	(pt 1048 96)
+	(pt 1080 96)
+	(bus)
+)
+(connector
+	(pt 1048 112)
+	(pt 1096 112)
+	(bus)
+)
+(connector
+	(pt 1112 128)
+	(pt 1048 128)
+	(bus)
+)
+(connector
+	(pt 1128 144)
+	(pt 1048 144)
+	(bus)
+)
+(connector
+	(pt 1144 160)
+	(pt 1048 160)
+	(bus)
+)
+(connector
+	(pt 1048 176)
+	(pt 1144 176)
+	(bus)
+)
+(connector
+	(pt 1048 192)
+	(pt 1144 192)
+	(bus)
+)
+(connector
+	(pt 1048 208)
+	(pt 1144 208)
+)
+(connector
+	(pt 1048 224)
+	(pt 1144 224)
+)
+(connector
+	(pt 1048 240)
+	(pt 1144 240)
+)
+(connector
+	(pt 1048 256)
+	(pt 1144 256)
+)
+(connector
+	(pt 1048 272)
+	(pt 1144 272)
+)
+(connector
+	(pt 1048 288)
+	(pt 1144 288)
+)
+(connector
+	(pt 1048 304)
+	(pt 1144 304)
+)
+(connector
+	(pt 1048 320)
+	(pt 1144 320)
+)
+(connector
+	(pt 1048 336)
+	(pt 1144 336)
+)
+(connector
+	(pt 1048 352)
+	(pt 1144 352)
+)
+(connector
+	(pt 1080 96)
+	(pt 1080 32)
+	(bus)
+)
+(connector
+	(pt 1096 112)
+	(pt 1096 -8)
+	(bus)
+)
+(connector
+	(pt 1112 128)
+	(pt 1112 -24)
+	(bus)
+)
+(connector
+	(pt 1128 144)
+	(pt 1128 -40)
+	(bus)
+)
+(connector
+	(pt 1144 160)
+	(pt 1144 -56)
+	(bus)
+)
+(connector
+	(pt 656 736)
+	(pt 656 728)
+)
+(connector
+	(text "HEX1[6..0]" (rect 978 848 1031 860)(font "Arial" ))
+	(pt 968 864)
+	(pt 1096 864)
+	(bus)
+)
+(connector
+	(text "HEX2[6..0]" (rect 978 864 1031 876)(font "Arial" ))
+	(pt 968 880)
+	(pt 1096 880)
+	(bus)
+)
+(connector
+	(text "HEX3[6..0]" (rect 978 880 1031 892)(font "Arial" ))
+	(pt 968 896)
+	(pt 1096 896)
+	(bus)
+)
+(connector
+	(text "MOUSE_X[1..0]" (rect 1018 912 1094 924)(font "Arial" ))
+	(pt 1008 928)
+	(pt 1120 928)
+	(bus)
+)
+(connector
+	(text "MOUSE_Y[1..0]" (rect 1018 928 1097 940)(font "Arial" ))
+	(pt 1008 944)
+	(pt 1120 944)
+	(bus)
+)
+(connector
+	(text "KEY[1]" (rect 666 720 701 732)(font "Arial" ))
+	(pt 656 736)
+	(pt 760 736)
+)
+(connector
+	(text "KEY[0]" (rect 666 736 701 748)(font "Arial" ))
+	(pt 656 752)
+	(pt 760 752)
+)
+(connector
+	(pt 1008 928)
+	(pt 1008 944)
+	(bus)
+)
+(connector
+	(pt 1008 944)
+	(pt 1008 952)
+	(bus)
+)
+(connector
+	(text "PS2_CLK" (rect 986 720 1033 732)(font "Arial" ))
+	(pt 968 736)
+	(pt 1072 736)
+)
+(connector
+	(text "PS2_DAT" (rect 978 736 1025 748)(font "Arial" ))
+	(pt 968 752)
+	(pt 1072 752)
+)
+(connector
+	(text "HEX0[6..0]" (rect 978 832 1031 844)(font "Arial" ))
+	(pt 968 848)
+	(pt 1096 848)
+	(bus)
+)
+(connector
+	(text "LEDG[2]" (rect 978 752 1020 764)(font "Arial" ))
+	(pt 968 768)
+	(pt 1096 768)
+)
+(connector
+	(text "VGA_CLK" (rect 1058 432 1107 444)(font "Arial" ))
+	(pt 1048 448)
+	(pt 1232 448)
+)
+(connector
+	(pt 760 144)
+	(pt 704 144)
+	(bus)
+)
+(connector
+	(text "oLEDG[9..0]" (rect 978 16 1039 28)(font "Arial" ))
+	(pt 1080 32)
+	(pt 968 32)
+	(bus)
+)
+(connector
+	(text "X[11..0]" (rect 1056 448 1093 460)(font "Arial" ))
+	(pt 1048 464)
+	(pt 1256 464)
+	(bus)
+)
+(connector
+	(text "Y[11..0]" (rect 1056 464 1096 476)(font "Arial" ))
+	(pt 1048 480)
+	(pt 1256 480)
+	(bus)
+)
+(connector
+	(pt 760 128)
+	(pt 680 128)
+	(bus)
+)
+(connector
+	(text "CLOCK_50" (rect 666 752 721 764)(font "Arial" ))
+	(pt 656 768)
+	(pt 760 768)
+)
+(connector
+	(pt 552 608)
+	(pt 640 608)
+)
+(connector
+	(pt 640 608)
+	(pt 640 616)
+)
+(connector
+	(pt 552 584)
+	(pt 640 584)
+)
+(connector
+	(text "CLOCK_50" (rect 602 80 657 92)(font "Arial" ))
+	(pt 592 96)
+	(pt 760 96)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -24 1037 -12)(font "Arial" ))
+	(pt 1096 -8)
+	(pt 968 -8)
+	(bus)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -40 1037 -28)(font "Arial" ))
+	(pt 1112 -24)
+	(pt 968 -24)
+	(bus)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -56 1037 -44)(font "Arial" ))
+	(pt 1128 -40)
+	(pt 968 -40)
+	(bus)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -72 1037 -60)(font "Arial" ))
+	(pt 1144 -56)
+	(pt 968 -56)
+	(bus)
+)
+(connector
+	(text "KEY[2..0]" (rect 602 96 650 108)(font "Arial" ))
+	(pt 592 112)
+	(pt 760 112)
+	(bus)
+)
+(connector
+	(pt 2376 1168)
+	(pt 2376 1216)
+	(bus)
+)
+(connector
+	(text "SW[5..4]" (rect 2306 1200 2349 1212)(font "Arial" ))
+	(pt 2376 1216)
+	(pt 2296 1216)
+	(bus)
+)
+(connector
+	(pt 1048 512)
+	(pt 1144 512)
+	(bus)
+)
+(connector
+	(pt 1048 528)
+	(pt 1144 528)
+	(bus)
+)
+(connector
+	(text "VGA_HS" (rect 1058 352 1101 364)(font "Arial" ))
+	(pt 1048 368)
+	(pt 1128 368)
+)
+(connector
+	(text "VGA_VS" (rect 1058 368 1100 380)(font "Arial" ))
+	(pt 1048 384)
+	(pt 1128 384)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 2122 1128 2230 1140)(font "Arial" ))
+	(pt 2304 1144)
+	(pt 2112 1144)
+	(bus)
+)
+(connector
+	(text "VGA_MOUSE_OUT[29..0]" (rect 2130 1112 2257 1124)(font "Arial" ))
+	(pt 2120 1128)
+	(pt 2304 1128)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[29..0]" (rect 2458 1104 2568 1116)(font "Arial" ))
+	(pt 2448 1120)
+	(pt 2600 1120)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[29..26]" (rect 922 1168 1038 1180)(font "Arial" ))
+	(pt 912 1184)
+	(pt 1120 1184)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[19..16]" (rect 922 1184 1038 1196)(font "Arial" ))
+	(pt 912 1200)
+	(pt 1120 1200)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[9..6]" (rect 922 1200 1027 1212)(font "Arial" ))
+	(pt 912 1216)
+	(pt 1120 1216)
+	(bus)
+)
+(connector
+	(text "R[9..0]" (rect 1058 384 1092 396)(font "Arial" ))
+	(pt 1048 400)
+	(pt 1256 400)
+	(bus)
+)
+(connector
+	(text "G[9..0]" (rect 1058 400 1092 412)(font "Arial" ))
+	(pt 1048 416)
+	(pt 1256 416)
+	(bus)
+)
+(connector
+	(text "B[9..0]" (rect 1058 416 1091 428)(font "Arial" ))
+	(pt 1048 432)
+	(pt 1256 432)
+	(bus)
+)
+(connector
+	(text "LEDG[0]" (rect 978 768 1020 780)(font "Arial" ))
+	(pt 968 784)
+	(pt 1096 784)
+)
+(connector
+	(text "LEDG[1]" (rect 978 784 1020 796)(font "Arial" ))
+	(pt 968 800)
+	(pt 1096 800)
+)
+(connector
+	(text "MOUSE_Y[9..2]" (rect 978 800 1057 812)(font "Arial" ))
+	(pt 968 816)
+	(pt 1096 816)
+	(bus)
+)
+(connector
+	(text "MOUSE_X[9..2]" (rect 978 816 1054 828)(font "Arial" ))
+	(pt 968 832)
+	(pt 1096 832)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1842 488 1891 500)(font "Arial" ))
+	(pt 1840 504)
+	(pt 1896 504)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 1706 472 1814 484)(font "Arial" ))
+	(pt 1896 488)
+	(pt 1696 488)
+	(bus)
+)
+(connector
+	(pt 1816 536)
+	(pt 1896 536)
+)
+(connector
+	(text "VGA_ACTIVE" (rect 1634 504 1701 516)(font "Arial" ))
+	(pt 1624 520)
+	(pt 1896 520)
+)
+(connector
+	(text "VGA_ACTIVE" (rect 1058 480 1125 492)(font "Arial" ))
+	(pt 1048 496)
+	(pt 1192 496)
+)
+(connector
+	(text "RGB_TAP[59..30]" (rect 2202 1080 2289 1092)(font "Arial" ))
+	(pt 2304 1096)
+	(pt 2192 1096)
+	(bus)
+)
+(connector
+	(text "X[9..0],Y[9..0]" (rect 1474 864 1543 876)(font "Arial" ))
+	(pt 1464 880)
+	(pt 1672 880)
+	(bus)
+)
+(connector
+	(text "SW[7..0]" (rect 1474 896 1517 908)(font "Arial" ))
+	(pt 1464 912)
+	(pt 1672 912)
+	(bus)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 1474 912 1582 924)(font "Arial" ))
+	(pt 1464 928)
+	(pt 1672 928)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1594 928 1643 940)(font "Arial" ))
+	(pt 1584 944)
+	(pt 1672 944)
+)
+(connector
+	(text "MOUSE_X[9..0],MOUSE_Y[9..0]" (rect 1472 880 1631 892)(font "Arial" ))
+	(pt 1464 896)
+	(pt 1672 896)
+	(bus)
+)
+(connector
+	(pt 1512 960)
+	(pt 1672 960)
+)
+(connector
+	(text "KEY[0]" (rect 1618 960 1653 972)(font "Arial" ))
+	(pt 1608 976)
+	(pt 1672 976)
+)
+(connector
+	(text "VGA_MOUSE_OUT[29..0]" (rect 2002 864 2129 876)(font "Arial" ))
+	(pt 1960 880)
+	(pt 2192 880)
+	(bus)
+)
+(connector
+	(text "<<__$DEF_ALIAS133>>" (rect 1954 1096 2072 1108)(font "Arial" )(invisible))
+	(pt 2304 1112)
+	(pt 1944 1112)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1626 1112 1675 1124)(font "Arial" ))
+	(pt 1616 1128)
+	(pt 1704 1128)
+)
+(connector
+	(pt 1544 1144)
+	(pt 1704 1144)
+)
+(connector
+	(text "KEY[0]" (rect 1650 1144 1685 1156)(font "Arial" ))
+	(pt 1640 1160)
+	(pt 1704 1160)
+)
+(connector
+	(text "RGB_TAP[89..0]" (rect 1602 1096 1683 1108)(font "Arial" ))
+	(pt 1704 1112)
+	(pt 1592 1112)
+	(bus)
+)
+(connector
+	(text "RGB_TAP[149..0]" (rect 2050 488 2137 500)(font "Arial" ))
+	(pt 2040 504)
+	(pt 2152 504)
+	(bus)
+)
+(junction (pt 1008 944))
+(text "MEMORY" (rect 1464 192 1517 206)(font "Arial" (font_size 8)))
+(text "PS/2 MOUSE CONTROLLER" (rect 760 992 1078 1014)(font "Arial" (font_size 14)))
+(text "PS/2 Interface" (rect 1088 736 1168 750)(font "Arial" (font_size 8)))
+(text "Mouse Buttons" (rect 1112 768 1196 782)(font "Arial" (font_size 8)))
+(text "Mouse XY Coordinates" (rect 1112 816 1242 830)(font "Arial" (font_size 8)))
+(text "7-Segments Mouse XY Coordinates" (rect 1112 864 1314 878)(font "Arial" (font_size 8)))
+(text "DIGITAL CAMERA" (rect 1416 488 1517 502)(font "Arial" (font_size 8)))
+(text "Hardware Block generated by the High-Level Synthesis Tool" (rect 1568 816 2229 838)(font "Arial" (font_size 14)(bold)))
+(text "Line Buffer" (rect 1912 376 2024 398)(font "Arial" (font_size 14)))
+(text "RED     GREEN    BLUE" (rect 2368 392 2580 410)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 584 2580 602)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 536 2580 554)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 488 2580 506)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 440 2580 458)(font "Arial" (font_size 12)))
+(text "149..120" (rect 2288 392 2347 408)(font "Arial" (font_size 10)(bold)))
+(text "119..90" (rect 2296 440 2346 456)(font "Arial" (font_size 10)(bold)))
+(text "89..60" (rect 2304 488 2346 504)(font "Arial" (font_size 10)(bold)))
+(text "59..30" (rect 2304 536 2346 552)(font "Arial" (font_size 10)(bold)))
+(text "29..0" (rect 2312 584 2346 600)(font "Arial" (font_size 10)(bold)))
+(text "RGB_TAP: 10 bits/colour x 3 colours x 5 rows" (rect 2296 352 2670 370)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 4" (rect 2560 584 2690 602)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 3" (rect 2560 536 2690 554)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 2" (rect 2560 488 2690 506)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 1" (rect 2560 440 2690 458)(font "Arial" (font_size 11)(bold)))
+(text "Current Row" (rect 2560 392 2666 410)(font "Arial" (font_size 11)(bold)))
+(text "29..20            19..10             9..0" (rect 2368 616 2548 630)(font "Arial" (font_size 8)))
+(line (pt 2416 616)(pt 2416 376))
+(line (pt 2480 616)(pt 2480 376))
+(line (pt 2352 616)(pt 2352 376)(color 0 0 0)(line_width 2))
+(line (pt 2544 616)(pt 2544 376)(color 0 0 0)(line_width 2))
+(line (pt 2352 376)(pt 2544 376)(color 0 0 0)(line_width 2))
+(line (pt 2352 616)(pt 2544 616)(color 0 0 0)(line_width 2))
+(line (pt 2352 568)(pt 2544 568)(color 0 0 0)(line_width 2))
+(line (pt 2352 520)(pt 2544 520)(color 0 0 0)(line_width 2))
+(line (pt 2352 472)(pt 2544 472)(color 0 0 0)(line_width 2))
+(line (pt 2352 424)(pt 2544 424)(color 0 0 0)(line_width 2))
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v
new file mode 100644
index 0000000..f7904df
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v
@@ -0,0 +1,158 @@
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| ??????????        :| ??/??/??  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| X-Y coords
+// --------------------------------------------------------------------
+ 
+
+
+
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						oVGA_X,
+						oVGA_Y,
+						oVGA_ACTIVE,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+output  		[11:0]		oVGA_X;
+output  		[11:0]		oVGA_Y;
+output         	oVGA_ACTIVE;
+
+
+
+
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+reg 				active;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+						
+assign oVGA_X = 		H_Cont;				
+assign oVGA_Y = 		V_Cont;				
+assign oVGA_ACTIVE = active;
+	
+						
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+		active		<= 0;	
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		begin
+			H_Cont	<=	H_Cont+1;
+			active <= 1'b1;
+			end
+		else
+		begin
+			H_Cont	<=	0;
+			active <= 1'b0;			
+			end
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+			oVGA_H_SYNC	<=	0;
+		else
+			oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak
new file mode 100644
index 0000000..c9c3537
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak
@@ -0,0 +1,122 @@
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		H_Cont	<=	H_Cont+1;
+		else
+		H_Cont	<=	0;
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+		oVGA_H_SYNC	<=	0;
+		else
+		oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h
new file mode 100644
index 0000000..9d0fd32
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h
@@ -0,0 +1,16 @@
+//	Horizontal Parameter	( Pixel )
+parameter	H_SYNC_CYC	=	96;
+parameter	H_SYNC_BACK	=	48;
+parameter	H_SYNC_ACT	=	640;	
+parameter	H_SYNC_FRONT=	16;
+parameter	H_SYNC_TOTAL=	800;
+
+//	Virtical Parameter		( Line )
+parameter	V_SYNC_CYC	=	2;
+parameter	V_SYNC_BACK	=	33;
+parameter	V_SYNC_ACT	=	480;	
+parameter	V_SYNC_FRONT=	10;
+parameter	V_SYNC_TOTAL=	525;
+//	Start Offset
+parameter	X_START		=	H_SYNC_CYC+H_SYNC_BACK;
+parameter	Y_START		=	V_SYNC_CYC+V_SYNC_BACK;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v
new file mode 100644
index 0000000..6063417
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v
@@ -0,0 +1,271 @@
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE2_115_PS2 Mouse Controller 
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author                    :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN,HdHuang        :| 05/16/10  :| Initial Revision
+//   V1.1 :| Rui Duarte
+// --------------------------------------------------------------------
+module ps2(
+           iSTART,   //press the button for transmitting instrucions to device;
+           iRST_n,   //FSM reset signal;
+           iCLK_50,  //clock source;
+           PS2_CLK,  //ps2_clock signal inout;
+           PS2_DAT,  //ps2_data  signal inout;
+           oLEFBUT,  //left button press display;
+           oRIGBUT,  //right button press display;
+           oMIDBUT,  //middle button press display;
+			  oX,		   // 8-bit X coordinate value
+			  oY, 	   // 8-bit Y coordinate value
+           oX_MOV1,  //lower SEG of mouse displacement display for X axis.
+           oX_MOV2,  //higher SEG of mouse displacement display for X axis.
+           oY_MOV1,  //lower SEG of mouse displacement display for Y axis.
+           oY_MOV2   //higher SEG of mouse displacement display for Y axis.
+           ); 
+           //interface;
+//=======================================================
+//  PORT declarations
+//=======================================================
+
+input iSTART;
+input iRST_n;
+input iCLK_50;
+
+inout PS2_CLK;
+inout PS2_DAT;
+
+output oLEFBUT;
+output oRIGBUT;
+output oMIDBUT;
+output [7:0] oX;
+output [7:0] oY;
+output [6:0] oX_MOV1;
+output [6:0] oX_MOV2;
+output [6:0] oY_MOV1;
+output [6:0] oY_MOV2;
+
+//instantiation
+SEG7_LUT U1(.oSEG(oX_MOV1),.iDIG(x_latch[3:0]));
+SEG7_LUT U2(.oSEG(oX_MOV2),.iDIG(x_latch[7:4]));
+SEG7_LUT U3(.oSEG(oY_MOV1),.iDIG(y_latch[3:0]));
+SEG7_LUT U4(.oSEG(oY_MOV2),.iDIG(y_latch[7:4]));
+//instruction define, users can charge the instruction byte here for other purpose according to ps/2 mouse datasheet.
+//the MSB is of parity check bit, that's when there are odd number of 1's with data bits, it's value is '0',otherwise it's '1' instead.
+
+parameter enable_byte =9'b011110100;
+
+
+//=======================================================
+//  REG/WIRE declarations
+//=======================================================
+reg [1:0] cur_state,nex_state;
+reg ce,de;
+reg [3:0] byte_cnt,delay;
+reg [5:0] ct;
+reg [7:0] x_latch,y_latch,cnt;
+reg [8:0] clk_div;
+reg [9:0] dout_reg;
+reg [32:0] shift_reg;
+reg       leflatch,riglatch,midlatch;
+reg       ps2_clk_in,ps2_clk_syn1,ps2_dat_in,ps2_dat_syn1;
+wire      clk,ps2_dat_syn0,ps2_clk_syn0,ps2_dat_out,ps2_clk_out,flag;
+
+//=======================================================
+//  PARAMETER declarations
+//=======================================================
+//state define
+parameter listen =2'b00,
+          pullclk=2'b01,
+          pulldat=2'b10,
+          trans  =2'b11;
+          
+//=======================================================
+//  Structural coding
+//=======================================================          
+//clk division, derive a 97.65625KHz clock from the 50MHz source;
+
+always@(posedge iCLK_50)
+	begin
+		clk_div <= clk_div+1;
+	end
+	
+assign clk = clk_div[8];
+//tristate output control for PS2_DAT and PS2_CLK;
+assign PS2_CLK = ce?ps2_clk_out:1'bZ;
+assign PS2_DAT = de?ps2_dat_out:1'bZ;
+assign ps2_clk_out = 1'b0;
+assign ps2_dat_out = dout_reg[0];
+assign ps2_clk_syn0 = ce?1'b1:PS2_CLK;
+assign ps2_dat_syn0 = de?1'b1:PS2_DAT;
+//
+assign oLEFBUT = leflatch;
+assign oRIGBUT = riglatch;
+assign oMIDBUT = midlatch;
+//
+assign oX = x_latch;
+assign oY = y_latch;
+//
+//multi-clock region simple synchronization
+always@(posedge clk)
+	begin
+		ps2_clk_syn1 <= ps2_clk_syn0;
+		ps2_clk_in   <= ps2_clk_syn1;
+		ps2_dat_syn1 <= ps2_dat_syn0;
+		ps2_dat_in   <= ps2_dat_syn1;
+	end
+//FSM shift
+always@(*)
+begin
+   case(cur_state)
+     listen  :begin
+              if ((!iSTART) && (cnt == 8'b11111111))
+                  nex_state = pullclk;
+              else
+                  nex_state = listen;
+                         ce = 1'b0;
+                         de = 1'b0;
+              end
+     pullclk :begin
+              if (delay == 4'b1100)
+                  nex_state = pulldat;
+              else
+                  nex_state = pullclk;
+                         ce = 1'b1;
+                         de = 1'b0;
+              end
+     pulldat :begin
+                  nex_state = trans;
+                         ce = 1'b1;
+                         de = 1'b1;
+              end
+     trans   :begin
+              if  (byte_cnt == 4'b1010)
+                  nex_state = listen;
+              else    
+                  nex_state = trans;
+                         ce = 1'b0;
+                         de = 1'b1;
+              end
+     default :    nex_state = listen;
+   endcase
+end
+//idle counter
+always@(posedge clk)
+begin
+  if ({ps2_clk_in,ps2_dat_in} == 2'b11)
+	begin
+		cnt <= cnt+1;
+    end
+  else begin
+		cnt <= 8'd0;
+       end
+end
+//periodically reset ct; ct counts the received data length;
+assign flag = (cnt == 8'hff)?1:0;
+always@(posedge ps2_clk_in,posedge flag)
+begin
+  if (flag)
+     ct <= 6'b000000;
+  else
+     ct <= ct+1;
+end
+//latch data from shift_reg;outputs is of 2's complement;
+//Please treat the cnt value here with caution, otherwise wrong data will be latched.
+always@(posedge clk,negedge iRST_n)
+begin
+   if (!iRST_n) 
+   begin
+      leflatch <= 1'b0;
+      riglatch <= 1'b0;
+      midlatch <= 1'b0;
+      x_latch  <= 8'd0;
+      y_latch  <= 8'd0;
+   end
+   else if (cnt == 8'b00011110 && (ct[5] == 1'b1 || ct[4] == 1'b1))
+   begin
+      leflatch <= shift_reg[1];
+      riglatch <= shift_reg[2];
+      midlatch <= shift_reg[3];
+      x_latch  <= x_latch+shift_reg[19 : 12];
+      y_latch  <= y_latch+shift_reg[30 : 23];
+   end
+end
+
+//pull ps2_clk low for 100us before transmit starts;
+always@(posedge clk)
+begin
+  if (cur_state == pullclk)
+     delay <= delay+1;
+  else
+     delay <= 4'b0000;
+end
+//transmit data to ps2 device;eg. 0xF4
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == trans)
+     dout_reg <= {1'b0,dout_reg[9:1]};
+  else
+     dout_reg <= {enable_byte,1'b0};
+end
+//transmit byte length counter
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == trans)
+     byte_cnt <= byte_cnt+1;
+  else
+     byte_cnt <= 4'b0000;
+end
+//receive data from ps2 device;
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == listen)
+     shift_reg <= {ps2_dat_in,shift_reg[32:1]};
+end
+//FSM movement
+always@(posedge clk,negedge iRST_n)
+begin
+  if (!iRST_n)
+     cur_state <= listen;
+  else
+     cur_state <= nex_state;
+end
+endmodule
+
+
+     
+
+
+     
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf
new file mode 100644
index 0000000..a895305
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf
@@ -0,0 +1,81 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 240 168)
+	(text "sdram_pll" (rect 92 0 158 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 240 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 240 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 178 152 401 315)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "5/2" (rect 77 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "5/2" (rect 77 121 165 253)(font "Arial" ))
+		(text "-117.00" (rect 98 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(line (pt 0 0)(pt 241 0))
+		(line (pt 241 0)(pt 241 169))
+		(line (pt 0 169)(pt 241 169))
+		(line (pt 0 0)(pt 0 169))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 91)(pt 48 132))
+		(line (pt 69 91)(pt 69 132)(line_width 3))
+		(line (pt 95 91)(pt 95 132)(line_width 3))
+		(line (pt 129 91)(pt 129 132)(line_width 3))
+		(line (pt 163 91)(pt 163 132))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 151))
+		(line (pt 40 151)(pt 207 151))
+		(line (pt 40 48)(pt 40 151))
+		(line (pt 239 64)(pt 207 64))
+		(line (pt 239 80)(pt 207 80))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf
new file mode 100644
index 0000000..a4a0f2e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="sdram_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip
new file mode 100644
index 0000000..7440d58
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v
new file mode 100644
index 0000000..6b4189b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-2600",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.60000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2600"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak
new file mode 100644
index 0000000..7fd74a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg
new file mode 100644
index 0000000..a48389a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html
new file mode 100644
index 0000000..2d27f12
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for sdram_pll.v </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file sdram_pll.v </CENTER></h2>
+<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
+<CENTER><img src=sdram_pll_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
new file mode 100644
index 0000000..9ff387e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
@@ -0,0 +1,429 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 21:47:19 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga_core
+// ------------------------------------------------------------------
+
+
+module mean_vga_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] slc_regs_regs_2_1_itm;
+  reg [9:0] slc_regs_regs_2_2_itm;
+  reg [9:0] slc_regs_regs_2_itm;
+  reg [9:0] slc_regs_regs_2_4_itm;
+  reg [9:0] slc_regs_regs_2_5_itm;
+  reg [9:0] slc_regs_regs_2_3_itm;
+  reg [9:0] slc_regs_regs_2_7_itm;
+  reg [9:0] slc_regs_regs_2_8_itm;
+  reg [9:0] slc_regs_regs_2_6_itm;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [13:0] ACC_acc_psp_sva;
+  wire [14:0] nl_ACC_acc_psp_sva;
+  wire [5:0] acc_imod_sva;
+  wire [6:0] nl_acc_imod_sva;
+  wire [11:0] acc_9_psp_sva;
+  wire [12:0] nl_acc_9_psp_sva;
+  wire [11:0] acc_14_psp_sva;
+  wire [12:0] nl_acc_14_psp_sva;
+  wire [13:0] ACC_acc_21_psp_sva;
+  wire [14:0] nl_ACC_acc_21_psp_sva;
+  wire [5:0] acc_imod_4_sva;
+  wire [6:0] nl_acc_imod_4_sva;
+  wire [3:0] acc_29_sdt;
+  wire [4:0] nl_acc_29_sdt;
+  wire [13:0] ACC_acc_20_psp_sva;
+  wire [14:0] nl_ACC_acc_20_psp_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [6:0] nl_acc_imod_2_sva;
+  wire [3:0] acc_19_sdt;
+  wire [4:0] nl_acc_19_sdt;
+  wire [3:0] acc_15_sdt;
+  wire [4:0] nl_acc_15_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC_acc_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_1_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_2_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[59:50]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[89:80])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[29:20])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[59:50])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[89:80])
+      + conv_u2u_10_11(slc_regs_regs_2_itm)));
+  assign ACC_acc_psp_sva = nl_ACC_acc_psp_sva[13:0];
+  assign nl_acc_imod_sva = conv_s2s_5_6({(({1'b1 , (acc_15_sdt[3:1])}) + 4'b1) ,
+      (acc_15_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_psp_sva[2:0]));
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_acc_9_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_20_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_20_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_2_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_20_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_2_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_20_psp_sva[13:12])
+      * 10'b100000001));
+  assign acc_9_psp_sva = nl_acc_9_psp_sva[11:0];
+  assign nl_acc_14_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_21_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_21_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_4_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_21_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_4_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_21_psp_sva[13:12])
+      * 10'b100000001));
+  assign acc_14_psp_sva = nl_acc_14_psp_sva[11:0];
+  assign nl_ACC_acc_21_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_7_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_8_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[49:40]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[79:70])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[19:10])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[49:40])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_u2u_10_11(slc_regs_regs_2_6_itm)));
+  assign ACC_acc_21_psp_sva = nl_ACC_acc_21_psp_sva[13:0];
+  assign nl_acc_imod_4_sva = conv_s2s_5_6({(({1'b1 , (acc_29_sdt[3:1])}) + 4'b1)
+      , (acc_29_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_21_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_21_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_21_psp_sva[2:0]));
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_acc_29_sdt = conv_u2u_3_4(~ (ACC_acc_21_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_21_psp_sva[8:6]);
+  assign acc_29_sdt = nl_acc_29_sdt[3:0];
+  assign nl_ACC_acc_20_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_4_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_5_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[39:30]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[69:60])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[9:0])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[39:30])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[69:60])
+      + conv_u2u_10_11(slc_regs_regs_2_3_itm)));
+  assign ACC_acc_20_psp_sva = nl_ACC_acc_20_psp_sva[13:0];
+  assign nl_acc_imod_2_sva = conv_s2s_5_6({(({1'b1 , (acc_19_sdt[3:1])}) + 4'b1)
+      , (acc_19_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_20_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_20_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_20_psp_sva[2:0]));
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign nl_acc_19_sdt = conv_u2u_3_4(~ (ACC_acc_20_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_20_psp_sva[8:6]);
+  assign acc_19_sdt = nl_acc_19_sdt[3:0];
+  assign nl_acc_15_sdt = conv_u2u_3_4(~ (ACC_acc_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_psp_sva[8:6]);
+  assign acc_15_sdt = nl_acc_15_sdt[3:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      slc_regs_regs_2_7_itm <= 10'b0;
+      slc_regs_regs_2_8_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+      slc_regs_regs_2_6_itm <= 10'b0;
+      slc_regs_regs_2_4_itm <= 10'b0;
+      slc_regs_regs_2_5_itm <= 10'b0;
+      slc_regs_regs_2_3_itm <= 10'b0;
+      slc_regs_regs_2_1_itm <= 10'b0;
+      slc_regs_regs_2_2_itm <= 10'b0;
+      slc_regs_regs_2_itm <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        slc_regs_regs_2_7_itm <= reg_regs_regs_0_sva_cse[49:40];
+        slc_regs_regs_2_8_itm <= reg_regs_regs_0_sva_cse[79:70];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+        slc_regs_regs_2_6_itm <= reg_regs_regs_0_sva_cse[19:10];
+        slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[39:30];
+        slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[69:60];
+        slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[9:0];
+        slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[59:50];
+        slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[89:80];
+        slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_psp_sva[11:9])
+            * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+            (acc_imod_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0])
+            , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+            + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_psp_sva[8:6])))
+            + ({4'b1001 , (acc_imod_sva[5])})))) + conv_u2u_20_10(conv_u2u_2_10(ACC_acc_psp_sva[13:12])
+            * 10'b100000001)) | ({5'b0 , (signext_5_2(acc_9_psp_sva[11:10]))});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= acc_9_psp_sva[9:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (acc_9_psp_sva[4:0]) | (signext_5_2(acc_14_psp_sva[11:10]));
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= acc_14_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_2;
+    input [1:0] vector;
+  begin
+    signext_5_2= {{3{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga
+//  Generated from file(s):
+//    5) $PROJECT_HOME/vga_mouse_filter/blur.c
+// ------------------------------------------------------------------
+
+
+module mean_vga (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  mean_vga_core mean_vga_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v.bak b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v.bak
new file mode 100644
index 0000000..6168631
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v.bak
@@ -0,0 +1,429 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 21:47:19 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga_core
+// ------------------------------------------------------------------
+
+
+module mean_vga_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] slc_regs_regs_2_1_itm;
+  reg [9:0] slc_regs_regs_2_2_itm;
+  reg [9:0] slc_regs_regs_2_itm;
+  reg [9:0] slc_regs_regs_2_4_itm;
+  reg [9:0] slc_regs_regs_2_5_itm;
+  reg [9:0] slc_regs_regs_2_3_itm;
+  reg [9:0] slc_regs_regs_2_7_itm;
+  reg [9:0] slc_regs_regs_2_8_itm;
+  reg [9:0] slc_regs_regs_2_6_itm;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [13:0] ACC_acc_psp_sva;
+  wire [14:0] nl_ACC_acc_psp_sva;
+  wire [5:0] acc_imod_sva;
+  wire [6:0] nl_acc_imod_sva;
+  wire [11:0] acc_9_psp_sva;
+  wire [12:0] nl_acc_9_psp_sva;
+  wire [11:0] acc_14_psp_sva;
+  wire [12:0] nl_acc_14_psp_sva;
+  wire [13:0] ACC_acc_21_psp_sva;
+  wire [14:0] nl_ACC_acc_21_psp_sva;
+  wire [5:0] acc_imod_4_sva;
+  wire [6:0] nl_acc_imod_4_sva;
+  wire [3:0] acc_29_sdt;
+  wire [4:0] nl_acc_29_sdt;
+  wire [13:0] ACC_acc_20_psp_sva;
+  wire [14:0] nl_ACC_acc_20_psp_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [6:0] nl_acc_imod_2_sva;
+  wire [3:0] acc_19_sdt;
+  wire [4:0] nl_acc_19_sdt;
+  wire [3:0] acc_15_sdt;
+  wire [4:0] nl_acc_15_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC_acc_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_1_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_2_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[59:50]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[89:80])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[29:20])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[59:50])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[89:80])
+      + conv_u2u_10_11(slc_regs_regs_2_itm)));
+  assign ACC_acc_psp_sva = nl_ACC_acc_psp_sva[13:0];
+  assign nl_acc_imod_sva = conv_s2s_5_6({(({1'b1 , (acc_15_sdt[3:1])}) + 4'b1) ,
+      (acc_15_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_psp_sva[2:0]));
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_acc_9_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_20_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_20_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_2_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_20_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_2_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_20_psp_sva[13:12])
+      * 10'b111000111));
+  assign acc_9_psp_sva = nl_acc_9_psp_sva[11:0];
+  assign nl_acc_14_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_21_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_21_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_4_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_21_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_4_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_21_psp_sva[13:12])
+      * 10'b111000111));
+  assign acc_14_psp_sva = nl_acc_14_psp_sva[11:0];
+  assign nl_ACC_acc_21_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_7_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_8_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[49:40]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[79:70])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[19:10])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[49:40])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_u2u_10_11(slc_regs_regs_2_6_itm)));
+  assign ACC_acc_21_psp_sva = nl_ACC_acc_21_psp_sva[13:0];
+  assign nl_acc_imod_4_sva = conv_s2s_5_6({(({1'b1 , (acc_29_sdt[3:1])}) + 4'b1)
+      , (acc_29_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_21_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_21_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_21_psp_sva[2:0]));
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_acc_29_sdt = conv_u2u_3_4(~ (ACC_acc_21_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_21_psp_sva[8:6]);
+  assign acc_29_sdt = nl_acc_29_sdt[3:0];
+  assign nl_ACC_acc_20_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_4_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_5_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[39:30]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[69:60])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[9:0])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[39:30])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[69:60])
+      + conv_u2u_10_11(slc_regs_regs_2_3_itm)));
+  assign ACC_acc_20_psp_sva = nl_ACC_acc_20_psp_sva[13:0];
+  assign nl_acc_imod_2_sva = conv_s2s_5_6({(({1'b1 , (acc_19_sdt[3:1])}) + 4'b1)
+      , (acc_19_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_20_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_20_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_20_psp_sva[2:0]));
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign nl_acc_19_sdt = conv_u2u_3_4(~ (ACC_acc_20_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_20_psp_sva[8:6]);
+  assign acc_19_sdt = nl_acc_19_sdt[3:0];
+  assign nl_acc_15_sdt = conv_u2u_3_4(~ (ACC_acc_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_psp_sva[8:6]);
+  assign acc_15_sdt = nl_acc_15_sdt[3:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      slc_regs_regs_2_7_itm <= 10'b0;
+      slc_regs_regs_2_8_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+      slc_regs_regs_2_6_itm <= 10'b0;
+      slc_regs_regs_2_4_itm <= 10'b0;
+      slc_regs_regs_2_5_itm <= 10'b0;
+      slc_regs_regs_2_3_itm <= 10'b0;
+      slc_regs_regs_2_1_itm <= 10'b0;
+      slc_regs_regs_2_2_itm <= 10'b0;
+      slc_regs_regs_2_itm <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        slc_regs_regs_2_7_itm <= reg_regs_regs_0_sva_cse[49:40];
+        slc_regs_regs_2_8_itm <= reg_regs_regs_0_sva_cse[79:70];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+        slc_regs_regs_2_6_itm <= reg_regs_regs_0_sva_cse[19:10];
+        slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[39:30];
+        slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[69:60];
+        slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[9:0];
+        slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[59:50];
+        slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[89:80];
+        slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_psp_sva[11:9])
+            * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+            (acc_imod_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0])
+            , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+            + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_psp_sva[8:6])))
+            + ({4'b1001 , (acc_imod_sva[5])})))) + conv_u2u_20_10(conv_u2u_2_10(ACC_acc_psp_sva[13:12])
+            * 10'b111000111)) | ({5'b0 , (signext_5_2(acc_9_psp_sva[11:10]))});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= acc_9_psp_sva[9:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (acc_9_psp_sva[4:0]) | (signext_5_2(acc_14_psp_sva[11:10]));
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= acc_14_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_2;
+    input [1:0] vector;
+  begin
+    signext_5_2= {{3{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga
+//  Generated from file(s):
+//    5) $PROJECT_HOME/vga_mouse_filter/blur.c
+// ------------------------------------------------------------------
+
+
+module mean_vga (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  mean_vga_core mean_vga_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
new file mode 100644
index 0000000..dda909a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
@@ -0,0 +1,171 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 11:57:58 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square_core
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square_core (
+  clk, en, arst_n, vga_xy_rsc_mgc_in_wire_d, mouse_xy_rsc_mgc_in_wire_d, cursor_size_rsc_mgc_in_wire_d,
+      video_in_rsc_mgc_in_wire_d, video_out_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [19:0] vga_xy_rsc_mgc_in_wire_d;
+  input [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  input [7:0] cursor_size_rsc_mgc_in_wire_d;
+  input [29:0] video_in_rsc_mgc_in_wire_d;
+  output [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_2;
+  wire or_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign video_out_rsc_mgc_out_stdreg_d = {reg_video_out_rsc_mgc_out_stdreg_d_tmp
+      , reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 , reg_video_out_rsc_mgc_out_stdreg_d_tmp_2};
+  assign or_itm = (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d}))));
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp <= (video_in_rsc_mgc_in_wire_d[29:20])
+            & ({{9{or_itm}}, or_itm});
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= video_in_rsc_mgc_in_wire_d[19:10];
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= (video_in_rsc_mgc_in_wire_d[9:0])
+            & ({{9{or_itm}}, or_itm});
+      end
+    end
+  end
+
+  function [0:0] readslicef_12_1_11;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 11;
+    readslicef_12_1_11 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square
+//  Generated from file(s):
+//   12) $PROJECT_HOME/vga_mouse_square__old/vga_mouse_square_working_demo_sw.c
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square (
+  vga_xy_rsc_z, mouse_xy_rsc_z, cursor_size_rsc_z, video_in_rsc_z, video_out_rsc_z,
+      clk, en, arst_n
+);
+  input [19:0] vga_xy_rsc_z;
+  input [19:0] mouse_xy_rsc_z;
+  input [7:0] cursor_size_rsc_z;
+  input [29:0] video_in_rsc_z;
+  output [29:0] video_out_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [19:0] vga_xy_rsc_mgc_in_wire_d;
+  wire [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  wire [7:0] cursor_size_rsc_mgc_in_wire_d;
+  wire [29:0] video_in_rsc_mgc_in_wire_d;
+  wire [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(20)) vga_xy_rsc_mgc_in_wire (
+      .d(vga_xy_rsc_mgc_in_wire_d),
+      .z(vga_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(20)) mouse_xy_rsc_mgc_in_wire (
+      .d(mouse_xy_rsc_mgc_in_wire_d),
+      .z(mouse_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(3),
+  .width(8)) cursor_size_rsc_mgc_in_wire (
+      .d(cursor_size_rsc_mgc_in_wire_d),
+      .z(cursor_size_rsc_z)
+    );
+  mgc_in_wire #(.rscid(4),
+  .width(30)) video_in_rsc_mgc_in_wire (
+      .d(video_in_rsc_mgc_in_wire_d),
+      .z(video_in_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(5),
+  .width(30)) video_out_rsc_mgc_out_stdreg (
+      .d(video_out_rsc_mgc_out_stdreg_d),
+      .z(video_out_rsc_z)
+    );
+  vga_mouse_square_core vga_mouse_square_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vga_xy_rsc_mgc_in_wire_d(vga_xy_rsc_mgc_in_wire_d),
+      .mouse_xy_rsc_mgc_in_wire_d(mouse_xy_rsc_mgc_in_wire_d),
+      .cursor_size_rsc_mgc_in_wire_d(cursor_size_rsc_mgc_in_wire_d),
+      .video_in_rsc_mgc_in_wire_d(video_in_rsc_mgc_in_wire_d),
+      .video_out_rsc_mgc_out_stdreg_d(video_out_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.cdb
new file mode 100644
index 0000000..fed3b3d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.hdb
new file mode 100644
index 0000000..10b47d0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(0).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.cdb
new file mode 100644
index 0000000..11212bc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.hdb
new file mode 100644
index 0000000..b084c22
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(1).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.cdb
new file mode 100644
index 0000000..44f49c4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.hdb
new file mode 100644
index 0000000..6a982c2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(10).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.cdb
new file mode 100644
index 0000000..076fc77
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.hdb
new file mode 100644
index 0000000..3a6978e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(11).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.cdb
new file mode 100644
index 0000000..d4398c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.hdb
new file mode 100644
index 0000000..667ef3a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(12).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.cdb
new file mode 100644
index 0000000..f749863
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.hdb
new file mode 100644
index 0000000..60a717a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(13).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.cdb
new file mode 100644
index 0000000..b55e91c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.hdb
new file mode 100644
index 0000000..993e08a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(14).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.cdb
new file mode 100644
index 0000000..94c98b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.hdb
new file mode 100644
index 0000000..b9cad57
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(15).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.cdb
new file mode 100644
index 0000000..94ab838
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.hdb
new file mode 100644
index 0000000..b6ead5b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(16).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.cdb
new file mode 100644
index 0000000..3b4d45f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.hdb
new file mode 100644
index 0000000..ec5de27
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(17).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.cdb
new file mode 100644
index 0000000..adab24a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.hdb
new file mode 100644
index 0000000..661ccaf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(18).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.cdb
new file mode 100644
index 0000000..93fc31f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.hdb
new file mode 100644
index 0000000..bb88a32
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(19).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.cdb
new file mode 100644
index 0000000..cfa3d78
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.hdb
new file mode 100644
index 0000000..520b5fa
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(2).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.cdb
new file mode 100644
index 0000000..72f2d34
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.hdb
new file mode 100644
index 0000000..2aee8da
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(20).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.cdb
new file mode 100644
index 0000000..9bfe37a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.hdb
new file mode 100644
index 0000000..488c860
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(21).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.cdb
new file mode 100644
index 0000000..aee32fe
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.hdb
new file mode 100644
index 0000000..5701492
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(22).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.cdb
new file mode 100644
index 0000000..7df5fc5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.hdb
new file mode 100644
index 0000000..5cd40e4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(23).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(24).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(24).cnf.cdb
new file mode 100644
index 0000000..8154e0a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(24).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(24).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(24).cnf.hdb
new file mode 100644
index 0000000..9934241
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(24).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(25).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(25).cnf.cdb
new file mode 100644
index 0000000..42f3d34
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(25).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(25).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(25).cnf.hdb
new file mode 100644
index 0000000..63603ce
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(25).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(26).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(26).cnf.cdb
new file mode 100644
index 0000000..5071e2a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(26).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(26).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(26).cnf.hdb
new file mode 100644
index 0000000..eed253c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(26).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(27).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(27).cnf.cdb
new file mode 100644
index 0000000..47ffcdb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(27).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(27).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(27).cnf.hdb
new file mode 100644
index 0000000..60d2624
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(27).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(28).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(28).cnf.cdb
new file mode 100644
index 0000000..9c5ee92
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(28).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(28).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(28).cnf.hdb
new file mode 100644
index 0000000..bbd07fc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(28).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(29).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(29).cnf.cdb
new file mode 100644
index 0000000..c31234d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(29).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(29).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(29).cnf.hdb
new file mode 100644
index 0000000..444a817
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(29).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(3).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(3).cnf.cdb
new file mode 100644
index 0000000..2e8313d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(3).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(3).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(3).cnf.hdb
new file mode 100644
index 0000000..7deee2a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(3).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(30).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(30).cnf.cdb
new file mode 100644
index 0000000..a7090a3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(30).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(30).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(30).cnf.hdb
new file mode 100644
index 0000000..33b9264
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(30).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(31).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(31).cnf.cdb
new file mode 100644
index 0000000..732460f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(31).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(31).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(31).cnf.hdb
new file mode 100644
index 0000000..d236fee
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(31).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(32).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(32).cnf.cdb
new file mode 100644
index 0000000..16925f8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(32).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(32).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(32).cnf.hdb
new file mode 100644
index 0000000..06de7cc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(32).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(33).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(33).cnf.cdb
new file mode 100644
index 0000000..d262432
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(33).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(33).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(33).cnf.hdb
new file mode 100644
index 0000000..5721538
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(33).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(34).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(34).cnf.cdb
new file mode 100644
index 0000000..8fe867e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(34).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(34).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(34).cnf.hdb
new file mode 100644
index 0000000..538d85a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(34).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(35).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(35).cnf.cdb
new file mode 100644
index 0000000..41a6595
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(35).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(35).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(35).cnf.hdb
new file mode 100644
index 0000000..41ed997
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(35).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(36).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(36).cnf.cdb
new file mode 100644
index 0000000..d151311
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(36).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(36).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(36).cnf.hdb
new file mode 100644
index 0000000..73a46a0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(36).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(37).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(37).cnf.cdb
new file mode 100644
index 0000000..c0dc434
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(37).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(37).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(37).cnf.hdb
new file mode 100644
index 0000000..359af67
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(37).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(38).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(38).cnf.cdb
new file mode 100644
index 0000000..9170e8d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(38).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(38).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(38).cnf.hdb
new file mode 100644
index 0000000..6b8c475
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(38).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(39).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(39).cnf.cdb
new file mode 100644
index 0000000..7158e97
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(39).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(39).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(39).cnf.hdb
new file mode 100644
index 0000000..62bcd96
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(39).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(4).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(4).cnf.cdb
new file mode 100644
index 0000000..273b69e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(4).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(4).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(4).cnf.hdb
new file mode 100644
index 0000000..c4f8fb7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(4).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(40).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(40).cnf.cdb
new file mode 100644
index 0000000..8810c15
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(40).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(40).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(40).cnf.hdb
new file mode 100644
index 0000000..c4255ff
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(40).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(41).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(41).cnf.cdb
new file mode 100644
index 0000000..96cdf47
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(41).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(41).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(41).cnf.hdb
new file mode 100644
index 0000000..6bc38c1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(41).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(42).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(42).cnf.cdb
new file mode 100644
index 0000000..6f1d418
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(42).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(42).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(42).cnf.hdb
new file mode 100644
index 0000000..6bc38c1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(42).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(43).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(43).cnf.cdb
new file mode 100644
index 0000000..575e2b7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(43).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(43).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(43).cnf.hdb
new file mode 100644
index 0000000..b63b256
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(43).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(44).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(44).cnf.cdb
new file mode 100644
index 0000000..62ae135
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(44).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(44).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(44).cnf.hdb
new file mode 100644
index 0000000..3b47ca6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(44).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(45).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(45).cnf.cdb
new file mode 100644
index 0000000..67a6618
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(45).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(45).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(45).cnf.hdb
new file mode 100644
index 0000000..5270294
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(45).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(46).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(46).cnf.cdb
new file mode 100644
index 0000000..f9519bc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(46).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(46).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(46).cnf.hdb
new file mode 100644
index 0000000..898ea51
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(46).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(47).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(47).cnf.cdb
new file mode 100644
index 0000000..08b24c1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(47).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(47).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(47).cnf.hdb
new file mode 100644
index 0000000..a89be5f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(47).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(48).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(48).cnf.cdb
new file mode 100644
index 0000000..021cf7a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(48).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(48).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(48).cnf.hdb
new file mode 100644
index 0000000..c708242
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(48).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(49).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(49).cnf.cdb
new file mode 100644
index 0000000..2a67842
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(49).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(49).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(49).cnf.hdb
new file mode 100644
index 0000000..5270294
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(49).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(5).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(5).cnf.cdb
new file mode 100644
index 0000000..a730d37
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(5).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(5).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(5).cnf.hdb
new file mode 100644
index 0000000..6813532
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(5).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(50).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(50).cnf.cdb
new file mode 100644
index 0000000..aac93e1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(50).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(50).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(50).cnf.hdb
new file mode 100644
index 0000000..aa38280
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(50).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(51).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(51).cnf.cdb
new file mode 100644
index 0000000..6b072c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(51).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(51).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(51).cnf.hdb
new file mode 100644
index 0000000..0770577
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(51).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(52).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(52).cnf.cdb
new file mode 100644
index 0000000..d9a6cc1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(52).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(52).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(52).cnf.hdb
new file mode 100644
index 0000000..657c10b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(52).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(53).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(53).cnf.cdb
new file mode 100644
index 0000000..4c4cf06
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(53).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(53).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(53).cnf.hdb
new file mode 100644
index 0000000..7e68645
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(53).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(54).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(54).cnf.cdb
new file mode 100644
index 0000000..a08a97c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(54).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(54).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(54).cnf.hdb
new file mode 100644
index 0000000..679159d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(54).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(55).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(55).cnf.cdb
new file mode 100644
index 0000000..22e3dbc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(55).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(55).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(55).cnf.hdb
new file mode 100644
index 0000000..26875f1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(55).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(56).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(56).cnf.cdb
new file mode 100644
index 0000000..22ecfc6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(56).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(56).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(56).cnf.hdb
new file mode 100644
index 0000000..dbe5d9d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(56).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(57).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(57).cnf.cdb
new file mode 100644
index 0000000..b9df076
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(57).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(57).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(57).cnf.hdb
new file mode 100644
index 0000000..9bce629
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(57).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(58).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(58).cnf.cdb
new file mode 100644
index 0000000..95711fb
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(58).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(58).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(58).cnf.hdb
new file mode 100644
index 0000000..b3ecbd1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(58).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(59).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(59).cnf.cdb
new file mode 100644
index 0000000..e2341b5
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(59).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(59).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(59).cnf.hdb
new file mode 100644
index 0000000..7b5e311
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(59).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(6).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(6).cnf.cdb
new file mode 100644
index 0000000..4bbc36f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(6).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(6).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(6).cnf.hdb
new file mode 100644
index 0000000..adab882
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(6).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(7).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(7).cnf.cdb
new file mode 100644
index 0000000..3695a42
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(7).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(7).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(7).cnf.hdb
new file mode 100644
index 0000000..dd1496c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(7).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(8).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(8).cnf.cdb
new file mode 100644
index 0000000..c4a4967
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(8).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(8).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(8).cnf.hdb
new file mode 100644
index 0000000..abcf6c9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(8).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(9).cnf.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(9).cnf.cdb
new file mode 100644
index 0000000..78f220b
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(9).cnf.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(9).cnf.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(9).cnf.hdb
new file mode 100644
index 0000000..dc54343
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.(9).cnf.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.bpm b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.bpm
new file mode 100644
index 0000000..9c9ebdd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.bpm
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.cdb
new file mode 100644
index 0000000..ab86e88
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.hdb
new file mode 100644
index 0000000..8cb18ba
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ace_cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm.qmsg
new file mode 100644
index 0000000..5319e7a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456854081388 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456854081390 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 17:41:20 2016 " "Processing started: Tue Mar 01 17:41:20 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456854081390 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456854081390 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456854081391 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456854082124 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456854082143 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "427 " "Peak virtual memory: 427 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456854082457 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 17:41:22 2016 " "Processing ended: Tue Mar 01 17:41:22 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456854082457 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456854082457 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456854082457 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456854082457 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm.rdb
new file mode 100644
index 0000000..f2786d6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm_labs.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm_labs.ddb
new file mode 100644
index 0000000..10dbc3f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.asm_labs.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cbx.xml b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cbx.xml
new file mode 100644
index 0000000..a2a61bd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cbx.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="DE0_D5M">
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" CBX_FILE_NAME="altpll_9ee2.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2" CBX_FILE_NAME="shift_taps_lpm.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" CBX_FILE_NAME="shift_taps_rnn.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" CBX_FILE_NAME="dcfifo_v5o1.tdf"/>
+		<CBX_INST_ENTRY INSTANCE_NAME="|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component" CBX_FILE_NAME="mux_u7e.tdf"/>
+	</PROJECT>
+</LOG_ROOT>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.bpm b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.bpm
new file mode 100644
index 0000000..9c9ebdd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.bpm
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.cdb
new file mode 100644
index 0000000..ab86e88
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.hdb
new file mode 100644
index 0000000..8cb18ba
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.idb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.idb
new file mode 100644
index 0000000..697affa
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.idb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.kpt
new file mode 100644
index 0000000..39c8abd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.logdb
new file mode 100644
index 0000000..105c8ca
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.logdb
@@ -0,0 +1,184 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,PASS,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,142;0;142;0;0;143;142;0;143;143;0;0;0;0;66;0;0;66;0;0;30;0;0;0;0;0;0;143;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,1;143;1;143;143;0;1;143;0;0;143;143;143;143;77;143;143;77;143;143;113;143;143;143;143;143;143;0;143;143,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,DRAM_LDQM,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKIN[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_UDQM,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_BA_1,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_BA_0,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CAS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CKE,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_RAS_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_WE_N,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_HS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_VS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_ADDR[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKOUT[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKOUT[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX2[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX3[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,DRAM_DQ[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_DAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,GPIO_1_CLKIN[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,10,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,20,
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.rdb
new file mode 100644
index 0000000..a1510e3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp_merge.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp_merge.kpt
new file mode 100644
index 0000000..3b82d37
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cmp_merge.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..da9e360
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..c2d6061
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.db_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.db_info
new file mode 100644
index 0000000..403c43e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 01 16:49:40 2016
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.eco.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.eco.cdb
new file mode 100644
index 0000000..74d5728
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.eco.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.fit.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.fit.qmsg
new file mode 100644
index 0000000..d29f8dd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.fit.qmsg
@@ -0,0 +1,69 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456854066082 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "DE0_D5M EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"DE0_D5M\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456854066347 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456854066420 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456854066420 ""}
+{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 Cyclone III PLL " "Implemented PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" as Cyclone III PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] 5 2 0 0 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1905 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1456854066485 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] 5 2 -117 -2600 " "Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] port" {  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1906 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1456854066485 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1905 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1456854066485 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456854066550 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456854066779 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456854066779 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456854066779 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456854066779 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 10034 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456854066783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 10036 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456854066783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 10038 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456854066783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 10040 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456854066783 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456854066783 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456854066786 ""}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1456854066794 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 143 " "No exact pin location assignment(s) for 1 pins of 143 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_CLK " "Pin VGA_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_CLK } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 292 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456854067575 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456854067575 ""}
+{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068052 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068052 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1456854068052 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1456854068052 ""}
+{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1456854068066 ""}
+{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068067 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068067 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1456854068067 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1456854068073 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1456854068073 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1456854068073 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1456854068073 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1456854068073 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854068092 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854068092 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854068092 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1456854068092 ""}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1456854068092 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068092 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068092 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "  20.000     CLOCK_50 " "  20.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068092 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068092 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\] " "   8.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1456854068092 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1456854068092 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p)) " "Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068232 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\] " "Destination node DE0_D5M:inst\|rClk\[0\]" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2248 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068232 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\] " "Destination node ps2:inst6\|clk_div\[8\]" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1204 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068232 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1376 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068232 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068232 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 10018 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068232 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[0\] (placed in counter C0 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G8 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1905 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068233 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2) " "Automatically promoted node DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|clk\[1\] (placed in counter C1 of PLL_2)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""}  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 31 2 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1905 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068233 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n)) " "Automatically promoted node GPIO_1_CLKIN\[0\]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0]~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 10027 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068233 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|rClk\[0\]  " "Automatically promoted node DE0_D5M:inst\|rClk\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|rClk\[0\]~0 " "Destination node DE0_D5M:inst\|rClk\[0\]~0" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5663 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1_CLKOUT\[0\]~output " "Destination node GPIO_1_CLKOUT\[0\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKOUT[0]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 9915 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGA_CLK~output " "Destination node VGA_CLK~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1272 736 912 1288 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 9899 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068233 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068233 ""}  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|rClk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2248 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068233 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK  " "Automatically promoted node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\|I2C_SCLK~1" {  } { { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 58 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4638 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0 " "Destination node DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK~0" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4823 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068234 ""}  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 69 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1376 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068234 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|ps2_clk_in  " "Automatically promoted node ps2:inst6\|ps2_clk_in " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|Equal2~0 " "Destination node ps2:inst6\|Equal2~0" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 186 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal2~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4459 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068234 ""}  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1227 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068234 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|clk_div\[8\]  " "Automatically promoted node ps2:inst6\|clk_div\[8\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|clk_div\[8\]~22 " "Destination node ps2:inst6\|clk_div\[8\]~22" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8]~22 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4453 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2:inst6\|ps2_clk_in " "Destination node ps2:inst6\|ps2_clk_in" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 101 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|ps2_clk_in } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1227 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068234 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068234 ""}  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 97 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|clk_div[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 1204 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068234 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|RD_MASK\[0\]~6 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|RD_MASK\[0\]~6" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 508 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4546 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[12\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[12\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5196 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[12\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR1_ADDR\[12\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5201 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[16\]~45 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[16\]~45" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~45 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5234 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[16\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD2_ADDR\[16\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5235 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5268 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~47 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rWR2_ADDR\[17\]~47" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5269 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[16\]~43 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[16\]~43" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~43 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5298 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[16\]~46 " "Destination node DE0_D5M:inst\|Sdram_Control_4Port:u7\|rRD1_ADDR\[16\]~46" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 443 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5303 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_0~2" {  } { { "V/Reset_Delay.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5640 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068235 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068235 ""}  } { { "V/Reset_Delay.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 46 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2172 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068235 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1  " "Automatically promoted node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068236 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "GPIO_1\[14\]~output " "Destination node GPIO_1\[14\]~output" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14]~output } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 5708 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068236 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1 " "Destination node DE0_D5M:inst\|Reset_Delay:u2\|oRST_1~1" {  } { { "V/Reset_Delay.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4858 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1456854068236 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1456854068236 ""}  } { { "V/Reset_Delay.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 47 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DE0_D5M:inst|Reset_Delay:u2|oRST_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 2173 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068236 ""}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2:inst6\|Equal3~2  " "Automatically promoted node ps2:inst6\|Equal3~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1456854068236 ""}  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2:inst6|Equal3~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 4475 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1456854068236 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456854068788 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456854068793 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456854068793 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456854068798 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456854068805 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456854068809 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456854068810 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456854068813 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456854069320 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456854069325 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456854069325 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456854069352 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456854069352 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456854069352 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 27 6 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 16 30 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 20 21 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 2 44 " "I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 15 28 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 28 19 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 38 5 " "I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456854069353 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456854069353 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456854069353 ""}
+{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 27 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "V/sdram_pll.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } } { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 328 1144 1320 344 "DRAM_CLK" "" } } } }  } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "Fitter" 0 -1 1456854069421 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Ignored I/O standard assignment to node \"AUD_ADCDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Ignored I/O standard assignment to node \"AUD_BCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Ignored I/O standard assignment to node \"AUD_DACDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Ignored I/O standard assignment to node \"AUD_DACLRCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Ignored I/O standard assignment to node \"AUD_XCK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[0\] " "Ignored I/O standard assignment to node \"BUTTON\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[1\] " "Ignored I/O standard assignment to node \"BUTTON\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "BUTTON\[2\] " "Ignored I/O standard assignment to node \"BUTTON\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_50_2 " "Ignored I/O standard assignment to node \"CLOCK_50_2\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_BYTE_N " "Ignored I/O standard assignment to node \"FL_BYTE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ15_AM1 " "Ignored I/O standard assignment to node \"FL_DQ15_AM1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[10\] " "Ignored I/O standard assignment to node \"FL_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[11\] " "Ignored I/O standard assignment to node \"FL_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[12\] " "Ignored I/O standard assignment to node \"FL_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[13\] " "Ignored I/O standard assignment to node \"FL_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[14\] " "Ignored I/O standard assignment to node \"FL_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[8\] " "Ignored I/O standard assignment to node \"FL_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[9\] " "Ignored I/O standard assignment to node \"FL_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[32\] " "Ignored I/O standard assignment to node \"GPIO_1\[32\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[33\] " "Ignored I/O standard assignment to node \"GPIO_1\[33\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[34\] " "Ignored I/O standard assignment to node \"GPIO_1\[34\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_1\[35\] " "Ignored I/O standard assignment to node \"GPIO_1\[35\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_DP " "Ignored I/O standard assignment to node \"HEX0_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[0\] " "Ignored I/O standard assignment to node \"HEX0_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[1\] " "Ignored I/O standard assignment to node \"HEX0_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[2\] " "Ignored I/O standard assignment to node \"HEX0_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[3\] " "Ignored I/O standard assignment to node \"HEX0_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[4\] " "Ignored I/O standard assignment to node \"HEX0_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[5\] " "Ignored I/O standard assignment to node \"HEX0_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_D\[6\] " "Ignored I/O standard assignment to node \"HEX0_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_DP " "Ignored I/O standard assignment to node \"HEX1_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[0\] " "Ignored I/O standard assignment to node \"HEX1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[1\] " "Ignored I/O standard assignment to node \"HEX1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[2\] " "Ignored I/O standard assignment to node \"HEX1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[3\] " "Ignored I/O standard assignment to node \"HEX1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[4\] " "Ignored I/O standard assignment to node \"HEX1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[5\] " "Ignored I/O standard assignment to node \"HEX1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[6\] " "Ignored I/O standard assignment to node \"HEX1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_DP " "Ignored I/O standard assignment to node \"HEX2_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[0\] " "Ignored I/O standard assignment to node \"HEX2_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[1\] " "Ignored I/O standard assignment to node \"HEX2_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[2\] " "Ignored I/O standard assignment to node \"HEX2_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[3\] " "Ignored I/O standard assignment to node \"HEX2_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[4\] " "Ignored I/O standard assignment to node \"HEX2_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[5\] " "Ignored I/O standard assignment to node \"HEX2_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[6\] " "Ignored I/O standard assignment to node \"HEX2_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_DP " "Ignored I/O standard assignment to node \"HEX3_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[0\] " "Ignored I/O standard assignment to node \"HEX3_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[1\] " "Ignored I/O standard assignment to node \"HEX3_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[2\] " "Ignored I/O standard assignment to node \"HEX3_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[3\] " "Ignored I/O standard assignment to node \"HEX3_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[4\] " "Ignored I/O standard assignment to node \"HEX3_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[5\] " "Ignored I/O standard assignment to node \"HEX3_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[6\] " "Ignored I/O standard assignment to node \"HEX3_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SCLK " "Ignored I/O standard assignment to node \"I2C_SCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "I2C_SDAT " "Ignored I/O standard assignment to node \"I2C_SDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "KEY\[3\] " "Ignored I/O standard assignment to node \"KEY\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_BLON " "Ignored I/O standard assignment to node \"LCD_BLON\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[0\] " "Ignored I/O standard assignment to node \"LCD_DATA\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[1\] " "Ignored I/O standard assignment to node \"LCD_DATA\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[2\] " "Ignored I/O standard assignment to node \"LCD_DATA\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[3\] " "Ignored I/O standard assignment to node \"LCD_DATA\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[4\] " "Ignored I/O standard assignment to node \"LCD_DATA\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[5\] " "Ignored I/O standard assignment to node \"LCD_DATA\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[6\] " "Ignored I/O standard assignment to node \"LCD_DATA\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[7\] " "Ignored I/O standard assignment to node \"LCD_DATA\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RS " "Ignored I/O standard assignment to node \"LCD_RS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RW " "Ignored I/O standard assignment to node \"LCD_RW\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBCLK " "Ignored I/O standard assignment to node \"PS2_KBCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBDAT " "Ignored I/O standard assignment to node \"PS2_KBDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT0 " "Ignored I/O standard assignment to node \"SD_DAT0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT3 " "Ignored I/O standard assignment to node \"SD_DAT3\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854069479 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1456854069479 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50_2 " "Node \"CLOCK_50_2\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456854069485 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456854069485 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456854069485 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456854069485 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456854069485 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456854069485 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1456854069485 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456854069486 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456854070265 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456854070812 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456854070835 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456854072956 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456854072956 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456854073648 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "11 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" {  } { { "loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 1 { 0 "Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456854075112 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456854075112 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456854076806 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456854076809 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456854076809 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "2.03 " "Total time spent on timing analysis during the Fitter is 2.03 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456854076900 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456854076931 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456854077366 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456854077394 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456854077686 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456854078469 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1456854079180 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "66 Cyclone III " "66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[1\] 3.3-V LVTTL AA11 " "Pin GPIO_1_CLKIN\[1\] uses I/O standard 3.3-V LVTTL at AA11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[9\] 3.3-V LVTTL D2 " "Pin SW\[9\] uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[8\] 3.3-V LVTTL E4 " "Pin SW\[8\] uses I/O standard 3.3-V LVTTL at E4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[15\] 3.3-V LVTTL F10 " "Pin DRAM_DQ\[15\] uses I/O standard 3.3-V LVTTL at F10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 154 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[14\] 3.3-V LVTTL E10 " "Pin DRAM_DQ\[14\] uses I/O standard 3.3-V LVTTL at E10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 155 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[13\] 3.3-V LVTTL A10 " "Pin DRAM_DQ\[13\] uses I/O standard 3.3-V LVTTL at A10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 156 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[12\] 3.3-V LVTTL B10 " "Pin DRAM_DQ\[12\] uses I/O standard 3.3-V LVTTL at B10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 157 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[11\] 3.3-V LVTTL C10 " "Pin DRAM_DQ\[11\] uses I/O standard 3.3-V LVTTL at C10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 158 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[10\] 3.3-V LVTTL A9 " "Pin DRAM_DQ\[10\] uses I/O standard 3.3-V LVTTL at A9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 159 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[9\] 3.3-V LVTTL B9 " "Pin DRAM_DQ\[9\] uses I/O standard 3.3-V LVTTL at B9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 160 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[8\] 3.3-V LVTTL A8 " "Pin DRAM_DQ\[8\] uses I/O standard 3.3-V LVTTL at A8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 161 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[7\] 3.3-V LVTTL F8 " "Pin DRAM_DQ\[7\] uses I/O standard 3.3-V LVTTL at F8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 162 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[6\] 3.3-V LVTTL H9 " "Pin DRAM_DQ\[6\] uses I/O standard 3.3-V LVTTL at H9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 163 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[5\] 3.3-V LVTTL G9 " "Pin DRAM_DQ\[5\] uses I/O standard 3.3-V LVTTL at G9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 164 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[4\] 3.3-V LVTTL F9 " "Pin DRAM_DQ\[4\] uses I/O standard 3.3-V LVTTL at F9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 165 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[3\] 3.3-V LVTTL E9 " "Pin DRAM_DQ\[3\] uses I/O standard 3.3-V LVTTL at E9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 166 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[2\] 3.3-V LVTTL H10 " "Pin DRAM_DQ\[2\] uses I/O standard 3.3-V LVTTL at H10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 167 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[1\] 3.3-V LVTTL G10 " "Pin DRAM_DQ\[1\] uses I/O standard 3.3-V LVTTL at G10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 168 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "DRAM_DQ\[0\] 3.3-V LVTTL D10 " "Pin DRAM_DQ\[0\] uses I/O standard 3.3-V LVTTL at D10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 168 1144 1328 184 "DRAM_DQ" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 169 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[31\] 3.3-V LVTTL V7 " "Pin GPIO_1\[31\] uses I/O standard 3.3-V LVTTL at V7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 170 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[30\] 3.3-V LVTTL V6 " "Pin GPIO_1\[30\] uses I/O standard 3.3-V LVTTL at V6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 171 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[29\] 3.3-V LVTTL U8 " "Pin GPIO_1\[29\] uses I/O standard 3.3-V LVTTL at U8" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 172 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[28\] 3.3-V LVTTL Y7 " "Pin GPIO_1\[28\] uses I/O standard 3.3-V LVTTL at Y7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 173 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[27\] 3.3-V LVTTL T9 " "Pin GPIO_1\[27\] uses I/O standard 3.3-V LVTTL at T9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 174 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[26\] 3.3-V LVTTL U9 " "Pin GPIO_1\[26\] uses I/O standard 3.3-V LVTTL at U9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 175 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[25\] 3.3-V LVTTL T10 " "Pin GPIO_1\[25\] uses I/O standard 3.3-V LVTTL at T10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 176 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[24\] 3.3-V LVTTL U10 " "Pin GPIO_1\[24\] uses I/O standard 3.3-V LVTTL at U10" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 177 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[23\] 3.3-V LVTTL R12 " "Pin GPIO_1\[23\] uses I/O standard 3.3-V LVTTL at R12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 178 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[22\] 3.3-V LVTTL R11 " "Pin GPIO_1\[22\] uses I/O standard 3.3-V LVTTL at R11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 179 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[21\] 3.3-V LVTTL T12 " "Pin GPIO_1\[21\] uses I/O standard 3.3-V LVTTL at T12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[20\] 3.3-V LVTTL U12 " "Pin GPIO_1\[20\] uses I/O standard 3.3-V LVTTL at U12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 181 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[19\] 3.3-V LVTTL R14 " "Pin GPIO_1\[19\] uses I/O standard 3.3-V LVTTL at R14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 182 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[18\] 3.3-V LVTTL T14 " "Pin GPIO_1\[18\] uses I/O standard 3.3-V LVTTL at T14" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 183 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[17\] 3.3-V LVTTL AB7 " "Pin GPIO_1\[17\] uses I/O standard 3.3-V LVTTL at AB7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 184 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[16\] 3.3-V LVTTL AA7 " "Pin GPIO_1\[16\] uses I/O standard 3.3-V LVTTL at AA7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 185 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[15\] 3.3-V LVTTL AA9 " "Pin GPIO_1\[15\] uses I/O standard 3.3-V LVTTL at AA9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 186 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[14\] 3.3-V LVTTL AB9 " "Pin GPIO_1\[14\] uses I/O standard 3.3-V LVTTL at AB9" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 187 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[13\] 3.3-V LVTTL V15 " "Pin GPIO_1\[13\] uses I/O standard 3.3-V LVTTL at V15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[12\] 3.3-V LVTTL W15 " "Pin GPIO_1\[12\] uses I/O standard 3.3-V LVTTL at W15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[11\] 3.3-V LVTTL T15 " "Pin GPIO_1\[11\] uses I/O standard 3.3-V LVTTL at T15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[10\] 3.3-V LVTTL U15 " "Pin GPIO_1\[10\] uses I/O standard 3.3-V LVTTL at U15" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[9\] 3.3-V LVTTL W17 " "Pin GPIO_1\[9\] uses I/O standard 3.3-V LVTTL at W17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[8\] 3.3-V LVTTL Y17 " "Pin GPIO_1\[8\] uses I/O standard 3.3-V LVTTL at Y17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[7\] 3.3-V LVTTL AB17 " "Pin GPIO_1\[7\] uses I/O standard 3.3-V LVTTL at AB17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[6\] 3.3-V LVTTL AA17 " "Pin GPIO_1\[6\] uses I/O standard 3.3-V LVTTL at AA17" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[5\] 3.3-V LVTTL AA18 " "Pin GPIO_1\[5\] uses I/O standard 3.3-V LVTTL at AA18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[4\] 3.3-V LVTTL AB18 " "Pin GPIO_1\[4\] uses I/O standard 3.3-V LVTTL at AB18" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[3\] 3.3-V LVTTL AB19 " "Pin GPIO_1\[3\] uses I/O standard 3.3-V LVTTL at AB19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[2\] 3.3-V LVTTL AA19 " "Pin GPIO_1\[2\] uses I/O standard 3.3-V LVTTL at AA19" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[1\] 3.3-V LVTTL AB20 " "Pin GPIO_1\[1\] uses I/O standard 3.3-V LVTTL at AB20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 200 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1\[0\] 3.3-V LVTTL AA20 " "Pin GPIO_1\[0\] uses I/O standard 3.3-V LVTTL at AA20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_DAT 3.3-V LVTTL P21 " "Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 576 376 552 592 "PS2_DAT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 295 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_CLK 3.3-V LVTTL P22 " "Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 600 376 552 616 "PS2_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 296 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[4\] 3.3-V LVTTL G5 " "Pin SW\[4\] uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[5\] 3.3-V LVTTL J7 " "Pin SW\[5\] uses I/O standard 3.3-V LVTTL at J7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL G21 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 88 424 592 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 282 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[0\] 3.3-V LVTTL H2 " "Pin KEY\[0\] uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[7\] 3.3-V LVTTL E3 " "Pin SW\[7\] uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[6\] 3.3-V LVTTL H7 " "Pin SW\[6\] uses I/O standard 3.3-V LVTTL at H7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL G4 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at G4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL H6 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at H6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL H5 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at H5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL J6 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at J6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[1\] 3.3-V LVTTL G3 " "Pin KEY\[1\] uses I/O standard 3.3-V LVTTL at G3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO_1_CLKIN\[0\] 3.3-V LVTTL AB11 " "Pin GPIO_1_CLKIN\[0\] uses I/O standard 3.3-V LVTTL at AB11" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1_CLKIN[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_CLKIN\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1_CLKIN[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "KEY\[2\] 3.3-V LVTTL F1 " "Pin KEY\[2\] uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { KEY[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 104 424 592 120 "KEY" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { KEY[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456854079213 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1456854079213 ""}
+{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "31 " "Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 170 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 171 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 172 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 173 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 174 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 175 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 176 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 177 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 178 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 179 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently enabled " "Pin GPIO_1\[20\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 181 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 183 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 184 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 185 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently enabled " "Pin GPIO_1\[15\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 186 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently enabled " "Pin GPIO_1\[14\] has a permanently enabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 187 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 188 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 189 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 190 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 191 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 192 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 193 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 194 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 195 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 196 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 197 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 198 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 199 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 200 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1456854079219 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1456854079219 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg " "Generated suppressed messages file C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456854079476 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 149 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 149 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1149 " "Peak virtual memory: 1149 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456854080107 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 17:41:20 2016 " "Processing ended: Tue Mar 01 17:41:20 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456854080107 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456854080107 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456854080107 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456854080107 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info
new file mode 100644
index 0000000..ca3a6aa
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hier_info
@@ -0,0 +1,15302 @@
+|TOP_DE0_CAMERA_MOUSE
+DRAM_LDQM <= DE0_D5M:inst.DRAM_LDQM
+CLOCK_50 => DE0_D5M:inst.CLOCK_50
+CLOCK_50 => ps2:inst6.iCLK_50
+DRAM_DQ[0] <> DE0_D5M:inst.DRAM_DQ[0]
+DRAM_DQ[1] <> DE0_D5M:inst.DRAM_DQ[1]
+DRAM_DQ[2] <> DE0_D5M:inst.DRAM_DQ[2]
+DRAM_DQ[3] <> DE0_D5M:inst.DRAM_DQ[3]
+DRAM_DQ[4] <> DE0_D5M:inst.DRAM_DQ[4]
+DRAM_DQ[5] <> DE0_D5M:inst.DRAM_DQ[5]
+DRAM_DQ[6] <> DE0_D5M:inst.DRAM_DQ[6]
+DRAM_DQ[7] <> DE0_D5M:inst.DRAM_DQ[7]
+DRAM_DQ[8] <> DE0_D5M:inst.DRAM_DQ[8]
+DRAM_DQ[9] <> DE0_D5M:inst.DRAM_DQ[9]
+DRAM_DQ[10] <> DE0_D5M:inst.DRAM_DQ[10]
+DRAM_DQ[11] <> DE0_D5M:inst.DRAM_DQ[11]
+DRAM_DQ[12] <> DE0_D5M:inst.DRAM_DQ[12]
+DRAM_DQ[13] <> DE0_D5M:inst.DRAM_DQ[13]
+DRAM_DQ[14] <> DE0_D5M:inst.DRAM_DQ[14]
+DRAM_DQ[15] <> DE0_D5M:inst.DRAM_DQ[15]
+GPIO_1[0] <> DE0_D5M:inst.GPIO_1[0]
+GPIO_1[1] <> DE0_D5M:inst.GPIO_1[1]
+GPIO_1[2] <> DE0_D5M:inst.GPIO_1[2]
+GPIO_1[3] <> DE0_D5M:inst.GPIO_1[3]
+GPIO_1[4] <> DE0_D5M:inst.GPIO_1[4]
+GPIO_1[5] <> DE0_D5M:inst.GPIO_1[5]
+GPIO_1[6] <> DE0_D5M:inst.GPIO_1[6]
+GPIO_1[7] <> DE0_D5M:inst.GPIO_1[7]
+GPIO_1[8] <> DE0_D5M:inst.GPIO_1[8]
+GPIO_1[9] <> DE0_D5M:inst.GPIO_1[9]
+GPIO_1[10] <> DE0_D5M:inst.GPIO_1[10]
+GPIO_1[11] <> DE0_D5M:inst.GPIO_1[11]
+GPIO_1[12] <> DE0_D5M:inst.GPIO_1[12]
+GPIO_1[13] <> DE0_D5M:inst.GPIO_1[13]
+GPIO_1[14] <> DE0_D5M:inst.GPIO_1[14]
+GPIO_1[15] <> DE0_D5M:inst.GPIO_1[15]
+GPIO_1[16] <> DE0_D5M:inst.GPIO_1[16]
+GPIO_1[17] <> DE0_D5M:inst.GPIO_1[17]
+GPIO_1[18] <> DE0_D5M:inst.GPIO_1[18]
+GPIO_1[19] <> DE0_D5M:inst.GPIO_1[19]
+GPIO_1[20] <> DE0_D5M:inst.GPIO_1[20]
+GPIO_1[21] <> DE0_D5M:inst.GPIO_1[21]
+GPIO_1[22] <> DE0_D5M:inst.GPIO_1[22]
+GPIO_1[23] <> DE0_D5M:inst.GPIO_1[23]
+GPIO_1[24] <> DE0_D5M:inst.GPIO_1[24]
+GPIO_1[25] <> DE0_D5M:inst.GPIO_1[25]
+GPIO_1[26] <> DE0_D5M:inst.GPIO_1[26]
+GPIO_1[27] <> DE0_D5M:inst.GPIO_1[27]
+GPIO_1[28] <> DE0_D5M:inst.GPIO_1[28]
+GPIO_1[29] <> DE0_D5M:inst.GPIO_1[29]
+GPIO_1[30] <> DE0_D5M:inst.GPIO_1[30]
+GPIO_1[31] <> DE0_D5M:inst.GPIO_1[31]
+GPIO_1_CLKIN[0] => DE0_D5M:inst.GPIO_1_CLKIN[0]
+GPIO_1_CLKIN[1] => DE0_D5M:inst.GPIO_1_CLKIN[1]
+KEY[0] => DE0_D5M:inst.KEY[0]
+KEY[0] => ps2:inst6.iRST_n
+KEY[0] => vga_mouse_square:vga_mouse_catapult_inst.arst_n
+KEY[0] => mean_vga:vga_blur_catapult_inst.arst_n
+KEY[1] => DE0_D5M:inst.KEY[1]
+KEY[1] => ps2:inst6.iSTART
+KEY[2] => DE0_D5M:inst.KEY[2]
+SW[0] => DE0_D5M:inst.SW[0]
+SW[0] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[0]
+SW[1] => DE0_D5M:inst.SW[1]
+SW[1] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[1]
+SW[2] => DE0_D5M:inst.SW[2]
+SW[2] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[2]
+SW[3] => DE0_D5M:inst.SW[3]
+SW[3] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[3]
+SW[4] => DE0_D5M:inst.SW[4]
+SW[4] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[4]
+SW[4] => vga_mux:inst10.sel[0]
+SW[5] => DE0_D5M:inst.SW[5]
+SW[5] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[5]
+SW[5] => vga_mux:inst10.sel[1]
+SW[6] => DE0_D5M:inst.SW[6]
+SW[6] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[6]
+SW[7] => DE0_D5M:inst.SW[7]
+SW[7] => vga_mouse_square:vga_mouse_catapult_inst.cursor_size_rsc_z[7]
+SW[8] => DE0_D5M:inst.SW[8]
+SW[9] => DE0_D5M:inst.SW[9]
+DRAM_UDQM <= DE0_D5M:inst.DRAM_UDQM
+DRAM_BA_1 <= DE0_D5M:inst.DRAM_BA_1
+DRAM_BA_0 <= DE0_D5M:inst.DRAM_BA_0
+DRAM_CAS_N <= DE0_D5M:inst.DRAM_CAS_N
+DRAM_CKE <= DE0_D5M:inst.DRAM_CKE
+DRAM_CS_N <= DE0_D5M:inst.DRAM_CS_N
+DRAM_RAS_N <= DE0_D5M:inst.DRAM_RAS_N
+DRAM_WE_N <= DE0_D5M:inst.DRAM_WE_N
+DRAM_CLK <= DE0_D5M:inst.DRAM_CLK
+VGA_CLK <= DE0_D5M:inst.VGA_CLK
+VGA_HS <= DE0_D5M:inst.VGA_HS
+VGA_VS <= DE0_D5M:inst.VGA_VS
+PS2_DAT <> ps2:inst6.PS2_DAT
+PS2_CLK <> ps2:inst6.PS2_CLK
+DRAM_ADDR[0] <= DE0_D5M:inst.DRAM_ADDR[0]
+DRAM_ADDR[1] <= DE0_D5M:inst.DRAM_ADDR[1]
+DRAM_ADDR[2] <= DE0_D5M:inst.DRAM_ADDR[2]
+DRAM_ADDR[3] <= DE0_D5M:inst.DRAM_ADDR[3]
+DRAM_ADDR[4] <= DE0_D5M:inst.DRAM_ADDR[4]
+DRAM_ADDR[5] <= DE0_D5M:inst.DRAM_ADDR[5]
+DRAM_ADDR[6] <= DE0_D5M:inst.DRAM_ADDR[6]
+DRAM_ADDR[7] <= DE0_D5M:inst.DRAM_ADDR[7]
+DRAM_ADDR[8] <= DE0_D5M:inst.DRAM_ADDR[8]
+DRAM_ADDR[9] <= DE0_D5M:inst.DRAM_ADDR[9]
+DRAM_ADDR[10] <= DE0_D5M:inst.DRAM_ADDR[10]
+DRAM_ADDR[11] <= DE0_D5M:inst.DRAM_ADDR[11]
+GPIO_1_CLKOUT[0] <= DE0_D5M:inst.GPIO_1_CLKOUT[0]
+GPIO_1_CLKOUT[1] <= DE0_D5M:inst.GPIO_1_CLKOUT[1]
+HEX0[0] <= ps2:inst6.oX_MOV1[0]
+HEX0[1] <= ps2:inst6.oX_MOV1[1]
+HEX0[2] <= ps2:inst6.oX_MOV1[2]
+HEX0[3] <= ps2:inst6.oX_MOV1[3]
+HEX0[4] <= ps2:inst6.oX_MOV1[4]
+HEX0[5] <= ps2:inst6.oX_MOV1[5]
+HEX0[6] <= ps2:inst6.oX_MOV1[6]
+HEX1[0] <= ps2:inst6.oX_MOV2[0]
+HEX1[1] <= ps2:inst6.oX_MOV2[1]
+HEX1[2] <= ps2:inst6.oX_MOV2[2]
+HEX1[3] <= ps2:inst6.oX_MOV2[3]
+HEX1[4] <= ps2:inst6.oX_MOV2[4]
+HEX1[5] <= ps2:inst6.oX_MOV2[5]
+HEX1[6] <= ps2:inst6.oX_MOV2[6]
+HEX2[0] <= ps2:inst6.oY_MOV1[0]
+HEX2[1] <= ps2:inst6.oY_MOV1[1]
+HEX2[2] <= ps2:inst6.oY_MOV1[2]
+HEX2[3] <= ps2:inst6.oY_MOV1[3]
+HEX2[4] <= ps2:inst6.oY_MOV1[4]
+HEX2[5] <= ps2:inst6.oY_MOV1[5]
+HEX2[6] <= ps2:inst6.oY_MOV1[6]
+HEX3[0] <= ps2:inst6.oY_MOV2[0]
+HEX3[1] <= ps2:inst6.oY_MOV2[1]
+HEX3[2] <= ps2:inst6.oY_MOV2[2]
+HEX3[3] <= ps2:inst6.oY_MOV2[3]
+HEX3[4] <= ps2:inst6.oY_MOV2[4]
+HEX3[5] <= ps2:inst6.oY_MOV2[5]
+HEX3[6] <= ps2:inst6.oY_MOV2[6]
+LEDG[0] <= ps2:inst6.oRIGBUT
+LEDG[1] <= ps2:inst6.oMIDBUT
+LEDG[2] <= ps2:inst6.oLEFBUT
+LEDG[3] <= <GND>
+LEDG[4] <= <GND>
+LEDG[5] <= <GND>
+LEDG[6] <= <GND>
+LEDG[7] <= <GND>
+LEDG[8] <= <GND>
+LEDG[9] <= <GND>
+VGA_B[0] <= VGA_MUX_OUT[6].DB_MAX_OUTPUT_PORT_TYPE
+VGA_B[1] <= VGA_MUX_OUT[7].DB_MAX_OUTPUT_PORT_TYPE
+VGA_B[2] <= VGA_MUX_OUT[8].DB_MAX_OUTPUT_PORT_TYPE
+VGA_B[3] <= VGA_MUX_OUT[9].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[0] <= VGA_MUX_OUT[16].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[1] <= VGA_MUX_OUT[17].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[2] <= VGA_MUX_OUT[18].DB_MAX_OUTPUT_PORT_TYPE
+VGA_G[3] <= VGA_MUX_OUT[19].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[0] <= VGA_MUX_OUT[26].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[1] <= VGA_MUX_OUT[27].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[2] <= VGA_MUX_OUT[28].DB_MAX_OUTPUT_PORT_TYPE
+VGA_R[3] <= VGA_MUX_OUT[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst
+CLOCK_50 => CLOCK_50.IN4
+KEY[0] => KEY[0].IN1
+KEY[1] => _.IN1
+KEY[2] => _.IN1
+SW[0] => SW[0].IN1
+SW[1] => SW[1].IN1
+SW[2] => SW[2].IN1
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+LEDG[0] <= Y_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[1] <= Y_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[2] <= Y_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[3] <= Y_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[4] <= Y_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[5] <= Y_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[6] <= Y_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[7] <= Y_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[8] <= Y_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+LEDG[9] <= Y_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+HEX0[0] <= SEG7_LUT_8:u5.oSEG0
+HEX0[1] <= SEG7_LUT_8:u5.oSEG0
+HEX0[2] <= SEG7_LUT_8:u5.oSEG0
+HEX0[3] <= SEG7_LUT_8:u5.oSEG0
+HEX0[4] <= SEG7_LUT_8:u5.oSEG0
+HEX0[5] <= SEG7_LUT_8:u5.oSEG0
+HEX0[6] <= SEG7_LUT_8:u5.oSEG0
+HEX1[0] <= SEG7_LUT_8:u5.oSEG1
+HEX1[1] <= SEG7_LUT_8:u5.oSEG1
+HEX1[2] <= SEG7_LUT_8:u5.oSEG1
+HEX1[3] <= SEG7_LUT_8:u5.oSEG1
+HEX1[4] <= SEG7_LUT_8:u5.oSEG1
+HEX1[5] <= SEG7_LUT_8:u5.oSEG1
+HEX1[6] <= SEG7_LUT_8:u5.oSEG1
+HEX2[0] <= SEG7_LUT_8:u5.oSEG2
+HEX2[1] <= SEG7_LUT_8:u5.oSEG2
+HEX2[2] <= SEG7_LUT_8:u5.oSEG2
+HEX2[3] <= SEG7_LUT_8:u5.oSEG2
+HEX2[4] <= SEG7_LUT_8:u5.oSEG2
+HEX2[5] <= SEG7_LUT_8:u5.oSEG2
+HEX2[6] <= SEG7_LUT_8:u5.oSEG2
+HEX3[0] <= SEG7_LUT_8:u5.oSEG3
+HEX3[1] <= SEG7_LUT_8:u5.oSEG3
+HEX3[2] <= SEG7_LUT_8:u5.oSEG3
+HEX3[3] <= SEG7_LUT_8:u5.oSEG3
+HEX3[4] <= SEG7_LUT_8:u5.oSEG3
+HEX3[5] <= SEG7_LUT_8:u5.oSEG3
+HEX3[6] <= SEG7_LUT_8:u5.oSEG3
+DRAM_DQ[0] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[1] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[2] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[3] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[4] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[5] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[6] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[7] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[8] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[9] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[10] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[11] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[12] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[13] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[14] <> Sdram_Control_4Port:u7.DQ
+DRAM_DQ[15] <> Sdram_Control_4Port:u7.DQ
+DRAM_ADDR[0] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[1] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[2] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[3] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[4] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[5] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[6] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[7] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[8] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[9] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[10] <= Sdram_Control_4Port:u7.SA
+DRAM_ADDR[11] <= Sdram_Control_4Port:u7.SA
+DRAM_LDQM <= Sdram_Control_4Port:u7.DQM
+DRAM_UDQM <= Sdram_Control_4Port:u7.DQM
+DRAM_WE_N <= Sdram_Control_4Port:u7.WE_N
+DRAM_CAS_N <= Sdram_Control_4Port:u7.CAS_N
+DRAM_RAS_N <= Sdram_Control_4Port:u7.RAS_N
+DRAM_CS_N <= Sdram_Control_4Port:u7.CS_N
+DRAM_BA_0 <= Sdram_Control_4Port:u7.BA
+DRAM_BA_1 <= Sdram_Control_4Port:u7.BA
+DRAM_CLK <= sdram_pll:u6.c1
+DRAM_CKE <= Sdram_Control_4Port:u7.CKE
+VGA_HS <= VGA_Controller:u1.oVGA_H_SYNC
+VGA_VS <= VGA_Controller:u1.oVGA_V_SYNC
+VGA_R[0] <= VGA_Controller:u1.oVGA_R
+VGA_R[1] <= VGA_Controller:u1.oVGA_R
+VGA_R[2] <= VGA_Controller:u1.oVGA_R
+VGA_R[3] <= VGA_Controller:u1.oVGA_R
+VGA_R[4] <= VGA_Controller:u1.oVGA_R
+VGA_R[5] <= VGA_Controller:u1.oVGA_R
+VGA_R[6] <= VGA_Controller:u1.oVGA_R
+VGA_R[7] <= VGA_Controller:u1.oVGA_R
+VGA_R[8] <= VGA_Controller:u1.oVGA_R
+VGA_R[9] <= VGA_Controller:u1.oVGA_R
+VGA_G[0] <= VGA_Controller:u1.oVGA_G
+VGA_G[1] <= VGA_Controller:u1.oVGA_G
+VGA_G[2] <= VGA_Controller:u1.oVGA_G
+VGA_G[3] <= VGA_Controller:u1.oVGA_G
+VGA_G[4] <= VGA_Controller:u1.oVGA_G
+VGA_G[5] <= VGA_Controller:u1.oVGA_G
+VGA_G[6] <= VGA_Controller:u1.oVGA_G
+VGA_G[7] <= VGA_Controller:u1.oVGA_G
+VGA_G[8] <= VGA_Controller:u1.oVGA_G
+VGA_G[9] <= VGA_Controller:u1.oVGA_G
+VGA_B[0] <= VGA_Controller:u1.oVGA_B
+VGA_B[1] <= VGA_Controller:u1.oVGA_B
+VGA_B[2] <= VGA_Controller:u1.oVGA_B
+VGA_B[3] <= VGA_Controller:u1.oVGA_B
+VGA_B[4] <= VGA_Controller:u1.oVGA_B
+VGA_B[5] <= VGA_Controller:u1.oVGA_B
+VGA_B[6] <= VGA_Controller:u1.oVGA_B
+VGA_B[7] <= VGA_Controller:u1.oVGA_B
+VGA_B[8] <= VGA_Controller:u1.oVGA_B
+VGA_B[9] <= VGA_Controller:u1.oVGA_B
+VGA_CLK <= GPIO_1_CLKOUT[0].DB_MAX_OUTPUT_PORT_TYPE
+VGA_X[0] <= VGA_Controller:u1.oVGA_Y
+VGA_X[1] <= VGA_Controller:u1.oVGA_Y
+VGA_X[2] <= VGA_Controller:u1.oVGA_Y
+VGA_X[3] <= VGA_Controller:u1.oVGA_Y
+VGA_X[4] <= VGA_Controller:u1.oVGA_Y
+VGA_X[5] <= VGA_Controller:u1.oVGA_Y
+VGA_X[6] <= VGA_Controller:u1.oVGA_Y
+VGA_X[7] <= VGA_Controller:u1.oVGA_Y
+VGA_X[8] <= VGA_Controller:u1.oVGA_Y
+VGA_X[9] <= VGA_Controller:u1.oVGA_Y
+VGA_X[10] <= VGA_Controller:u1.oVGA_Y
+VGA_X[11] <= VGA_Controller:u1.oVGA_Y
+VGA_Y[0] <= VGA_Controller:u1.oVGA_X
+VGA_Y[1] <= VGA_Controller:u1.oVGA_X
+VGA_Y[2] <= VGA_Controller:u1.oVGA_X
+VGA_Y[3] <= VGA_Controller:u1.oVGA_X
+VGA_Y[4] <= VGA_Controller:u1.oVGA_X
+VGA_Y[5] <= VGA_Controller:u1.oVGA_X
+VGA_Y[6] <= VGA_Controller:u1.oVGA_X
+VGA_Y[7] <= VGA_Controller:u1.oVGA_X
+VGA_Y[8] <= VGA_Controller:u1.oVGA_X
+VGA_Y[9] <= VGA_Controller:u1.oVGA_X
+VGA_Y[10] <= VGA_Controller:u1.oVGA_X
+VGA_Y[11] <= VGA_Controller:u1.oVGA_X
+VGA_ACTIVE <= VGA_Controller:u1.oVGA_ACTIVE
+GPIO_1_CLKIN[0] => CCD_PIXCLK.IN2
+GPIO_1_CLKIN[1] => ~NO_FANOUT~
+GPIO_1_CLKOUT[0] <= GPIO_1_CLKOUT[0].DB_MAX_OUTPUT_PORT_TYPE
+GPIO_1_CLKOUT[1] <= <GND>
+GPIO_1[12] <> <UNC>
+GPIO_1[13] <> <UNC>
+GPIO_1[14] <> GPIO_1[14]
+GPIO_1[15] <> <VCC>
+GPIO_1[16] <> <UNC>
+GPIO_1[19] <> I2C_CCD_Config:u8.I2C_SDAT
+GPIO_1[20] <> I2C_CCD_Config:u8.I2C_SCLK
+GPIO_1[21] <> <UNC>
+GPIO_1[22] <> <UNC>
+GPIO_1[23] <> <UNC>
+GPIO_1[24] <> <UNC>
+GPIO_1[25] <> <UNC>
+GPIO_1[26] <> <UNC>
+GPIO_1[27] <> <UNC>
+GPIO_1[28] <> <UNC>
+GPIO_1[29] <> <UNC>
+GPIO_1[30] <> <UNC>
+GPIO_1[31] <> <UNC>
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1
+iRed[0] => oVGA_R.DATAB
+iRed[1] => oVGA_R.DATAB
+iRed[2] => oVGA_R.DATAB
+iRed[3] => oVGA_R.DATAB
+iRed[4] => oVGA_R.DATAB
+iRed[5] => oVGA_R.DATAB
+iRed[6] => oVGA_R.DATAB
+iRed[7] => oVGA_R.DATAB
+iRed[8] => oVGA_R.DATAB
+iRed[9] => oVGA_R.DATAB
+iGreen[0] => oVGA_G.DATAB
+iGreen[1] => oVGA_G.DATAB
+iGreen[2] => oVGA_G.DATAB
+iGreen[3] => oVGA_G.DATAB
+iGreen[4] => oVGA_G.DATAB
+iGreen[5] => oVGA_G.DATAB
+iGreen[6] => oVGA_G.DATAB
+iGreen[7] => oVGA_G.DATAB
+iGreen[8] => oVGA_G.DATAB
+iGreen[9] => oVGA_G.DATAB
+iBlue[0] => oVGA_B.DATAB
+iBlue[1] => oVGA_B.DATAB
+iBlue[2] => oVGA_B.DATAB
+iBlue[3] => oVGA_B.DATAB
+iBlue[4] => oVGA_B.DATAB
+iBlue[5] => oVGA_B.DATAB
+iBlue[6] => oVGA_B.DATAB
+iBlue[7] => oVGA_B.DATAB
+iBlue[8] => oVGA_B.DATAB
+iBlue[9] => oVGA_B.DATAB
+oRequest <= oRequest~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[0] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[1] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[2] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[3] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[4] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[5] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[6] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[7] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[8] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_R[9] <= oVGA_R.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[0] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[1] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[2] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[3] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[4] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[5] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[6] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[7] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[8] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_G[9] <= oVGA_G.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[0] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[1] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[2] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[3] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[4] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[5] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[6] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[7] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[8] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_B[9] <= oVGA_B.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_H_SYNC <= oVGA_H_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_V_SYNC <= oVGA_V_SYNC~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_SYNC <= <GND>
+oVGA_BLANK <= oVGA_BLANK.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_CLOCK <= iCLK.DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[0] <= H_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[1] <= H_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[2] <= H_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[3] <= H_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[4] <= H_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[5] <= H_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[6] <= H_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[7] <= H_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[8] <= H_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[9] <= H_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[10] <= H_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_X[11] <= H_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[0] <= V_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[1] <= V_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[2] <= V_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[3] <= V_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[4] <= V_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[5] <= V_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[6] <= V_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[7] <= V_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[8] <= V_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[9] <= V_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[10] <= V_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_Y[11] <= V_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oVGA_ACTIVE <= active.DB_MAX_OUTPUT_PORT_TYPE
+iCLK => oVGA_V_SYNC~reg0.CLK
+iCLK => V_Cont[0].CLK
+iCLK => V_Cont[1].CLK
+iCLK => V_Cont[2].CLK
+iCLK => V_Cont[3].CLK
+iCLK => V_Cont[4].CLK
+iCLK => V_Cont[5].CLK
+iCLK => V_Cont[6].CLK
+iCLK => V_Cont[7].CLK
+iCLK => V_Cont[8].CLK
+iCLK => V_Cont[9].CLK
+iCLK => V_Cont[10].CLK
+iCLK => V_Cont[11].CLK
+iCLK => active.CLK
+iCLK => oVGA_H_SYNC~reg0.CLK
+iCLK => H_Cont[0].CLK
+iCLK => H_Cont[1].CLK
+iCLK => H_Cont[2].CLK
+iCLK => H_Cont[3].CLK
+iCLK => H_Cont[4].CLK
+iCLK => H_Cont[5].CLK
+iCLK => H_Cont[6].CLK
+iCLK => H_Cont[7].CLK
+iCLK => H_Cont[8].CLK
+iCLK => H_Cont[9].CLK
+iCLK => H_Cont[10].CLK
+iCLK => H_Cont[11].CLK
+iCLK => oRequest~reg0.CLK
+iCLK => oVGA_CLOCK.DATAIN
+iRST_N => active.ACLR
+iRST_N => oVGA_H_SYNC~reg0.ACLR
+iRST_N => H_Cont[0].ACLR
+iRST_N => H_Cont[1].ACLR
+iRST_N => H_Cont[2].ACLR
+iRST_N => H_Cont[3].ACLR
+iRST_N => H_Cont[4].ACLR
+iRST_N => H_Cont[5].ACLR
+iRST_N => H_Cont[6].ACLR
+iRST_N => H_Cont[7].ACLR
+iRST_N => H_Cont[8].ACLR
+iRST_N => H_Cont[9].ACLR
+iRST_N => H_Cont[10].ACLR
+iRST_N => H_Cont[11].ACLR
+iRST_N => oRequest~reg0.ACLR
+iRST_N => oVGA_V_SYNC~reg0.ACLR
+iRST_N => V_Cont[0].ACLR
+iRST_N => V_Cont[1].ACLR
+iRST_N => V_Cont[2].ACLR
+iRST_N => V_Cont[3].ACLR
+iRST_N => V_Cont[4].ACLR
+iRST_N => V_Cont[5].ACLR
+iRST_N => V_Cont[6].ACLR
+iRST_N => V_Cont[7].ACLR
+iRST_N => V_Cont[8].ACLR
+iRST_N => V_Cont[9].ACLR
+iRST_N => V_Cont[10].ACLR
+iRST_N => V_Cont[11].ACLR
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2
+iCLK => oRST_2~reg0.CLK
+iCLK => oRST_1~reg0.CLK
+iCLK => oRST_0~reg0.CLK
+iCLK => Cont[0].CLK
+iCLK => Cont[1].CLK
+iCLK => Cont[2].CLK
+iCLK => Cont[3].CLK
+iCLK => Cont[4].CLK
+iCLK => Cont[5].CLK
+iCLK => Cont[6].CLK
+iCLK => Cont[7].CLK
+iCLK => Cont[8].CLK
+iCLK => Cont[9].CLK
+iCLK => Cont[10].CLK
+iCLK => Cont[11].CLK
+iCLK => Cont[12].CLK
+iCLK => Cont[13].CLK
+iCLK => Cont[14].CLK
+iCLK => Cont[15].CLK
+iCLK => Cont[16].CLK
+iCLK => Cont[17].CLK
+iCLK => Cont[18].CLK
+iCLK => Cont[19].CLK
+iCLK => Cont[20].CLK
+iCLK => Cont[21].CLK
+iCLK => Cont[22].CLK
+iCLK => Cont[23].CLK
+iCLK => Cont[24].CLK
+iCLK => Cont[25].CLK
+iCLK => Cont[26].CLK
+iCLK => Cont[27].CLK
+iCLK => Cont[28].CLK
+iCLK => Cont[29].CLK
+iCLK => Cont[30].CLK
+iCLK => Cont[31].CLK
+iRST => oRST_2~reg0.ACLR
+iRST => oRST_1~reg0.ACLR
+iRST => oRST_0~reg0.ACLR
+iRST => Cont[0].ACLR
+iRST => Cont[1].ACLR
+iRST => Cont[2].ACLR
+iRST => Cont[3].ACLR
+iRST => Cont[4].ACLR
+iRST => Cont[5].ACLR
+iRST => Cont[6].ACLR
+iRST => Cont[7].ACLR
+iRST => Cont[8].ACLR
+iRST => Cont[9].ACLR
+iRST => Cont[10].ACLR
+iRST => Cont[11].ACLR
+iRST => Cont[12].ACLR
+iRST => Cont[13].ACLR
+iRST => Cont[14].ACLR
+iRST => Cont[15].ACLR
+iRST => Cont[16].ACLR
+iRST => Cont[17].ACLR
+iRST => Cont[18].ACLR
+iRST => Cont[19].ACLR
+iRST => Cont[20].ACLR
+iRST => Cont[21].ACLR
+iRST => Cont[22].ACLR
+iRST => Cont[23].ACLR
+iRST => Cont[24].ACLR
+iRST => Cont[25].ACLR
+iRST => Cont[26].ACLR
+iRST => Cont[27].ACLR
+iRST => Cont[28].ACLR
+iRST => Cont[29].ACLR
+iRST => Cont[30].ACLR
+iRST => Cont[31].ACLR
+oRST_0 <= oRST_0~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oRST_1 <= oRST_1~reg0.DB_MAX_OUTPUT_PORT_TYPE
+oRST_2 <= oRST_2~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3
+oDATA[0] <= mCCD_DATA[0].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[1] <= mCCD_DATA[1].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[2] <= mCCD_DATA[2].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[3] <= mCCD_DATA[3].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[4] <= mCCD_DATA[4].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[5] <= mCCD_DATA[5].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[6] <= mCCD_DATA[6].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[7] <= mCCD_DATA[7].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[8] <= mCCD_DATA[8].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[9] <= mCCD_DATA[9].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[10] <= mCCD_DATA[10].DB_MAX_OUTPUT_PORT_TYPE
+oDATA[11] <= mCCD_DATA[11].DB_MAX_OUTPUT_PORT_TYPE
+oDVAL <= oDVAL.DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[0] <= X_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[1] <= X_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[2] <= X_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[3] <= X_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[4] <= X_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[5] <= X_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[6] <= X_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[7] <= X_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[8] <= X_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[9] <= X_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[10] <= X_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[11] <= X_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[12] <= X_Cont[12].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[13] <= X_Cont[13].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[14] <= X_Cont[14].DB_MAX_OUTPUT_PORT_TYPE
+oX_Cont[15] <= X_Cont[15].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[0] <= Y_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[1] <= Y_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[2] <= Y_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[3] <= Y_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[4] <= Y_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[5] <= Y_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[6] <= Y_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[7] <= Y_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[8] <= Y_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[9] <= Y_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[10] <= Y_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[11] <= Y_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[12] <= Y_Cont[12].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[13] <= Y_Cont[13].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[14] <= Y_Cont[14].DB_MAX_OUTPUT_PORT_TYPE
+oY_Cont[15] <= Y_Cont[15].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[0] <= Frame_Cont[0].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[1] <= Frame_Cont[1].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[2] <= Frame_Cont[2].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[3] <= Frame_Cont[3].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[4] <= Frame_Cont[4].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[5] <= Frame_Cont[5].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[6] <= Frame_Cont[6].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[7] <= Frame_Cont[7].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[8] <= Frame_Cont[8].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[9] <= Frame_Cont[9].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[10] <= Frame_Cont[10].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[11] <= Frame_Cont[11].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[12] <= Frame_Cont[12].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[13] <= Frame_Cont[13].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[14] <= Frame_Cont[14].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[15] <= Frame_Cont[15].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[16] <= Frame_Cont[16].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[17] <= Frame_Cont[17].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[18] <= Frame_Cont[18].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[19] <= Frame_Cont[19].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[20] <= Frame_Cont[20].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[21] <= Frame_Cont[21].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[22] <= Frame_Cont[22].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[23] <= Frame_Cont[23].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[24] <= Frame_Cont[24].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[25] <= Frame_Cont[25].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[26] <= Frame_Cont[26].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[27] <= Frame_Cont[27].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[28] <= Frame_Cont[28].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[29] <= Frame_Cont[29].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[30] <= Frame_Cont[30].DB_MAX_OUTPUT_PORT_TYPE
+oFrame_Cont[31] <= Frame_Cont[31].DB_MAX_OUTPUT_PORT_TYPE
+iDATA[0] => mCCD_DATA.DATAB
+iDATA[1] => mCCD_DATA.DATAB
+iDATA[2] => mCCD_DATA.DATAB
+iDATA[3] => mCCD_DATA.DATAB
+iDATA[4] => mCCD_DATA.DATAB
+iDATA[5] => mCCD_DATA.DATAB
+iDATA[6] => mCCD_DATA.DATAB
+iDATA[7] => mCCD_DATA.DATAB
+iDATA[8] => mCCD_DATA.DATAB
+iDATA[9] => mCCD_DATA.DATAB
+iDATA[10] => mCCD_DATA.DATAB
+iDATA[11] => mCCD_DATA.DATAB
+iFVAL => Pre_FVAL.DATAIN
+iFVAL => Equal0.IN1
+iFVAL => Equal1.IN0
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_DATA.OUTPUTSELECT
+iLVAL => mCCD_LVAL.DATAIN
+iSTART => mSTART.OUTPUTSELECT
+iEND => mSTART.OUTPUTSELECT
+iCLK => mCCD_DATA[0].CLK
+iCLK => mCCD_DATA[1].CLK
+iCLK => mCCD_DATA[2].CLK
+iCLK => mCCD_DATA[3].CLK
+iCLK => mCCD_DATA[4].CLK
+iCLK => mCCD_DATA[5].CLK
+iCLK => mCCD_DATA[6].CLK
+iCLK => mCCD_DATA[7].CLK
+iCLK => mCCD_DATA[8].CLK
+iCLK => mCCD_DATA[9].CLK
+iCLK => mCCD_DATA[10].CLK
+iCLK => mCCD_DATA[11].CLK
+iCLK => Frame_Cont[0].CLK
+iCLK => Frame_Cont[1].CLK
+iCLK => Frame_Cont[2].CLK
+iCLK => Frame_Cont[3].CLK
+iCLK => Frame_Cont[4].CLK
+iCLK => Frame_Cont[5].CLK
+iCLK => Frame_Cont[6].CLK
+iCLK => Frame_Cont[7].CLK
+iCLK => Frame_Cont[8].CLK
+iCLK => Frame_Cont[9].CLK
+iCLK => Frame_Cont[10].CLK
+iCLK => Frame_Cont[11].CLK
+iCLK => Frame_Cont[12].CLK
+iCLK => Frame_Cont[13].CLK
+iCLK => Frame_Cont[14].CLK
+iCLK => Frame_Cont[15].CLK
+iCLK => Frame_Cont[16].CLK
+iCLK => Frame_Cont[17].CLK
+iCLK => Frame_Cont[18].CLK
+iCLK => Frame_Cont[19].CLK
+iCLK => Frame_Cont[20].CLK
+iCLK => Frame_Cont[21].CLK
+iCLK => Frame_Cont[22].CLK
+iCLK => Frame_Cont[23].CLK
+iCLK => Frame_Cont[24].CLK
+iCLK => Frame_Cont[25].CLK
+iCLK => Frame_Cont[26].CLK
+iCLK => Frame_Cont[27].CLK
+iCLK => Frame_Cont[28].CLK
+iCLK => Frame_Cont[29].CLK
+iCLK => Frame_Cont[30].CLK
+iCLK => Frame_Cont[31].CLK
+iCLK => Y_Cont[0].CLK
+iCLK => Y_Cont[1].CLK
+iCLK => Y_Cont[2].CLK
+iCLK => Y_Cont[3].CLK
+iCLK => Y_Cont[4].CLK
+iCLK => Y_Cont[5].CLK
+iCLK => Y_Cont[6].CLK
+iCLK => Y_Cont[7].CLK
+iCLK => Y_Cont[8].CLK
+iCLK => Y_Cont[9].CLK
+iCLK => Y_Cont[10].CLK
+iCLK => Y_Cont[11].CLK
+iCLK => Y_Cont[12].CLK
+iCLK => Y_Cont[13].CLK
+iCLK => Y_Cont[14].CLK
+iCLK => Y_Cont[15].CLK
+iCLK => X_Cont[0].CLK
+iCLK => X_Cont[1].CLK
+iCLK => X_Cont[2].CLK
+iCLK => X_Cont[3].CLK
+iCLK => X_Cont[4].CLK
+iCLK => X_Cont[5].CLK
+iCLK => X_Cont[6].CLK
+iCLK => X_Cont[7].CLK
+iCLK => X_Cont[8].CLK
+iCLK => X_Cont[9].CLK
+iCLK => X_Cont[10].CLK
+iCLK => X_Cont[11].CLK
+iCLK => X_Cont[12].CLK
+iCLK => X_Cont[13].CLK
+iCLK => X_Cont[14].CLK
+iCLK => X_Cont[15].CLK
+iCLK => mCCD_LVAL.CLK
+iCLK => mCCD_FVAL.CLK
+iCLK => Pre_FVAL.CLK
+iCLK => mSTART.CLK
+iRST => Y_Cont[0].ACLR
+iRST => Y_Cont[1].ACLR
+iRST => Y_Cont[2].ACLR
+iRST => Y_Cont[3].ACLR
+iRST => Y_Cont[4].ACLR
+iRST => Y_Cont[5].ACLR
+iRST => Y_Cont[6].ACLR
+iRST => Y_Cont[7].ACLR
+iRST => Y_Cont[8].ACLR
+iRST => Y_Cont[9].ACLR
+iRST => Y_Cont[10].ACLR
+iRST => Y_Cont[11].ACLR
+iRST => Y_Cont[12].ACLR
+iRST => Y_Cont[13].ACLR
+iRST => Y_Cont[14].ACLR
+iRST => Y_Cont[15].ACLR
+iRST => X_Cont[0].ACLR
+iRST => X_Cont[1].ACLR
+iRST => X_Cont[2].ACLR
+iRST => X_Cont[3].ACLR
+iRST => X_Cont[4].ACLR
+iRST => X_Cont[5].ACLR
+iRST => X_Cont[6].ACLR
+iRST => X_Cont[7].ACLR
+iRST => X_Cont[8].ACLR
+iRST => X_Cont[9].ACLR
+iRST => X_Cont[10].ACLR
+iRST => X_Cont[11].ACLR
+iRST => X_Cont[12].ACLR
+iRST => X_Cont[13].ACLR
+iRST => X_Cont[14].ACLR
+iRST => X_Cont[15].ACLR
+iRST => mCCD_LVAL.ACLR
+iRST => mCCD_FVAL.ACLR
+iRST => Pre_FVAL.ACLR
+iRST => mCCD_DATA[0].ACLR
+iRST => mCCD_DATA[1].ACLR
+iRST => mCCD_DATA[2].ACLR
+iRST => mCCD_DATA[3].ACLR
+iRST => mCCD_DATA[4].ACLR
+iRST => mCCD_DATA[5].ACLR
+iRST => mCCD_DATA[6].ACLR
+iRST => mCCD_DATA[7].ACLR
+iRST => mCCD_DATA[8].ACLR
+iRST => mCCD_DATA[9].ACLR
+iRST => mCCD_DATA[10].ACLR
+iRST => mCCD_DATA[11].ACLR
+iRST => Frame_Cont[0].ACLR
+iRST => Frame_Cont[1].ACLR
+iRST => Frame_Cont[2].ACLR
+iRST => Frame_Cont[3].ACLR
+iRST => Frame_Cont[4].ACLR
+iRST => Frame_Cont[5].ACLR
+iRST => Frame_Cont[6].ACLR
+iRST => Frame_Cont[7].ACLR
+iRST => Frame_Cont[8].ACLR
+iRST => Frame_Cont[9].ACLR
+iRST => Frame_Cont[10].ACLR
+iRST => Frame_Cont[11].ACLR
+iRST => Frame_Cont[12].ACLR
+iRST => Frame_Cont[13].ACLR
+iRST => Frame_Cont[14].ACLR
+iRST => Frame_Cont[15].ACLR
+iRST => Frame_Cont[16].ACLR
+iRST => Frame_Cont[17].ACLR
+iRST => Frame_Cont[18].ACLR
+iRST => Frame_Cont[19].ACLR
+iRST => Frame_Cont[20].ACLR
+iRST => Frame_Cont[21].ACLR
+iRST => Frame_Cont[22].ACLR
+iRST => Frame_Cont[23].ACLR
+iRST => Frame_Cont[24].ACLR
+iRST => Frame_Cont[25].ACLR
+iRST => Frame_Cont[26].ACLR
+iRST => Frame_Cont[27].ACLR
+iRST => Frame_Cont[28].ACLR
+iRST => Frame_Cont[29].ACLR
+iRST => Frame_Cont[30].ACLR
+iRST => Frame_Cont[31].ACLR
+iRST => mSTART.ACLR
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4
+oRed[0] <= mCCD_R[0].DB_MAX_OUTPUT_PORT_TYPE
+oRed[1] <= mCCD_R[1].DB_MAX_OUTPUT_PORT_TYPE
+oRed[2] <= mCCD_R[2].DB_MAX_OUTPUT_PORT_TYPE
+oRed[3] <= mCCD_R[3].DB_MAX_OUTPUT_PORT_TYPE
+oRed[4] <= mCCD_R[4].DB_MAX_OUTPUT_PORT_TYPE
+oRed[5] <= mCCD_R[5].DB_MAX_OUTPUT_PORT_TYPE
+oRed[6] <= mCCD_R[6].DB_MAX_OUTPUT_PORT_TYPE
+oRed[7] <= mCCD_R[7].DB_MAX_OUTPUT_PORT_TYPE
+oRed[8] <= mCCD_R[8].DB_MAX_OUTPUT_PORT_TYPE
+oRed[9] <= mCCD_R[9].DB_MAX_OUTPUT_PORT_TYPE
+oRed[10] <= mCCD_R[10].DB_MAX_OUTPUT_PORT_TYPE
+oRed[11] <= mCCD_R[11].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[0] <= mCCD_G[1].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[1] <= mCCD_G[2].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[2] <= mCCD_G[3].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[3] <= mCCD_G[4].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[4] <= mCCD_G[5].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[5] <= mCCD_G[6].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[6] <= mCCD_G[7].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[7] <= mCCD_G[8].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[8] <= mCCD_G[9].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[9] <= mCCD_G[10].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[10] <= mCCD_G[11].DB_MAX_OUTPUT_PORT_TYPE
+oGreen[11] <= mCCD_G[12].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[0] <= mCCD_B[0].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[1] <= mCCD_B[1].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[2] <= mCCD_B[2].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[3] <= mCCD_B[3].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[4] <= mCCD_B[4].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[5] <= mCCD_B[5].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[6] <= mCCD_B[6].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[7] <= mCCD_B[7].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[8] <= mCCD_B[8].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[9] <= mCCD_B[9].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[10] <= mCCD_B[10].DB_MAX_OUTPUT_PORT_TYPE
+oBlue[11] <= mCCD_B[11].DB_MAX_OUTPUT_PORT_TYPE
+oDVAL <= mDVAL.DB_MAX_OUTPUT_PORT_TYPE
+iX_Cont[0] => mDVAL.IN0
+iX_Cont[0] => Equal0.IN1
+iX_Cont[0] => Equal1.IN1
+iX_Cont[0] => Equal2.IN1
+iX_Cont[0] => Equal3.IN0
+iX_Cont[1] => ~NO_FANOUT~
+iX_Cont[2] => ~NO_FANOUT~
+iX_Cont[3] => ~NO_FANOUT~
+iX_Cont[4] => ~NO_FANOUT~
+iX_Cont[5] => ~NO_FANOUT~
+iX_Cont[6] => ~NO_FANOUT~
+iX_Cont[7] => ~NO_FANOUT~
+iX_Cont[8] => ~NO_FANOUT~
+iX_Cont[9] => ~NO_FANOUT~
+iX_Cont[10] => ~NO_FANOUT~
+iY_Cont[0] => mDVAL.IN1
+iY_Cont[0] => Equal0.IN0
+iY_Cont[0] => Equal1.IN0
+iY_Cont[0] => Equal2.IN0
+iY_Cont[0] => Equal3.IN1
+iY_Cont[1] => ~NO_FANOUT~
+iY_Cont[2] => ~NO_FANOUT~
+iY_Cont[3] => ~NO_FANOUT~
+iY_Cont[4] => ~NO_FANOUT~
+iY_Cont[5] => ~NO_FANOUT~
+iY_Cont[6] => ~NO_FANOUT~
+iY_Cont[7] => ~NO_FANOUT~
+iY_Cont[8] => ~NO_FANOUT~
+iY_Cont[9] => ~NO_FANOUT~
+iY_Cont[10] => ~NO_FANOUT~
+iDATA[0] => iDATA[0].IN1
+iDATA[1] => iDATA[1].IN1
+iDATA[2] => iDATA[2].IN1
+iDATA[3] => iDATA[3].IN1
+iDATA[4] => iDATA[4].IN1
+iDATA[5] => iDATA[5].IN1
+iDATA[6] => iDATA[6].IN1
+iDATA[7] => iDATA[7].IN1
+iDATA[8] => iDATA[8].IN1
+iDATA[9] => iDATA[9].IN1
+iDATA[10] => iDATA[10].IN1
+iDATA[11] => iDATA[11].IN1
+iDVAL => iDVAL.IN1
+iCLK => iCLK.IN1
+iRST => mDVAL.ACLR
+iRST => mDATAd_1[0].ACLR
+iRST => mDATAd_1[1].ACLR
+iRST => mDATAd_1[2].ACLR
+iRST => mDATAd_1[3].ACLR
+iRST => mDATAd_1[4].ACLR
+iRST => mDATAd_1[5].ACLR
+iRST => mDATAd_1[6].ACLR
+iRST => mDATAd_1[7].ACLR
+iRST => mDATAd_1[8].ACLR
+iRST => mDATAd_1[9].ACLR
+iRST => mDATAd_1[10].ACLR
+iRST => mDATAd_1[11].ACLR
+iRST => mDATAd_0[0].ACLR
+iRST => mDATAd_0[1].ACLR
+iRST => mDATAd_0[2].ACLR
+iRST => mDATAd_0[3].ACLR
+iRST => mDATAd_0[4].ACLR
+iRST => mDATAd_0[5].ACLR
+iRST => mDATAd_0[6].ACLR
+iRST => mDATAd_0[7].ACLR
+iRST => mDATAd_0[8].ACLR
+iRST => mDATAd_0[9].ACLR
+iRST => mDATAd_0[10].ACLR
+iRST => mDATAd_0[11].ACLR
+iRST => mCCD_B[0].ACLR
+iRST => mCCD_B[1].ACLR
+iRST => mCCD_B[2].ACLR
+iRST => mCCD_B[3].ACLR
+iRST => mCCD_B[4].ACLR
+iRST => mCCD_B[5].ACLR
+iRST => mCCD_B[6].ACLR
+iRST => mCCD_B[7].ACLR
+iRST => mCCD_B[8].ACLR
+iRST => mCCD_B[9].ACLR
+iRST => mCCD_B[10].ACLR
+iRST => mCCD_B[11].ACLR
+iRST => mCCD_G[1].ACLR
+iRST => mCCD_G[2].ACLR
+iRST => mCCD_G[3].ACLR
+iRST => mCCD_G[4].ACLR
+iRST => mCCD_G[5].ACLR
+iRST => mCCD_G[6].ACLR
+iRST => mCCD_G[7].ACLR
+iRST => mCCD_G[8].ACLR
+iRST => mCCD_G[9].ACLR
+iRST => mCCD_G[10].ACLR
+iRST => mCCD_G[11].ACLR
+iRST => mCCD_G[12].ACLR
+iRST => mCCD_R[0].ACLR
+iRST => mCCD_R[1].ACLR
+iRST => mCCD_R[2].ACLR
+iRST => mCCD_R[3].ACLR
+iRST => mCCD_R[4].ACLR
+iRST => mCCD_R[5].ACLR
+iRST => mCCD_R[6].ACLR
+iRST => mCCD_R[7].ACLR
+iRST => mCCD_R[8].ACLR
+iRST => mCCD_R[9].ACLR
+iRST => mCCD_R[10].ACLR
+iRST => mCCD_R[11].ACLR
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0
+clken => clken.IN1
+clock => clock.IN1
+shiftin[0] => shiftin[0].IN1
+shiftin[1] => shiftin[1].IN1
+shiftin[2] => shiftin[2].IN1
+shiftin[3] => shiftin[3].IN1
+shiftin[4] => shiftin[4].IN1
+shiftin[5] => shiftin[5].IN1
+shiftin[6] => shiftin[6].IN1
+shiftin[7] => shiftin[7].IN1
+shiftin[8] => shiftin[8].IN1
+shiftin[9] => shiftin[9].IN1
+shiftin[10] => shiftin[10].IN1
+shiftin[11] => shiftin[11].IN1
+shiftout[0] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[1] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[2] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[3] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[4] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[5] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[6] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[7] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[8] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[9] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[10] <= altshift_taps:altshift_taps_component.shiftout
+shiftout[11] <= altshift_taps:altshift_taps_component.shiftout
+taps0x[0] <= altshift_taps:altshift_taps_component.taps
+taps0x[1] <= altshift_taps:altshift_taps_component.taps
+taps0x[2] <= altshift_taps:altshift_taps_component.taps
+taps0x[3] <= altshift_taps:altshift_taps_component.taps
+taps0x[4] <= altshift_taps:altshift_taps_component.taps
+taps0x[5] <= altshift_taps:altshift_taps_component.taps
+taps0x[6] <= altshift_taps:altshift_taps_component.taps
+taps0x[7] <= altshift_taps:altshift_taps_component.taps
+taps0x[8] <= altshift_taps:altshift_taps_component.taps
+taps0x[9] <= altshift_taps:altshift_taps_component.taps
+taps0x[10] <= altshift_taps:altshift_taps_component.taps
+taps0x[11] <= altshift_taps:altshift_taps_component.taps
+taps1x[0] <= altshift_taps:altshift_taps_component.taps
+taps1x[1] <= altshift_taps:altshift_taps_component.taps
+taps1x[2] <= altshift_taps:altshift_taps_component.taps
+taps1x[3] <= altshift_taps:altshift_taps_component.taps
+taps1x[4] <= altshift_taps:altshift_taps_component.taps
+taps1x[5] <= altshift_taps:altshift_taps_component.taps
+taps1x[6] <= altshift_taps:altshift_taps_component.taps
+taps1x[7] <= altshift_taps:altshift_taps_component.taps
+taps1x[8] <= altshift_taps:altshift_taps_component.taps
+taps1x[9] <= altshift_taps:altshift_taps_component.taps
+taps1x[10] <= altshift_taps:altshift_taps_component.taps
+taps1x[11] <= altshift_taps:altshift_taps_component.taps
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+shiftin[0] => shift_taps_rnn:auto_generated.shiftin[0]
+shiftin[1] => shift_taps_rnn:auto_generated.shiftin[1]
+shiftin[2] => shift_taps_rnn:auto_generated.shiftin[2]
+shiftin[3] => shift_taps_rnn:auto_generated.shiftin[3]
+shiftin[4] => shift_taps_rnn:auto_generated.shiftin[4]
+shiftin[5] => shift_taps_rnn:auto_generated.shiftin[5]
+shiftin[6] => shift_taps_rnn:auto_generated.shiftin[6]
+shiftin[7] => shift_taps_rnn:auto_generated.shiftin[7]
+shiftin[8] => shift_taps_rnn:auto_generated.shiftin[8]
+shiftin[9] => shift_taps_rnn:auto_generated.shiftin[9]
+shiftin[10] => shift_taps_rnn:auto_generated.shiftin[10]
+shiftin[11] => shift_taps_rnn:auto_generated.shiftin[11]
+clock => shift_taps_rnn:auto_generated.clock
+clken => shift_taps_rnn:auto_generated.clken
+shiftout[0] <= shift_taps_rnn:auto_generated.shiftout[0]
+shiftout[1] <= shift_taps_rnn:auto_generated.shiftout[1]
+shiftout[2] <= shift_taps_rnn:auto_generated.shiftout[2]
+shiftout[3] <= shift_taps_rnn:auto_generated.shiftout[3]
+shiftout[4] <= shift_taps_rnn:auto_generated.shiftout[4]
+shiftout[5] <= shift_taps_rnn:auto_generated.shiftout[5]
+shiftout[6] <= shift_taps_rnn:auto_generated.shiftout[6]
+shiftout[7] <= shift_taps_rnn:auto_generated.shiftout[7]
+shiftout[8] <= shift_taps_rnn:auto_generated.shiftout[8]
+shiftout[9] <= shift_taps_rnn:auto_generated.shiftout[9]
+shiftout[10] <= shift_taps_rnn:auto_generated.shiftout[10]
+shiftout[11] <= shift_taps_rnn:auto_generated.shiftout[11]
+taps[0] <= shift_taps_rnn:auto_generated.taps[0]
+taps[1] <= shift_taps_rnn:auto_generated.taps[1]
+taps[2] <= shift_taps_rnn:auto_generated.taps[2]
+taps[3] <= shift_taps_rnn:auto_generated.taps[3]
+taps[4] <= shift_taps_rnn:auto_generated.taps[4]
+taps[5] <= shift_taps_rnn:auto_generated.taps[5]
+taps[6] <= shift_taps_rnn:auto_generated.taps[6]
+taps[7] <= shift_taps_rnn:auto_generated.taps[7]
+taps[8] <= shift_taps_rnn:auto_generated.taps[8]
+taps[9] <= shift_taps_rnn:auto_generated.taps[9]
+taps[10] <= shift_taps_rnn:auto_generated.taps[10]
+taps[11] <= shift_taps_rnn:auto_generated.taps[11]
+taps[12] <= shift_taps_rnn:auto_generated.taps[12]
+taps[13] <= shift_taps_rnn:auto_generated.taps[13]
+taps[14] <= shift_taps_rnn:auto_generated.taps[14]
+taps[15] <= shift_taps_rnn:auto_generated.taps[15]
+taps[16] <= shift_taps_rnn:auto_generated.taps[16]
+taps[17] <= shift_taps_rnn:auto_generated.taps[17]
+taps[18] <= shift_taps_rnn:auto_generated.taps[18]
+taps[19] <= shift_taps_rnn:auto_generated.taps[19]
+taps[20] <= shift_taps_rnn:auto_generated.taps[20]
+taps[21] <= shift_taps_rnn:auto_generated.taps[21]
+taps[22] <= shift_taps_rnn:auto_generated.taps[22]
+taps[23] <= shift_taps_rnn:auto_generated.taps[23]
+aclr => ~NO_FANOUT~
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated
+clken => altsyncram_lp81:altsyncram2.clocken0
+clken => cntr_cuf:cntr1.clk_en
+clock => altsyncram_lp81:altsyncram2.clock0
+clock => cntr_cuf:cntr1.clock
+shiftin[0] => altsyncram_lp81:altsyncram2.data_a[0]
+shiftin[1] => altsyncram_lp81:altsyncram2.data_a[1]
+shiftin[2] => altsyncram_lp81:altsyncram2.data_a[2]
+shiftin[3] => altsyncram_lp81:altsyncram2.data_a[3]
+shiftin[4] => altsyncram_lp81:altsyncram2.data_a[4]
+shiftin[5] => altsyncram_lp81:altsyncram2.data_a[5]
+shiftin[6] => altsyncram_lp81:altsyncram2.data_a[6]
+shiftin[7] => altsyncram_lp81:altsyncram2.data_a[7]
+shiftin[8] => altsyncram_lp81:altsyncram2.data_a[8]
+shiftin[9] => altsyncram_lp81:altsyncram2.data_a[9]
+shiftin[10] => altsyncram_lp81:altsyncram2.data_a[10]
+shiftin[11] => altsyncram_lp81:altsyncram2.data_a[11]
+shiftout[0] <= altsyncram_lp81:altsyncram2.q_b[12]
+shiftout[1] <= altsyncram_lp81:altsyncram2.q_b[13]
+shiftout[2] <= altsyncram_lp81:altsyncram2.q_b[14]
+shiftout[3] <= altsyncram_lp81:altsyncram2.q_b[15]
+shiftout[4] <= altsyncram_lp81:altsyncram2.q_b[16]
+shiftout[5] <= altsyncram_lp81:altsyncram2.q_b[17]
+shiftout[6] <= altsyncram_lp81:altsyncram2.q_b[18]
+shiftout[7] <= altsyncram_lp81:altsyncram2.q_b[19]
+shiftout[8] <= altsyncram_lp81:altsyncram2.q_b[20]
+shiftout[9] <= altsyncram_lp81:altsyncram2.q_b[21]
+shiftout[10] <= altsyncram_lp81:altsyncram2.q_b[22]
+shiftout[11] <= altsyncram_lp81:altsyncram2.q_b[23]
+taps[0] <= altsyncram_lp81:altsyncram2.q_b[0]
+taps[1] <= altsyncram_lp81:altsyncram2.q_b[1]
+taps[2] <= altsyncram_lp81:altsyncram2.q_b[2]
+taps[3] <= altsyncram_lp81:altsyncram2.q_b[3]
+taps[4] <= altsyncram_lp81:altsyncram2.q_b[4]
+taps[5] <= altsyncram_lp81:altsyncram2.q_b[5]
+taps[6] <= altsyncram_lp81:altsyncram2.q_b[6]
+taps[7] <= altsyncram_lp81:altsyncram2.q_b[7]
+taps[8] <= altsyncram_lp81:altsyncram2.q_b[8]
+taps[9] <= altsyncram_lp81:altsyncram2.q_b[9]
+taps[10] <= altsyncram_lp81:altsyncram2.q_b[10]
+taps[11] <= altsyncram_lp81:altsyncram2.q_b[11]
+taps[12] <= altsyncram_lp81:altsyncram2.q_b[12]
+taps[13] <= altsyncram_lp81:altsyncram2.q_b[13]
+taps[14] <= altsyncram_lp81:altsyncram2.q_b[14]
+taps[15] <= altsyncram_lp81:altsyncram2.q_b[15]
+taps[16] <= altsyncram_lp81:altsyncram2.q_b[16]
+taps[17] <= altsyncram_lp81:altsyncram2.q_b[17]
+taps[18] <= altsyncram_lp81:altsyncram2.q_b[18]
+taps[19] <= altsyncram_lp81:altsyncram2.q_b[19]
+taps[20] <= altsyncram_lp81:altsyncram2.q_b[20]
+taps[21] <= altsyncram_lp81:altsyncram2.q_b[21]
+taps[22] <= altsyncram_lp81:altsyncram2.q_b[22]
+taps[23] <= altsyncram_lp81:altsyncram2.q_b[23]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+address_a[0] => ram_block3a0.PORTAADDR
+address_a[0] => ram_block3a1.PORTAADDR
+address_a[0] => ram_block3a2.PORTAADDR
+address_a[0] => ram_block3a3.PORTAADDR
+address_a[0] => ram_block3a4.PORTAADDR
+address_a[0] => ram_block3a5.PORTAADDR
+address_a[0] => ram_block3a6.PORTAADDR
+address_a[0] => ram_block3a7.PORTAADDR
+address_a[0] => ram_block3a8.PORTAADDR
+address_a[0] => ram_block3a9.PORTAADDR
+address_a[0] => ram_block3a10.PORTAADDR
+address_a[0] => ram_block3a11.PORTAADDR
+address_a[0] => ram_block3a12.PORTAADDR
+address_a[0] => ram_block3a13.PORTAADDR
+address_a[0] => ram_block3a14.PORTAADDR
+address_a[0] => ram_block3a15.PORTAADDR
+address_a[0] => ram_block3a16.PORTAADDR
+address_a[0] => ram_block3a17.PORTAADDR
+address_a[0] => ram_block3a18.PORTAADDR
+address_a[0] => ram_block3a19.PORTAADDR
+address_a[0] => ram_block3a20.PORTAADDR
+address_a[0] => ram_block3a21.PORTAADDR
+address_a[0] => ram_block3a22.PORTAADDR
+address_a[0] => ram_block3a23.PORTAADDR
+address_a[1] => ram_block3a0.PORTAADDR1
+address_a[1] => ram_block3a1.PORTAADDR1
+address_a[1] => ram_block3a2.PORTAADDR1
+address_a[1] => ram_block3a3.PORTAADDR1
+address_a[1] => ram_block3a4.PORTAADDR1
+address_a[1] => ram_block3a5.PORTAADDR1
+address_a[1] => ram_block3a6.PORTAADDR1
+address_a[1] => ram_block3a7.PORTAADDR1
+address_a[1] => ram_block3a8.PORTAADDR1
+address_a[1] => ram_block3a9.PORTAADDR1
+address_a[1] => ram_block3a10.PORTAADDR1
+address_a[1] => ram_block3a11.PORTAADDR1
+address_a[1] => ram_block3a12.PORTAADDR1
+address_a[1] => ram_block3a13.PORTAADDR1
+address_a[1] => ram_block3a14.PORTAADDR1
+address_a[1] => ram_block3a15.PORTAADDR1
+address_a[1] => ram_block3a16.PORTAADDR1
+address_a[1] => ram_block3a17.PORTAADDR1
+address_a[1] => ram_block3a18.PORTAADDR1
+address_a[1] => ram_block3a19.PORTAADDR1
+address_a[1] => ram_block3a20.PORTAADDR1
+address_a[1] => ram_block3a21.PORTAADDR1
+address_a[1] => ram_block3a22.PORTAADDR1
+address_a[1] => ram_block3a23.PORTAADDR1
+address_a[2] => ram_block3a0.PORTAADDR2
+address_a[2] => ram_block3a1.PORTAADDR2
+address_a[2] => ram_block3a2.PORTAADDR2
+address_a[2] => ram_block3a3.PORTAADDR2
+address_a[2] => ram_block3a4.PORTAADDR2
+address_a[2] => ram_block3a5.PORTAADDR2
+address_a[2] => ram_block3a6.PORTAADDR2
+address_a[2] => ram_block3a7.PORTAADDR2
+address_a[2] => ram_block3a8.PORTAADDR2
+address_a[2] => ram_block3a9.PORTAADDR2
+address_a[2] => ram_block3a10.PORTAADDR2
+address_a[2] => ram_block3a11.PORTAADDR2
+address_a[2] => ram_block3a12.PORTAADDR2
+address_a[2] => ram_block3a13.PORTAADDR2
+address_a[2] => ram_block3a14.PORTAADDR2
+address_a[2] => ram_block3a15.PORTAADDR2
+address_a[2] => ram_block3a16.PORTAADDR2
+address_a[2] => ram_block3a17.PORTAADDR2
+address_a[2] => ram_block3a18.PORTAADDR2
+address_a[2] => ram_block3a19.PORTAADDR2
+address_a[2] => ram_block3a20.PORTAADDR2
+address_a[2] => ram_block3a21.PORTAADDR2
+address_a[2] => ram_block3a22.PORTAADDR2
+address_a[2] => ram_block3a23.PORTAADDR2
+address_a[3] => ram_block3a0.PORTAADDR3
+address_a[3] => ram_block3a1.PORTAADDR3
+address_a[3] => ram_block3a2.PORTAADDR3
+address_a[3] => ram_block3a3.PORTAADDR3
+address_a[3] => ram_block3a4.PORTAADDR3
+address_a[3] => ram_block3a5.PORTAADDR3
+address_a[3] => ram_block3a6.PORTAADDR3
+address_a[3] => ram_block3a7.PORTAADDR3
+address_a[3] => ram_block3a8.PORTAADDR3
+address_a[3] => ram_block3a9.PORTAADDR3
+address_a[3] => ram_block3a10.PORTAADDR3
+address_a[3] => ram_block3a11.PORTAADDR3
+address_a[3] => ram_block3a12.PORTAADDR3
+address_a[3] => ram_block3a13.PORTAADDR3
+address_a[3] => ram_block3a14.PORTAADDR3
+address_a[3] => ram_block3a15.PORTAADDR3
+address_a[3] => ram_block3a16.PORTAADDR3
+address_a[3] => ram_block3a17.PORTAADDR3
+address_a[3] => ram_block3a18.PORTAADDR3
+address_a[3] => ram_block3a19.PORTAADDR3
+address_a[3] => ram_block3a20.PORTAADDR3
+address_a[3] => ram_block3a21.PORTAADDR3
+address_a[3] => ram_block3a22.PORTAADDR3
+address_a[3] => ram_block3a23.PORTAADDR3
+address_a[4] => ram_block3a0.PORTAADDR4
+address_a[4] => ram_block3a1.PORTAADDR4
+address_a[4] => ram_block3a2.PORTAADDR4
+address_a[4] => ram_block3a3.PORTAADDR4
+address_a[4] => ram_block3a4.PORTAADDR4
+address_a[4] => ram_block3a5.PORTAADDR4
+address_a[4] => ram_block3a6.PORTAADDR4
+address_a[4] => ram_block3a7.PORTAADDR4
+address_a[4] => ram_block3a8.PORTAADDR4
+address_a[4] => ram_block3a9.PORTAADDR4
+address_a[4] => ram_block3a10.PORTAADDR4
+address_a[4] => ram_block3a11.PORTAADDR4
+address_a[4] => ram_block3a12.PORTAADDR4
+address_a[4] => ram_block3a13.PORTAADDR4
+address_a[4] => ram_block3a14.PORTAADDR4
+address_a[4] => ram_block3a15.PORTAADDR4
+address_a[4] => ram_block3a16.PORTAADDR4
+address_a[4] => ram_block3a17.PORTAADDR4
+address_a[4] => ram_block3a18.PORTAADDR4
+address_a[4] => ram_block3a19.PORTAADDR4
+address_a[4] => ram_block3a20.PORTAADDR4
+address_a[4] => ram_block3a21.PORTAADDR4
+address_a[4] => ram_block3a22.PORTAADDR4
+address_a[4] => ram_block3a23.PORTAADDR4
+address_a[5] => ram_block3a0.PORTAADDR5
+address_a[5] => ram_block3a1.PORTAADDR5
+address_a[5] => ram_block3a2.PORTAADDR5
+address_a[5] => ram_block3a3.PORTAADDR5
+address_a[5] => ram_block3a4.PORTAADDR5
+address_a[5] => ram_block3a5.PORTAADDR5
+address_a[5] => ram_block3a6.PORTAADDR5
+address_a[5] => ram_block3a7.PORTAADDR5
+address_a[5] => ram_block3a8.PORTAADDR5
+address_a[5] => ram_block3a9.PORTAADDR5
+address_a[5] => ram_block3a10.PORTAADDR5
+address_a[5] => ram_block3a11.PORTAADDR5
+address_a[5] => ram_block3a12.PORTAADDR5
+address_a[5] => ram_block3a13.PORTAADDR5
+address_a[5] => ram_block3a14.PORTAADDR5
+address_a[5] => ram_block3a15.PORTAADDR5
+address_a[5] => ram_block3a16.PORTAADDR5
+address_a[5] => ram_block3a17.PORTAADDR5
+address_a[5] => ram_block3a18.PORTAADDR5
+address_a[5] => ram_block3a19.PORTAADDR5
+address_a[5] => ram_block3a20.PORTAADDR5
+address_a[5] => ram_block3a21.PORTAADDR5
+address_a[5] => ram_block3a22.PORTAADDR5
+address_a[5] => ram_block3a23.PORTAADDR5
+address_a[6] => ram_block3a0.PORTAADDR6
+address_a[6] => ram_block3a1.PORTAADDR6
+address_a[6] => ram_block3a2.PORTAADDR6
+address_a[6] => ram_block3a3.PORTAADDR6
+address_a[6] => ram_block3a4.PORTAADDR6
+address_a[6] => ram_block3a5.PORTAADDR6
+address_a[6] => ram_block3a6.PORTAADDR6
+address_a[6] => ram_block3a7.PORTAADDR6
+address_a[6] => ram_block3a8.PORTAADDR6
+address_a[6] => ram_block3a9.PORTAADDR6
+address_a[6] => ram_block3a10.PORTAADDR6
+address_a[6] => ram_block3a11.PORTAADDR6
+address_a[6] => ram_block3a12.PORTAADDR6
+address_a[6] => ram_block3a13.PORTAADDR6
+address_a[6] => ram_block3a14.PORTAADDR6
+address_a[6] => ram_block3a15.PORTAADDR6
+address_a[6] => ram_block3a16.PORTAADDR6
+address_a[6] => ram_block3a17.PORTAADDR6
+address_a[6] => ram_block3a18.PORTAADDR6
+address_a[6] => ram_block3a19.PORTAADDR6
+address_a[6] => ram_block3a20.PORTAADDR6
+address_a[6] => ram_block3a21.PORTAADDR6
+address_a[6] => ram_block3a22.PORTAADDR6
+address_a[6] => ram_block3a23.PORTAADDR6
+address_a[7] => ram_block3a0.PORTAADDR7
+address_a[7] => ram_block3a1.PORTAADDR7
+address_a[7] => ram_block3a2.PORTAADDR7
+address_a[7] => ram_block3a3.PORTAADDR7
+address_a[7] => ram_block3a4.PORTAADDR7
+address_a[7] => ram_block3a5.PORTAADDR7
+address_a[7] => ram_block3a6.PORTAADDR7
+address_a[7] => ram_block3a7.PORTAADDR7
+address_a[7] => ram_block3a8.PORTAADDR7
+address_a[7] => ram_block3a9.PORTAADDR7
+address_a[7] => ram_block3a10.PORTAADDR7
+address_a[7] => ram_block3a11.PORTAADDR7
+address_a[7] => ram_block3a12.PORTAADDR7
+address_a[7] => ram_block3a13.PORTAADDR7
+address_a[7] => ram_block3a14.PORTAADDR7
+address_a[7] => ram_block3a15.PORTAADDR7
+address_a[7] => ram_block3a16.PORTAADDR7
+address_a[7] => ram_block3a17.PORTAADDR7
+address_a[7] => ram_block3a18.PORTAADDR7
+address_a[7] => ram_block3a19.PORTAADDR7
+address_a[7] => ram_block3a20.PORTAADDR7
+address_a[7] => ram_block3a21.PORTAADDR7
+address_a[7] => ram_block3a22.PORTAADDR7
+address_a[7] => ram_block3a23.PORTAADDR7
+address_a[8] => ram_block3a0.PORTAADDR8
+address_a[8] => ram_block3a1.PORTAADDR8
+address_a[8] => ram_block3a2.PORTAADDR8
+address_a[8] => ram_block3a3.PORTAADDR8
+address_a[8] => ram_block3a4.PORTAADDR8
+address_a[8] => ram_block3a5.PORTAADDR8
+address_a[8] => ram_block3a6.PORTAADDR8
+address_a[8] => ram_block3a7.PORTAADDR8
+address_a[8] => ram_block3a8.PORTAADDR8
+address_a[8] => ram_block3a9.PORTAADDR8
+address_a[8] => ram_block3a10.PORTAADDR8
+address_a[8] => ram_block3a11.PORTAADDR8
+address_a[8] => ram_block3a12.PORTAADDR8
+address_a[8] => ram_block3a13.PORTAADDR8
+address_a[8] => ram_block3a14.PORTAADDR8
+address_a[8] => ram_block3a15.PORTAADDR8
+address_a[8] => ram_block3a16.PORTAADDR8
+address_a[8] => ram_block3a17.PORTAADDR8
+address_a[8] => ram_block3a18.PORTAADDR8
+address_a[8] => ram_block3a19.PORTAADDR8
+address_a[8] => ram_block3a20.PORTAADDR8
+address_a[8] => ram_block3a21.PORTAADDR8
+address_a[8] => ram_block3a22.PORTAADDR8
+address_a[8] => ram_block3a23.PORTAADDR8
+address_a[9] => ram_block3a0.PORTAADDR9
+address_a[9] => ram_block3a1.PORTAADDR9
+address_a[9] => ram_block3a2.PORTAADDR9
+address_a[9] => ram_block3a3.PORTAADDR9
+address_a[9] => ram_block3a4.PORTAADDR9
+address_a[9] => ram_block3a5.PORTAADDR9
+address_a[9] => ram_block3a6.PORTAADDR9
+address_a[9] => ram_block3a7.PORTAADDR9
+address_a[9] => ram_block3a8.PORTAADDR9
+address_a[9] => ram_block3a9.PORTAADDR9
+address_a[9] => ram_block3a10.PORTAADDR9
+address_a[9] => ram_block3a11.PORTAADDR9
+address_a[9] => ram_block3a12.PORTAADDR9
+address_a[9] => ram_block3a13.PORTAADDR9
+address_a[9] => ram_block3a14.PORTAADDR9
+address_a[9] => ram_block3a15.PORTAADDR9
+address_a[9] => ram_block3a16.PORTAADDR9
+address_a[9] => ram_block3a17.PORTAADDR9
+address_a[9] => ram_block3a18.PORTAADDR9
+address_a[9] => ram_block3a19.PORTAADDR9
+address_a[9] => ram_block3a20.PORTAADDR9
+address_a[9] => ram_block3a21.PORTAADDR9
+address_a[9] => ram_block3a22.PORTAADDR9
+address_a[9] => ram_block3a23.PORTAADDR9
+address_a[10] => ram_block3a0.PORTAADDR10
+address_a[10] => ram_block3a1.PORTAADDR10
+address_a[10] => ram_block3a2.PORTAADDR10
+address_a[10] => ram_block3a3.PORTAADDR10
+address_a[10] => ram_block3a4.PORTAADDR10
+address_a[10] => ram_block3a5.PORTAADDR10
+address_a[10] => ram_block3a6.PORTAADDR10
+address_a[10] => ram_block3a7.PORTAADDR10
+address_a[10] => ram_block3a8.PORTAADDR10
+address_a[10] => ram_block3a9.PORTAADDR10
+address_a[10] => ram_block3a10.PORTAADDR10
+address_a[10] => ram_block3a11.PORTAADDR10
+address_a[10] => ram_block3a12.PORTAADDR10
+address_a[10] => ram_block3a13.PORTAADDR10
+address_a[10] => ram_block3a14.PORTAADDR10
+address_a[10] => ram_block3a15.PORTAADDR10
+address_a[10] => ram_block3a16.PORTAADDR10
+address_a[10] => ram_block3a17.PORTAADDR10
+address_a[10] => ram_block3a18.PORTAADDR10
+address_a[10] => ram_block3a19.PORTAADDR10
+address_a[10] => ram_block3a20.PORTAADDR10
+address_a[10] => ram_block3a21.PORTAADDR10
+address_a[10] => ram_block3a22.PORTAADDR10
+address_a[10] => ram_block3a23.PORTAADDR10
+address_b[0] => ram_block3a0.PORTBADDR
+address_b[0] => ram_block3a1.PORTBADDR
+address_b[0] => ram_block3a2.PORTBADDR
+address_b[0] => ram_block3a3.PORTBADDR
+address_b[0] => ram_block3a4.PORTBADDR
+address_b[0] => ram_block3a5.PORTBADDR
+address_b[0] => ram_block3a6.PORTBADDR
+address_b[0] => ram_block3a7.PORTBADDR
+address_b[0] => ram_block3a8.PORTBADDR
+address_b[0] => ram_block3a9.PORTBADDR
+address_b[0] => ram_block3a10.PORTBADDR
+address_b[0] => ram_block3a11.PORTBADDR
+address_b[0] => ram_block3a12.PORTBADDR
+address_b[0] => ram_block3a13.PORTBADDR
+address_b[0] => ram_block3a14.PORTBADDR
+address_b[0] => ram_block3a15.PORTBADDR
+address_b[0] => ram_block3a16.PORTBADDR
+address_b[0] => ram_block3a17.PORTBADDR
+address_b[0] => ram_block3a18.PORTBADDR
+address_b[0] => ram_block3a19.PORTBADDR
+address_b[0] => ram_block3a20.PORTBADDR
+address_b[0] => ram_block3a21.PORTBADDR
+address_b[0] => ram_block3a22.PORTBADDR
+address_b[0] => ram_block3a23.PORTBADDR
+address_b[1] => ram_block3a0.PORTBADDR1
+address_b[1] => ram_block3a1.PORTBADDR1
+address_b[1] => ram_block3a2.PORTBADDR1
+address_b[1] => ram_block3a3.PORTBADDR1
+address_b[1] => ram_block3a4.PORTBADDR1
+address_b[1] => ram_block3a5.PORTBADDR1
+address_b[1] => ram_block3a6.PORTBADDR1
+address_b[1] => ram_block3a7.PORTBADDR1
+address_b[1] => ram_block3a8.PORTBADDR1
+address_b[1] => ram_block3a9.PORTBADDR1
+address_b[1] => ram_block3a10.PORTBADDR1
+address_b[1] => ram_block3a11.PORTBADDR1
+address_b[1] => ram_block3a12.PORTBADDR1
+address_b[1] => ram_block3a13.PORTBADDR1
+address_b[1] => ram_block3a14.PORTBADDR1
+address_b[1] => ram_block3a15.PORTBADDR1
+address_b[1] => ram_block3a16.PORTBADDR1
+address_b[1] => ram_block3a17.PORTBADDR1
+address_b[1] => ram_block3a18.PORTBADDR1
+address_b[1] => ram_block3a19.PORTBADDR1
+address_b[1] => ram_block3a20.PORTBADDR1
+address_b[1] => ram_block3a21.PORTBADDR1
+address_b[1] => ram_block3a22.PORTBADDR1
+address_b[1] => ram_block3a23.PORTBADDR1
+address_b[2] => ram_block3a0.PORTBADDR2
+address_b[2] => ram_block3a1.PORTBADDR2
+address_b[2] => ram_block3a2.PORTBADDR2
+address_b[2] => ram_block3a3.PORTBADDR2
+address_b[2] => ram_block3a4.PORTBADDR2
+address_b[2] => ram_block3a5.PORTBADDR2
+address_b[2] => ram_block3a6.PORTBADDR2
+address_b[2] => ram_block3a7.PORTBADDR2
+address_b[2] => ram_block3a8.PORTBADDR2
+address_b[2] => ram_block3a9.PORTBADDR2
+address_b[2] => ram_block3a10.PORTBADDR2
+address_b[2] => ram_block3a11.PORTBADDR2
+address_b[2] => ram_block3a12.PORTBADDR2
+address_b[2] => ram_block3a13.PORTBADDR2
+address_b[2] => ram_block3a14.PORTBADDR2
+address_b[2] => ram_block3a15.PORTBADDR2
+address_b[2] => ram_block3a16.PORTBADDR2
+address_b[2] => ram_block3a17.PORTBADDR2
+address_b[2] => ram_block3a18.PORTBADDR2
+address_b[2] => ram_block3a19.PORTBADDR2
+address_b[2] => ram_block3a20.PORTBADDR2
+address_b[2] => ram_block3a21.PORTBADDR2
+address_b[2] => ram_block3a22.PORTBADDR2
+address_b[2] => ram_block3a23.PORTBADDR2
+address_b[3] => ram_block3a0.PORTBADDR3
+address_b[3] => ram_block3a1.PORTBADDR3
+address_b[3] => ram_block3a2.PORTBADDR3
+address_b[3] => ram_block3a3.PORTBADDR3
+address_b[3] => ram_block3a4.PORTBADDR3
+address_b[3] => ram_block3a5.PORTBADDR3
+address_b[3] => ram_block3a6.PORTBADDR3
+address_b[3] => ram_block3a7.PORTBADDR3
+address_b[3] => ram_block3a8.PORTBADDR3
+address_b[3] => ram_block3a9.PORTBADDR3
+address_b[3] => ram_block3a10.PORTBADDR3
+address_b[3] => ram_block3a11.PORTBADDR3
+address_b[3] => ram_block3a12.PORTBADDR3
+address_b[3] => ram_block3a13.PORTBADDR3
+address_b[3] => ram_block3a14.PORTBADDR3
+address_b[3] => ram_block3a15.PORTBADDR3
+address_b[3] => ram_block3a16.PORTBADDR3
+address_b[3] => ram_block3a17.PORTBADDR3
+address_b[3] => ram_block3a18.PORTBADDR3
+address_b[3] => ram_block3a19.PORTBADDR3
+address_b[3] => ram_block3a20.PORTBADDR3
+address_b[3] => ram_block3a21.PORTBADDR3
+address_b[3] => ram_block3a22.PORTBADDR3
+address_b[3] => ram_block3a23.PORTBADDR3
+address_b[4] => ram_block3a0.PORTBADDR4
+address_b[4] => ram_block3a1.PORTBADDR4
+address_b[4] => ram_block3a2.PORTBADDR4
+address_b[4] => ram_block3a3.PORTBADDR4
+address_b[4] => ram_block3a4.PORTBADDR4
+address_b[4] => ram_block3a5.PORTBADDR4
+address_b[4] => ram_block3a6.PORTBADDR4
+address_b[4] => ram_block3a7.PORTBADDR4
+address_b[4] => ram_block3a8.PORTBADDR4
+address_b[4] => ram_block3a9.PORTBADDR4
+address_b[4] => ram_block3a10.PORTBADDR4
+address_b[4] => ram_block3a11.PORTBADDR4
+address_b[4] => ram_block3a12.PORTBADDR4
+address_b[4] => ram_block3a13.PORTBADDR4
+address_b[4] => ram_block3a14.PORTBADDR4
+address_b[4] => ram_block3a15.PORTBADDR4
+address_b[4] => ram_block3a16.PORTBADDR4
+address_b[4] => ram_block3a17.PORTBADDR4
+address_b[4] => ram_block3a18.PORTBADDR4
+address_b[4] => ram_block3a19.PORTBADDR4
+address_b[4] => ram_block3a20.PORTBADDR4
+address_b[4] => ram_block3a21.PORTBADDR4
+address_b[4] => ram_block3a22.PORTBADDR4
+address_b[4] => ram_block3a23.PORTBADDR4
+address_b[5] => ram_block3a0.PORTBADDR5
+address_b[5] => ram_block3a1.PORTBADDR5
+address_b[5] => ram_block3a2.PORTBADDR5
+address_b[5] => ram_block3a3.PORTBADDR5
+address_b[5] => ram_block3a4.PORTBADDR5
+address_b[5] => ram_block3a5.PORTBADDR5
+address_b[5] => ram_block3a6.PORTBADDR5
+address_b[5] => ram_block3a7.PORTBADDR5
+address_b[5] => ram_block3a8.PORTBADDR5
+address_b[5] => ram_block3a9.PORTBADDR5
+address_b[5] => ram_block3a10.PORTBADDR5
+address_b[5] => ram_block3a11.PORTBADDR5
+address_b[5] => ram_block3a12.PORTBADDR5
+address_b[5] => ram_block3a13.PORTBADDR5
+address_b[5] => ram_block3a14.PORTBADDR5
+address_b[5] => ram_block3a15.PORTBADDR5
+address_b[5] => ram_block3a16.PORTBADDR5
+address_b[5] => ram_block3a17.PORTBADDR5
+address_b[5] => ram_block3a18.PORTBADDR5
+address_b[5] => ram_block3a19.PORTBADDR5
+address_b[5] => ram_block3a20.PORTBADDR5
+address_b[5] => ram_block3a21.PORTBADDR5
+address_b[5] => ram_block3a22.PORTBADDR5
+address_b[5] => ram_block3a23.PORTBADDR5
+address_b[6] => ram_block3a0.PORTBADDR6
+address_b[6] => ram_block3a1.PORTBADDR6
+address_b[6] => ram_block3a2.PORTBADDR6
+address_b[6] => ram_block3a3.PORTBADDR6
+address_b[6] => ram_block3a4.PORTBADDR6
+address_b[6] => ram_block3a5.PORTBADDR6
+address_b[6] => ram_block3a6.PORTBADDR6
+address_b[6] => ram_block3a7.PORTBADDR6
+address_b[6] => ram_block3a8.PORTBADDR6
+address_b[6] => ram_block3a9.PORTBADDR6
+address_b[6] => ram_block3a10.PORTBADDR6
+address_b[6] => ram_block3a11.PORTBADDR6
+address_b[6] => ram_block3a12.PORTBADDR6
+address_b[6] => ram_block3a13.PORTBADDR6
+address_b[6] => ram_block3a14.PORTBADDR6
+address_b[6] => ram_block3a15.PORTBADDR6
+address_b[6] => ram_block3a16.PORTBADDR6
+address_b[6] => ram_block3a17.PORTBADDR6
+address_b[6] => ram_block3a18.PORTBADDR6
+address_b[6] => ram_block3a19.PORTBADDR6
+address_b[6] => ram_block3a20.PORTBADDR6
+address_b[6] => ram_block3a21.PORTBADDR6
+address_b[6] => ram_block3a22.PORTBADDR6
+address_b[6] => ram_block3a23.PORTBADDR6
+address_b[7] => ram_block3a0.PORTBADDR7
+address_b[7] => ram_block3a1.PORTBADDR7
+address_b[7] => ram_block3a2.PORTBADDR7
+address_b[7] => ram_block3a3.PORTBADDR7
+address_b[7] => ram_block3a4.PORTBADDR7
+address_b[7] => ram_block3a5.PORTBADDR7
+address_b[7] => ram_block3a6.PORTBADDR7
+address_b[7] => ram_block3a7.PORTBADDR7
+address_b[7] => ram_block3a8.PORTBADDR7
+address_b[7] => ram_block3a9.PORTBADDR7
+address_b[7] => ram_block3a10.PORTBADDR7
+address_b[7] => ram_block3a11.PORTBADDR7
+address_b[7] => ram_block3a12.PORTBADDR7
+address_b[7] => ram_block3a13.PORTBADDR7
+address_b[7] => ram_block3a14.PORTBADDR7
+address_b[7] => ram_block3a15.PORTBADDR7
+address_b[7] => ram_block3a16.PORTBADDR7
+address_b[7] => ram_block3a17.PORTBADDR7
+address_b[7] => ram_block3a18.PORTBADDR7
+address_b[7] => ram_block3a19.PORTBADDR7
+address_b[7] => ram_block3a20.PORTBADDR7
+address_b[7] => ram_block3a21.PORTBADDR7
+address_b[7] => ram_block3a22.PORTBADDR7
+address_b[7] => ram_block3a23.PORTBADDR7
+address_b[8] => ram_block3a0.PORTBADDR8
+address_b[8] => ram_block3a1.PORTBADDR8
+address_b[8] => ram_block3a2.PORTBADDR8
+address_b[8] => ram_block3a3.PORTBADDR8
+address_b[8] => ram_block3a4.PORTBADDR8
+address_b[8] => ram_block3a5.PORTBADDR8
+address_b[8] => ram_block3a6.PORTBADDR8
+address_b[8] => ram_block3a7.PORTBADDR8
+address_b[8] => ram_block3a8.PORTBADDR8
+address_b[8] => ram_block3a9.PORTBADDR8
+address_b[8] => ram_block3a10.PORTBADDR8
+address_b[8] => ram_block3a11.PORTBADDR8
+address_b[8] => ram_block3a12.PORTBADDR8
+address_b[8] => ram_block3a13.PORTBADDR8
+address_b[8] => ram_block3a14.PORTBADDR8
+address_b[8] => ram_block3a15.PORTBADDR8
+address_b[8] => ram_block3a16.PORTBADDR8
+address_b[8] => ram_block3a17.PORTBADDR8
+address_b[8] => ram_block3a18.PORTBADDR8
+address_b[8] => ram_block3a19.PORTBADDR8
+address_b[8] => ram_block3a20.PORTBADDR8
+address_b[8] => ram_block3a21.PORTBADDR8
+address_b[8] => ram_block3a22.PORTBADDR8
+address_b[8] => ram_block3a23.PORTBADDR8
+address_b[9] => ram_block3a0.PORTBADDR9
+address_b[9] => ram_block3a1.PORTBADDR9
+address_b[9] => ram_block3a2.PORTBADDR9
+address_b[9] => ram_block3a3.PORTBADDR9
+address_b[9] => ram_block3a4.PORTBADDR9
+address_b[9] => ram_block3a5.PORTBADDR9
+address_b[9] => ram_block3a6.PORTBADDR9
+address_b[9] => ram_block3a7.PORTBADDR9
+address_b[9] => ram_block3a8.PORTBADDR9
+address_b[9] => ram_block3a9.PORTBADDR9
+address_b[9] => ram_block3a10.PORTBADDR9
+address_b[9] => ram_block3a11.PORTBADDR9
+address_b[9] => ram_block3a12.PORTBADDR9
+address_b[9] => ram_block3a13.PORTBADDR9
+address_b[9] => ram_block3a14.PORTBADDR9
+address_b[9] => ram_block3a15.PORTBADDR9
+address_b[9] => ram_block3a16.PORTBADDR9
+address_b[9] => ram_block3a17.PORTBADDR9
+address_b[9] => ram_block3a18.PORTBADDR9
+address_b[9] => ram_block3a19.PORTBADDR9
+address_b[9] => ram_block3a20.PORTBADDR9
+address_b[9] => ram_block3a21.PORTBADDR9
+address_b[9] => ram_block3a22.PORTBADDR9
+address_b[9] => ram_block3a23.PORTBADDR9
+address_b[10] => ram_block3a0.PORTBADDR10
+address_b[10] => ram_block3a1.PORTBADDR10
+address_b[10] => ram_block3a2.PORTBADDR10
+address_b[10] => ram_block3a3.PORTBADDR10
+address_b[10] => ram_block3a4.PORTBADDR10
+address_b[10] => ram_block3a5.PORTBADDR10
+address_b[10] => ram_block3a6.PORTBADDR10
+address_b[10] => ram_block3a7.PORTBADDR10
+address_b[10] => ram_block3a8.PORTBADDR10
+address_b[10] => ram_block3a9.PORTBADDR10
+address_b[10] => ram_block3a10.PORTBADDR10
+address_b[10] => ram_block3a11.PORTBADDR10
+address_b[10] => ram_block3a12.PORTBADDR10
+address_b[10] => ram_block3a13.PORTBADDR10
+address_b[10] => ram_block3a14.PORTBADDR10
+address_b[10] => ram_block3a15.PORTBADDR10
+address_b[10] => ram_block3a16.PORTBADDR10
+address_b[10] => ram_block3a17.PORTBADDR10
+address_b[10] => ram_block3a18.PORTBADDR10
+address_b[10] => ram_block3a19.PORTBADDR10
+address_b[10] => ram_block3a20.PORTBADDR10
+address_b[10] => ram_block3a21.PORTBADDR10
+address_b[10] => ram_block3a22.PORTBADDR10
+address_b[10] => ram_block3a23.PORTBADDR10
+clock0 => ram_block3a0.CLK0
+clock0 => ram_block3a1.CLK0
+clock0 => ram_block3a2.CLK0
+clock0 => ram_block3a3.CLK0
+clock0 => ram_block3a4.CLK0
+clock0 => ram_block3a5.CLK0
+clock0 => ram_block3a6.CLK0
+clock0 => ram_block3a7.CLK0
+clock0 => ram_block3a8.CLK0
+clock0 => ram_block3a9.CLK0
+clock0 => ram_block3a10.CLK0
+clock0 => ram_block3a11.CLK0
+clock0 => ram_block3a12.CLK0
+clock0 => ram_block3a13.CLK0
+clock0 => ram_block3a14.CLK0
+clock0 => ram_block3a15.CLK0
+clock0 => ram_block3a16.CLK0
+clock0 => ram_block3a17.CLK0
+clock0 => ram_block3a18.CLK0
+clock0 => ram_block3a19.CLK0
+clock0 => ram_block3a20.CLK0
+clock0 => ram_block3a21.CLK0
+clock0 => ram_block3a22.CLK0
+clock0 => ram_block3a23.CLK0
+clocken0 => ram_block3a0.ENA0
+clocken0 => ram_block3a1.ENA0
+clocken0 => ram_block3a2.ENA0
+clocken0 => ram_block3a3.ENA0
+clocken0 => ram_block3a4.ENA0
+clocken0 => ram_block3a5.ENA0
+clocken0 => ram_block3a6.ENA0
+clocken0 => ram_block3a7.ENA0
+clocken0 => ram_block3a8.ENA0
+clocken0 => ram_block3a9.ENA0
+clocken0 => ram_block3a10.ENA0
+clocken0 => ram_block3a11.ENA0
+clocken0 => ram_block3a12.ENA0
+clocken0 => ram_block3a13.ENA0
+clocken0 => ram_block3a14.ENA0
+clocken0 => ram_block3a15.ENA0
+clocken0 => ram_block3a16.ENA0
+clocken0 => ram_block3a17.ENA0
+clocken0 => ram_block3a18.ENA0
+clocken0 => ram_block3a19.ENA0
+clocken0 => ram_block3a20.ENA0
+clocken0 => ram_block3a21.ENA0
+clocken0 => ram_block3a22.ENA0
+clocken0 => ram_block3a23.ENA0
+data_a[0] => ram_block3a0.PORTADATAIN
+data_a[1] => ram_block3a1.PORTADATAIN
+data_a[2] => ram_block3a2.PORTADATAIN
+data_a[3] => ram_block3a3.PORTADATAIN
+data_a[4] => ram_block3a4.PORTADATAIN
+data_a[5] => ram_block3a5.PORTADATAIN
+data_a[6] => ram_block3a6.PORTADATAIN
+data_a[7] => ram_block3a7.PORTADATAIN
+data_a[8] => ram_block3a8.PORTADATAIN
+data_a[9] => ram_block3a9.PORTADATAIN
+data_a[10] => ram_block3a10.PORTADATAIN
+data_a[11] => ram_block3a11.PORTADATAIN
+data_a[12] => ram_block3a12.PORTADATAIN
+data_a[13] => ram_block3a13.PORTADATAIN
+data_a[14] => ram_block3a14.PORTADATAIN
+data_a[15] => ram_block3a15.PORTADATAIN
+data_a[16] => ram_block3a16.PORTADATAIN
+data_a[17] => ram_block3a17.PORTADATAIN
+data_a[18] => ram_block3a18.PORTADATAIN
+data_a[19] => ram_block3a19.PORTADATAIN
+data_a[20] => ram_block3a20.PORTADATAIN
+data_a[21] => ram_block3a21.PORTADATAIN
+data_a[22] => ram_block3a22.PORTADATAIN
+data_a[23] => ram_block3a23.PORTADATAIN
+q_b[0] <= ram_block3a0.PORTBDATAOUT
+q_b[1] <= ram_block3a1.PORTBDATAOUT
+q_b[2] <= ram_block3a2.PORTBDATAOUT
+q_b[3] <= ram_block3a3.PORTBDATAOUT
+q_b[4] <= ram_block3a4.PORTBDATAOUT
+q_b[5] <= ram_block3a5.PORTBDATAOUT
+q_b[6] <= ram_block3a6.PORTBDATAOUT
+q_b[7] <= ram_block3a7.PORTBDATAOUT
+q_b[8] <= ram_block3a8.PORTBDATAOUT
+q_b[9] <= ram_block3a9.PORTBDATAOUT
+q_b[10] <= ram_block3a10.PORTBDATAOUT
+q_b[11] <= ram_block3a11.PORTBDATAOUT
+q_b[12] <= ram_block3a12.PORTBDATAOUT
+q_b[13] <= ram_block3a13.PORTBDATAOUT
+q_b[14] <= ram_block3a14.PORTBDATAOUT
+q_b[15] <= ram_block3a15.PORTBDATAOUT
+q_b[16] <= ram_block3a16.PORTBDATAOUT
+q_b[17] <= ram_block3a17.PORTBDATAOUT
+q_b[18] <= ram_block3a18.PORTBDATAOUT
+q_b[19] <= ram_block3a19.PORTBDATAOUT
+q_b[20] <= ram_block3a20.PORTBDATAOUT
+q_b[21] <= ram_block3a21.PORTBDATAOUT
+q_b[22] <= ram_block3a22.PORTBDATAOUT
+q_b[23] <= ram_block3a23.PORTBDATAOUT
+wren_a => ram_block3a0.PORTAWE
+wren_a => ram_block3a1.PORTAWE
+wren_a => ram_block3a2.PORTAWE
+wren_a => ram_block3a3.PORTAWE
+wren_a => ram_block3a4.PORTAWE
+wren_a => ram_block3a5.PORTAWE
+wren_a => ram_block3a6.PORTAWE
+wren_a => ram_block3a7.PORTAWE
+wren_a => ram_block3a8.PORTAWE
+wren_a => ram_block3a9.PORTAWE
+wren_a => ram_block3a10.PORTAWE
+wren_a => ram_block3a11.PORTAWE
+wren_a => ram_block3a12.PORTAWE
+wren_a => ram_block3a13.PORTAWE
+wren_a => ram_block3a14.PORTAWE
+wren_a => ram_block3a15.PORTAWE
+wren_a => ram_block3a16.PORTAWE
+wren_a => ram_block3a17.PORTAWE
+wren_a => ram_block3a18.PORTAWE
+wren_a => ram_block3a19.PORTAWE
+wren_a => ram_block3a20.PORTAWE
+wren_a => ram_block3a21.PORTAWE
+wren_a => ram_block3a22.PORTAWE
+wren_a => ram_block3a23.PORTAWE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1
+clk_en => counter_reg_bit[10].IN0
+clock => counter_reg_bit[10].CLK
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+q[10] <= counter_reg_bit[10].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+dataa[10] => data_wire[7].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+datab[10] => data_wire[7].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5
+oSEG0[0] <= SEG7_LUT:u0.port0
+oSEG0[1] <= SEG7_LUT:u0.port0
+oSEG0[2] <= SEG7_LUT:u0.port0
+oSEG0[3] <= SEG7_LUT:u0.port0
+oSEG0[4] <= SEG7_LUT:u0.port0
+oSEG0[5] <= SEG7_LUT:u0.port0
+oSEG0[6] <= SEG7_LUT:u0.port0
+oSEG1[0] <= SEG7_LUT:u1.port0
+oSEG1[1] <= SEG7_LUT:u1.port0
+oSEG1[2] <= SEG7_LUT:u1.port0
+oSEG1[3] <= SEG7_LUT:u1.port0
+oSEG1[4] <= SEG7_LUT:u1.port0
+oSEG1[5] <= SEG7_LUT:u1.port0
+oSEG1[6] <= SEG7_LUT:u1.port0
+oSEG2[0] <= SEG7_LUT:u2.port0
+oSEG2[1] <= SEG7_LUT:u2.port0
+oSEG2[2] <= SEG7_LUT:u2.port0
+oSEG2[3] <= SEG7_LUT:u2.port0
+oSEG2[4] <= SEG7_LUT:u2.port0
+oSEG2[5] <= SEG7_LUT:u2.port0
+oSEG2[6] <= SEG7_LUT:u2.port0
+oSEG3[0] <= SEG7_LUT:u3.port0
+oSEG3[1] <= SEG7_LUT:u3.port0
+oSEG3[2] <= SEG7_LUT:u3.port0
+oSEG3[3] <= SEG7_LUT:u3.port0
+oSEG3[4] <= SEG7_LUT:u3.port0
+oSEG3[5] <= SEG7_LUT:u3.port0
+oSEG3[6] <= SEG7_LUT:u3.port0
+oSEG4[0] <= SEG7_LUT:u4.port0
+oSEG4[1] <= SEG7_LUT:u4.port0
+oSEG4[2] <= SEG7_LUT:u4.port0
+oSEG4[3] <= SEG7_LUT:u4.port0
+oSEG4[4] <= SEG7_LUT:u4.port0
+oSEG4[5] <= SEG7_LUT:u4.port0
+oSEG4[6] <= SEG7_LUT:u4.port0
+oSEG5[0] <= SEG7_LUT:u5.port0
+oSEG5[1] <= SEG7_LUT:u5.port0
+oSEG5[2] <= SEG7_LUT:u5.port0
+oSEG5[3] <= SEG7_LUT:u5.port0
+oSEG5[4] <= SEG7_LUT:u5.port0
+oSEG5[5] <= SEG7_LUT:u5.port0
+oSEG5[6] <= SEG7_LUT:u5.port0
+oSEG6[0] <= SEG7_LUT:u6.port0
+oSEG6[1] <= SEG7_LUT:u6.port0
+oSEG6[2] <= SEG7_LUT:u6.port0
+oSEG6[3] <= SEG7_LUT:u6.port0
+oSEG6[4] <= SEG7_LUT:u6.port0
+oSEG6[5] <= SEG7_LUT:u6.port0
+oSEG6[6] <= SEG7_LUT:u6.port0
+oSEG7[0] <= SEG7_LUT:u7.port0
+oSEG7[1] <= SEG7_LUT:u7.port0
+oSEG7[2] <= SEG7_LUT:u7.port0
+oSEG7[3] <= SEG7_LUT:u7.port0
+oSEG7[4] <= SEG7_LUT:u7.port0
+oSEG7[5] <= SEG7_LUT:u7.port0
+oSEG7[6] <= SEG7_LUT:u7.port0
+iDIG[0] => iDIG[0].IN1
+iDIG[1] => iDIG[1].IN1
+iDIG[2] => iDIG[2].IN1
+iDIG[3] => iDIG[3].IN1
+iDIG[4] => iDIG[4].IN1
+iDIG[5] => iDIG[5].IN1
+iDIG[6] => iDIG[6].IN1
+iDIG[7] => iDIG[7].IN1
+iDIG[8] => iDIG[8].IN1
+iDIG[9] => iDIG[9].IN1
+iDIG[10] => iDIG[10].IN1
+iDIG[11] => iDIG[11].IN1
+iDIG[12] => iDIG[12].IN1
+iDIG[13] => iDIG[13].IN1
+iDIG[14] => iDIG[14].IN1
+iDIG[15] => iDIG[15].IN1
+iDIG[16] => iDIG[16].IN1
+iDIG[17] => iDIG[17].IN1
+iDIG[18] => iDIG[18].IN1
+iDIG[19] => iDIG[19].IN1
+iDIG[20] => iDIG[20].IN1
+iDIG[21] => iDIG[21].IN1
+iDIG[22] => iDIG[22].IN1
+iDIG[23] => iDIG[23].IN1
+iDIG[24] => iDIG[24].IN1
+iDIG[25] => iDIG[25].IN1
+iDIG[26] => iDIG[26].IN1
+iDIG[27] => iDIG[27].IN1
+iDIG[28] => iDIG[28].IN1
+iDIG[29] => iDIG[29].IN1
+iDIG[30] => iDIG[30].IN1
+iDIG[31] => iDIG[31].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u4
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u5
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u6
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u7
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6
+inclk0 => sub_wire4[0].IN1
+c0 <= altpll:altpll_component.clk
+c1 <= altpll:altpll_component.clk
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+inclk[0] => altpll_9ee2:auto_generated.inclk[0]
+inclk[1] => altpll_9ee2:auto_generated.inclk[1]
+fbin => ~NO_FANOUT~
+pllena => ~NO_FANOUT~
+clkswitch => ~NO_FANOUT~
+areset => ~NO_FANOUT~
+pfdena => ~NO_FANOUT~
+clkena[0] => ~NO_FANOUT~
+clkena[1] => ~NO_FANOUT~
+clkena[2] => ~NO_FANOUT~
+clkena[3] => ~NO_FANOUT~
+clkena[4] => ~NO_FANOUT~
+clkena[5] => ~NO_FANOUT~
+extclkena[0] => ~NO_FANOUT~
+extclkena[1] => ~NO_FANOUT~
+extclkena[2] => ~NO_FANOUT~
+extclkena[3] => ~NO_FANOUT~
+scanclk => ~NO_FANOUT~
+scanclkena => ~NO_FANOUT~
+scanaclr => ~NO_FANOUT~
+scanread => ~NO_FANOUT~
+scanwrite => ~NO_FANOUT~
+scandata => ~NO_FANOUT~
+phasecounterselect[0] => ~NO_FANOUT~
+phasecounterselect[1] => ~NO_FANOUT~
+phasecounterselect[2] => ~NO_FANOUT~
+phasecounterselect[3] => ~NO_FANOUT~
+phaseupdown => ~NO_FANOUT~
+phasestep => ~NO_FANOUT~
+configupdate => ~NO_FANOUT~
+fbmimicbidir <> <GND>
+clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
+clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
+clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
+clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
+clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
+extclk[0] <= <GND>
+extclk[1] <= <GND>
+extclk[2] <= <GND>
+extclk[3] <= <GND>
+clkbad[0] <= <GND>
+clkbad[1] <= <GND>
+enable1 <= <GND>
+enable0 <= <GND>
+activeclock <= <GND>
+clkloss <= <GND>
+locked <= <GND>
+scandataout <= <GND>
+scandone <= <GND>
+sclkout0 <= <GND>
+sclkout1 <= <GND>
+phasedone <= <GND>
+vcooverrange <= <GND>
+vcounderrange <= <GND>
+fbout <= <GND>
+fref <= <GND>
+icdrclk <= <GND>
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated
+clk[0] <= pll1.CLK
+clk[1] <= pll1.CLK1
+clk[2] <= pll1.CLK2
+clk[3] <= pll1.CLK3
+clk[4] <= pll1.CLK4
+inclk[0] => pll1.CLK
+inclk[1] => pll1.CLK1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7
+REF_CLK => ~NO_FANOUT~
+RESET_N => RESET_N.IN3
+CLK => CLK.IN7
+WR1_DATA[0] => WR1_DATA[0].IN1
+WR1_DATA[1] => WR1_DATA[1].IN1
+WR1_DATA[2] => WR1_DATA[2].IN1
+WR1_DATA[3] => WR1_DATA[3].IN1
+WR1_DATA[4] => WR1_DATA[4].IN1
+WR1_DATA[5] => WR1_DATA[5].IN1
+WR1_DATA[6] => WR1_DATA[6].IN1
+WR1_DATA[7] => WR1_DATA[7].IN1
+WR1_DATA[8] => WR1_DATA[8].IN1
+WR1_DATA[9] => WR1_DATA[9].IN1
+WR1_DATA[10] => WR1_DATA[10].IN1
+WR1_DATA[11] => WR1_DATA[11].IN1
+WR1_DATA[12] => WR1_DATA[12].IN1
+WR1_DATA[13] => WR1_DATA[13].IN1
+WR1_DATA[14] => WR1_DATA[14].IN1
+WR1_DATA[15] => WR1_DATA[15].IN1
+WR1 => WR1.IN1
+WR1_ADDR[0] => rWR1_ADDR.DATAA
+WR1_ADDR[0] => rWR1_ADDR.DATAB
+WR1_ADDR[1] => rWR1_ADDR.DATAA
+WR1_ADDR[1] => rWR1_ADDR.DATAB
+WR1_ADDR[2] => rWR1_ADDR.DATAA
+WR1_ADDR[2] => rWR1_ADDR.DATAB
+WR1_ADDR[3] => rWR1_ADDR.DATAA
+WR1_ADDR[3] => rWR1_ADDR.DATAB
+WR1_ADDR[4] => rWR1_ADDR.DATAA
+WR1_ADDR[4] => rWR1_ADDR.DATAB
+WR1_ADDR[5] => rWR1_ADDR.DATAA
+WR1_ADDR[5] => rWR1_ADDR.DATAB
+WR1_ADDR[6] => rWR1_ADDR.DATAA
+WR1_ADDR[6] => rWR1_ADDR.DATAB
+WR1_ADDR[7] => rWR1_ADDR.DATAA
+WR1_ADDR[7] => rWR1_ADDR.DATAB
+WR1_ADDR[8] => rWR1_ADDR.DATAA
+WR1_ADDR[8] => rWR1_ADDR.DATAB
+WR1_ADDR[9] => rWR1_ADDR.DATAA
+WR1_ADDR[9] => rWR1_ADDR.DATAB
+WR1_ADDR[10] => rWR1_ADDR.DATAA
+WR1_ADDR[10] => rWR1_ADDR.DATAB
+WR1_ADDR[11] => rWR1_ADDR.DATAA
+WR1_ADDR[11] => rWR1_ADDR.DATAB
+WR1_ADDR[12] => rWR1_ADDR.DATAA
+WR1_ADDR[12] => rWR1_ADDR.DATAB
+WR1_ADDR[13] => rWR1_ADDR.DATAA
+WR1_ADDR[13] => rWR1_ADDR.DATAB
+WR1_ADDR[14] => rWR1_ADDR.DATAA
+WR1_ADDR[14] => rWR1_ADDR.DATAB
+WR1_ADDR[15] => rWR1_ADDR.DATAA
+WR1_ADDR[15] => rWR1_ADDR.DATAB
+WR1_ADDR[16] => rWR1_ADDR.DATAA
+WR1_ADDR[16] => rWR1_ADDR.DATAB
+WR1_ADDR[17] => rWR1_ADDR.DATAA
+WR1_ADDR[17] => rWR1_ADDR.DATAB
+WR1_ADDR[18] => rWR1_ADDR.DATAA
+WR1_ADDR[18] => rWR1_ADDR.DATAB
+WR1_ADDR[19] => rWR1_ADDR.DATAA
+WR1_ADDR[19] => rWR1_ADDR.DATAB
+WR1_ADDR[20] => rWR1_ADDR.DATAA
+WR1_ADDR[20] => rWR1_ADDR.DATAB
+WR1_ADDR[21] => rWR1_ADDR.DATAA
+WR1_ADDR[21] => rWR1_ADDR.DATAB
+WR1_ADDR[22] => rWR1_ADDR.DATAA
+WR1_ADDR[22] => rWR1_ADDR.DATAB
+WR1_MAX_ADDR[0] => ~NO_FANOUT~
+WR1_MAX_ADDR[1] => ~NO_FANOUT~
+WR1_MAX_ADDR[2] => ~NO_FANOUT~
+WR1_MAX_ADDR[3] => ~NO_FANOUT~
+WR1_MAX_ADDR[4] => ~NO_FANOUT~
+WR1_MAX_ADDR[5] => ~NO_FANOUT~
+WR1_MAX_ADDR[6] => ~NO_FANOUT~
+WR1_MAX_ADDR[7] => ~NO_FANOUT~
+WR1_MAX_ADDR[8] => ~NO_FANOUT~
+WR1_MAX_ADDR[9] => ~NO_FANOUT~
+WR1_MAX_ADDR[10] => ~NO_FANOUT~
+WR1_MAX_ADDR[11] => ~NO_FANOUT~
+WR1_MAX_ADDR[12] => ~NO_FANOUT~
+WR1_MAX_ADDR[13] => ~NO_FANOUT~
+WR1_MAX_ADDR[14] => ~NO_FANOUT~
+WR1_MAX_ADDR[15] => ~NO_FANOUT~
+WR1_MAX_ADDR[16] => ~NO_FANOUT~
+WR1_MAX_ADDR[17] => ~NO_FANOUT~
+WR1_MAX_ADDR[18] => ~NO_FANOUT~
+WR1_MAX_ADDR[19] => ~NO_FANOUT~
+WR1_MAX_ADDR[20] => ~NO_FANOUT~
+WR1_MAX_ADDR[21] => ~NO_FANOUT~
+WR1_MAX_ADDR[22] => ~NO_FANOUT~
+WR1_LENGTH[0] => rWR1_LENGTH[0].DATAIN
+WR1_LENGTH[1] => rWR1_LENGTH[1].DATAIN
+WR1_LENGTH[2] => rWR1_LENGTH[2].DATAIN
+WR1_LENGTH[3] => rWR1_LENGTH[3].DATAIN
+WR1_LENGTH[4] => rWR1_LENGTH[4].DATAIN
+WR1_LENGTH[5] => rWR1_LENGTH[5].DATAIN
+WR1_LENGTH[6] => rWR1_LENGTH[6].DATAIN
+WR1_LENGTH[7] => rWR1_LENGTH[7].DATAIN
+WR1_LENGTH[8] => rWR1_LENGTH[8].DATAIN
+WR1_LOAD => WR1_LOAD.IN1
+WR1_CLK => WR1_CLK.IN1
+WR2_DATA[0] => WR2_DATA[0].IN1
+WR2_DATA[1] => WR2_DATA[1].IN1
+WR2_DATA[2] => WR2_DATA[2].IN1
+WR2_DATA[3] => WR2_DATA[3].IN1
+WR2_DATA[4] => WR2_DATA[4].IN1
+WR2_DATA[5] => WR2_DATA[5].IN1
+WR2_DATA[6] => WR2_DATA[6].IN1
+WR2_DATA[7] => WR2_DATA[7].IN1
+WR2_DATA[8] => WR2_DATA[8].IN1
+WR2_DATA[9] => WR2_DATA[9].IN1
+WR2_DATA[10] => WR2_DATA[10].IN1
+WR2_DATA[11] => WR2_DATA[11].IN1
+WR2_DATA[12] => WR2_DATA[12].IN1
+WR2_DATA[13] => WR2_DATA[13].IN1
+WR2_DATA[14] => WR2_DATA[14].IN1
+WR2_DATA[15] => WR2_DATA[15].IN1
+WR2 => WR2.IN1
+WR2_ADDR[0] => rWR2_ADDR.DATAA
+WR2_ADDR[0] => rWR2_ADDR.DATAB
+WR2_ADDR[1] => rWR2_ADDR.DATAA
+WR2_ADDR[1] => rWR2_ADDR.DATAB
+WR2_ADDR[2] => rWR2_ADDR.DATAA
+WR2_ADDR[2] => rWR2_ADDR.DATAB
+WR2_ADDR[3] => rWR2_ADDR.DATAA
+WR2_ADDR[3] => rWR2_ADDR.DATAB
+WR2_ADDR[4] => rWR2_ADDR.DATAA
+WR2_ADDR[4] => rWR2_ADDR.DATAB
+WR2_ADDR[5] => rWR2_ADDR.DATAA
+WR2_ADDR[5] => rWR2_ADDR.DATAB
+WR2_ADDR[6] => rWR2_ADDR.DATAA
+WR2_ADDR[6] => rWR2_ADDR.DATAB
+WR2_ADDR[7] => rWR2_ADDR.DATAA
+WR2_ADDR[7] => rWR2_ADDR.DATAB
+WR2_ADDR[8] => rWR2_ADDR.DATAA
+WR2_ADDR[8] => rWR2_ADDR.DATAB
+WR2_ADDR[9] => rWR2_ADDR.DATAA
+WR2_ADDR[9] => rWR2_ADDR.DATAB
+WR2_ADDR[10] => rWR2_ADDR.DATAA
+WR2_ADDR[10] => rWR2_ADDR.DATAB
+WR2_ADDR[11] => rWR2_ADDR.DATAA
+WR2_ADDR[11] => rWR2_ADDR.DATAB
+WR2_ADDR[12] => rWR2_ADDR.DATAA
+WR2_ADDR[12] => rWR2_ADDR.DATAB
+WR2_ADDR[13] => rWR2_ADDR.DATAA
+WR2_ADDR[13] => rWR2_ADDR.DATAB
+WR2_ADDR[14] => rWR2_ADDR.DATAA
+WR2_ADDR[14] => rWR2_ADDR.DATAB
+WR2_ADDR[15] => rWR2_ADDR.DATAA
+WR2_ADDR[15] => rWR2_ADDR.DATAB
+WR2_ADDR[16] => rWR2_ADDR.DATAA
+WR2_ADDR[16] => rWR2_ADDR.DATAB
+WR2_ADDR[17] => rWR2_ADDR.DATAA
+WR2_ADDR[17] => rWR2_ADDR.DATAB
+WR2_ADDR[18] => rWR2_ADDR.DATAA
+WR2_ADDR[18] => rWR2_ADDR.DATAB
+WR2_ADDR[19] => rWR2_ADDR.DATAA
+WR2_ADDR[19] => rWR2_ADDR.DATAB
+WR2_ADDR[20] => rWR2_ADDR.DATAA
+WR2_ADDR[20] => rWR2_ADDR.DATAB
+WR2_ADDR[21] => rWR2_ADDR.DATAA
+WR2_ADDR[21] => rWR2_ADDR.DATAB
+WR2_ADDR[22] => rWR2_ADDR.DATAA
+WR2_ADDR[22] => rWR2_ADDR.DATAB
+WR2_MAX_ADDR[0] => ~NO_FANOUT~
+WR2_MAX_ADDR[1] => ~NO_FANOUT~
+WR2_MAX_ADDR[2] => ~NO_FANOUT~
+WR2_MAX_ADDR[3] => ~NO_FANOUT~
+WR2_MAX_ADDR[4] => ~NO_FANOUT~
+WR2_MAX_ADDR[5] => ~NO_FANOUT~
+WR2_MAX_ADDR[6] => ~NO_FANOUT~
+WR2_MAX_ADDR[7] => ~NO_FANOUT~
+WR2_MAX_ADDR[8] => ~NO_FANOUT~
+WR2_MAX_ADDR[9] => ~NO_FANOUT~
+WR2_MAX_ADDR[10] => ~NO_FANOUT~
+WR2_MAX_ADDR[11] => ~NO_FANOUT~
+WR2_MAX_ADDR[12] => ~NO_FANOUT~
+WR2_MAX_ADDR[13] => ~NO_FANOUT~
+WR2_MAX_ADDR[14] => ~NO_FANOUT~
+WR2_MAX_ADDR[15] => ~NO_FANOUT~
+WR2_MAX_ADDR[16] => ~NO_FANOUT~
+WR2_MAX_ADDR[17] => ~NO_FANOUT~
+WR2_MAX_ADDR[18] => ~NO_FANOUT~
+WR2_MAX_ADDR[19] => ~NO_FANOUT~
+WR2_MAX_ADDR[20] => ~NO_FANOUT~
+WR2_MAX_ADDR[21] => ~NO_FANOUT~
+WR2_MAX_ADDR[22] => ~NO_FANOUT~
+WR2_LENGTH[0] => rWR2_LENGTH[0].DATAIN
+WR2_LENGTH[1] => rWR2_LENGTH[1].DATAIN
+WR2_LENGTH[2] => rWR2_LENGTH[2].DATAIN
+WR2_LENGTH[3] => rWR2_LENGTH[3].DATAIN
+WR2_LENGTH[4] => rWR2_LENGTH[4].DATAIN
+WR2_LENGTH[5] => rWR2_LENGTH[5].DATAIN
+WR2_LENGTH[6] => rWR2_LENGTH[6].DATAIN
+WR2_LENGTH[7] => rWR2_LENGTH[7].DATAIN
+WR2_LENGTH[8] => rWR2_LENGTH[8].DATAIN
+WR2_LOAD => WR2_LOAD.IN1
+WR2_CLK => WR2_CLK.IN1
+RD1_DATA[0] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[1] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[2] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[3] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[4] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[5] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[6] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[7] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[8] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[9] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[10] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[11] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[12] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[13] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[14] <= Sdram_FIFO:read_fifo1.q
+RD1_DATA[15] <= Sdram_FIFO:read_fifo1.q
+RD1 => RD1.IN1
+RD1_ADDR[0] => rRD1_ADDR.DATAA
+RD1_ADDR[0] => rRD1_ADDR.DATAB
+RD1_ADDR[1] => rRD1_ADDR.DATAA
+RD1_ADDR[1] => rRD1_ADDR.DATAB
+RD1_ADDR[2] => rRD1_ADDR.DATAA
+RD1_ADDR[2] => rRD1_ADDR.DATAB
+RD1_ADDR[3] => rRD1_ADDR.DATAA
+RD1_ADDR[3] => rRD1_ADDR.DATAB
+RD1_ADDR[4] => rRD1_ADDR.DATAA
+RD1_ADDR[4] => rRD1_ADDR.DATAB
+RD1_ADDR[5] => rRD1_ADDR.DATAA
+RD1_ADDR[5] => rRD1_ADDR.DATAB
+RD1_ADDR[6] => rRD1_ADDR.DATAA
+RD1_ADDR[6] => rRD1_ADDR.DATAB
+RD1_ADDR[7] => rRD1_ADDR.DATAA
+RD1_ADDR[7] => rRD1_ADDR.DATAB
+RD1_ADDR[8] => rRD1_ADDR.DATAA
+RD1_ADDR[8] => rRD1_ADDR.DATAB
+RD1_ADDR[9] => rRD1_ADDR.DATAA
+RD1_ADDR[9] => rRD1_ADDR.DATAB
+RD1_ADDR[10] => rRD1_ADDR.DATAA
+RD1_ADDR[10] => rRD1_ADDR.DATAB
+RD1_ADDR[11] => rRD1_ADDR.DATAA
+RD1_ADDR[11] => rRD1_ADDR.DATAB
+RD1_ADDR[12] => rRD1_ADDR.DATAA
+RD1_ADDR[12] => rRD1_ADDR.DATAB
+RD1_ADDR[13] => rRD1_ADDR.DATAA
+RD1_ADDR[13] => rRD1_ADDR.DATAB
+RD1_ADDR[14] => rRD1_ADDR.DATAA
+RD1_ADDR[14] => rRD1_ADDR.DATAB
+RD1_ADDR[15] => rRD1_ADDR.DATAA
+RD1_ADDR[15] => rRD1_ADDR.DATAB
+RD1_ADDR[16] => rRD1_ADDR.DATAA
+RD1_ADDR[16] => rRD1_ADDR.DATAB
+RD1_ADDR[17] => rRD1_ADDR.DATAA
+RD1_ADDR[17] => rRD1_ADDR.DATAB
+RD1_ADDR[18] => rRD1_ADDR.DATAA
+RD1_ADDR[18] => rRD1_ADDR.DATAB
+RD1_ADDR[19] => rRD1_ADDR.DATAA
+RD1_ADDR[19] => rRD1_ADDR.DATAB
+RD1_ADDR[20] => rRD1_ADDR.DATAA
+RD1_ADDR[20] => rRD1_ADDR.DATAB
+RD1_ADDR[21] => rRD1_ADDR.DATAA
+RD1_ADDR[21] => rRD1_ADDR.DATAB
+RD1_ADDR[22] => rRD1_ADDR.DATAA
+RD1_ADDR[22] => rRD1_ADDR.DATAB
+RD1_MAX_ADDR[0] => ~NO_FANOUT~
+RD1_MAX_ADDR[1] => ~NO_FANOUT~
+RD1_MAX_ADDR[2] => ~NO_FANOUT~
+RD1_MAX_ADDR[3] => ~NO_FANOUT~
+RD1_MAX_ADDR[4] => ~NO_FANOUT~
+RD1_MAX_ADDR[5] => ~NO_FANOUT~
+RD1_MAX_ADDR[6] => ~NO_FANOUT~
+RD1_MAX_ADDR[7] => ~NO_FANOUT~
+RD1_MAX_ADDR[8] => ~NO_FANOUT~
+RD1_MAX_ADDR[9] => ~NO_FANOUT~
+RD1_MAX_ADDR[10] => ~NO_FANOUT~
+RD1_MAX_ADDR[11] => ~NO_FANOUT~
+RD1_MAX_ADDR[12] => ~NO_FANOUT~
+RD1_MAX_ADDR[13] => ~NO_FANOUT~
+RD1_MAX_ADDR[14] => ~NO_FANOUT~
+RD1_MAX_ADDR[15] => ~NO_FANOUT~
+RD1_MAX_ADDR[16] => ~NO_FANOUT~
+RD1_MAX_ADDR[17] => ~NO_FANOUT~
+RD1_MAX_ADDR[18] => ~NO_FANOUT~
+RD1_MAX_ADDR[19] => ~NO_FANOUT~
+RD1_MAX_ADDR[20] => ~NO_FANOUT~
+RD1_MAX_ADDR[21] => ~NO_FANOUT~
+RD1_MAX_ADDR[22] => ~NO_FANOUT~
+RD1_LENGTH[0] => rRD1_LENGTH[0].DATAIN
+RD1_LENGTH[1] => rRD1_LENGTH[1].DATAIN
+RD1_LENGTH[2] => rRD1_LENGTH[2].DATAIN
+RD1_LENGTH[3] => rRD1_LENGTH[3].DATAIN
+RD1_LENGTH[4] => rRD1_LENGTH[4].DATAIN
+RD1_LENGTH[5] => rRD1_LENGTH[5].DATAIN
+RD1_LENGTH[6] => rRD1_LENGTH[6].DATAIN
+RD1_LENGTH[7] => rRD1_LENGTH[7].DATAIN
+RD1_LENGTH[8] => rRD1_LENGTH[8].DATAIN
+RD1_LOAD => RD1_LOAD.IN1
+RD1_CLK => RD1_CLK.IN1
+RD2_DATA[0] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[1] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[2] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[3] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[4] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[5] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[6] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[7] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[8] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[9] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[10] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[11] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[12] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[13] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[14] <= Sdram_FIFO:read_fifo2.q
+RD2_DATA[15] <= Sdram_FIFO:read_fifo2.q
+RD2 => RD2.IN1
+RD2_ADDR[0] => rRD2_ADDR.DATAA
+RD2_ADDR[0] => rRD2_ADDR.DATAB
+RD2_ADDR[1] => rRD2_ADDR.DATAA
+RD2_ADDR[1] => rRD2_ADDR.DATAB
+RD2_ADDR[2] => rRD2_ADDR.DATAA
+RD2_ADDR[2] => rRD2_ADDR.DATAB
+RD2_ADDR[3] => rRD2_ADDR.DATAA
+RD2_ADDR[3] => rRD2_ADDR.DATAB
+RD2_ADDR[4] => rRD2_ADDR.DATAA
+RD2_ADDR[4] => rRD2_ADDR.DATAB
+RD2_ADDR[5] => rRD2_ADDR.DATAA
+RD2_ADDR[5] => rRD2_ADDR.DATAB
+RD2_ADDR[6] => rRD2_ADDR.DATAA
+RD2_ADDR[6] => rRD2_ADDR.DATAB
+RD2_ADDR[7] => rRD2_ADDR.DATAA
+RD2_ADDR[7] => rRD2_ADDR.DATAB
+RD2_ADDR[8] => rRD2_ADDR.DATAA
+RD2_ADDR[8] => rRD2_ADDR.DATAB
+RD2_ADDR[9] => rRD2_ADDR.DATAA
+RD2_ADDR[9] => rRD2_ADDR.DATAB
+RD2_ADDR[10] => rRD2_ADDR.DATAA
+RD2_ADDR[10] => rRD2_ADDR.DATAB
+RD2_ADDR[11] => rRD2_ADDR.DATAA
+RD2_ADDR[11] => rRD2_ADDR.DATAB
+RD2_ADDR[12] => rRD2_ADDR.DATAA
+RD2_ADDR[12] => rRD2_ADDR.DATAB
+RD2_ADDR[13] => rRD2_ADDR.DATAA
+RD2_ADDR[13] => rRD2_ADDR.DATAB
+RD2_ADDR[14] => rRD2_ADDR.DATAA
+RD2_ADDR[14] => rRD2_ADDR.DATAB
+RD2_ADDR[15] => rRD2_ADDR.DATAA
+RD2_ADDR[15] => rRD2_ADDR.DATAB
+RD2_ADDR[16] => rRD2_ADDR.DATAA
+RD2_ADDR[16] => rRD2_ADDR.DATAB
+RD2_ADDR[17] => rRD2_ADDR.DATAA
+RD2_ADDR[17] => rRD2_ADDR.DATAB
+RD2_ADDR[18] => rRD2_ADDR.DATAA
+RD2_ADDR[18] => rRD2_ADDR.DATAB
+RD2_ADDR[19] => rRD2_ADDR.DATAA
+RD2_ADDR[19] => rRD2_ADDR.DATAB
+RD2_ADDR[20] => rRD2_ADDR.DATAA
+RD2_ADDR[20] => rRD2_ADDR.DATAB
+RD2_ADDR[21] => rRD2_ADDR.DATAA
+RD2_ADDR[21] => rRD2_ADDR.DATAB
+RD2_ADDR[22] => rRD2_ADDR.DATAA
+RD2_ADDR[22] => rRD2_ADDR.DATAB
+RD2_MAX_ADDR[0] => ~NO_FANOUT~
+RD2_MAX_ADDR[1] => ~NO_FANOUT~
+RD2_MAX_ADDR[2] => ~NO_FANOUT~
+RD2_MAX_ADDR[3] => ~NO_FANOUT~
+RD2_MAX_ADDR[4] => ~NO_FANOUT~
+RD2_MAX_ADDR[5] => ~NO_FANOUT~
+RD2_MAX_ADDR[6] => ~NO_FANOUT~
+RD2_MAX_ADDR[7] => ~NO_FANOUT~
+RD2_MAX_ADDR[8] => ~NO_FANOUT~
+RD2_MAX_ADDR[9] => ~NO_FANOUT~
+RD2_MAX_ADDR[10] => ~NO_FANOUT~
+RD2_MAX_ADDR[11] => ~NO_FANOUT~
+RD2_MAX_ADDR[12] => ~NO_FANOUT~
+RD2_MAX_ADDR[13] => ~NO_FANOUT~
+RD2_MAX_ADDR[14] => ~NO_FANOUT~
+RD2_MAX_ADDR[15] => ~NO_FANOUT~
+RD2_MAX_ADDR[16] => ~NO_FANOUT~
+RD2_MAX_ADDR[17] => ~NO_FANOUT~
+RD2_MAX_ADDR[18] => ~NO_FANOUT~
+RD2_MAX_ADDR[19] => ~NO_FANOUT~
+RD2_MAX_ADDR[20] => ~NO_FANOUT~
+RD2_MAX_ADDR[21] => ~NO_FANOUT~
+RD2_MAX_ADDR[22] => ~NO_FANOUT~
+RD2_LENGTH[0] => rRD2_LENGTH[0].DATAIN
+RD2_LENGTH[1] => rRD2_LENGTH[1].DATAIN
+RD2_LENGTH[2] => rRD2_LENGTH[2].DATAIN
+RD2_LENGTH[3] => rRD2_LENGTH[3].DATAIN
+RD2_LENGTH[4] => rRD2_LENGTH[4].DATAIN
+RD2_LENGTH[5] => rRD2_LENGTH[5].DATAIN
+RD2_LENGTH[6] => rRD2_LENGTH[6].DATAIN
+RD2_LENGTH[7] => rRD2_LENGTH[7].DATAIN
+RD2_LENGTH[8] => rRD2_LENGTH[8].DATAIN
+RD2_LOAD => RD2_LOAD.IN1
+RD2_CLK => RD2_CLK.IN1
+SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[0] <= CS_N[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[1] <= CS_N[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RAS_N <= RAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CAS_N <= CAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+WE_N <= WE_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQ[0] <> DQ[0]
+DQ[1] <> DQ[1]
+DQ[2] <> DQ[2]
+DQ[3] <> DQ[3]
+DQ[4] <> DQ[4]
+DQ[5] <> DQ[5]
+DQ[6] <> DQ[6]
+DQ[7] <> DQ[7]
+DQ[8] <> DQ[8]
+DQ[9] <> DQ[9]
+DQ[10] <> DQ[10]
+DQ[11] <> DQ[11]
+DQ[12] <> DQ[12]
+DQ[13] <> DQ[13]
+DQ[14] <> DQ[14]
+DQ[15] <> DQ[15]
+DQM[0] <= DQM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQM[1] <= DQM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+CLK => INIT_REQ~reg0.CLK
+CLK => LOAD_MODE~reg0.CLK
+CLK => PRECHARGE~reg0.CLK
+CLK => REFRESH~reg0.CLK
+CLK => init_timer[0].CLK
+CLK => init_timer[1].CLK
+CLK => init_timer[2].CLK
+CLK => init_timer[3].CLK
+CLK => init_timer[4].CLK
+CLK => init_timer[5].CLK
+CLK => init_timer[6].CLK
+CLK => init_timer[7].CLK
+CLK => init_timer[8].CLK
+CLK => init_timer[9].CLK
+CLK => init_timer[10].CLK
+CLK => init_timer[11].CLK
+CLK => init_timer[12].CLK
+CLK => init_timer[13].CLK
+CLK => init_timer[14].CLK
+CLK => init_timer[15].CLK
+CLK => REF_REQ~reg0.CLK
+CLK => timer[0].CLK
+CLK => timer[1].CLK
+CLK => timer[2].CLK
+CLK => timer[3].CLK
+CLK => timer[4].CLK
+CLK => timer[5].CLK
+CLK => timer[6].CLK
+CLK => timer[7].CLK
+CLK => timer[8].CLK
+CLK => timer[9].CLK
+CLK => timer[10].CLK
+CLK => timer[11].CLK
+CLK => timer[12].CLK
+CLK => timer[13].CLK
+CLK => timer[14].CLK
+CLK => timer[15].CLK
+CLK => CMD_ACK~reg0.CLK
+CLK => SADDR[0]~reg0.CLK
+CLK => SADDR[1]~reg0.CLK
+CLK => SADDR[2]~reg0.CLK
+CLK => SADDR[3]~reg0.CLK
+CLK => SADDR[4]~reg0.CLK
+CLK => SADDR[5]~reg0.CLK
+CLK => SADDR[6]~reg0.CLK
+CLK => SADDR[7]~reg0.CLK
+CLK => SADDR[8]~reg0.CLK
+CLK => SADDR[9]~reg0.CLK
+CLK => SADDR[10]~reg0.CLK
+CLK => SADDR[11]~reg0.CLK
+CLK => SADDR[12]~reg0.CLK
+CLK => SADDR[13]~reg0.CLK
+CLK => SADDR[14]~reg0.CLK
+CLK => SADDR[15]~reg0.CLK
+CLK => SADDR[16]~reg0.CLK
+CLK => SADDR[17]~reg0.CLK
+CLK => SADDR[18]~reg0.CLK
+CLK => SADDR[19]~reg0.CLK
+CLK => SADDR[20]~reg0.CLK
+CLK => SADDR[21]~reg0.CLK
+CLK => SADDR[22]~reg0.CLK
+CLK => WRITEA~reg0.CLK
+CLK => READA~reg0.CLK
+CLK => NOP~reg0.CLK
+RESET_N => SADDR[0]~reg0.ACLR
+RESET_N => SADDR[1]~reg0.ACLR
+RESET_N => SADDR[2]~reg0.ACLR
+RESET_N => SADDR[3]~reg0.ACLR
+RESET_N => SADDR[4]~reg0.ACLR
+RESET_N => SADDR[5]~reg0.ACLR
+RESET_N => SADDR[6]~reg0.ACLR
+RESET_N => SADDR[7]~reg0.ACLR
+RESET_N => SADDR[8]~reg0.ACLR
+RESET_N => SADDR[9]~reg0.ACLR
+RESET_N => SADDR[10]~reg0.ACLR
+RESET_N => SADDR[11]~reg0.ACLR
+RESET_N => SADDR[12]~reg0.ACLR
+RESET_N => SADDR[13]~reg0.ACLR
+RESET_N => SADDR[14]~reg0.ACLR
+RESET_N => SADDR[15]~reg0.ACLR
+RESET_N => SADDR[16]~reg0.ACLR
+RESET_N => SADDR[17]~reg0.ACLR
+RESET_N => SADDR[18]~reg0.ACLR
+RESET_N => SADDR[19]~reg0.ACLR
+RESET_N => SADDR[20]~reg0.ACLR
+RESET_N => SADDR[21]~reg0.ACLR
+RESET_N => SADDR[22]~reg0.ACLR
+RESET_N => WRITEA~reg0.ACLR
+RESET_N => READA~reg0.ACLR
+RESET_N => NOP~reg0.ACLR
+RESET_N => INIT_REQ~reg0.ACLR
+RESET_N => LOAD_MODE~reg0.ACLR
+RESET_N => PRECHARGE~reg0.ACLR
+RESET_N => REFRESH~reg0.ACLR
+RESET_N => init_timer[0].ACLR
+RESET_N => init_timer[1].ACLR
+RESET_N => init_timer[2].ACLR
+RESET_N => init_timer[3].ACLR
+RESET_N => init_timer[4].ACLR
+RESET_N => init_timer[5].ACLR
+RESET_N => init_timer[6].ACLR
+RESET_N => init_timer[7].ACLR
+RESET_N => init_timer[8].ACLR
+RESET_N => init_timer[9].ACLR
+RESET_N => init_timer[10].ACLR
+RESET_N => init_timer[11].ACLR
+RESET_N => init_timer[12].ACLR
+RESET_N => init_timer[13].ACLR
+RESET_N => init_timer[14].ACLR
+RESET_N => init_timer[15].ACLR
+RESET_N => REF_REQ~reg0.ACLR
+RESET_N => timer[0].ACLR
+RESET_N => timer[1].ACLR
+RESET_N => timer[2].ACLR
+RESET_N => timer[3].ACLR
+RESET_N => timer[4].ACLR
+RESET_N => timer[5].ACLR
+RESET_N => timer[6].ACLR
+RESET_N => timer[7].ACLR
+RESET_N => timer[8].ACLR
+RESET_N => timer[9].ACLR
+RESET_N => timer[10].ACLR
+RESET_N => timer[11].ACLR
+RESET_N => timer[12].ACLR
+RESET_N => timer[13].ACLR
+RESET_N => timer[14].ACLR
+RESET_N => timer[15].ACLR
+RESET_N => CMD_ACK~reg0.ACLR
+CMD[0] => Equal0.IN2
+CMD[0] => Equal1.IN0
+CMD[0] => Equal2.IN2
+CMD[1] => Equal0.IN1
+CMD[1] => Equal1.IN2
+CMD[1] => Equal2.IN0
+CMD[2] => Equal0.IN0
+CMD[2] => Equal1.IN1
+CMD[2] => Equal2.IN1
+ADDR[0] => SADDR[0]~reg0.DATAIN
+ADDR[1] => SADDR[1]~reg0.DATAIN
+ADDR[2] => SADDR[2]~reg0.DATAIN
+ADDR[3] => SADDR[3]~reg0.DATAIN
+ADDR[4] => SADDR[4]~reg0.DATAIN
+ADDR[5] => SADDR[5]~reg0.DATAIN
+ADDR[6] => SADDR[6]~reg0.DATAIN
+ADDR[7] => SADDR[7]~reg0.DATAIN
+ADDR[8] => SADDR[8]~reg0.DATAIN
+ADDR[9] => SADDR[9]~reg0.DATAIN
+ADDR[10] => SADDR[10]~reg0.DATAIN
+ADDR[11] => SADDR[11]~reg0.DATAIN
+ADDR[12] => SADDR[12]~reg0.DATAIN
+ADDR[13] => SADDR[13]~reg0.DATAIN
+ADDR[14] => SADDR[14]~reg0.DATAIN
+ADDR[15] => SADDR[15]~reg0.DATAIN
+ADDR[16] => SADDR[16]~reg0.DATAIN
+ADDR[17] => SADDR[17]~reg0.DATAIN
+ADDR[18] => SADDR[18]~reg0.DATAIN
+ADDR[19] => SADDR[19]~reg0.DATAIN
+ADDR[20] => SADDR[20]~reg0.DATAIN
+ADDR[21] => SADDR[21]~reg0.DATAIN
+ADDR[22] => SADDR[22]~reg0.DATAIN
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => timer.OUTPUTSELECT
+REF_ACK => REF_REQ.OUTPUTSELECT
+INIT_ACK => ~NO_FANOUT~
+CM_ACK => always1.IN1
+NOP <= NOP~reg0.DB_MAX_OUTPUT_PORT_TYPE
+READA <= READA~reg0.DB_MAX_OUTPUT_PORT_TYPE
+WRITEA <= WRITEA~reg0.DB_MAX_OUTPUT_PORT_TYPE
+REFRESH <= REFRESH~reg0.DB_MAX_OUTPUT_PORT_TYPE
+PRECHARGE <= PRECHARGE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+LOAD_MODE <= LOAD_MODE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[0] <= SADDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[1] <= SADDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[2] <= SADDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[3] <= SADDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[4] <= SADDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[5] <= SADDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[6] <= SADDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[7] <= SADDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[8] <= SADDR[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[9] <= SADDR[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[10] <= SADDR[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[11] <= SADDR[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[12] <= SADDR[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[13] <= SADDR[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[14] <= SADDR[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[15] <= SADDR[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[16] <= SADDR[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[17] <= SADDR[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[18] <= SADDR[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[19] <= SADDR[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[20] <= SADDR[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[21] <= SADDR[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SADDR[22] <= SADDR[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+REF_REQ <= REF_REQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
+INIT_REQ <= INIT_REQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CMD_ACK <= CMD_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+CLK => CKE~reg0.CLK
+CLK => WE_N~reg0.CLK
+CLK => CAS_N~reg0.CLK
+CLK => RAS_N~reg0.CLK
+CLK => CS_N[0]~reg0.CLK
+CLK => CS_N[1]~reg0.CLK
+CLK => BA[0]~reg0.CLK
+CLK => BA[1]~reg0.CLK
+CLK => SA[0]~reg0.CLK
+CLK => SA[1]~reg0.CLK
+CLK => SA[2]~reg0.CLK
+CLK => SA[3]~reg0.CLK
+CLK => SA[4]~reg0.CLK
+CLK => SA[5]~reg0.CLK
+CLK => SA[6]~reg0.CLK
+CLK => SA[7]~reg0.CLK
+CLK => SA[8]~reg0.CLK
+CLK => SA[9]~reg0.CLK
+CLK => SA[10]~reg0.CLK
+CLK => SA[11]~reg0.CLK
+CLK => REF_ACK~reg0.CLK
+CLK => CM_ACK~reg0.CLK
+CLK => do_rw.CLK
+CLK => rw_shift[0].CLK
+CLK => rw_shift[1].CLK
+CLK => oe4.CLK
+CLK => OE~reg0.CLK
+CLK => ex_write.CLK
+CLK => ex_read.CLK
+CLK => rp_done.CLK
+CLK => rp_shift[0].CLK
+CLK => rp_shift[1].CLK
+CLK => rp_shift[2].CLK
+CLK => rp_shift[3].CLK
+CLK => rw_flag.CLK
+CLK => command_delay[0].CLK
+CLK => command_delay[1].CLK
+CLK => command_delay[2].CLK
+CLK => command_delay[3].CLK
+CLK => command_delay[4].CLK
+CLK => command_delay[5].CLK
+CLK => command_delay[6].CLK
+CLK => command_delay[7].CLK
+CLK => command_done.CLK
+CLK => do_initial.CLK
+CLK => do_load_mode.CLK
+CLK => do_precharge.CLK
+CLK => do_refresh.CLK
+CLK => do_writea.CLK
+CLK => do_reada.CLK
+RESET_N => CKE~reg0.DATAIN
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => SA.OUTPUTSELECT
+RESET_N => BA.OUTPUTSELECT
+RESET_N => BA.OUTPUTSELECT
+RESET_N => CS_N.OUTPUTSELECT
+RESET_N => CS_N.OUTPUTSELECT
+RESET_N => RAS_N.OUTPUTSELECT
+RESET_N => CAS_N.OUTPUTSELECT
+RESET_N => WE_N.OUTPUTSELECT
+RESET_N => REF_ACK~reg0.ACLR
+RESET_N => CM_ACK~reg0.ACLR
+RESET_N => OE~reg0.ACLR
+RESET_N => ex_write.ACLR
+RESET_N => ex_read.ACLR
+RESET_N => rp_done.ACLR
+RESET_N => rp_shift[0].ACLR
+RESET_N => rp_shift[1].ACLR
+RESET_N => rp_shift[2].ACLR
+RESET_N => rp_shift[3].ACLR
+RESET_N => rw_flag.ACLR
+RESET_N => command_delay[0].ACLR
+RESET_N => command_delay[1].ACLR
+RESET_N => command_delay[2].ACLR
+RESET_N => command_delay[3].ACLR
+RESET_N => command_delay[4].ACLR
+RESET_N => command_delay[5].ACLR
+RESET_N => command_delay[6].ACLR
+RESET_N => command_delay[7].ACLR
+RESET_N => command_done.ACLR
+RESET_N => do_initial.ACLR
+RESET_N => do_load_mode.ACLR
+RESET_N => do_precharge.ACLR
+RESET_N => do_refresh.ACLR
+RESET_N => do_writea.ACLR
+RESET_N => do_reada.ACLR
+RESET_N => do_rw.ACLR
+RESET_N => rw_shift[0].ACLR
+RESET_N => rw_shift[1].ACLR
+RESET_N => oe4.ENA
+SADDR[0] => SA.DATAA
+SADDR[1] => SA.DATAA
+SADDR[2] => SA.DATAA
+SADDR[3] => SA.DATAA
+SADDR[4] => SA.DATAA
+SADDR[5] => SA.DATAA
+SADDR[6] => SA.DATAA
+SADDR[7] => SA.DATAA
+SADDR[8] => SA.DATAB
+SADDR[9] => SA.DATAB
+SADDR[10] => SA.DATAB
+SADDR[11] => SA.DATAB
+SADDR[12] => SA.DATAB
+SADDR[13] => SA.DATAB
+SADDR[14] => SA.DATAB
+SADDR[15] => SA.DATAB
+SADDR[16] => SA.DATAB
+SADDR[17] => SA.DATAB
+SADDR[18] => SA.DATAB
+SADDR[19] => SA.DATAB
+SADDR[20] => BA.DATAA
+SADDR[21] => BA.DATAA
+SADDR[22] => CS_N.DATAA
+SADDR[22] => CS_N.DATAA
+NOP => ~NO_FANOUT~
+READA => always0.IN1
+WRITEA => always0.IN1
+REFRESH => always0.IN0
+PRECHARGE => always0.IN1
+LOAD_MODE => always0.IN1
+REF_REQ => always0.IN1
+REF_REQ => always3.IN1
+REF_REQ => always0.IN1
+REF_REQ => always0.IN1
+INIT_REQ => do_reada.OUTPUTSELECT
+INIT_REQ => do_writea.OUTPUTSELECT
+INIT_REQ => do_refresh.OUTPUTSELECT
+INIT_REQ => do_precharge.OUTPUTSELECT
+INIT_REQ => do_load_mode.OUTPUTSELECT
+INIT_REQ => command_done.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => command_delay.OUTPUTSELECT
+INIT_REQ => rw_flag.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_shift.OUTPUTSELECT
+INIT_REQ => rp_done.OUTPUTSELECT
+INIT_REQ => ex_read.OUTPUTSELECT
+INIT_REQ => ex_write.OUTPUTSELECT
+INIT_REQ => do_initial.DATAIN
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_shift.OUTPUTSELECT
+PM_STOP => rp_done.OUTPUTSELECT
+PM_STOP => ex_read.OUTPUTSELECT
+PM_STOP => ex_write.OUTPUTSELECT
+PM_STOP => always1.IN1
+PM_DONE => ~NO_FANOUT~
+REF_ACK <= REF_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CM_ACK <= CM_ACK~reg0.DB_MAX_OUTPUT_PORT_TYPE
+OE <= OE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[0] <= SA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[1] <= SA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[2] <= SA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[3] <= SA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[4] <= SA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[5] <= SA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[6] <= SA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[7] <= SA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[8] <= SA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[9] <= SA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[10] <= SA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+SA[11] <= SA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[0] <= CS_N[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CS_N[1] <= CS_N[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
+RAS_N <= RAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+CAS_N <= CAS_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+WE_N <= WE_N~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+CLK => DQM[0]~reg0.CLK
+CLK => DQM[1]~reg0.CLK
+RESET_N => DQM[0]~reg0.PRESET
+RESET_N => DQM[1]~reg0.ACLR
+DATAIN[0] => DQOUT[0].DATAIN
+DATAIN[1] => DQOUT[1].DATAIN
+DATAIN[2] => DQOUT[2].DATAIN
+DATAIN[3] => DQOUT[3].DATAIN
+DATAIN[4] => DQOUT[4].DATAIN
+DATAIN[5] => DQOUT[5].DATAIN
+DATAIN[6] => DQOUT[6].DATAIN
+DATAIN[7] => DQOUT[7].DATAIN
+DATAIN[8] => DQOUT[8].DATAIN
+DATAIN[9] => DQOUT[9].DATAIN
+DATAIN[10] => DQOUT[10].DATAIN
+DATAIN[11] => DQOUT[11].DATAIN
+DATAIN[12] => DQOUT[12].DATAIN
+DATAIN[13] => DQOUT[13].DATAIN
+DATAIN[14] => DQOUT[14].DATAIN
+DATAIN[15] => DQOUT[15].DATAIN
+DM[0] => DQM[0]~reg0.DATAIN
+DM[1] => DQM[1]~reg0.DATAIN
+DQOUT[0] <= DATAIN[0].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[1] <= DATAIN[1].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[2] <= DATAIN[2].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[3] <= DATAIN[3].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[4] <= DATAIN[4].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[5] <= DATAIN[5].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[6] <= DATAIN[6].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[7] <= DATAIN[7].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[8] <= DATAIN[8].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[9] <= DATAIN[9].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[10] <= DATAIN[10].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[11] <= DATAIN[11].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[12] <= DATAIN[12].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[13] <= DATAIN[13].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[14] <= DATAIN[14].DB_MAX_OUTPUT_PORT_TYPE
+DQOUT[15] <= DATAIN[15].DB_MAX_OUTPUT_PORT_TYPE
+DQM[0] <= DQM[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+DQM[1] <= DQM[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2
+aclr => aclr.IN1
+data[0] => data[0].IN1
+data[1] => data[1].IN1
+data[2] => data[2].IN1
+data[3] => data[3].IN1
+data[4] => data[4].IN1
+data[5] => data[5].IN1
+data[6] => data[6].IN1
+data[7] => data[7].IN1
+data[8] => data[8].IN1
+data[9] => data[9].IN1
+data[10] => data[10].IN1
+data[11] => data[11].IN1
+data[12] => data[12].IN1
+data[13] => data[13].IN1
+data[14] => data[14].IN1
+data[15] => data[15].IN1
+rdclk => rdclk.IN1
+rdreq => rdreq.IN1
+wrclk => wrclk.IN1
+wrreq => wrreq.IN1
+q[0] <= dcfifo:dcfifo_component.q
+q[1] <= dcfifo:dcfifo_component.q
+q[2] <= dcfifo:dcfifo_component.q
+q[3] <= dcfifo:dcfifo_component.q
+q[4] <= dcfifo:dcfifo_component.q
+q[5] <= dcfifo:dcfifo_component.q
+q[6] <= dcfifo:dcfifo_component.q
+q[7] <= dcfifo:dcfifo_component.q
+q[8] <= dcfifo:dcfifo_component.q
+q[9] <= dcfifo:dcfifo_component.q
+q[10] <= dcfifo:dcfifo_component.q
+q[11] <= dcfifo:dcfifo_component.q
+q[12] <= dcfifo:dcfifo_component.q
+q[13] <= dcfifo:dcfifo_component.q
+q[14] <= dcfifo:dcfifo_component.q
+q[15] <= dcfifo:dcfifo_component.q
+rdempty <= dcfifo:dcfifo_component.rdempty
+rdusedw[0] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[1] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[2] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[3] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[4] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[5] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[6] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[7] <= dcfifo:dcfifo_component.rdusedw
+rdusedw[8] <= dcfifo:dcfifo_component.rdusedw
+wrfull <= dcfifo:dcfifo_component.wrfull
+wrusedw[0] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[1] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[2] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[3] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[4] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[5] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[6] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[7] <= dcfifo:dcfifo_component.wrusedw
+wrusedw[8] <= dcfifo:dcfifo_component.wrusedw
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+data[0] => dcfifo_v5o1:auto_generated.data[0]
+data[1] => dcfifo_v5o1:auto_generated.data[1]
+data[2] => dcfifo_v5o1:auto_generated.data[2]
+data[3] => dcfifo_v5o1:auto_generated.data[3]
+data[4] => dcfifo_v5o1:auto_generated.data[4]
+data[5] => dcfifo_v5o1:auto_generated.data[5]
+data[6] => dcfifo_v5o1:auto_generated.data[6]
+data[7] => dcfifo_v5o1:auto_generated.data[7]
+data[8] => dcfifo_v5o1:auto_generated.data[8]
+data[9] => dcfifo_v5o1:auto_generated.data[9]
+data[10] => dcfifo_v5o1:auto_generated.data[10]
+data[11] => dcfifo_v5o1:auto_generated.data[11]
+data[12] => dcfifo_v5o1:auto_generated.data[12]
+data[13] => dcfifo_v5o1:auto_generated.data[13]
+data[14] => dcfifo_v5o1:auto_generated.data[14]
+data[15] => dcfifo_v5o1:auto_generated.data[15]
+q[0] <= dcfifo_v5o1:auto_generated.q[0]
+q[1] <= dcfifo_v5o1:auto_generated.q[1]
+q[2] <= dcfifo_v5o1:auto_generated.q[2]
+q[3] <= dcfifo_v5o1:auto_generated.q[3]
+q[4] <= dcfifo_v5o1:auto_generated.q[4]
+q[5] <= dcfifo_v5o1:auto_generated.q[5]
+q[6] <= dcfifo_v5o1:auto_generated.q[6]
+q[7] <= dcfifo_v5o1:auto_generated.q[7]
+q[8] <= dcfifo_v5o1:auto_generated.q[8]
+q[9] <= dcfifo_v5o1:auto_generated.q[9]
+q[10] <= dcfifo_v5o1:auto_generated.q[10]
+q[11] <= dcfifo_v5o1:auto_generated.q[11]
+q[12] <= dcfifo_v5o1:auto_generated.q[12]
+q[13] <= dcfifo_v5o1:auto_generated.q[13]
+q[14] <= dcfifo_v5o1:auto_generated.q[14]
+q[15] <= dcfifo_v5o1:auto_generated.q[15]
+rdclk => dcfifo_v5o1:auto_generated.rdclk
+rdreq => dcfifo_v5o1:auto_generated.rdreq
+wrclk => dcfifo_v5o1:auto_generated.wrclk
+wrreq => dcfifo_v5o1:auto_generated.wrreq
+aclr => dcfifo_v5o1:auto_generated.aclr
+rdempty <= dcfifo_v5o1:auto_generated.rdempty
+rdfull <= <UNC>
+wrempty <= <GND>
+wrfull <= dcfifo_v5o1:auto_generated.wrfull
+rdusedw[0] <= dcfifo_v5o1:auto_generated.rdusedw[0]
+rdusedw[1] <= dcfifo_v5o1:auto_generated.rdusedw[1]
+rdusedw[2] <= dcfifo_v5o1:auto_generated.rdusedw[2]
+rdusedw[3] <= dcfifo_v5o1:auto_generated.rdusedw[3]
+rdusedw[4] <= dcfifo_v5o1:auto_generated.rdusedw[4]
+rdusedw[5] <= dcfifo_v5o1:auto_generated.rdusedw[5]
+rdusedw[6] <= dcfifo_v5o1:auto_generated.rdusedw[6]
+rdusedw[7] <= dcfifo_v5o1:auto_generated.rdusedw[7]
+rdusedw[8] <= dcfifo_v5o1:auto_generated.rdusedw[8]
+wrusedw[0] <= dcfifo_v5o1:auto_generated.wrusedw[0]
+wrusedw[1] <= dcfifo_v5o1:auto_generated.wrusedw[1]
+wrusedw[2] <= dcfifo_v5o1:auto_generated.wrusedw[2]
+wrusedw[3] <= dcfifo_v5o1:auto_generated.wrusedw[3]
+wrusedw[4] <= dcfifo_v5o1:auto_generated.wrusedw[4]
+wrusedw[5] <= dcfifo_v5o1:auto_generated.wrusedw[5]
+wrusedw[6] <= dcfifo_v5o1:auto_generated.wrusedw[6]
+wrusedw[7] <= dcfifo_v5o1:auto_generated.wrusedw[7]
+wrusedw[8] <= dcfifo_v5o1:auto_generated.wrusedw[8]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+aclr => a_graycounter_s57:rdptr_g1p.aclr
+aclr => a_graycounter_ojc:wrptr_g1p.aclr
+aclr => altsyncram_de51:fifo_ram.aclr1
+aclr => delayed_wrptr_g[9].IN0
+aclr => rdptr_g[9].IN0
+aclr => wrptr_g[9].IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+aclr => _.IN0
+data[0] => altsyncram_de51:fifo_ram.data_a[0]
+data[1] => altsyncram_de51:fifo_ram.data_a[1]
+data[2] => altsyncram_de51:fifo_ram.data_a[2]
+data[3] => altsyncram_de51:fifo_ram.data_a[3]
+data[4] => altsyncram_de51:fifo_ram.data_a[4]
+data[5] => altsyncram_de51:fifo_ram.data_a[5]
+data[6] => altsyncram_de51:fifo_ram.data_a[6]
+data[7] => altsyncram_de51:fifo_ram.data_a[7]
+data[8] => altsyncram_de51:fifo_ram.data_a[8]
+data[9] => altsyncram_de51:fifo_ram.data_a[9]
+data[10] => altsyncram_de51:fifo_ram.data_a[10]
+data[11] => altsyncram_de51:fifo_ram.data_a[11]
+data[12] => altsyncram_de51:fifo_ram.data_a[12]
+data[13] => altsyncram_de51:fifo_ram.data_a[13]
+data[14] => altsyncram_de51:fifo_ram.data_a[14]
+data[15] => altsyncram_de51:fifo_ram.data_a[15]
+q[0] <= altsyncram_de51:fifo_ram.q_b[0]
+q[1] <= altsyncram_de51:fifo_ram.q_b[1]
+q[2] <= altsyncram_de51:fifo_ram.q_b[2]
+q[3] <= altsyncram_de51:fifo_ram.q_b[3]
+q[4] <= altsyncram_de51:fifo_ram.q_b[4]
+q[5] <= altsyncram_de51:fifo_ram.q_b[5]
+q[6] <= altsyncram_de51:fifo_ram.q_b[6]
+q[7] <= altsyncram_de51:fifo_ram.q_b[7]
+q[8] <= altsyncram_de51:fifo_ram.q_b[8]
+q[9] <= altsyncram_de51:fifo_ram.q_b[9]
+q[10] <= altsyncram_de51:fifo_ram.q_b[10]
+q[11] <= altsyncram_de51:fifo_ram.q_b[11]
+q[12] <= altsyncram_de51:fifo_ram.q_b[12]
+q[13] <= altsyncram_de51:fifo_ram.q_b[13]
+q[14] <= altsyncram_de51:fifo_ram.q_b[14]
+q[15] <= altsyncram_de51:fifo_ram.q_b[15]
+rdclk => a_graycounter_s57:rdptr_g1p.clock
+rdclk => altsyncram_de51:fifo_ram.clock1
+rdclk => dffpipe_oe9:rs_brp.clock
+rdclk => dffpipe_oe9:rs_bwp.clock
+rdclk => alt_synch_pipe_qld:rs_dgwp.clock
+rdclk => rdptr_g[9].CLK
+rdclk => rdptr_g[8].CLK
+rdclk => rdptr_g[7].CLK
+rdclk => rdptr_g[6].CLK
+rdclk => rdptr_g[5].CLK
+rdclk => rdptr_g[4].CLK
+rdclk => rdptr_g[3].CLK
+rdclk => rdptr_g[2].CLK
+rdclk => rdptr_g[1].CLK
+rdclk => rdptr_g[0].CLK
+rdempty <= int_rdempty.DB_MAX_OUTPUT_PORT_TYPE
+rdreq => valid_rdreq.IN0
+rdusedw[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+rdusedw[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE
+wrclk => a_graycounter_ojc:wrptr_g1p.clock
+wrclk => altsyncram_de51:fifo_ram.clock0
+wrclk => dffpipe_oe9:ws_brp.clock
+wrclk => dffpipe_oe9:ws_bwp.clock
+wrclk => alt_synch_pipe_rld:ws_dgrp.clock
+wrclk => delayed_wrptr_g[9].CLK
+wrclk => delayed_wrptr_g[8].CLK
+wrclk => delayed_wrptr_g[7].CLK
+wrclk => delayed_wrptr_g[6].CLK
+wrclk => delayed_wrptr_g[5].CLK
+wrclk => delayed_wrptr_g[4].CLK
+wrclk => delayed_wrptr_g[3].CLK
+wrclk => delayed_wrptr_g[2].CLK
+wrclk => delayed_wrptr_g[1].CLK
+wrclk => delayed_wrptr_g[0].CLK
+wrclk => wrptr_g[9].CLK
+wrclk => wrptr_g[8].CLK
+wrclk => wrptr_g[7].CLK
+wrclk => wrptr_g[6].CLK
+wrclk => wrptr_g[5].CLK
+wrclk => wrptr_g[4].CLK
+wrclk => wrptr_g[3].CLK
+wrclk => wrptr_g[2].CLK
+wrclk => wrptr_g[1].CLK
+wrclk => wrptr_g[0].CLK
+wrfull <= int_wrfull.DB_MAX_OUTPUT_PORT_TYPE
+wrreq => valid_wrreq.IN0
+wrusedw[0] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[1] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[2] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[3] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[4] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[5] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[6] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[7] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+wrusedw[8] <= op_2.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin
+bin[0] <= xor0.DB_MAX_OUTPUT_PORT_TYPE
+bin[1] <= xor1.DB_MAX_OUTPUT_PORT_TYPE
+bin[2] <= xor2.DB_MAX_OUTPUT_PORT_TYPE
+bin[3] <= xor3.DB_MAX_OUTPUT_PORT_TYPE
+bin[4] <= xor4.DB_MAX_OUTPUT_PORT_TYPE
+bin[5] <= xor5.DB_MAX_OUTPUT_PORT_TYPE
+bin[6] <= xor6.DB_MAX_OUTPUT_PORT_TYPE
+bin[7] <= xor7.DB_MAX_OUTPUT_PORT_TYPE
+bin[8] <= xor8.DB_MAX_OUTPUT_PORT_TYPE
+bin[9] <= gray[9].DB_MAX_OUTPUT_PORT_TYPE
+gray[0] => xor0.IN0
+gray[1] => xor1.IN0
+gray[2] => xor2.IN0
+gray[3] => xor3.IN0
+gray[4] => xor4.IN0
+gray[5] => xor5.IN0
+gray[6] => xor6.IN0
+gray[7] => xor7.IN0
+gray[8] => xor8.IN1
+gray[9] => bin[9].DATAIN
+gray[9] => xor8.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+aclr => counter5a1.IN0
+aclr => counter5a0.IN0
+aclr => parity6.IN0
+aclr => sub_parity7a[2].IN0
+aclr => sub_parity7a[1].IN0
+aclr => sub_parity7a[0].IN0
+clock => counter5a0.CLK
+clock => counter5a1.CLK
+clock => counter5a2.CLK
+clock => counter5a3.CLK
+clock => counter5a4.CLK
+clock => counter5a5.CLK
+clock => counter5a6.CLK
+clock => counter5a7.CLK
+clock => counter5a8.CLK
+clock => counter5a9.CLK
+clock => parity6.CLK
+clock => sub_parity7a[2].CLK
+clock => sub_parity7a[1].CLK
+clock => sub_parity7a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter5a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter5a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter5a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter5a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter5a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter5a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter5a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter5a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter5a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter5a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+aclr => counter8a1.IN0
+aclr => counter8a0.IN0
+aclr => parity9.IN0
+aclr => sub_parity10a[2].IN0
+aclr => sub_parity10a[1].IN0
+aclr => sub_parity10a[0].IN0
+clock => counter8a0.CLK
+clock => counter8a1.CLK
+clock => counter8a2.CLK
+clock => counter8a3.CLK
+clock => counter8a4.CLK
+clock => counter8a5.CLK
+clock => counter8a6.CLK
+clock => counter8a7.CLK
+clock => counter8a8.CLK
+clock => counter8a9.CLK
+clock => parity9.CLK
+clock => sub_parity10a[2].CLK
+clock => sub_parity10a[1].CLK
+clock => sub_parity10a[0].CLK
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => _.IN0
+cnt_en => cntr_cout[0].IN0
+cnt_en => parity_cout.IN1
+q[0] <= counter8a0.DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter8a1.DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter8a2.DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter8a3.DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter8a4.DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter8a5.DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter8a6.DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter8a7.DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter8a8.DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter8a9.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+aclr1 => ram_block11a0.CLR1
+aclr1 => ram_block11a1.CLR1
+aclr1 => ram_block11a2.CLR1
+aclr1 => ram_block11a3.CLR1
+aclr1 => ram_block11a4.CLR1
+aclr1 => ram_block11a5.CLR1
+aclr1 => ram_block11a6.CLR1
+aclr1 => ram_block11a7.CLR1
+aclr1 => ram_block11a8.CLR1
+aclr1 => ram_block11a9.CLR1
+aclr1 => ram_block11a10.CLR1
+aclr1 => ram_block11a11.CLR1
+aclr1 => ram_block11a12.CLR1
+aclr1 => ram_block11a13.CLR1
+aclr1 => ram_block11a14.CLR1
+aclr1 => ram_block11a15.CLR1
+address_a[0] => ram_block11a0.PORTAADDR
+address_a[0] => ram_block11a1.PORTAADDR
+address_a[0] => ram_block11a2.PORTAADDR
+address_a[0] => ram_block11a3.PORTAADDR
+address_a[0] => ram_block11a4.PORTAADDR
+address_a[0] => ram_block11a5.PORTAADDR
+address_a[0] => ram_block11a6.PORTAADDR
+address_a[0] => ram_block11a7.PORTAADDR
+address_a[0] => ram_block11a8.PORTAADDR
+address_a[0] => ram_block11a9.PORTAADDR
+address_a[0] => ram_block11a10.PORTAADDR
+address_a[0] => ram_block11a11.PORTAADDR
+address_a[0] => ram_block11a12.PORTAADDR
+address_a[0] => ram_block11a13.PORTAADDR
+address_a[0] => ram_block11a14.PORTAADDR
+address_a[0] => ram_block11a15.PORTAADDR
+address_a[1] => ram_block11a0.PORTAADDR1
+address_a[1] => ram_block11a1.PORTAADDR1
+address_a[1] => ram_block11a2.PORTAADDR1
+address_a[1] => ram_block11a3.PORTAADDR1
+address_a[1] => ram_block11a4.PORTAADDR1
+address_a[1] => ram_block11a5.PORTAADDR1
+address_a[1] => ram_block11a6.PORTAADDR1
+address_a[1] => ram_block11a7.PORTAADDR1
+address_a[1] => ram_block11a8.PORTAADDR1
+address_a[1] => ram_block11a9.PORTAADDR1
+address_a[1] => ram_block11a10.PORTAADDR1
+address_a[1] => ram_block11a11.PORTAADDR1
+address_a[1] => ram_block11a12.PORTAADDR1
+address_a[1] => ram_block11a13.PORTAADDR1
+address_a[1] => ram_block11a14.PORTAADDR1
+address_a[1] => ram_block11a15.PORTAADDR1
+address_a[2] => ram_block11a0.PORTAADDR2
+address_a[2] => ram_block11a1.PORTAADDR2
+address_a[2] => ram_block11a2.PORTAADDR2
+address_a[2] => ram_block11a3.PORTAADDR2
+address_a[2] => ram_block11a4.PORTAADDR2
+address_a[2] => ram_block11a5.PORTAADDR2
+address_a[2] => ram_block11a6.PORTAADDR2
+address_a[2] => ram_block11a7.PORTAADDR2
+address_a[2] => ram_block11a8.PORTAADDR2
+address_a[2] => ram_block11a9.PORTAADDR2
+address_a[2] => ram_block11a10.PORTAADDR2
+address_a[2] => ram_block11a11.PORTAADDR2
+address_a[2] => ram_block11a12.PORTAADDR2
+address_a[2] => ram_block11a13.PORTAADDR2
+address_a[2] => ram_block11a14.PORTAADDR2
+address_a[2] => ram_block11a15.PORTAADDR2
+address_a[3] => ram_block11a0.PORTAADDR3
+address_a[3] => ram_block11a1.PORTAADDR3
+address_a[3] => ram_block11a2.PORTAADDR3
+address_a[3] => ram_block11a3.PORTAADDR3
+address_a[3] => ram_block11a4.PORTAADDR3
+address_a[3] => ram_block11a5.PORTAADDR3
+address_a[3] => ram_block11a6.PORTAADDR3
+address_a[3] => ram_block11a7.PORTAADDR3
+address_a[3] => ram_block11a8.PORTAADDR3
+address_a[3] => ram_block11a9.PORTAADDR3
+address_a[3] => ram_block11a10.PORTAADDR3
+address_a[3] => ram_block11a11.PORTAADDR3
+address_a[3] => ram_block11a12.PORTAADDR3
+address_a[3] => ram_block11a13.PORTAADDR3
+address_a[3] => ram_block11a14.PORTAADDR3
+address_a[3] => ram_block11a15.PORTAADDR3
+address_a[4] => ram_block11a0.PORTAADDR4
+address_a[4] => ram_block11a1.PORTAADDR4
+address_a[4] => ram_block11a2.PORTAADDR4
+address_a[4] => ram_block11a3.PORTAADDR4
+address_a[4] => ram_block11a4.PORTAADDR4
+address_a[4] => ram_block11a5.PORTAADDR4
+address_a[4] => ram_block11a6.PORTAADDR4
+address_a[4] => ram_block11a7.PORTAADDR4
+address_a[4] => ram_block11a8.PORTAADDR4
+address_a[4] => ram_block11a9.PORTAADDR4
+address_a[4] => ram_block11a10.PORTAADDR4
+address_a[4] => ram_block11a11.PORTAADDR4
+address_a[4] => ram_block11a12.PORTAADDR4
+address_a[4] => ram_block11a13.PORTAADDR4
+address_a[4] => ram_block11a14.PORTAADDR4
+address_a[4] => ram_block11a15.PORTAADDR4
+address_a[5] => ram_block11a0.PORTAADDR5
+address_a[5] => ram_block11a1.PORTAADDR5
+address_a[5] => ram_block11a2.PORTAADDR5
+address_a[5] => ram_block11a3.PORTAADDR5
+address_a[5] => ram_block11a4.PORTAADDR5
+address_a[5] => ram_block11a5.PORTAADDR5
+address_a[5] => ram_block11a6.PORTAADDR5
+address_a[5] => ram_block11a7.PORTAADDR5
+address_a[5] => ram_block11a8.PORTAADDR5
+address_a[5] => ram_block11a9.PORTAADDR5
+address_a[5] => ram_block11a10.PORTAADDR5
+address_a[5] => ram_block11a11.PORTAADDR5
+address_a[5] => ram_block11a12.PORTAADDR5
+address_a[5] => ram_block11a13.PORTAADDR5
+address_a[5] => ram_block11a14.PORTAADDR5
+address_a[5] => ram_block11a15.PORTAADDR5
+address_a[6] => ram_block11a0.PORTAADDR6
+address_a[6] => ram_block11a1.PORTAADDR6
+address_a[6] => ram_block11a2.PORTAADDR6
+address_a[6] => ram_block11a3.PORTAADDR6
+address_a[6] => ram_block11a4.PORTAADDR6
+address_a[6] => ram_block11a5.PORTAADDR6
+address_a[6] => ram_block11a6.PORTAADDR6
+address_a[6] => ram_block11a7.PORTAADDR6
+address_a[6] => ram_block11a8.PORTAADDR6
+address_a[6] => ram_block11a9.PORTAADDR6
+address_a[6] => ram_block11a10.PORTAADDR6
+address_a[6] => ram_block11a11.PORTAADDR6
+address_a[6] => ram_block11a12.PORTAADDR6
+address_a[6] => ram_block11a13.PORTAADDR6
+address_a[6] => ram_block11a14.PORTAADDR6
+address_a[6] => ram_block11a15.PORTAADDR6
+address_a[7] => ram_block11a0.PORTAADDR7
+address_a[7] => ram_block11a1.PORTAADDR7
+address_a[7] => ram_block11a2.PORTAADDR7
+address_a[7] => ram_block11a3.PORTAADDR7
+address_a[7] => ram_block11a4.PORTAADDR7
+address_a[7] => ram_block11a5.PORTAADDR7
+address_a[7] => ram_block11a6.PORTAADDR7
+address_a[7] => ram_block11a7.PORTAADDR7
+address_a[7] => ram_block11a8.PORTAADDR7
+address_a[7] => ram_block11a9.PORTAADDR7
+address_a[7] => ram_block11a10.PORTAADDR7
+address_a[7] => ram_block11a11.PORTAADDR7
+address_a[7] => ram_block11a12.PORTAADDR7
+address_a[7] => ram_block11a13.PORTAADDR7
+address_a[7] => ram_block11a14.PORTAADDR7
+address_a[7] => ram_block11a15.PORTAADDR7
+address_a[8] => ram_block11a0.PORTAADDR8
+address_a[8] => ram_block11a1.PORTAADDR8
+address_a[8] => ram_block11a2.PORTAADDR8
+address_a[8] => ram_block11a3.PORTAADDR8
+address_a[8] => ram_block11a4.PORTAADDR8
+address_a[8] => ram_block11a5.PORTAADDR8
+address_a[8] => ram_block11a6.PORTAADDR8
+address_a[8] => ram_block11a7.PORTAADDR8
+address_a[8] => ram_block11a8.PORTAADDR8
+address_a[8] => ram_block11a9.PORTAADDR8
+address_a[8] => ram_block11a10.PORTAADDR8
+address_a[8] => ram_block11a11.PORTAADDR8
+address_a[8] => ram_block11a12.PORTAADDR8
+address_a[8] => ram_block11a13.PORTAADDR8
+address_a[8] => ram_block11a14.PORTAADDR8
+address_a[8] => ram_block11a15.PORTAADDR8
+address_b[0] => ram_block11a0.PORTBADDR
+address_b[0] => ram_block11a1.PORTBADDR
+address_b[0] => ram_block11a2.PORTBADDR
+address_b[0] => ram_block11a3.PORTBADDR
+address_b[0] => ram_block11a4.PORTBADDR
+address_b[0] => ram_block11a5.PORTBADDR
+address_b[0] => ram_block11a6.PORTBADDR
+address_b[0] => ram_block11a7.PORTBADDR
+address_b[0] => ram_block11a8.PORTBADDR
+address_b[0] => ram_block11a9.PORTBADDR
+address_b[0] => ram_block11a10.PORTBADDR
+address_b[0] => ram_block11a11.PORTBADDR
+address_b[0] => ram_block11a12.PORTBADDR
+address_b[0] => ram_block11a13.PORTBADDR
+address_b[0] => ram_block11a14.PORTBADDR
+address_b[0] => ram_block11a15.PORTBADDR
+address_b[1] => ram_block11a0.PORTBADDR1
+address_b[1] => ram_block11a1.PORTBADDR1
+address_b[1] => ram_block11a2.PORTBADDR1
+address_b[1] => ram_block11a3.PORTBADDR1
+address_b[1] => ram_block11a4.PORTBADDR1
+address_b[1] => ram_block11a5.PORTBADDR1
+address_b[1] => ram_block11a6.PORTBADDR1
+address_b[1] => ram_block11a7.PORTBADDR1
+address_b[1] => ram_block11a8.PORTBADDR1
+address_b[1] => ram_block11a9.PORTBADDR1
+address_b[1] => ram_block11a10.PORTBADDR1
+address_b[1] => ram_block11a11.PORTBADDR1
+address_b[1] => ram_block11a12.PORTBADDR1
+address_b[1] => ram_block11a13.PORTBADDR1
+address_b[1] => ram_block11a14.PORTBADDR1
+address_b[1] => ram_block11a15.PORTBADDR1
+address_b[2] => ram_block11a0.PORTBADDR2
+address_b[2] => ram_block11a1.PORTBADDR2
+address_b[2] => ram_block11a2.PORTBADDR2
+address_b[2] => ram_block11a3.PORTBADDR2
+address_b[2] => ram_block11a4.PORTBADDR2
+address_b[2] => ram_block11a5.PORTBADDR2
+address_b[2] => ram_block11a6.PORTBADDR2
+address_b[2] => ram_block11a7.PORTBADDR2
+address_b[2] => ram_block11a8.PORTBADDR2
+address_b[2] => ram_block11a9.PORTBADDR2
+address_b[2] => ram_block11a10.PORTBADDR2
+address_b[2] => ram_block11a11.PORTBADDR2
+address_b[2] => ram_block11a12.PORTBADDR2
+address_b[2] => ram_block11a13.PORTBADDR2
+address_b[2] => ram_block11a14.PORTBADDR2
+address_b[2] => ram_block11a15.PORTBADDR2
+address_b[3] => ram_block11a0.PORTBADDR3
+address_b[3] => ram_block11a1.PORTBADDR3
+address_b[3] => ram_block11a2.PORTBADDR3
+address_b[3] => ram_block11a3.PORTBADDR3
+address_b[3] => ram_block11a4.PORTBADDR3
+address_b[3] => ram_block11a5.PORTBADDR3
+address_b[3] => ram_block11a6.PORTBADDR3
+address_b[3] => ram_block11a7.PORTBADDR3
+address_b[3] => ram_block11a8.PORTBADDR3
+address_b[3] => ram_block11a9.PORTBADDR3
+address_b[3] => ram_block11a10.PORTBADDR3
+address_b[3] => ram_block11a11.PORTBADDR3
+address_b[3] => ram_block11a12.PORTBADDR3
+address_b[3] => ram_block11a13.PORTBADDR3
+address_b[3] => ram_block11a14.PORTBADDR3
+address_b[3] => ram_block11a15.PORTBADDR3
+address_b[4] => ram_block11a0.PORTBADDR4
+address_b[4] => ram_block11a1.PORTBADDR4
+address_b[4] => ram_block11a2.PORTBADDR4
+address_b[4] => ram_block11a3.PORTBADDR4
+address_b[4] => ram_block11a4.PORTBADDR4
+address_b[4] => ram_block11a5.PORTBADDR4
+address_b[4] => ram_block11a6.PORTBADDR4
+address_b[4] => ram_block11a7.PORTBADDR4
+address_b[4] => ram_block11a8.PORTBADDR4
+address_b[4] => ram_block11a9.PORTBADDR4
+address_b[4] => ram_block11a10.PORTBADDR4
+address_b[4] => ram_block11a11.PORTBADDR4
+address_b[4] => ram_block11a12.PORTBADDR4
+address_b[4] => ram_block11a13.PORTBADDR4
+address_b[4] => ram_block11a14.PORTBADDR4
+address_b[4] => ram_block11a15.PORTBADDR4
+address_b[5] => ram_block11a0.PORTBADDR5
+address_b[5] => ram_block11a1.PORTBADDR5
+address_b[5] => ram_block11a2.PORTBADDR5
+address_b[5] => ram_block11a3.PORTBADDR5
+address_b[5] => ram_block11a4.PORTBADDR5
+address_b[5] => ram_block11a5.PORTBADDR5
+address_b[5] => ram_block11a6.PORTBADDR5
+address_b[5] => ram_block11a7.PORTBADDR5
+address_b[5] => ram_block11a8.PORTBADDR5
+address_b[5] => ram_block11a9.PORTBADDR5
+address_b[5] => ram_block11a10.PORTBADDR5
+address_b[5] => ram_block11a11.PORTBADDR5
+address_b[5] => ram_block11a12.PORTBADDR5
+address_b[5] => ram_block11a13.PORTBADDR5
+address_b[5] => ram_block11a14.PORTBADDR5
+address_b[5] => ram_block11a15.PORTBADDR5
+address_b[6] => ram_block11a0.PORTBADDR6
+address_b[6] => ram_block11a1.PORTBADDR6
+address_b[6] => ram_block11a2.PORTBADDR6
+address_b[6] => ram_block11a3.PORTBADDR6
+address_b[6] => ram_block11a4.PORTBADDR6
+address_b[6] => ram_block11a5.PORTBADDR6
+address_b[6] => ram_block11a6.PORTBADDR6
+address_b[6] => ram_block11a7.PORTBADDR6
+address_b[6] => ram_block11a8.PORTBADDR6
+address_b[6] => ram_block11a9.PORTBADDR6
+address_b[6] => ram_block11a10.PORTBADDR6
+address_b[6] => ram_block11a11.PORTBADDR6
+address_b[6] => ram_block11a12.PORTBADDR6
+address_b[6] => ram_block11a13.PORTBADDR6
+address_b[6] => ram_block11a14.PORTBADDR6
+address_b[6] => ram_block11a15.PORTBADDR6
+address_b[7] => ram_block11a0.PORTBADDR7
+address_b[7] => ram_block11a1.PORTBADDR7
+address_b[7] => ram_block11a2.PORTBADDR7
+address_b[7] => ram_block11a3.PORTBADDR7
+address_b[7] => ram_block11a4.PORTBADDR7
+address_b[7] => ram_block11a5.PORTBADDR7
+address_b[7] => ram_block11a6.PORTBADDR7
+address_b[7] => ram_block11a7.PORTBADDR7
+address_b[7] => ram_block11a8.PORTBADDR7
+address_b[7] => ram_block11a9.PORTBADDR7
+address_b[7] => ram_block11a10.PORTBADDR7
+address_b[7] => ram_block11a11.PORTBADDR7
+address_b[7] => ram_block11a12.PORTBADDR7
+address_b[7] => ram_block11a13.PORTBADDR7
+address_b[7] => ram_block11a14.PORTBADDR7
+address_b[7] => ram_block11a15.PORTBADDR7
+address_b[8] => ram_block11a0.PORTBADDR8
+address_b[8] => ram_block11a1.PORTBADDR8
+address_b[8] => ram_block11a2.PORTBADDR8
+address_b[8] => ram_block11a3.PORTBADDR8
+address_b[8] => ram_block11a4.PORTBADDR8
+address_b[8] => ram_block11a5.PORTBADDR8
+address_b[8] => ram_block11a6.PORTBADDR8
+address_b[8] => ram_block11a7.PORTBADDR8
+address_b[8] => ram_block11a8.PORTBADDR8
+address_b[8] => ram_block11a9.PORTBADDR8
+address_b[8] => ram_block11a10.PORTBADDR8
+address_b[8] => ram_block11a11.PORTBADDR8
+address_b[8] => ram_block11a12.PORTBADDR8
+address_b[8] => ram_block11a13.PORTBADDR8
+address_b[8] => ram_block11a14.PORTBADDR8
+address_b[8] => ram_block11a15.PORTBADDR8
+addressstall_b => ram_block11a0.PORTBADDRSTALL
+addressstall_b => ram_block11a1.PORTBADDRSTALL
+addressstall_b => ram_block11a2.PORTBADDRSTALL
+addressstall_b => ram_block11a3.PORTBADDRSTALL
+addressstall_b => ram_block11a4.PORTBADDRSTALL
+addressstall_b => ram_block11a5.PORTBADDRSTALL
+addressstall_b => ram_block11a6.PORTBADDRSTALL
+addressstall_b => ram_block11a7.PORTBADDRSTALL
+addressstall_b => ram_block11a8.PORTBADDRSTALL
+addressstall_b => ram_block11a9.PORTBADDRSTALL
+addressstall_b => ram_block11a10.PORTBADDRSTALL
+addressstall_b => ram_block11a11.PORTBADDRSTALL
+addressstall_b => ram_block11a12.PORTBADDRSTALL
+addressstall_b => ram_block11a13.PORTBADDRSTALL
+addressstall_b => ram_block11a14.PORTBADDRSTALL
+addressstall_b => ram_block11a15.PORTBADDRSTALL
+clock0 => ram_block11a0.CLK0
+clock0 => ram_block11a1.CLK0
+clock0 => ram_block11a2.CLK0
+clock0 => ram_block11a3.CLK0
+clock0 => ram_block11a4.CLK0
+clock0 => ram_block11a5.CLK0
+clock0 => ram_block11a6.CLK0
+clock0 => ram_block11a7.CLK0
+clock0 => ram_block11a8.CLK0
+clock0 => ram_block11a9.CLK0
+clock0 => ram_block11a10.CLK0
+clock0 => ram_block11a11.CLK0
+clock0 => ram_block11a12.CLK0
+clock0 => ram_block11a13.CLK0
+clock0 => ram_block11a14.CLK0
+clock0 => ram_block11a15.CLK0
+clock1 => ram_block11a0.CLK1
+clock1 => ram_block11a1.CLK1
+clock1 => ram_block11a2.CLK1
+clock1 => ram_block11a3.CLK1
+clock1 => ram_block11a4.CLK1
+clock1 => ram_block11a5.CLK1
+clock1 => ram_block11a6.CLK1
+clock1 => ram_block11a7.CLK1
+clock1 => ram_block11a8.CLK1
+clock1 => ram_block11a9.CLK1
+clock1 => ram_block11a10.CLK1
+clock1 => ram_block11a11.CLK1
+clock1 => ram_block11a12.CLK1
+clock1 => ram_block11a13.CLK1
+clock1 => ram_block11a14.CLK1
+clock1 => ram_block11a15.CLK1
+clocken1 => ram_block11a0.ENA1
+clocken1 => ram_block11a1.ENA1
+clocken1 => ram_block11a2.ENA1
+clocken1 => ram_block11a3.ENA1
+clocken1 => ram_block11a4.ENA1
+clocken1 => ram_block11a5.ENA1
+clocken1 => ram_block11a6.ENA1
+clocken1 => ram_block11a7.ENA1
+clocken1 => ram_block11a8.ENA1
+clocken1 => ram_block11a9.ENA1
+clocken1 => ram_block11a10.ENA1
+clocken1 => ram_block11a11.ENA1
+clocken1 => ram_block11a12.ENA1
+clocken1 => ram_block11a13.ENA1
+clocken1 => ram_block11a14.ENA1
+clocken1 => ram_block11a15.ENA1
+data_a[0] => ram_block11a0.PORTADATAIN
+data_a[1] => ram_block11a1.PORTADATAIN
+data_a[2] => ram_block11a2.PORTADATAIN
+data_a[3] => ram_block11a3.PORTADATAIN
+data_a[4] => ram_block11a4.PORTADATAIN
+data_a[5] => ram_block11a5.PORTADATAIN
+data_a[6] => ram_block11a6.PORTADATAIN
+data_a[7] => ram_block11a7.PORTADATAIN
+data_a[8] => ram_block11a8.PORTADATAIN
+data_a[9] => ram_block11a9.PORTADATAIN
+data_a[10] => ram_block11a10.PORTADATAIN
+data_a[11] => ram_block11a11.PORTADATAIN
+data_a[12] => ram_block11a12.PORTADATAIN
+data_a[13] => ram_block11a13.PORTADATAIN
+data_a[14] => ram_block11a14.PORTADATAIN
+data_a[15] => ram_block11a15.PORTADATAIN
+q_b[0] <= ram_block11a0.PORTBDATAOUT
+q_b[1] <= ram_block11a1.PORTBDATAOUT
+q_b[2] <= ram_block11a2.PORTBDATAOUT
+q_b[3] <= ram_block11a3.PORTBDATAOUT
+q_b[4] <= ram_block11a4.PORTBDATAOUT
+q_b[5] <= ram_block11a5.PORTBDATAOUT
+q_b[6] <= ram_block11a6.PORTBDATAOUT
+q_b[7] <= ram_block11a7.PORTBDATAOUT
+q_b[8] <= ram_block11a8.PORTBDATAOUT
+q_b[9] <= ram_block11a9.PORTBDATAOUT
+q_b[10] <= ram_block11a10.PORTBDATAOUT
+q_b[11] <= ram_block11a11.PORTBDATAOUT
+q_b[12] <= ram_block11a12.PORTBDATAOUT
+q_b[13] <= ram_block11a13.PORTBDATAOUT
+q_b[14] <= ram_block11a14.PORTBDATAOUT
+q_b[15] <= ram_block11a15.PORTBDATAOUT
+wren_a => ram_block11a0.PORTAWE
+wren_a => ram_block11a0.ENA0
+wren_a => ram_block11a1.PORTAWE
+wren_a => ram_block11a1.ENA0
+wren_a => ram_block11a2.PORTAWE
+wren_a => ram_block11a2.ENA0
+wren_a => ram_block11a3.PORTAWE
+wren_a => ram_block11a3.ENA0
+wren_a => ram_block11a4.PORTAWE
+wren_a => ram_block11a4.ENA0
+wren_a => ram_block11a5.PORTAWE
+wren_a => ram_block11a5.ENA0
+wren_a => ram_block11a6.PORTAWE
+wren_a => ram_block11a6.ENA0
+wren_a => ram_block11a7.PORTAWE
+wren_a => ram_block11a7.ENA0
+wren_a => ram_block11a8.PORTAWE
+wren_a => ram_block11a8.ENA0
+wren_a => ram_block11a9.PORTAWE
+wren_a => ram_block11a9.ENA0
+wren_a => ram_block11a10.PORTAWE
+wren_a => ram_block11a10.ENA0
+wren_a => ram_block11a11.PORTAWE
+wren_a => ram_block11a11.ENA0
+wren_a => ram_block11a12.PORTAWE
+wren_a => ram_block11a12.ENA0
+wren_a => ram_block11a13.PORTAWE
+wren_a => ram_block11a13.ENA0
+wren_a => ram_block11a14.PORTAWE
+wren_a => ram_block11a14.ENA0
+wren_a => ram_block11a15.PORTAWE
+wren_a => ram_block11a15.ENA0
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+clock => dffpipe_pe9:dffpipe13.clock
+clrn => dffpipe_pe9:dffpipe13.clrn
+d[0] => dffpipe_pe9:dffpipe13.d[0]
+d[1] => dffpipe_pe9:dffpipe13.d[1]
+d[2] => dffpipe_pe9:dffpipe13.d[2]
+d[3] => dffpipe_pe9:dffpipe13.d[3]
+d[4] => dffpipe_pe9:dffpipe13.d[4]
+d[5] => dffpipe_pe9:dffpipe13.d[5]
+d[6] => dffpipe_pe9:dffpipe13.d[6]
+d[7] => dffpipe_pe9:dffpipe13.d[7]
+d[8] => dffpipe_pe9:dffpipe13.d[8]
+d[9] => dffpipe_pe9:dffpipe13.d[9]
+q[0] <= dffpipe_pe9:dffpipe13.q[0]
+q[1] <= dffpipe_pe9:dffpipe13.q[1]
+q[2] <= dffpipe_pe9:dffpipe13.q[2]
+q[3] <= dffpipe_pe9:dffpipe13.q[3]
+q[4] <= dffpipe_pe9:dffpipe13.q[4]
+q[5] <= dffpipe_pe9:dffpipe13.q[5]
+q[6] <= dffpipe_pe9:dffpipe13.q[6]
+q[7] <= dffpipe_pe9:dffpipe13.q[7]
+q[8] <= dffpipe_pe9:dffpipe13.q[8]
+q[9] <= dffpipe_pe9:dffpipe13.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+clock => dffe14a[9].CLK
+clock => dffe14a[8].CLK
+clock => dffe14a[7].CLK
+clock => dffe14a[6].CLK
+clock => dffe14a[5].CLK
+clock => dffe14a[4].CLK
+clock => dffe14a[3].CLK
+clock => dffe14a[2].CLK
+clock => dffe14a[1].CLK
+clock => dffe14a[0].CLK
+clock => dffe15a[9].CLK
+clock => dffe15a[8].CLK
+clock => dffe15a[7].CLK
+clock => dffe15a[6].CLK
+clock => dffe15a[5].CLK
+clock => dffe15a[4].CLK
+clock => dffe15a[3].CLK
+clock => dffe15a[2].CLK
+clock => dffe15a[1].CLK
+clock => dffe15a[0].CLK
+clrn => dffe14a[9].ACLR
+clrn => dffe14a[8].ACLR
+clrn => dffe14a[7].ACLR
+clrn => dffe14a[6].ACLR
+clrn => dffe14a[5].ACLR
+clrn => dffe14a[4].ACLR
+clrn => dffe14a[3].ACLR
+clrn => dffe14a[2].ACLR
+clrn => dffe14a[1].ACLR
+clrn => dffe14a[0].ACLR
+clrn => dffe15a[9].ACLR
+clrn => dffe15a[8].ACLR
+clrn => dffe15a[7].ACLR
+clrn => dffe15a[6].ACLR
+clrn => dffe15a[5].ACLR
+clrn => dffe15a[4].ACLR
+clrn => dffe15a[3].ACLR
+clrn => dffe15a[2].ACLR
+clrn => dffe15a[1].ACLR
+clrn => dffe15a[0].ACLR
+d[0] => dffe14a[0].IN0
+d[1] => dffe14a[1].IN0
+d[2] => dffe14a[2].IN0
+d[3] => dffe14a[3].IN0
+d[4] => dffe14a[4].IN0
+d[5] => dffe14a[5].IN0
+d[6] => dffe14a[6].IN0
+d[7] => dffe14a[7].IN0
+d[8] => dffe14a[8].IN0
+d[9] => dffe14a[9].IN0
+q[0] <= dffe15a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe15a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe15a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe15a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe15a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe15a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe15a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe15a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe15a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe15a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+clock => dffe12a[9].CLK
+clock => dffe12a[8].CLK
+clock => dffe12a[7].CLK
+clock => dffe12a[6].CLK
+clock => dffe12a[5].CLK
+clock => dffe12a[4].CLK
+clock => dffe12a[3].CLK
+clock => dffe12a[2].CLK
+clock => dffe12a[1].CLK
+clock => dffe12a[0].CLK
+clrn => dffe12a[9].ACLR
+clrn => dffe12a[8].ACLR
+clrn => dffe12a[7].ACLR
+clrn => dffe12a[6].ACLR
+clrn => dffe12a[5].ACLR
+clrn => dffe12a[4].ACLR
+clrn => dffe12a[3].ACLR
+clrn => dffe12a[2].ACLR
+clrn => dffe12a[1].ACLR
+clrn => dffe12a[0].ACLR
+d[0] => dffe12a[0].IN0
+d[1] => dffe12a[1].IN0
+d[2] => dffe12a[2].IN0
+d[3] => dffe12a[3].IN0
+d[4] => dffe12a[4].IN0
+d[5] => dffe12a[5].IN0
+d[6] => dffe12a[6].IN0
+d[7] => dffe12a[7].IN0
+d[8] => dffe12a[8].IN0
+d[9] => dffe12a[9].IN0
+q[0] <= dffe12a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe12a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe12a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe12a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe12a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe12a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe12a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe12a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe12a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe12a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+clock => dffpipe_qe9:dffpipe16.clock
+clrn => dffpipe_qe9:dffpipe16.clrn
+d[0] => dffpipe_qe9:dffpipe16.d[0]
+d[1] => dffpipe_qe9:dffpipe16.d[1]
+d[2] => dffpipe_qe9:dffpipe16.d[2]
+d[3] => dffpipe_qe9:dffpipe16.d[3]
+d[4] => dffpipe_qe9:dffpipe16.d[4]
+d[5] => dffpipe_qe9:dffpipe16.d[5]
+d[6] => dffpipe_qe9:dffpipe16.d[6]
+d[7] => dffpipe_qe9:dffpipe16.d[7]
+d[8] => dffpipe_qe9:dffpipe16.d[8]
+d[9] => dffpipe_qe9:dffpipe16.d[9]
+q[0] <= dffpipe_qe9:dffpipe16.q[0]
+q[1] <= dffpipe_qe9:dffpipe16.q[1]
+q[2] <= dffpipe_qe9:dffpipe16.q[2]
+q[3] <= dffpipe_qe9:dffpipe16.q[3]
+q[4] <= dffpipe_qe9:dffpipe16.q[4]
+q[5] <= dffpipe_qe9:dffpipe16.q[5]
+q[6] <= dffpipe_qe9:dffpipe16.q[6]
+q[7] <= dffpipe_qe9:dffpipe16.q[7]
+q[8] <= dffpipe_qe9:dffpipe16.q[8]
+q[9] <= dffpipe_qe9:dffpipe16.q[9]
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+clock => dffe17a[9].CLK
+clock => dffe17a[8].CLK
+clock => dffe17a[7].CLK
+clock => dffe17a[6].CLK
+clock => dffe17a[5].CLK
+clock => dffe17a[4].CLK
+clock => dffe17a[3].CLK
+clock => dffe17a[2].CLK
+clock => dffe17a[1].CLK
+clock => dffe17a[0].CLK
+clock => dffe18a[9].CLK
+clock => dffe18a[8].CLK
+clock => dffe18a[7].CLK
+clock => dffe18a[6].CLK
+clock => dffe18a[5].CLK
+clock => dffe18a[4].CLK
+clock => dffe18a[3].CLK
+clock => dffe18a[2].CLK
+clock => dffe18a[1].CLK
+clock => dffe18a[0].CLK
+clrn => dffe17a[9].ACLR
+clrn => dffe17a[8].ACLR
+clrn => dffe17a[7].ACLR
+clrn => dffe17a[6].ACLR
+clrn => dffe17a[5].ACLR
+clrn => dffe17a[4].ACLR
+clrn => dffe17a[3].ACLR
+clrn => dffe17a[2].ACLR
+clrn => dffe17a[1].ACLR
+clrn => dffe17a[0].ACLR
+clrn => dffe18a[9].ACLR
+clrn => dffe18a[8].ACLR
+clrn => dffe18a[7].ACLR
+clrn => dffe18a[6].ACLR
+clrn => dffe18a[5].ACLR
+clrn => dffe18a[4].ACLR
+clrn => dffe18a[3].ACLR
+clrn => dffe18a[2].ACLR
+clrn => dffe18a[1].ACLR
+clrn => dffe18a[0].ACLR
+d[0] => dffe17a[0].IN0
+d[1] => dffe17a[1].IN0
+d[2] => dffe17a[2].IN0
+d[3] => dffe17a[3].IN0
+d[4] => dffe17a[4].IN0
+d[5] => dffe17a[5].IN0
+d[6] => dffe17a[6].IN0
+d[7] => dffe17a[7].IN0
+d[8] => dffe17a[8].IN0
+d[9] => dffe17a[9].IN0
+q[0] <= dffe18a[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= dffe18a[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= dffe18a[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= dffe18a[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= dffe18a[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= dffe18a[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= dffe18a[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= dffe18a[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= dffe18a[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= dffe18a[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8
+iCLK => mI2C_CLK_DIV[0].CLK
+iCLK => mI2C_CLK_DIV[1].CLK
+iCLK => mI2C_CLK_DIV[2].CLK
+iCLK => mI2C_CLK_DIV[3].CLK
+iCLK => mI2C_CLK_DIV[4].CLK
+iCLK => mI2C_CLK_DIV[5].CLK
+iCLK => mI2C_CLK_DIV[6].CLK
+iCLK => mI2C_CLK_DIV[7].CLK
+iCLK => mI2C_CLK_DIV[8].CLK
+iCLK => mI2C_CLK_DIV[9].CLK
+iCLK => mI2C_CLK_DIV[10].CLK
+iCLK => mI2C_CLK_DIV[11].CLK
+iCLK => mI2C_CLK_DIV[12].CLK
+iCLK => mI2C_CLK_DIV[13].CLK
+iCLK => mI2C_CLK_DIV[14].CLK
+iCLK => mI2C_CLK_DIV[15].CLK
+iCLK => mI2C_CTRL_CLK.CLK
+iCLK => combo_cnt[0].CLK
+iCLK => combo_cnt[1].CLK
+iCLK => combo_cnt[2].CLK
+iCLK => combo_cnt[3].CLK
+iCLK => combo_cnt[4].CLK
+iCLK => combo_cnt[5].CLK
+iCLK => combo_cnt[6].CLK
+iCLK => combo_cnt[7].CLK
+iCLK => combo_cnt[8].CLK
+iCLK => combo_cnt[9].CLK
+iCLK => combo_cnt[10].CLK
+iCLK => combo_cnt[11].CLK
+iCLK => combo_cnt[12].CLK
+iCLK => combo_cnt[13].CLK
+iCLK => combo_cnt[14].CLK
+iCLK => combo_cnt[15].CLK
+iCLK => combo_cnt[16].CLK
+iCLK => combo_cnt[17].CLK
+iCLK => combo_cnt[18].CLK
+iCLK => combo_cnt[19].CLK
+iCLK => combo_cnt[20].CLK
+iCLK => combo_cnt[21].CLK
+iCLK => combo_cnt[22].CLK
+iCLK => combo_cnt[23].CLK
+iCLK => combo_cnt[24].CLK
+iCLK => sensor_exposure[0].CLK
+iCLK => sensor_exposure[1].CLK
+iCLK => sensor_exposure[2].CLK
+iCLK => sensor_exposure[3].CLK
+iCLK => sensor_exposure[4].CLK
+iCLK => sensor_exposure[5].CLK
+iCLK => sensor_exposure[6].CLK
+iCLK => sensor_exposure[7].CLK
+iCLK => sensor_exposure[8].CLK
+iCLK => sensor_exposure[9].CLK
+iCLK => sensor_exposure[10].CLK
+iCLK => sensor_exposure[11].CLK
+iCLK => sensor_exposure[12].CLK
+iCLK => sensor_exposure[13].CLK
+iCLK => sensor_exposure[14].CLK
+iCLK => sensor_exposure[15].CLK
+iCLK => iexposure_adj_delay[0].CLK
+iCLK => iexposure_adj_delay[1].CLK
+iCLK => iexposure_adj_delay[2].CLK
+iCLK => iexposure_adj_delay[3].CLK
+iRST_N => i2c_reset.IN1
+iRST_N => combo_cnt[0].ACLR
+iRST_N => combo_cnt[1].ACLR
+iRST_N => combo_cnt[2].ACLR
+iRST_N => combo_cnt[3].ACLR
+iRST_N => combo_cnt[4].ACLR
+iRST_N => combo_cnt[5].ACLR
+iRST_N => combo_cnt[6].ACLR
+iRST_N => combo_cnt[7].ACLR
+iRST_N => combo_cnt[8].ACLR
+iRST_N => combo_cnt[9].ACLR
+iRST_N => combo_cnt[10].ACLR
+iRST_N => combo_cnt[11].ACLR
+iRST_N => combo_cnt[12].ACLR
+iRST_N => combo_cnt[13].ACLR
+iRST_N => combo_cnt[14].ACLR
+iRST_N => combo_cnt[15].ACLR
+iRST_N => combo_cnt[16].ACLR
+iRST_N => combo_cnt[17].ACLR
+iRST_N => combo_cnt[18].ACLR
+iRST_N => combo_cnt[19].ACLR
+iRST_N => combo_cnt[20].ACLR
+iRST_N => combo_cnt[21].ACLR
+iRST_N => combo_cnt[22].ACLR
+iRST_N => combo_cnt[23].ACLR
+iRST_N => combo_cnt[24].ACLR
+iRST_N => sensor_exposure[0].ACLR
+iRST_N => sensor_exposure[1].ACLR
+iRST_N => sensor_exposure[2].ACLR
+iRST_N => sensor_exposure[3].ACLR
+iRST_N => sensor_exposure[4].ACLR
+iRST_N => sensor_exposure[5].ACLR
+iRST_N => sensor_exposure[6].PRESET
+iRST_N => sensor_exposure[7].PRESET
+iRST_N => sensor_exposure[8].PRESET
+iRST_N => sensor_exposure[9].PRESET
+iRST_N => sensor_exposure[10].PRESET
+iRST_N => sensor_exposure[11].ACLR
+iRST_N => sensor_exposure[12].ACLR
+iRST_N => sensor_exposure[13].ACLR
+iRST_N => sensor_exposure[14].ACLR
+iRST_N => sensor_exposure[15].ACLR
+iRST_N => iexposure_adj_delay[0].ACLR
+iRST_N => iexposure_adj_delay[1].ACLR
+iRST_N => iexposure_adj_delay[2].ACLR
+iRST_N => iexposure_adj_delay[3].ACLR
+iUART_CTRL => ~NO_FANOUT~
+iZOOM_MODE_SW => Mux18.IN69
+iZOOM_MODE_SW => Mux19.IN66
+iZOOM_MODE_SW => Mux21.IN69
+iZOOM_MODE_SW => Mux22.IN69
+iZOOM_MODE_SW => Mux19.IN67
+iZOOM_MODE_SW => Mux13.IN68
+iZOOM_MODE_SW => Mux16.IN69
+iZOOM_MODE_SW => Mux17.IN69
+iZOOM_MODE_SW => Mux12.IN69
+iZOOM_MODE_SW => Mux13.IN69
+iZOOM_MODE_SW => Mux15.IN69
+iZOOM_MODE_SW => Mux19.IN68
+iZOOM_MODE_SW => Mux23.IN68
+iZOOM_MODE_SW => Mux19.IN69
+iZOOM_MODE_SW => Mux23.IN69
+iEXPOSURE_ADJ => iexposure_adj_delay[0].DATAIN
+iEXPOSURE_ADJ => Equal0.IN0
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+iEXPOSURE_DEC_p => sensor_exposure.OUTPUTSELECT
+I2C_SCLK <= I2C_Controller:u0.I2C_SCLK
+I2C_SDAT <> I2C_Controller:u0.I2C_SDAT
+
+
+|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0
+CLOCK => SD[0].CLK
+CLOCK => SD[1].CLK
+CLOCK => SD[2].CLK
+CLOCK => SD[3].CLK
+CLOCK => SD[4].CLK
+CLOCK => SD[5].CLK
+CLOCK => SD[6].CLK
+CLOCK => SD[7].CLK
+CLOCK => SD[8].CLK
+CLOCK => SD[9].CLK
+CLOCK => SD[10].CLK
+CLOCK => SD[11].CLK
+CLOCK => SD[12].CLK
+CLOCK => SD[13].CLK
+CLOCK => SD[14].CLK
+CLOCK => SD[15].CLK
+CLOCK => SD[16].CLK
+CLOCK => SD[17].CLK
+CLOCK => SD[18].CLK
+CLOCK => SD[19].CLK
+CLOCK => SD[20].CLK
+CLOCK => SD[21].CLK
+CLOCK => SD[22].CLK
+CLOCK => SD[23].CLK
+CLOCK => SD[24].CLK
+CLOCK => SD[25].CLK
+CLOCK => SD[26].CLK
+CLOCK => SD[27].CLK
+CLOCK => SD[28].CLK
+CLOCK => SD[29].CLK
+CLOCK => SD[30].CLK
+CLOCK => SD[31].CLK
+CLOCK => END~reg0.CLK
+CLOCK => ACK4.CLK
+CLOCK => ACK3.CLK
+CLOCK => ACK2.CLK
+CLOCK => ACK1.CLK
+CLOCK => SDO.CLK
+CLOCK => SCLK.CLK
+CLOCK => SD_COUNTER[0].CLK
+CLOCK => SD_COUNTER[1].CLK
+CLOCK => SD_COUNTER[2].CLK
+CLOCK => SD_COUNTER[3].CLK
+CLOCK => SD_COUNTER[4].CLK
+CLOCK => SD_COUNTER[5].CLK
+CLOCK => SD_COUNTER[6].CLK
+CLOCK => comb.DATAB
+I2C_SCLK <= comb.DB_MAX_OUTPUT_PORT_TYPE
+I2C_SDAT <> I2C_SDAT
+I2C_DATA[0] => SD.DATAB
+I2C_DATA[1] => SD.DATAB
+I2C_DATA[2] => SD.DATAB
+I2C_DATA[3] => SD.DATAB
+I2C_DATA[4] => SD.DATAB
+I2C_DATA[5] => SD.DATAB
+I2C_DATA[6] => SD.DATAB
+I2C_DATA[7] => SD.DATAB
+I2C_DATA[8] => SD.DATAB
+I2C_DATA[9] => SD.DATAB
+I2C_DATA[10] => SD.DATAB
+I2C_DATA[11] => SD.DATAB
+I2C_DATA[12] => SD.DATAB
+I2C_DATA[13] => SD.DATAB
+I2C_DATA[14] => SD.DATAB
+I2C_DATA[15] => SD.DATAB
+I2C_DATA[16] => SD.DATAB
+I2C_DATA[17] => SD.DATAB
+I2C_DATA[18] => SD.DATAB
+I2C_DATA[19] => SD.DATAB
+I2C_DATA[20] => SD.DATAB
+I2C_DATA[21] => SD.DATAB
+I2C_DATA[22] => SD.DATAB
+I2C_DATA[23] => SD.DATAB
+I2C_DATA[24] => SD.DATAB
+I2C_DATA[25] => SD.DATAB
+I2C_DATA[26] => SD.DATAB
+I2C_DATA[27] => SD.DATAB
+I2C_DATA[28] => SD.DATAB
+I2C_DATA[29] => SD.DATAB
+I2C_DATA[30] => SD.DATAB
+I2C_DATA[31] => SD.DATAB
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+GO => SD_COUNTER.OUTPUTSELECT
+END <= END~reg0.DB_MAX_OUTPUT_PORT_TYPE
+ACK <= comb.DB_MAX_OUTPUT_PORT_TYPE
+RESET => END~reg0.PRESET
+RESET => ACK4.ACLR
+RESET => ACK3.ACLR
+RESET => ACK2.ACLR
+RESET => ACK1.ACLR
+RESET => SDO.PRESET
+RESET => SCLK.PRESET
+RESET => SD_COUNTER[0].PRESET
+RESET => SD_COUNTER[1].PRESET
+RESET => SD_COUNTER[2].PRESET
+RESET => SD_COUNTER[3].PRESET
+RESET => SD_COUNTER[4].PRESET
+RESET => SD_COUNTER[5].PRESET
+RESET => SD_COUNTER[6].ACLR
+RESET => SD[0].ENA
+RESET => SD[31].ENA
+RESET => SD[30].ENA
+RESET => SD[29].ENA
+RESET => SD[28].ENA
+RESET => SD[27].ENA
+RESET => SD[26].ENA
+RESET => SD[25].ENA
+RESET => SD[24].ENA
+RESET => SD[23].ENA
+RESET => SD[22].ENA
+RESET => SD[21].ENA
+RESET => SD[20].ENA
+RESET => SD[19].ENA
+RESET => SD[18].ENA
+RESET => SD[17].ENA
+RESET => SD[16].ENA
+RESET => SD[15].ENA
+RESET => SD[14].ENA
+RESET => SD[13].ENA
+RESET => SD[12].ENA
+RESET => SD[11].ENA
+RESET => SD[10].ENA
+RESET => SD[9].ENA
+RESET => SD[8].ENA
+RESET => SD[7].ENA
+RESET => SD[6].ENA
+RESET => SD[5].ENA
+RESET => SD[4].ENA
+RESET => SD[3].ENA
+RESET => SD[2].ENA
+RESET => SD[1].ENA
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6
+iSTART => always2.IN1
+iRST_n => y_latch[0].ACLR
+iRST_n => y_latch[1].ACLR
+iRST_n => y_latch[2].ACLR
+iRST_n => y_latch[3].ACLR
+iRST_n => y_latch[4].ACLR
+iRST_n => y_latch[5].ACLR
+iRST_n => y_latch[6].ACLR
+iRST_n => y_latch[7].ACLR
+iRST_n => x_latch[0].ACLR
+iRST_n => x_latch[1].ACLR
+iRST_n => x_latch[2].ACLR
+iRST_n => x_latch[3].ACLR
+iRST_n => x_latch[4].ACLR
+iRST_n => x_latch[5].ACLR
+iRST_n => x_latch[6].ACLR
+iRST_n => x_latch[7].ACLR
+iRST_n => midlatch.ACLR
+iRST_n => riglatch.ACLR
+iRST_n => leflatch.ACLR
+iRST_n => cur_state~3.DATAIN
+iCLK_50 => clk_div[0].CLK
+iCLK_50 => clk_div[1].CLK
+iCLK_50 => clk_div[2].CLK
+iCLK_50 => clk_div[3].CLK
+iCLK_50 => clk_div[4].CLK
+iCLK_50 => clk_div[5].CLK
+iCLK_50 => clk_div[6].CLK
+iCLK_50 => clk_div[7].CLK
+iCLK_50 => clk_div[8].CLK
+PS2_CLK <> PS2_CLK
+PS2_DAT <> PS2_DAT
+oLEFBUT <= leflatch.DB_MAX_OUTPUT_PORT_TYPE
+oRIGBUT <= riglatch.DB_MAX_OUTPUT_PORT_TYPE
+oMIDBUT <= midlatch.DB_MAX_OUTPUT_PORT_TYPE
+oX[0] <= x_latch[0].DB_MAX_OUTPUT_PORT_TYPE
+oX[1] <= x_latch[1].DB_MAX_OUTPUT_PORT_TYPE
+oX[2] <= x_latch[2].DB_MAX_OUTPUT_PORT_TYPE
+oX[3] <= x_latch[3].DB_MAX_OUTPUT_PORT_TYPE
+oX[4] <= x_latch[4].DB_MAX_OUTPUT_PORT_TYPE
+oX[5] <= x_latch[5].DB_MAX_OUTPUT_PORT_TYPE
+oX[6] <= x_latch[6].DB_MAX_OUTPUT_PORT_TYPE
+oX[7] <= x_latch[7].DB_MAX_OUTPUT_PORT_TYPE
+oY[0] <= y_latch[0].DB_MAX_OUTPUT_PORT_TYPE
+oY[1] <= y_latch[1].DB_MAX_OUTPUT_PORT_TYPE
+oY[2] <= y_latch[2].DB_MAX_OUTPUT_PORT_TYPE
+oY[3] <= y_latch[3].DB_MAX_OUTPUT_PORT_TYPE
+oY[4] <= y_latch[4].DB_MAX_OUTPUT_PORT_TYPE
+oY[5] <= y_latch[5].DB_MAX_OUTPUT_PORT_TYPE
+oY[6] <= y_latch[6].DB_MAX_OUTPUT_PORT_TYPE
+oY[7] <= y_latch[7].DB_MAX_OUTPUT_PORT_TYPE
+oX_MOV1[0] <= SEG7_LUT:U1.oSEG
+oX_MOV1[1] <= SEG7_LUT:U1.oSEG
+oX_MOV1[2] <= SEG7_LUT:U1.oSEG
+oX_MOV1[3] <= SEG7_LUT:U1.oSEG
+oX_MOV1[4] <= SEG7_LUT:U1.oSEG
+oX_MOV1[5] <= SEG7_LUT:U1.oSEG
+oX_MOV1[6] <= SEG7_LUT:U1.oSEG
+oX_MOV2[0] <= SEG7_LUT:U2.oSEG
+oX_MOV2[1] <= SEG7_LUT:U2.oSEG
+oX_MOV2[2] <= SEG7_LUT:U2.oSEG
+oX_MOV2[3] <= SEG7_LUT:U2.oSEG
+oX_MOV2[4] <= SEG7_LUT:U2.oSEG
+oX_MOV2[5] <= SEG7_LUT:U2.oSEG
+oX_MOV2[6] <= SEG7_LUT:U2.oSEG
+oY_MOV1[0] <= SEG7_LUT:U3.oSEG
+oY_MOV1[1] <= SEG7_LUT:U3.oSEG
+oY_MOV1[2] <= SEG7_LUT:U3.oSEG
+oY_MOV1[3] <= SEG7_LUT:U3.oSEG
+oY_MOV1[4] <= SEG7_LUT:U3.oSEG
+oY_MOV1[5] <= SEG7_LUT:U3.oSEG
+oY_MOV1[6] <= SEG7_LUT:U3.oSEG
+oY_MOV2[0] <= SEG7_LUT:U4.oSEG
+oY_MOV2[1] <= SEG7_LUT:U4.oSEG
+oY_MOV2[2] <= SEG7_LUT:U4.oSEG
+oY_MOV2[3] <= SEG7_LUT:U4.oSEG
+oY_MOV2[4] <= SEG7_LUT:U4.oSEG
+oY_MOV2[5] <= SEG7_LUT:U4.oSEG
+oY_MOV2[6] <= SEG7_LUT:U4.oSEG
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4
+oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+iDIG[0] => Decoder0.IN3
+iDIG[1] => Decoder0.IN2
+iDIG[2] => Decoder0.IN1
+iDIG[3] => Decoder0.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10
+data0x[0] => LPM_MUX:LPM_MUX_component.DATA[0][0]
+data0x[1] => LPM_MUX:LPM_MUX_component.DATA[0][1]
+data0x[2] => LPM_MUX:LPM_MUX_component.DATA[0][2]
+data0x[3] => LPM_MUX:LPM_MUX_component.DATA[0][3]
+data0x[4] => LPM_MUX:LPM_MUX_component.DATA[0][4]
+data0x[5] => LPM_MUX:LPM_MUX_component.DATA[0][5]
+data0x[6] => LPM_MUX:LPM_MUX_component.DATA[0][6]
+data0x[7] => LPM_MUX:LPM_MUX_component.DATA[0][7]
+data0x[8] => LPM_MUX:LPM_MUX_component.DATA[0][8]
+data0x[9] => LPM_MUX:LPM_MUX_component.DATA[0][9]
+data0x[10] => LPM_MUX:LPM_MUX_component.DATA[0][10]
+data0x[11] => LPM_MUX:LPM_MUX_component.DATA[0][11]
+data0x[12] => LPM_MUX:LPM_MUX_component.DATA[0][12]
+data0x[13] => LPM_MUX:LPM_MUX_component.DATA[0][13]
+data0x[14] => LPM_MUX:LPM_MUX_component.DATA[0][14]
+data0x[15] => LPM_MUX:LPM_MUX_component.DATA[0][15]
+data0x[16] => LPM_MUX:LPM_MUX_component.DATA[0][16]
+data0x[17] => LPM_MUX:LPM_MUX_component.DATA[0][17]
+data0x[18] => LPM_MUX:LPM_MUX_component.DATA[0][18]
+data0x[19] => LPM_MUX:LPM_MUX_component.DATA[0][19]
+data0x[20] => LPM_MUX:LPM_MUX_component.DATA[0][20]
+data0x[21] => LPM_MUX:LPM_MUX_component.DATA[0][21]
+data0x[22] => LPM_MUX:LPM_MUX_component.DATA[0][22]
+data0x[23] => LPM_MUX:LPM_MUX_component.DATA[0][23]
+data0x[24] => LPM_MUX:LPM_MUX_component.DATA[0][24]
+data0x[25] => LPM_MUX:LPM_MUX_component.DATA[0][25]
+data0x[26] => LPM_MUX:LPM_MUX_component.DATA[0][26]
+data0x[27] => LPM_MUX:LPM_MUX_component.DATA[0][27]
+data0x[28] => LPM_MUX:LPM_MUX_component.DATA[0][28]
+data0x[29] => LPM_MUX:LPM_MUX_component.DATA[0][29]
+data1x[0] => LPM_MUX:LPM_MUX_component.DATA[1][0]
+data1x[1] => LPM_MUX:LPM_MUX_component.DATA[1][1]
+data1x[2] => LPM_MUX:LPM_MUX_component.DATA[1][2]
+data1x[3] => LPM_MUX:LPM_MUX_component.DATA[1][3]
+data1x[4] => LPM_MUX:LPM_MUX_component.DATA[1][4]
+data1x[5] => LPM_MUX:LPM_MUX_component.DATA[1][5]
+data1x[6] => LPM_MUX:LPM_MUX_component.DATA[1][6]
+data1x[7] => LPM_MUX:LPM_MUX_component.DATA[1][7]
+data1x[8] => LPM_MUX:LPM_MUX_component.DATA[1][8]
+data1x[9] => LPM_MUX:LPM_MUX_component.DATA[1][9]
+data1x[10] => LPM_MUX:LPM_MUX_component.DATA[1][10]
+data1x[11] => LPM_MUX:LPM_MUX_component.DATA[1][11]
+data1x[12] => LPM_MUX:LPM_MUX_component.DATA[1][12]
+data1x[13] => LPM_MUX:LPM_MUX_component.DATA[1][13]
+data1x[14] => LPM_MUX:LPM_MUX_component.DATA[1][14]
+data1x[15] => LPM_MUX:LPM_MUX_component.DATA[1][15]
+data1x[16] => LPM_MUX:LPM_MUX_component.DATA[1][16]
+data1x[17] => LPM_MUX:LPM_MUX_component.DATA[1][17]
+data1x[18] => LPM_MUX:LPM_MUX_component.DATA[1][18]
+data1x[19] => LPM_MUX:LPM_MUX_component.DATA[1][19]
+data1x[20] => LPM_MUX:LPM_MUX_component.DATA[1][20]
+data1x[21] => LPM_MUX:LPM_MUX_component.DATA[1][21]
+data1x[22] => LPM_MUX:LPM_MUX_component.DATA[1][22]
+data1x[23] => LPM_MUX:LPM_MUX_component.DATA[1][23]
+data1x[24] => LPM_MUX:LPM_MUX_component.DATA[1][24]
+data1x[25] => LPM_MUX:LPM_MUX_component.DATA[1][25]
+data1x[26] => LPM_MUX:LPM_MUX_component.DATA[1][26]
+data1x[27] => LPM_MUX:LPM_MUX_component.DATA[1][27]
+data1x[28] => LPM_MUX:LPM_MUX_component.DATA[1][28]
+data1x[29] => LPM_MUX:LPM_MUX_component.DATA[1][29]
+data2x[0] => LPM_MUX:LPM_MUX_component.DATA[2][0]
+data2x[1] => LPM_MUX:LPM_MUX_component.DATA[2][1]
+data2x[2] => LPM_MUX:LPM_MUX_component.DATA[2][2]
+data2x[3] => LPM_MUX:LPM_MUX_component.DATA[2][3]
+data2x[4] => LPM_MUX:LPM_MUX_component.DATA[2][4]
+data2x[5] => LPM_MUX:LPM_MUX_component.DATA[2][5]
+data2x[6] => LPM_MUX:LPM_MUX_component.DATA[2][6]
+data2x[7] => LPM_MUX:LPM_MUX_component.DATA[2][7]
+data2x[8] => LPM_MUX:LPM_MUX_component.DATA[2][8]
+data2x[9] => LPM_MUX:LPM_MUX_component.DATA[2][9]
+data2x[10] => LPM_MUX:LPM_MUX_component.DATA[2][10]
+data2x[11] => LPM_MUX:LPM_MUX_component.DATA[2][11]
+data2x[12] => LPM_MUX:LPM_MUX_component.DATA[2][12]
+data2x[13] => LPM_MUX:LPM_MUX_component.DATA[2][13]
+data2x[14] => LPM_MUX:LPM_MUX_component.DATA[2][14]
+data2x[15] => LPM_MUX:LPM_MUX_component.DATA[2][15]
+data2x[16] => LPM_MUX:LPM_MUX_component.DATA[2][16]
+data2x[17] => LPM_MUX:LPM_MUX_component.DATA[2][17]
+data2x[18] => LPM_MUX:LPM_MUX_component.DATA[2][18]
+data2x[19] => LPM_MUX:LPM_MUX_component.DATA[2][19]
+data2x[20] => LPM_MUX:LPM_MUX_component.DATA[2][20]
+data2x[21] => LPM_MUX:LPM_MUX_component.DATA[2][21]
+data2x[22] => LPM_MUX:LPM_MUX_component.DATA[2][22]
+data2x[23] => LPM_MUX:LPM_MUX_component.DATA[2][23]
+data2x[24] => LPM_MUX:LPM_MUX_component.DATA[2][24]
+data2x[25] => LPM_MUX:LPM_MUX_component.DATA[2][25]
+data2x[26] => LPM_MUX:LPM_MUX_component.DATA[2][26]
+data2x[27] => LPM_MUX:LPM_MUX_component.DATA[2][27]
+data2x[28] => LPM_MUX:LPM_MUX_component.DATA[2][28]
+data2x[29] => LPM_MUX:LPM_MUX_component.DATA[2][29]
+data3x[0] => LPM_MUX:LPM_MUX_component.DATA[3][0]
+data3x[1] => LPM_MUX:LPM_MUX_component.DATA[3][1]
+data3x[2] => LPM_MUX:LPM_MUX_component.DATA[3][2]
+data3x[3] => LPM_MUX:LPM_MUX_component.DATA[3][3]
+data3x[4] => LPM_MUX:LPM_MUX_component.DATA[3][4]
+data3x[5] => LPM_MUX:LPM_MUX_component.DATA[3][5]
+data3x[6] => LPM_MUX:LPM_MUX_component.DATA[3][6]
+data3x[7] => LPM_MUX:LPM_MUX_component.DATA[3][7]
+data3x[8] => LPM_MUX:LPM_MUX_component.DATA[3][8]
+data3x[9] => LPM_MUX:LPM_MUX_component.DATA[3][9]
+data3x[10] => LPM_MUX:LPM_MUX_component.DATA[3][10]
+data3x[11] => LPM_MUX:LPM_MUX_component.DATA[3][11]
+data3x[12] => LPM_MUX:LPM_MUX_component.DATA[3][12]
+data3x[13] => LPM_MUX:LPM_MUX_component.DATA[3][13]
+data3x[14] => LPM_MUX:LPM_MUX_component.DATA[3][14]
+data3x[15] => LPM_MUX:LPM_MUX_component.DATA[3][15]
+data3x[16] => LPM_MUX:LPM_MUX_component.DATA[3][16]
+data3x[17] => LPM_MUX:LPM_MUX_component.DATA[3][17]
+data3x[18] => LPM_MUX:LPM_MUX_component.DATA[3][18]
+data3x[19] => LPM_MUX:LPM_MUX_component.DATA[3][19]
+data3x[20] => LPM_MUX:LPM_MUX_component.DATA[3][20]
+data3x[21] => LPM_MUX:LPM_MUX_component.DATA[3][21]
+data3x[22] => LPM_MUX:LPM_MUX_component.DATA[3][22]
+data3x[23] => LPM_MUX:LPM_MUX_component.DATA[3][23]
+data3x[24] => LPM_MUX:LPM_MUX_component.DATA[3][24]
+data3x[25] => LPM_MUX:LPM_MUX_component.DATA[3][25]
+data3x[26] => LPM_MUX:LPM_MUX_component.DATA[3][26]
+data3x[27] => LPM_MUX:LPM_MUX_component.DATA[3][27]
+data3x[28] => LPM_MUX:LPM_MUX_component.DATA[3][28]
+data3x[29] => LPM_MUX:LPM_MUX_component.DATA[3][29]
+sel[0] => LPM_MUX:LPM_MUX_component.SEL[0]
+sel[1] => LPM_MUX:LPM_MUX_component.SEL[1]
+result[0] <= LPM_MUX:LPM_MUX_component.RESULT[0]
+result[1] <= LPM_MUX:LPM_MUX_component.RESULT[1]
+result[2] <= LPM_MUX:LPM_MUX_component.RESULT[2]
+result[3] <= LPM_MUX:LPM_MUX_component.RESULT[3]
+result[4] <= LPM_MUX:LPM_MUX_component.RESULT[4]
+result[5] <= LPM_MUX:LPM_MUX_component.RESULT[5]
+result[6] <= LPM_MUX:LPM_MUX_component.RESULT[6]
+result[7] <= LPM_MUX:LPM_MUX_component.RESULT[7]
+result[8] <= LPM_MUX:LPM_MUX_component.RESULT[8]
+result[9] <= LPM_MUX:LPM_MUX_component.RESULT[9]
+result[10] <= LPM_MUX:LPM_MUX_component.RESULT[10]
+result[11] <= LPM_MUX:LPM_MUX_component.RESULT[11]
+result[12] <= LPM_MUX:LPM_MUX_component.RESULT[12]
+result[13] <= LPM_MUX:LPM_MUX_component.RESULT[13]
+result[14] <= LPM_MUX:LPM_MUX_component.RESULT[14]
+result[15] <= LPM_MUX:LPM_MUX_component.RESULT[15]
+result[16] <= LPM_MUX:LPM_MUX_component.RESULT[16]
+result[17] <= LPM_MUX:LPM_MUX_component.RESULT[17]
+result[18] <= LPM_MUX:LPM_MUX_component.RESULT[18]
+result[19] <= LPM_MUX:LPM_MUX_component.RESULT[19]
+result[20] <= LPM_MUX:LPM_MUX_component.RESULT[20]
+result[21] <= LPM_MUX:LPM_MUX_component.RESULT[21]
+result[22] <= LPM_MUX:LPM_MUX_component.RESULT[22]
+result[23] <= LPM_MUX:LPM_MUX_component.RESULT[23]
+result[24] <= LPM_MUX:LPM_MUX_component.RESULT[24]
+result[25] <= LPM_MUX:LPM_MUX_component.RESULT[25]
+result[26] <= LPM_MUX:LPM_MUX_component.RESULT[26]
+result[27] <= LPM_MUX:LPM_MUX_component.RESULT[27]
+result[28] <= LPM_MUX:LPM_MUX_component.RESULT[28]
+result[29] <= LPM_MUX:LPM_MUX_component.RESULT[29]
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component
+data[0][0] => mux_u7e:auto_generated.data[0]
+data[0][1] => mux_u7e:auto_generated.data[1]
+data[0][2] => mux_u7e:auto_generated.data[2]
+data[0][3] => mux_u7e:auto_generated.data[3]
+data[0][4] => mux_u7e:auto_generated.data[4]
+data[0][5] => mux_u7e:auto_generated.data[5]
+data[0][6] => mux_u7e:auto_generated.data[6]
+data[0][7] => mux_u7e:auto_generated.data[7]
+data[0][8] => mux_u7e:auto_generated.data[8]
+data[0][9] => mux_u7e:auto_generated.data[9]
+data[0][10] => mux_u7e:auto_generated.data[10]
+data[0][11] => mux_u7e:auto_generated.data[11]
+data[0][12] => mux_u7e:auto_generated.data[12]
+data[0][13] => mux_u7e:auto_generated.data[13]
+data[0][14] => mux_u7e:auto_generated.data[14]
+data[0][15] => mux_u7e:auto_generated.data[15]
+data[0][16] => mux_u7e:auto_generated.data[16]
+data[0][17] => mux_u7e:auto_generated.data[17]
+data[0][18] => mux_u7e:auto_generated.data[18]
+data[0][19] => mux_u7e:auto_generated.data[19]
+data[0][20] => mux_u7e:auto_generated.data[20]
+data[0][21] => mux_u7e:auto_generated.data[21]
+data[0][22] => mux_u7e:auto_generated.data[22]
+data[0][23] => mux_u7e:auto_generated.data[23]
+data[0][24] => mux_u7e:auto_generated.data[24]
+data[0][25] => mux_u7e:auto_generated.data[25]
+data[0][26] => mux_u7e:auto_generated.data[26]
+data[0][27] => mux_u7e:auto_generated.data[27]
+data[0][28] => mux_u7e:auto_generated.data[28]
+data[0][29] => mux_u7e:auto_generated.data[29]
+data[1][0] => mux_u7e:auto_generated.data[30]
+data[1][1] => mux_u7e:auto_generated.data[31]
+data[1][2] => mux_u7e:auto_generated.data[32]
+data[1][3] => mux_u7e:auto_generated.data[33]
+data[1][4] => mux_u7e:auto_generated.data[34]
+data[1][5] => mux_u7e:auto_generated.data[35]
+data[1][6] => mux_u7e:auto_generated.data[36]
+data[1][7] => mux_u7e:auto_generated.data[37]
+data[1][8] => mux_u7e:auto_generated.data[38]
+data[1][9] => mux_u7e:auto_generated.data[39]
+data[1][10] => mux_u7e:auto_generated.data[40]
+data[1][11] => mux_u7e:auto_generated.data[41]
+data[1][12] => mux_u7e:auto_generated.data[42]
+data[1][13] => mux_u7e:auto_generated.data[43]
+data[1][14] => mux_u7e:auto_generated.data[44]
+data[1][15] => mux_u7e:auto_generated.data[45]
+data[1][16] => mux_u7e:auto_generated.data[46]
+data[1][17] => mux_u7e:auto_generated.data[47]
+data[1][18] => mux_u7e:auto_generated.data[48]
+data[1][19] => mux_u7e:auto_generated.data[49]
+data[1][20] => mux_u7e:auto_generated.data[50]
+data[1][21] => mux_u7e:auto_generated.data[51]
+data[1][22] => mux_u7e:auto_generated.data[52]
+data[1][23] => mux_u7e:auto_generated.data[53]
+data[1][24] => mux_u7e:auto_generated.data[54]
+data[1][25] => mux_u7e:auto_generated.data[55]
+data[1][26] => mux_u7e:auto_generated.data[56]
+data[1][27] => mux_u7e:auto_generated.data[57]
+data[1][28] => mux_u7e:auto_generated.data[58]
+data[1][29] => mux_u7e:auto_generated.data[59]
+data[2][0] => mux_u7e:auto_generated.data[60]
+data[2][1] => mux_u7e:auto_generated.data[61]
+data[2][2] => mux_u7e:auto_generated.data[62]
+data[2][3] => mux_u7e:auto_generated.data[63]
+data[2][4] => mux_u7e:auto_generated.data[64]
+data[2][5] => mux_u7e:auto_generated.data[65]
+data[2][6] => mux_u7e:auto_generated.data[66]
+data[2][7] => mux_u7e:auto_generated.data[67]
+data[2][8] => mux_u7e:auto_generated.data[68]
+data[2][9] => mux_u7e:auto_generated.data[69]
+data[2][10] => mux_u7e:auto_generated.data[70]
+data[2][11] => mux_u7e:auto_generated.data[71]
+data[2][12] => mux_u7e:auto_generated.data[72]
+data[2][13] => mux_u7e:auto_generated.data[73]
+data[2][14] => mux_u7e:auto_generated.data[74]
+data[2][15] => mux_u7e:auto_generated.data[75]
+data[2][16] => mux_u7e:auto_generated.data[76]
+data[2][17] => mux_u7e:auto_generated.data[77]
+data[2][18] => mux_u7e:auto_generated.data[78]
+data[2][19] => mux_u7e:auto_generated.data[79]
+data[2][20] => mux_u7e:auto_generated.data[80]
+data[2][21] => mux_u7e:auto_generated.data[81]
+data[2][22] => mux_u7e:auto_generated.data[82]
+data[2][23] => mux_u7e:auto_generated.data[83]
+data[2][24] => mux_u7e:auto_generated.data[84]
+data[2][25] => mux_u7e:auto_generated.data[85]
+data[2][26] => mux_u7e:auto_generated.data[86]
+data[2][27] => mux_u7e:auto_generated.data[87]
+data[2][28] => mux_u7e:auto_generated.data[88]
+data[2][29] => mux_u7e:auto_generated.data[89]
+data[3][0] => mux_u7e:auto_generated.data[90]
+data[3][1] => mux_u7e:auto_generated.data[91]
+data[3][2] => mux_u7e:auto_generated.data[92]
+data[3][3] => mux_u7e:auto_generated.data[93]
+data[3][4] => mux_u7e:auto_generated.data[94]
+data[3][5] => mux_u7e:auto_generated.data[95]
+data[3][6] => mux_u7e:auto_generated.data[96]
+data[3][7] => mux_u7e:auto_generated.data[97]
+data[3][8] => mux_u7e:auto_generated.data[98]
+data[3][9] => mux_u7e:auto_generated.data[99]
+data[3][10] => mux_u7e:auto_generated.data[100]
+data[3][11] => mux_u7e:auto_generated.data[101]
+data[3][12] => mux_u7e:auto_generated.data[102]
+data[3][13] => mux_u7e:auto_generated.data[103]
+data[3][14] => mux_u7e:auto_generated.data[104]
+data[3][15] => mux_u7e:auto_generated.data[105]
+data[3][16] => mux_u7e:auto_generated.data[106]
+data[3][17] => mux_u7e:auto_generated.data[107]
+data[3][18] => mux_u7e:auto_generated.data[108]
+data[3][19] => mux_u7e:auto_generated.data[109]
+data[3][20] => mux_u7e:auto_generated.data[110]
+data[3][21] => mux_u7e:auto_generated.data[111]
+data[3][22] => mux_u7e:auto_generated.data[112]
+data[3][23] => mux_u7e:auto_generated.data[113]
+data[3][24] => mux_u7e:auto_generated.data[114]
+data[3][25] => mux_u7e:auto_generated.data[115]
+data[3][26] => mux_u7e:auto_generated.data[116]
+data[3][27] => mux_u7e:auto_generated.data[117]
+data[3][28] => mux_u7e:auto_generated.data[118]
+data[3][29] => mux_u7e:auto_generated.data[119]
+sel[0] => mux_u7e:auto_generated.sel[0]
+sel[1] => mux_u7e:auto_generated.sel[1]
+clock => ~NO_FANOUT~
+aclr => ~NO_FANOUT~
+clken => ~NO_FANOUT~
+result[0] <= mux_u7e:auto_generated.result[0]
+result[1] <= mux_u7e:auto_generated.result[1]
+result[2] <= mux_u7e:auto_generated.result[2]
+result[3] <= mux_u7e:auto_generated.result[3]
+result[4] <= mux_u7e:auto_generated.result[4]
+result[5] <= mux_u7e:auto_generated.result[5]
+result[6] <= mux_u7e:auto_generated.result[6]
+result[7] <= mux_u7e:auto_generated.result[7]
+result[8] <= mux_u7e:auto_generated.result[8]
+result[9] <= mux_u7e:auto_generated.result[9]
+result[10] <= mux_u7e:auto_generated.result[10]
+result[11] <= mux_u7e:auto_generated.result[11]
+result[12] <= mux_u7e:auto_generated.result[12]
+result[13] <= mux_u7e:auto_generated.result[13]
+result[14] <= mux_u7e:auto_generated.result[14]
+result[15] <= mux_u7e:auto_generated.result[15]
+result[16] <= mux_u7e:auto_generated.result[16]
+result[17] <= mux_u7e:auto_generated.result[17]
+result[18] <= mux_u7e:auto_generated.result[18]
+result[19] <= mux_u7e:auto_generated.result[19]
+result[20] <= mux_u7e:auto_generated.result[20]
+result[21] <= mux_u7e:auto_generated.result[21]
+result[22] <= mux_u7e:auto_generated.result[22]
+result[23] <= mux_u7e:auto_generated.result[23]
+result[24] <= mux_u7e:auto_generated.result[24]
+result[25] <= mux_u7e:auto_generated.result[25]
+result[26] <= mux_u7e:auto_generated.result[26]
+result[27] <= mux_u7e:auto_generated.result[27]
+result[28] <= mux_u7e:auto_generated.result[28]
+result[29] <= mux_u7e:auto_generated.result[29]
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|LPM_MUX:LPM_MUX_component|mux_u7e:auto_generated
+data[0] => _.IN0
+data[0] => _.IN0
+data[1] => _.IN0
+data[1] => _.IN0
+data[2] => _.IN0
+data[2] => _.IN0
+data[3] => _.IN0
+data[3] => _.IN0
+data[4] => _.IN0
+data[4] => _.IN0
+data[5] => _.IN0
+data[5] => _.IN0
+data[6] => _.IN0
+data[6] => _.IN0
+data[7] => _.IN0
+data[7] => _.IN0
+data[8] => _.IN0
+data[8] => _.IN0
+data[9] => _.IN0
+data[9] => _.IN0
+data[10] => _.IN0
+data[10] => _.IN0
+data[11] => _.IN0
+data[11] => _.IN0
+data[12] => _.IN0
+data[12] => _.IN0
+data[13] => _.IN0
+data[13] => _.IN0
+data[14] => _.IN0
+data[14] => _.IN0
+data[15] => _.IN0
+data[15] => _.IN0
+data[16] => _.IN0
+data[16] => _.IN0
+data[17] => _.IN0
+data[17] => _.IN0
+data[18] => _.IN0
+data[18] => _.IN0
+data[19] => _.IN0
+data[19] => _.IN0
+data[20] => _.IN0
+data[20] => _.IN0
+data[21] => _.IN0
+data[21] => _.IN0
+data[22] => _.IN0
+data[22] => _.IN0
+data[23] => _.IN0
+data[23] => _.IN0
+data[24] => _.IN0
+data[24] => _.IN0
+data[25] => _.IN0
+data[25] => _.IN0
+data[26] => _.IN0
+data[26] => _.IN0
+data[27] => _.IN0
+data[27] => _.IN0
+data[28] => _.IN0
+data[28] => _.IN0
+data[29] => _.IN0
+data[29] => _.IN0
+data[30] => _.IN0
+data[31] => _.IN0
+data[32] => _.IN0
+data[33] => _.IN0
+data[34] => _.IN0
+data[35] => _.IN0
+data[36] => _.IN0
+data[37] => _.IN0
+data[38] => _.IN0
+data[39] => _.IN0
+data[40] => _.IN0
+data[41] => _.IN0
+data[42] => _.IN0
+data[43] => _.IN0
+data[44] => _.IN0
+data[45] => _.IN0
+data[46] => _.IN0
+data[47] => _.IN0
+data[48] => _.IN0
+data[49] => _.IN0
+data[50] => _.IN0
+data[51] => _.IN0
+data[52] => _.IN0
+data[53] => _.IN0
+data[54] => _.IN0
+data[55] => _.IN0
+data[56] => _.IN0
+data[57] => _.IN0
+data[58] => _.IN0
+data[59] => _.IN0
+data[60] => _.IN1
+data[60] => _.IN1
+data[61] => _.IN1
+data[61] => _.IN1
+data[62] => _.IN1
+data[62] => _.IN1
+data[63] => _.IN1
+data[63] => _.IN1
+data[64] => _.IN1
+data[64] => _.IN1
+data[65] => _.IN1
+data[65] => _.IN1
+data[66] => _.IN1
+data[66] => _.IN1
+data[67] => _.IN1
+data[67] => _.IN1
+data[68] => _.IN1
+data[68] => _.IN1
+data[69] => _.IN1
+data[69] => _.IN1
+data[70] => _.IN1
+data[70] => _.IN1
+data[71] => _.IN1
+data[71] => _.IN1
+data[72] => _.IN1
+data[72] => _.IN1
+data[73] => _.IN1
+data[73] => _.IN1
+data[74] => _.IN1
+data[74] => _.IN1
+data[75] => _.IN1
+data[75] => _.IN1
+data[76] => _.IN1
+data[76] => _.IN1
+data[77] => _.IN1
+data[77] => _.IN1
+data[78] => _.IN1
+data[78] => _.IN1
+data[79] => _.IN1
+data[79] => _.IN1
+data[80] => _.IN1
+data[80] => _.IN1
+data[81] => _.IN1
+data[81] => _.IN1
+data[82] => _.IN1
+data[82] => _.IN1
+data[83] => _.IN1
+data[83] => _.IN1
+data[84] => _.IN1
+data[84] => _.IN1
+data[85] => _.IN1
+data[85] => _.IN1
+data[86] => _.IN1
+data[86] => _.IN1
+data[87] => _.IN1
+data[87] => _.IN1
+data[88] => _.IN1
+data[88] => _.IN1
+data[89] => _.IN1
+data[89] => _.IN1
+data[90] => _.IN0
+data[91] => _.IN0
+data[92] => _.IN0
+data[93] => _.IN0
+data[94] => _.IN0
+data[95] => _.IN0
+data[96] => _.IN0
+data[97] => _.IN0
+data[98] => _.IN0
+data[99] => _.IN0
+data[100] => _.IN0
+data[101] => _.IN0
+data[102] => _.IN0
+data[103] => _.IN0
+data[104] => _.IN0
+data[105] => _.IN0
+data[106] => _.IN0
+data[107] => _.IN0
+data[108] => _.IN0
+data[109] => _.IN0
+data[110] => _.IN0
+data[111] => _.IN0
+data[112] => _.IN0
+data[113] => _.IN0
+data[114] => _.IN0
+data[115] => _.IN0
+data[116] => _.IN0
+data[117] => _.IN0
+data[118] => _.IN0
+data[119] => _.IN0
+result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
+result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
+result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
+result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
+result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
+result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
+result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
+result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
+result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
+result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
+result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
+result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE
+result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE
+result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE
+result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE
+result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE
+result[16] <= result_node[16].DB_MAX_OUTPUT_PORT_TYPE
+result[17] <= result_node[17].DB_MAX_OUTPUT_PORT_TYPE
+result[18] <= result_node[18].DB_MAX_OUTPUT_PORT_TYPE
+result[19] <= result_node[19].DB_MAX_OUTPUT_PORT_TYPE
+result[20] <= result_node[20].DB_MAX_OUTPUT_PORT_TYPE
+result[21] <= result_node[21].DB_MAX_OUTPUT_PORT_TYPE
+result[22] <= result_node[22].DB_MAX_OUTPUT_PORT_TYPE
+result[23] <= result_node[23].DB_MAX_OUTPUT_PORT_TYPE
+result[24] <= result_node[24].DB_MAX_OUTPUT_PORT_TYPE
+result[25] <= result_node[25].DB_MAX_OUTPUT_PORT_TYPE
+result[26] <= result_node[26].DB_MAX_OUTPUT_PORT_TYPE
+result[27] <= result_node[27].DB_MAX_OUTPUT_PORT_TYPE
+result[28] <= result_node[28].DB_MAX_OUTPUT_PORT_TYPE
+result[29] <= result_node[29].DB_MAX_OUTPUT_PORT_TYPE
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN1
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[0] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+sel[1] => _.IN0
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst
+vga_xy_rsc_z[0] => vga_xy_rsc_z[0].IN1
+vga_xy_rsc_z[1] => vga_xy_rsc_z[1].IN1
+vga_xy_rsc_z[2] => vga_xy_rsc_z[2].IN1
+vga_xy_rsc_z[3] => vga_xy_rsc_z[3].IN1
+vga_xy_rsc_z[4] => vga_xy_rsc_z[4].IN1
+vga_xy_rsc_z[5] => vga_xy_rsc_z[5].IN1
+vga_xy_rsc_z[6] => vga_xy_rsc_z[6].IN1
+vga_xy_rsc_z[7] => vga_xy_rsc_z[7].IN1
+vga_xy_rsc_z[8] => vga_xy_rsc_z[8].IN1
+vga_xy_rsc_z[9] => vga_xy_rsc_z[9].IN1
+vga_xy_rsc_z[10] => vga_xy_rsc_z[10].IN1
+vga_xy_rsc_z[11] => vga_xy_rsc_z[11].IN1
+vga_xy_rsc_z[12] => vga_xy_rsc_z[12].IN1
+vga_xy_rsc_z[13] => vga_xy_rsc_z[13].IN1
+vga_xy_rsc_z[14] => vga_xy_rsc_z[14].IN1
+vga_xy_rsc_z[15] => vga_xy_rsc_z[15].IN1
+vga_xy_rsc_z[16] => vga_xy_rsc_z[16].IN1
+vga_xy_rsc_z[17] => vga_xy_rsc_z[17].IN1
+vga_xy_rsc_z[18] => vga_xy_rsc_z[18].IN1
+vga_xy_rsc_z[19] => vga_xy_rsc_z[19].IN1
+mouse_xy_rsc_z[0] => mouse_xy_rsc_z[0].IN1
+mouse_xy_rsc_z[1] => mouse_xy_rsc_z[1].IN1
+mouse_xy_rsc_z[2] => mouse_xy_rsc_z[2].IN1
+mouse_xy_rsc_z[3] => mouse_xy_rsc_z[3].IN1
+mouse_xy_rsc_z[4] => mouse_xy_rsc_z[4].IN1
+mouse_xy_rsc_z[5] => mouse_xy_rsc_z[5].IN1
+mouse_xy_rsc_z[6] => mouse_xy_rsc_z[6].IN1
+mouse_xy_rsc_z[7] => mouse_xy_rsc_z[7].IN1
+mouse_xy_rsc_z[8] => mouse_xy_rsc_z[8].IN1
+mouse_xy_rsc_z[9] => mouse_xy_rsc_z[9].IN1
+mouse_xy_rsc_z[10] => mouse_xy_rsc_z[10].IN1
+mouse_xy_rsc_z[11] => mouse_xy_rsc_z[11].IN1
+mouse_xy_rsc_z[12] => mouse_xy_rsc_z[12].IN1
+mouse_xy_rsc_z[13] => mouse_xy_rsc_z[13].IN1
+mouse_xy_rsc_z[14] => mouse_xy_rsc_z[14].IN1
+mouse_xy_rsc_z[15] => mouse_xy_rsc_z[15].IN1
+mouse_xy_rsc_z[16] => mouse_xy_rsc_z[16].IN1
+mouse_xy_rsc_z[17] => mouse_xy_rsc_z[17].IN1
+mouse_xy_rsc_z[18] => mouse_xy_rsc_z[18].IN1
+mouse_xy_rsc_z[19] => mouse_xy_rsc_z[19].IN1
+cursor_size_rsc_z[0] => cursor_size_rsc_z[0].IN1
+cursor_size_rsc_z[1] => cursor_size_rsc_z[1].IN1
+cursor_size_rsc_z[2] => cursor_size_rsc_z[2].IN1
+cursor_size_rsc_z[3] => cursor_size_rsc_z[3].IN1
+cursor_size_rsc_z[4] => cursor_size_rsc_z[4].IN1
+cursor_size_rsc_z[5] => cursor_size_rsc_z[5].IN1
+cursor_size_rsc_z[6] => cursor_size_rsc_z[6].IN1
+cursor_size_rsc_z[7] => cursor_size_rsc_z[7].IN1
+video_in_rsc_z[0] => video_in_rsc_z[0].IN1
+video_in_rsc_z[1] => video_in_rsc_z[1].IN1
+video_in_rsc_z[2] => video_in_rsc_z[2].IN1
+video_in_rsc_z[3] => video_in_rsc_z[3].IN1
+video_in_rsc_z[4] => video_in_rsc_z[4].IN1
+video_in_rsc_z[5] => video_in_rsc_z[5].IN1
+video_in_rsc_z[6] => video_in_rsc_z[6].IN1
+video_in_rsc_z[7] => video_in_rsc_z[7].IN1
+video_in_rsc_z[8] => video_in_rsc_z[8].IN1
+video_in_rsc_z[9] => video_in_rsc_z[9].IN1
+video_in_rsc_z[10] => video_in_rsc_z[10].IN1
+video_in_rsc_z[11] => video_in_rsc_z[11].IN1
+video_in_rsc_z[12] => video_in_rsc_z[12].IN1
+video_in_rsc_z[13] => video_in_rsc_z[13].IN1
+video_in_rsc_z[14] => video_in_rsc_z[14].IN1
+video_in_rsc_z[15] => video_in_rsc_z[15].IN1
+video_in_rsc_z[16] => video_in_rsc_z[16].IN1
+video_in_rsc_z[17] => video_in_rsc_z[17].IN1
+video_in_rsc_z[18] => video_in_rsc_z[18].IN1
+video_in_rsc_z[19] => video_in_rsc_z[19].IN1
+video_in_rsc_z[20] => video_in_rsc_z[20].IN1
+video_in_rsc_z[21] => video_in_rsc_z[21].IN1
+video_in_rsc_z[22] => video_in_rsc_z[22].IN1
+video_in_rsc_z[23] => video_in_rsc_z[23].IN1
+video_in_rsc_z[24] => video_in_rsc_z[24].IN1
+video_in_rsc_z[25] => video_in_rsc_z[25].IN1
+video_in_rsc_z[26] => video_in_rsc_z[26].IN1
+video_in_rsc_z[27] => video_in_rsc_z[27].IN1
+video_in_rsc_z[28] => video_in_rsc_z[28].IN1
+video_in_rsc_z[29] => video_in_rsc_z[29].IN1
+video_out_rsc_z[0] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[1] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[2] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[3] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[4] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[5] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[6] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[7] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[8] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[9] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[10] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[11] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[12] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[13] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[14] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[15] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[16] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[17] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[18] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[19] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[20] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[21] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[22] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[23] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[24] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[25] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[26] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[27] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[28] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+video_out_rsc_z[29] <= mgc_out_stdreg:video_out_rsc_mgc_out_stdreg.z
+clk => clk.IN1
+en => en.IN1
+arst_n => arst_n.IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE
+d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE
+d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE
+d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE
+d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE
+d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE
+d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE
+d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE
+d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE
+d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+z[20] => d[20].DATAIN
+z[21] => d[21].DATAIN
+z[22] => d[22].DATAIN
+z[23] => d[23].DATAIN
+z[24] => d[24].DATAIN
+z[25] => d[25].DATAIN
+z[26] => d[26].DATAIN
+z[27] => d[27].DATAIN
+z[28] => d[28].DATAIN
+z[29] => d[29].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg
+d[0] => z[0].DATAIN
+d[1] => z[1].DATAIN
+d[2] => z[2].DATAIN
+d[3] => z[3].DATAIN
+d[4] => z[4].DATAIN
+d[5] => z[5].DATAIN
+d[6] => z[6].DATAIN
+d[7] => z[7].DATAIN
+d[8] => z[8].DATAIN
+d[9] => z[9].DATAIN
+d[10] => z[10].DATAIN
+d[11] => z[11].DATAIN
+d[12] => z[12].DATAIN
+d[13] => z[13].DATAIN
+d[14] => z[14].DATAIN
+d[15] => z[15].DATAIN
+d[16] => z[16].DATAIN
+d[17] => z[17].DATAIN
+d[18] => z[18].DATAIN
+d[19] => z[19].DATAIN
+d[20] => z[20].DATAIN
+d[21] => z[21].DATAIN
+d[22] => z[22].DATAIN
+d[23] => z[23].DATAIN
+d[24] => z[24].DATAIN
+d[25] => z[25].DATAIN
+d[26] => z[26].DATAIN
+d[27] => z[27].DATAIN
+d[28] => z[28].DATAIN
+d[29] => z[29].DATAIN
+z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
+z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
+z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
+z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
+z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
+z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
+z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
+z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
+z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
+z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
+z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
+z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
+z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
+z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
+z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
+z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
+z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
+z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
+z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
+z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
+z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
+z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
+z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
+z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
+z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
+z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
+z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
+z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
+z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
+z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].CLK
+clk => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].CLK
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].ENA
+en => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].ENA
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].ACLR
+arst_n => reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].ACLR
+vga_xy_rsc_mgc_in_wire_d[0] => Add6.IN20
+vga_xy_rsc_mgc_in_wire_d[0] => Add4.IN10
+vga_xy_rsc_mgc_in_wire_d[1] => Add6.IN19
+vga_xy_rsc_mgc_in_wire_d[1] => Add4.IN9
+vga_xy_rsc_mgc_in_wire_d[2] => Add6.IN18
+vga_xy_rsc_mgc_in_wire_d[2] => Add4.IN8
+vga_xy_rsc_mgc_in_wire_d[3] => Add6.IN17
+vga_xy_rsc_mgc_in_wire_d[3] => Add4.IN7
+vga_xy_rsc_mgc_in_wire_d[4] => Add6.IN16
+vga_xy_rsc_mgc_in_wire_d[4] => Add4.IN6
+vga_xy_rsc_mgc_in_wire_d[5] => Add6.IN15
+vga_xy_rsc_mgc_in_wire_d[5] => Add4.IN5
+vga_xy_rsc_mgc_in_wire_d[6] => Add6.IN14
+vga_xy_rsc_mgc_in_wire_d[6] => Add4.IN4
+vga_xy_rsc_mgc_in_wire_d[7] => Add6.IN13
+vga_xy_rsc_mgc_in_wire_d[7] => Add4.IN3
+vga_xy_rsc_mgc_in_wire_d[8] => Add6.IN12
+vga_xy_rsc_mgc_in_wire_d[8] => Add4.IN2
+vga_xy_rsc_mgc_in_wire_d[9] => Add6.IN11
+vga_xy_rsc_mgc_in_wire_d[9] => Add4.IN1
+vga_xy_rsc_mgc_in_wire_d[10] => Add2.IN20
+vga_xy_rsc_mgc_in_wire_d[10] => Add0.IN10
+vga_xy_rsc_mgc_in_wire_d[11] => Add2.IN19
+vga_xy_rsc_mgc_in_wire_d[11] => Add0.IN9
+vga_xy_rsc_mgc_in_wire_d[12] => Add2.IN18
+vga_xy_rsc_mgc_in_wire_d[12] => Add0.IN8
+vga_xy_rsc_mgc_in_wire_d[13] => Add2.IN17
+vga_xy_rsc_mgc_in_wire_d[13] => Add0.IN7
+vga_xy_rsc_mgc_in_wire_d[14] => Add2.IN16
+vga_xy_rsc_mgc_in_wire_d[14] => Add0.IN6
+vga_xy_rsc_mgc_in_wire_d[15] => Add2.IN15
+vga_xy_rsc_mgc_in_wire_d[15] => Add0.IN5
+vga_xy_rsc_mgc_in_wire_d[16] => Add2.IN14
+vga_xy_rsc_mgc_in_wire_d[16] => Add0.IN4
+vga_xy_rsc_mgc_in_wire_d[17] => Add2.IN13
+vga_xy_rsc_mgc_in_wire_d[17] => Add0.IN3
+vga_xy_rsc_mgc_in_wire_d[18] => Add2.IN12
+vga_xy_rsc_mgc_in_wire_d[18] => Add0.IN2
+vga_xy_rsc_mgc_in_wire_d[19] => Add2.IN11
+vga_xy_rsc_mgc_in_wire_d[19] => Add0.IN1
+mouse_xy_rsc_mgc_in_wire_d[0] => Add4.IN20
+mouse_xy_rsc_mgc_in_wire_d[0] => Add6.IN10
+mouse_xy_rsc_mgc_in_wire_d[1] => Add4.IN19
+mouse_xy_rsc_mgc_in_wire_d[1] => Add6.IN9
+mouse_xy_rsc_mgc_in_wire_d[2] => Add4.IN18
+mouse_xy_rsc_mgc_in_wire_d[2] => Add6.IN8
+mouse_xy_rsc_mgc_in_wire_d[3] => Add4.IN17
+mouse_xy_rsc_mgc_in_wire_d[3] => Add6.IN7
+mouse_xy_rsc_mgc_in_wire_d[4] => Add4.IN16
+mouse_xy_rsc_mgc_in_wire_d[4] => Add6.IN6
+mouse_xy_rsc_mgc_in_wire_d[5] => Add4.IN15
+mouse_xy_rsc_mgc_in_wire_d[5] => Add6.IN5
+mouse_xy_rsc_mgc_in_wire_d[6] => Add4.IN14
+mouse_xy_rsc_mgc_in_wire_d[6] => Add6.IN4
+mouse_xy_rsc_mgc_in_wire_d[7] => Add4.IN13
+mouse_xy_rsc_mgc_in_wire_d[7] => Add6.IN3
+mouse_xy_rsc_mgc_in_wire_d[8] => Add4.IN12
+mouse_xy_rsc_mgc_in_wire_d[8] => Add6.IN2
+mouse_xy_rsc_mgc_in_wire_d[9] => Add4.IN11
+mouse_xy_rsc_mgc_in_wire_d[9] => Add6.IN1
+mouse_xy_rsc_mgc_in_wire_d[10] => Add0.IN20
+mouse_xy_rsc_mgc_in_wire_d[10] => Add2.IN10
+mouse_xy_rsc_mgc_in_wire_d[11] => Add0.IN19
+mouse_xy_rsc_mgc_in_wire_d[11] => Add2.IN9
+mouse_xy_rsc_mgc_in_wire_d[12] => Add0.IN18
+mouse_xy_rsc_mgc_in_wire_d[12] => Add2.IN8
+mouse_xy_rsc_mgc_in_wire_d[13] => Add0.IN17
+mouse_xy_rsc_mgc_in_wire_d[13] => Add2.IN7
+mouse_xy_rsc_mgc_in_wire_d[14] => Add0.IN16
+mouse_xy_rsc_mgc_in_wire_d[14] => Add2.IN6
+mouse_xy_rsc_mgc_in_wire_d[15] => Add0.IN15
+mouse_xy_rsc_mgc_in_wire_d[15] => Add2.IN5
+mouse_xy_rsc_mgc_in_wire_d[16] => Add0.IN14
+mouse_xy_rsc_mgc_in_wire_d[16] => Add2.IN4
+mouse_xy_rsc_mgc_in_wire_d[17] => Add0.IN13
+mouse_xy_rsc_mgc_in_wire_d[17] => Add2.IN3
+mouse_xy_rsc_mgc_in_wire_d[18] => Add0.IN12
+mouse_xy_rsc_mgc_in_wire_d[18] => Add2.IN2
+mouse_xy_rsc_mgc_in_wire_d[19] => Add0.IN11
+mouse_xy_rsc_mgc_in_wire_d[19] => Add2.IN1
+cursor_size_rsc_mgc_in_wire_d[0] => Add1.IN22
+cursor_size_rsc_mgc_in_wire_d[0] => Add3.IN22
+cursor_size_rsc_mgc_in_wire_d[0] => Add5.IN22
+cursor_size_rsc_mgc_in_wire_d[0] => Add7.IN22
+cursor_size_rsc_mgc_in_wire_d[1] => Add1.IN21
+cursor_size_rsc_mgc_in_wire_d[1] => Add3.IN21
+cursor_size_rsc_mgc_in_wire_d[1] => Add5.IN21
+cursor_size_rsc_mgc_in_wire_d[1] => Add7.IN21
+cursor_size_rsc_mgc_in_wire_d[2] => Add1.IN20
+cursor_size_rsc_mgc_in_wire_d[2] => Add3.IN20
+cursor_size_rsc_mgc_in_wire_d[2] => Add5.IN20
+cursor_size_rsc_mgc_in_wire_d[2] => Add7.IN20
+cursor_size_rsc_mgc_in_wire_d[3] => Add1.IN19
+cursor_size_rsc_mgc_in_wire_d[3] => Add3.IN19
+cursor_size_rsc_mgc_in_wire_d[3] => Add5.IN19
+cursor_size_rsc_mgc_in_wire_d[3] => Add7.IN19
+cursor_size_rsc_mgc_in_wire_d[4] => Add1.IN18
+cursor_size_rsc_mgc_in_wire_d[4] => Add3.IN18
+cursor_size_rsc_mgc_in_wire_d[4] => Add5.IN18
+cursor_size_rsc_mgc_in_wire_d[4] => Add7.IN18
+cursor_size_rsc_mgc_in_wire_d[5] => Add1.IN17
+cursor_size_rsc_mgc_in_wire_d[5] => Add3.IN17
+cursor_size_rsc_mgc_in_wire_d[5] => Add5.IN17
+cursor_size_rsc_mgc_in_wire_d[5] => Add7.IN17
+cursor_size_rsc_mgc_in_wire_d[6] => Add1.IN16
+cursor_size_rsc_mgc_in_wire_d[6] => Add3.IN16
+cursor_size_rsc_mgc_in_wire_d[6] => Add5.IN16
+cursor_size_rsc_mgc_in_wire_d[6] => Add7.IN16
+cursor_size_rsc_mgc_in_wire_d[7] => Add1.IN15
+cursor_size_rsc_mgc_in_wire_d[7] => Add3.IN15
+cursor_size_rsc_mgc_in_wire_d[7] => Add5.IN15
+cursor_size_rsc_mgc_in_wire_d[7] => Add7.IN15
+video_in_rsc_mgc_in_wire_d[0] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[1] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[2] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[3] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[4] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[5] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[6] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[7] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[8] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[9] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_2.IN1
+video_in_rsc_mgc_in_wire_d[10] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].DATAIN
+video_in_rsc_mgc_in_wire_d[11] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].DATAIN
+video_in_rsc_mgc_in_wire_d[12] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].DATAIN
+video_in_rsc_mgc_in_wire_d[13] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].DATAIN
+video_in_rsc_mgc_in_wire_d[14] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].DATAIN
+video_in_rsc_mgc_in_wire_d[15] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].DATAIN
+video_in_rsc_mgc_in_wire_d[16] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].DATAIN
+video_in_rsc_mgc_in_wire_d[17] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].DATAIN
+video_in_rsc_mgc_in_wire_d[18] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].DATAIN
+video_in_rsc_mgc_in_wire_d[19] => reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].DATAIN
+video_in_rsc_mgc_in_wire_d[20] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[21] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[22] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[23] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[24] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[25] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[26] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[27] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[28] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_in_rsc_mgc_in_wire_d[29] => reg_video_out_rsc_mgc_out_stdreg_d_tmp.IN1
+video_out_rsc_mgc_out_stdreg_d[0] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[0].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[1] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[1].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[2] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[2].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[3] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[3].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[4] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[4].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[5] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[5].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[6] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[7] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[8] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[9] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[10] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[0].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[11] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[1].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[12] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[2].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[13] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[3].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[14] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[4].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[15] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[5].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[16] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[17] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[18] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[19] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[20] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[0].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[21] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[1].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[22] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[2].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[23] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[3].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[24] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[4].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[25] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[5].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[26] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[6].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[27] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[7].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[28] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[8].DB_MAX_OUTPUT_PORT_TYPE
+video_out_rsc_mgc_out_stdreg_d[29] <= reg_video_out_rsc_mgc_out_stdreg_d_tmp[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst
+vin_rsc_z[0] => vin_rsc_z[0].IN1
+vin_rsc_z[1] => vin_rsc_z[1].IN1
+vin_rsc_z[2] => vin_rsc_z[2].IN1
+vin_rsc_z[3] => vin_rsc_z[3].IN1
+vin_rsc_z[4] => vin_rsc_z[4].IN1
+vin_rsc_z[5] => vin_rsc_z[5].IN1
+vin_rsc_z[6] => vin_rsc_z[6].IN1
+vin_rsc_z[7] => vin_rsc_z[7].IN1
+vin_rsc_z[8] => vin_rsc_z[8].IN1
+vin_rsc_z[9] => vin_rsc_z[9].IN1
+vin_rsc_z[10] => vin_rsc_z[10].IN1
+vin_rsc_z[11] => vin_rsc_z[11].IN1
+vin_rsc_z[12] => vin_rsc_z[12].IN1
+vin_rsc_z[13] => vin_rsc_z[13].IN1
+vin_rsc_z[14] => vin_rsc_z[14].IN1
+vin_rsc_z[15] => vin_rsc_z[15].IN1
+vin_rsc_z[16] => vin_rsc_z[16].IN1
+vin_rsc_z[17] => vin_rsc_z[17].IN1
+vin_rsc_z[18] => vin_rsc_z[18].IN1
+vin_rsc_z[19] => vin_rsc_z[19].IN1
+vin_rsc_z[20] => vin_rsc_z[20].IN1
+vin_rsc_z[21] => vin_rsc_z[21].IN1
+vin_rsc_z[22] => vin_rsc_z[22].IN1
+vin_rsc_z[23] => vin_rsc_z[23].IN1
+vin_rsc_z[24] => vin_rsc_z[24].IN1
+vin_rsc_z[25] => vin_rsc_z[25].IN1
+vin_rsc_z[26] => vin_rsc_z[26].IN1
+vin_rsc_z[27] => vin_rsc_z[27].IN1
+vin_rsc_z[28] => vin_rsc_z[28].IN1
+vin_rsc_z[29] => vin_rsc_z[29].IN1
+vin_rsc_z[30] => vin_rsc_z[30].IN1
+vin_rsc_z[31] => vin_rsc_z[31].IN1
+vin_rsc_z[32] => vin_rsc_z[32].IN1
+vin_rsc_z[33] => vin_rsc_z[33].IN1
+vin_rsc_z[34] => vin_rsc_z[34].IN1
+vin_rsc_z[35] => vin_rsc_z[35].IN1
+vin_rsc_z[36] => vin_rsc_z[36].IN1
+vin_rsc_z[37] => vin_rsc_z[37].IN1
+vin_rsc_z[38] => vin_rsc_z[38].IN1
+vin_rsc_z[39] => vin_rsc_z[39].IN1
+vin_rsc_z[40] => vin_rsc_z[40].IN1
+vin_rsc_z[41] => vin_rsc_z[41].IN1
+vin_rsc_z[42] => vin_rsc_z[42].IN1
+vin_rsc_z[43] => vin_rsc_z[43].IN1
+vin_rsc_z[44] => vin_rsc_z[44].IN1
+vin_rsc_z[45] => vin_rsc_z[45].IN1
+vin_rsc_z[46] => vin_rsc_z[46].IN1
+vin_rsc_z[47] => vin_rsc_z[47].IN1
+vin_rsc_z[48] => vin_rsc_z[48].IN1
+vin_rsc_z[49] => vin_rsc_z[49].IN1
+vin_rsc_z[50] => vin_rsc_z[50].IN1
+vin_rsc_z[51] => vin_rsc_z[51].IN1
+vin_rsc_z[52] => vin_rsc_z[52].IN1
+vin_rsc_z[53] => vin_rsc_z[53].IN1
+vin_rsc_z[54] => vin_rsc_z[54].IN1
+vin_rsc_z[55] => vin_rsc_z[55].IN1
+vin_rsc_z[56] => vin_rsc_z[56].IN1
+vin_rsc_z[57] => vin_rsc_z[57].IN1
+vin_rsc_z[58] => vin_rsc_z[58].IN1
+vin_rsc_z[59] => vin_rsc_z[59].IN1
+vin_rsc_z[60] => vin_rsc_z[60].IN1
+vin_rsc_z[61] => vin_rsc_z[61].IN1
+vin_rsc_z[62] => vin_rsc_z[62].IN1
+vin_rsc_z[63] => vin_rsc_z[63].IN1
+vin_rsc_z[64] => vin_rsc_z[64].IN1
+vin_rsc_z[65] => vin_rsc_z[65].IN1
+vin_rsc_z[66] => vin_rsc_z[66].IN1
+vin_rsc_z[67] => vin_rsc_z[67].IN1
+vin_rsc_z[68] => vin_rsc_z[68].IN1
+vin_rsc_z[69] => vin_rsc_z[69].IN1
+vin_rsc_z[70] => vin_rsc_z[70].IN1
+vin_rsc_z[71] => vin_rsc_z[71].IN1
+vin_rsc_z[72] => vin_rsc_z[72].IN1
+vin_rsc_z[73] => vin_rsc_z[73].IN1
+vin_rsc_z[74] => vin_rsc_z[74].IN1
+vin_rsc_z[75] => vin_rsc_z[75].IN1
+vin_rsc_z[76] => vin_rsc_z[76].IN1
+vin_rsc_z[77] => vin_rsc_z[77].IN1
+vin_rsc_z[78] => vin_rsc_z[78].IN1
+vin_rsc_z[79] => vin_rsc_z[79].IN1
+vin_rsc_z[80] => vin_rsc_z[80].IN1
+vin_rsc_z[81] => vin_rsc_z[81].IN1
+vin_rsc_z[82] => vin_rsc_z[82].IN1
+vin_rsc_z[83] => vin_rsc_z[83].IN1
+vin_rsc_z[84] => vin_rsc_z[84].IN1
+vin_rsc_z[85] => vin_rsc_z[85].IN1
+vin_rsc_z[86] => vin_rsc_z[86].IN1
+vin_rsc_z[87] => vin_rsc_z[87].IN1
+vin_rsc_z[88] => vin_rsc_z[88].IN1
+vin_rsc_z[89] => vin_rsc_z[89].IN1
+vout_rsc_z[0] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[1] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[2] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[3] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[4] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[5] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[6] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[7] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[8] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[9] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[10] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[11] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[12] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[13] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[14] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[15] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[16] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[17] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[18] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[19] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[20] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[21] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[22] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[23] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[24] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[25] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[26] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[27] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[28] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+vout_rsc_z[29] <= mgc_out_stdreg:vout_rsc_mgc_out_stdreg.z
+clk => clk.IN1
+en => en.IN1
+arst_n => arst_n.IN1
+
+
+|TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+d[8] <= z[8].DB_MAX_OUTPUT_PORT_TYPE
+d[9] <= z[9].DB_MAX_OUTPUT_PORT_TYPE
+d[10] <= z[10].DB_MAX_OUTPUT_PORT_TYPE
+d[11] <= z[11].DB_MAX_OUTPUT_PORT_TYPE
+d[12] <= z[12].DB_MAX_OUTPUT_PORT_TYPE
+d[13] <= z[13].DB_MAX_OUTPUT_PORT_TYPE
+d[14] <= z[14].DB_MAX_OUTPUT_PORT_TYPE
+d[15] <= z[15].DB_MAX_OUTPUT_PORT_TYPE
+d[16] <= z[16].DB_MAX_OUTPUT_PORT_TYPE
+d[17] <= z[17].DB_MAX_OUTPUT_PORT_TYPE
+d[18] <= z[18].DB_MAX_OUTPUT_PORT_TYPE
+d[19] <= z[19].DB_MAX_OUTPUT_PORT_TYPE
+d[20] <= z[20].DB_MAX_OUTPUT_PORT_TYPE
+d[21] <= z[21].DB_MAX_OUTPUT_PORT_TYPE
+d[22] <= z[22].DB_MAX_OUTPUT_PORT_TYPE
+d[23] <= z[23].DB_MAX_OUTPUT_PORT_TYPE
+d[24] <= z[24].DB_MAX_OUTPUT_PORT_TYPE
+d[25] <= z[25].DB_MAX_OUTPUT_PORT_TYPE
+d[26] <= z[26].DB_MAX_OUTPUT_PORT_TYPE
+d[27] <= z[27].DB_MAX_OUTPUT_PORT_TYPE
+d[28] <= z[28].DB_MAX_OUTPUT_PORT_TYPE
+d[29] <= z[29].DB_MAX_OUTPUT_PORT_TYPE
+d[30] <= z[30].DB_MAX_OUTPUT_PORT_TYPE
+d[31] <= z[31].DB_MAX_OUTPUT_PORT_TYPE
+d[32] <= z[32].DB_MAX_OUTPUT_PORT_TYPE
+d[33] <= z[33].DB_MAX_OUTPUT_PORT_TYPE
+d[34] <= z[34].DB_MAX_OUTPUT_PORT_TYPE
+d[35] <= z[35].DB_MAX_OUTPUT_PORT_TYPE
+d[36] <= z[36].DB_MAX_OUTPUT_PORT_TYPE
+d[37] <= z[37].DB_MAX_OUTPUT_PORT_TYPE
+d[38] <= z[38].DB_MAX_OUTPUT_PORT_TYPE
+d[39] <= z[39].DB_MAX_OUTPUT_PORT_TYPE
+d[40] <= z[40].DB_MAX_OUTPUT_PORT_TYPE
+d[41] <= z[41].DB_MAX_OUTPUT_PORT_TYPE
+d[42] <= z[42].DB_MAX_OUTPUT_PORT_TYPE
+d[43] <= z[43].DB_MAX_OUTPUT_PORT_TYPE
+d[44] <= z[44].DB_MAX_OUTPUT_PORT_TYPE
+d[45] <= z[45].DB_MAX_OUTPUT_PORT_TYPE
+d[46] <= z[46].DB_MAX_OUTPUT_PORT_TYPE
+d[47] <= z[47].DB_MAX_OUTPUT_PORT_TYPE
+d[48] <= z[48].DB_MAX_OUTPUT_PORT_TYPE
+d[49] <= z[49].DB_MAX_OUTPUT_PORT_TYPE
+d[50] <= z[50].DB_MAX_OUTPUT_PORT_TYPE
+d[51] <= z[51].DB_MAX_OUTPUT_PORT_TYPE
+d[52] <= z[52].DB_MAX_OUTPUT_PORT_TYPE
+d[53] <= z[53].DB_MAX_OUTPUT_PORT_TYPE
+d[54] <= z[54].DB_MAX_OUTPUT_PORT_TYPE
+d[55] <= z[55].DB_MAX_OUTPUT_PORT_TYPE
+d[56] <= z[56].DB_MAX_OUTPUT_PORT_TYPE
+d[57] <= z[57].DB_MAX_OUTPUT_PORT_TYPE
+d[58] <= z[58].DB_MAX_OUTPUT_PORT_TYPE
+d[59] <= z[59].DB_MAX_OUTPUT_PORT_TYPE
+d[60] <= z[60].DB_MAX_OUTPUT_PORT_TYPE
+d[61] <= z[61].DB_MAX_OUTPUT_PORT_TYPE
+d[62] <= z[62].DB_MAX_OUTPUT_PORT_TYPE
+d[63] <= z[63].DB_MAX_OUTPUT_PORT_TYPE
+d[64] <= z[64].DB_MAX_OUTPUT_PORT_TYPE
+d[65] <= z[65].DB_MAX_OUTPUT_PORT_TYPE
+d[66] <= z[66].DB_MAX_OUTPUT_PORT_TYPE
+d[67] <= z[67].DB_MAX_OUTPUT_PORT_TYPE
+d[68] <= z[68].DB_MAX_OUTPUT_PORT_TYPE
+d[69] <= z[69].DB_MAX_OUTPUT_PORT_TYPE
+d[70] <= z[70].DB_MAX_OUTPUT_PORT_TYPE
+d[71] <= z[71].DB_MAX_OUTPUT_PORT_TYPE
+d[72] <= z[72].DB_MAX_OUTPUT_PORT_TYPE
+d[73] <= z[73].DB_MAX_OUTPUT_PORT_TYPE
+d[74] <= z[74].DB_MAX_OUTPUT_PORT_TYPE
+d[75] <= z[75].DB_MAX_OUTPUT_PORT_TYPE
+d[76] <= z[76].DB_MAX_OUTPUT_PORT_TYPE
+d[77] <= z[77].DB_MAX_OUTPUT_PORT_TYPE
+d[78] <= z[78].DB_MAX_OUTPUT_PORT_TYPE
+d[79] <= z[79].DB_MAX_OUTPUT_PORT_TYPE
+d[80] <= z[80].DB_MAX_OUTPUT_PORT_TYPE
+d[81] <= z[81].DB_MAX_OUTPUT_PORT_TYPE
+d[82] <= z[82].DB_MAX_OUTPUT_PORT_TYPE
+d[83] <= z[83].DB_MAX_OUTPUT_PORT_TYPE
+d[84] <= z[84].DB_MAX_OUTPUT_PORT_TYPE
+d[85] <= z[85].DB_MAX_OUTPUT_PORT_TYPE
+d[86] <= z[86].DB_MAX_OUTPUT_PORT_TYPE
+d[87] <= z[87].DB_MAX_OUTPUT_PORT_TYPE
+d[88] <= z[88].DB_MAX_OUTPUT_PORT_TYPE
+d[89] <= z[89].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+z[8] => d[8].DATAIN
+z[9] => d[9].DATAIN
+z[10] => d[10].DATAIN
+z[11] => d[11].DATAIN
+z[12] => d[12].DATAIN
+z[13] => d[13].DATAIN
+z[14] => d[14].DATAIN
+z[15] => d[15].DATAIN
+z[16] => d[16].DATAIN
+z[17] => d[17].DATAIN
+z[18] => d[18].DATAIN
+z[19] => d[19].DATAIN
+z[20] => d[20].DATAIN
+z[21] => d[21].DATAIN
+z[22] => d[22].DATAIN
+z[23] => d[23].DATAIN
+z[24] => d[24].DATAIN
+z[25] => d[25].DATAIN
+z[26] => d[26].DATAIN
+z[27] => d[27].DATAIN
+z[28] => d[28].DATAIN
+z[29] => d[29].DATAIN
+z[30] => d[30].DATAIN
+z[31] => d[31].DATAIN
+z[32] => d[32].DATAIN
+z[33] => d[33].DATAIN
+z[34] => d[34].DATAIN
+z[35] => d[35].DATAIN
+z[36] => d[36].DATAIN
+z[37] => d[37].DATAIN
+z[38] => d[38].DATAIN
+z[39] => d[39].DATAIN
+z[40] => d[40].DATAIN
+z[41] => d[41].DATAIN
+z[42] => d[42].DATAIN
+z[43] => d[43].DATAIN
+z[44] => d[44].DATAIN
+z[45] => d[45].DATAIN
+z[46] => d[46].DATAIN
+z[47] => d[47].DATAIN
+z[48] => d[48].DATAIN
+z[49] => d[49].DATAIN
+z[50] => d[50].DATAIN
+z[51] => d[51].DATAIN
+z[52] => d[52].DATAIN
+z[53] => d[53].DATAIN
+z[54] => d[54].DATAIN
+z[55] => d[55].DATAIN
+z[56] => d[56].DATAIN
+z[57] => d[57].DATAIN
+z[58] => d[58].DATAIN
+z[59] => d[59].DATAIN
+z[60] => d[60].DATAIN
+z[61] => d[61].DATAIN
+z[62] => d[62].DATAIN
+z[63] => d[63].DATAIN
+z[64] => d[64].DATAIN
+z[65] => d[65].DATAIN
+z[66] => d[66].DATAIN
+z[67] => d[67].DATAIN
+z[68] => d[68].DATAIN
+z[69] => d[69].DATAIN
+z[70] => d[70].DATAIN
+z[71] => d[71].DATAIN
+z[72] => d[72].DATAIN
+z[73] => d[73].DATAIN
+z[74] => d[74].DATAIN
+z[75] => d[75].DATAIN
+z[76] => d[76].DATAIN
+z[77] => d[77].DATAIN
+z[78] => d[78].DATAIN
+z[79] => d[79].DATAIN
+z[80] => d[80].DATAIN
+z[81] => d[81].DATAIN
+z[82] => d[82].DATAIN
+z[83] => d[83].DATAIN
+z[84] => d[84].DATAIN
+z[85] => d[85].DATAIN
+z[86] => d[86].DATAIN
+z[87] => d[87].DATAIN
+z[88] => d[88].DATAIN
+z[89] => d[89].DATAIN
+
+
+|TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+d[0] => z[0].DATAIN
+d[1] => z[1].DATAIN
+d[2] => z[2].DATAIN
+d[3] => z[3].DATAIN
+d[4] => z[4].DATAIN
+d[5] => z[5].DATAIN
+d[6] => z[6].DATAIN
+d[7] => z[7].DATAIN
+d[8] => z[8].DATAIN
+d[9] => z[9].DATAIN
+d[10] => z[10].DATAIN
+d[11] => z[11].DATAIN
+d[12] => z[12].DATAIN
+d[13] => z[13].DATAIN
+d[14] => z[14].DATAIN
+d[15] => z[15].DATAIN
+d[16] => z[16].DATAIN
+d[17] => z[17].DATAIN
+d[18] => z[18].DATAIN
+d[19] => z[19].DATAIN
+d[20] => z[20].DATAIN
+d[21] => z[21].DATAIN
+d[22] => z[22].DATAIN
+d[23] => z[23].DATAIN
+d[24] => z[24].DATAIN
+d[25] => z[25].DATAIN
+d[26] => z[26].DATAIN
+d[27] => z[27].DATAIN
+d[28] => z[28].DATAIN
+d[29] => z[29].DATAIN
+z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
+z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
+z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
+z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
+z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
+z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
+z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
+z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
+z[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE
+z[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE
+z[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE
+z[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE
+z[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE
+z[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE
+z[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE
+z[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE
+z[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE
+z[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE
+z[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE
+z[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE
+z[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE
+z[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE
+z[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE
+z[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE
+z[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE
+z[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE
+z[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE
+z[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE
+z[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE
+z[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[0].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[1].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[2].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[3].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[4].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[5].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[0].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[1].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[2].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[3].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[4].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[0].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[0].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[1].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[2].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[3].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[4].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[5].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[6].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[7].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[8].CLK
+clk => reg_vout_rsc_mgc_out_stdreg_d_tmp[9].CLK
+clk => slc_regs_regs_2_itm[0].CLK
+clk => slc_regs_regs_2_itm[1].CLK
+clk => slc_regs_regs_2_itm[2].CLK
+clk => slc_regs_regs_2_itm[3].CLK
+clk => slc_regs_regs_2_itm[4].CLK
+clk => slc_regs_regs_2_itm[5].CLK
+clk => slc_regs_regs_2_itm[6].CLK
+clk => slc_regs_regs_2_itm[7].CLK
+clk => slc_regs_regs_2_itm[8].CLK
+clk => slc_regs_regs_2_itm[9].CLK
+clk => slc_regs_regs_2_2_itm[0].CLK
+clk => slc_regs_regs_2_2_itm[1].CLK
+clk => slc_regs_regs_2_2_itm[2].CLK
+clk => slc_regs_regs_2_2_itm[3].CLK
+clk => slc_regs_regs_2_2_itm[4].CLK
+clk => slc_regs_regs_2_2_itm[5].CLK
+clk => slc_regs_regs_2_2_itm[6].CLK
+clk => slc_regs_regs_2_2_itm[7].CLK
+clk => slc_regs_regs_2_2_itm[8].CLK
+clk => slc_regs_regs_2_2_itm[9].CLK
+clk => slc_regs_regs_2_1_itm[0].CLK
+clk => slc_regs_regs_2_1_itm[1].CLK
+clk => slc_regs_regs_2_1_itm[2].CLK
+clk => slc_regs_regs_2_1_itm[3].CLK
+clk => slc_regs_regs_2_1_itm[4].CLK
+clk => slc_regs_regs_2_1_itm[5].CLK
+clk => slc_regs_regs_2_1_itm[6].CLK
+clk => slc_regs_regs_2_1_itm[7].CLK
+clk => slc_regs_regs_2_1_itm[8].CLK
+clk => slc_regs_regs_2_1_itm[9].CLK
+clk => slc_regs_regs_2_3_itm[0].CLK
+clk => slc_regs_regs_2_3_itm[1].CLK
+clk => slc_regs_regs_2_3_itm[2].CLK
+clk => slc_regs_regs_2_3_itm[3].CLK
+clk => slc_regs_regs_2_3_itm[4].CLK
+clk => slc_regs_regs_2_3_itm[5].CLK
+clk => slc_regs_regs_2_3_itm[6].CLK
+clk => slc_regs_regs_2_3_itm[7].CLK
+clk => slc_regs_regs_2_3_itm[8].CLK
+clk => slc_regs_regs_2_3_itm[9].CLK
+clk => slc_regs_regs_2_5_itm[0].CLK
+clk => slc_regs_regs_2_5_itm[1].CLK
+clk => slc_regs_regs_2_5_itm[2].CLK
+clk => slc_regs_regs_2_5_itm[3].CLK
+clk => slc_regs_regs_2_5_itm[4].CLK
+clk => slc_regs_regs_2_5_itm[5].CLK
+clk => slc_regs_regs_2_5_itm[6].CLK
+clk => slc_regs_regs_2_5_itm[7].CLK
+clk => slc_regs_regs_2_5_itm[8].CLK
+clk => slc_regs_regs_2_5_itm[9].CLK
+clk => slc_regs_regs_2_4_itm[0].CLK
+clk => slc_regs_regs_2_4_itm[1].CLK
+clk => slc_regs_regs_2_4_itm[2].CLK
+clk => slc_regs_regs_2_4_itm[3].CLK
+clk => slc_regs_regs_2_4_itm[4].CLK
+clk => slc_regs_regs_2_4_itm[5].CLK
+clk => slc_regs_regs_2_4_itm[6].CLK
+clk => slc_regs_regs_2_4_itm[7].CLK
+clk => slc_regs_regs_2_4_itm[8].CLK
+clk => slc_regs_regs_2_4_itm[9].CLK
+clk => slc_regs_regs_2_6_itm[0].CLK
+clk => slc_regs_regs_2_6_itm[1].CLK
+clk => slc_regs_regs_2_6_itm[2].CLK
+clk => slc_regs_regs_2_6_itm[3].CLK
+clk => slc_regs_regs_2_6_itm[4].CLK
+clk => slc_regs_regs_2_6_itm[5].CLK
+clk => slc_regs_regs_2_6_itm[6].CLK
+clk => slc_regs_regs_2_6_itm[7].CLK
+clk => slc_regs_regs_2_6_itm[8].CLK
+clk => slc_regs_regs_2_6_itm[9].CLK
+clk => reg_regs_regs_0_sva_cse[0].CLK
+clk => reg_regs_regs_0_sva_cse[1].CLK
+clk => reg_regs_regs_0_sva_cse[2].CLK
+clk => reg_regs_regs_0_sva_cse[3].CLK
+clk => reg_regs_regs_0_sva_cse[4].CLK
+clk => reg_regs_regs_0_sva_cse[5].CLK
+clk => reg_regs_regs_0_sva_cse[6].CLK
+clk => reg_regs_regs_0_sva_cse[7].CLK
+clk => reg_regs_regs_0_sva_cse[8].CLK
+clk => reg_regs_regs_0_sva_cse[9].CLK
+clk => reg_regs_regs_0_sva_cse[10].CLK
+clk => reg_regs_regs_0_sva_cse[11].CLK
+clk => reg_regs_regs_0_sva_cse[12].CLK
+clk => reg_regs_regs_0_sva_cse[13].CLK
+clk => reg_regs_regs_0_sva_cse[14].CLK
+clk => reg_regs_regs_0_sva_cse[15].CLK
+clk => reg_regs_regs_0_sva_cse[16].CLK
+clk => reg_regs_regs_0_sva_cse[17].CLK
+clk => reg_regs_regs_0_sva_cse[18].CLK
+clk => reg_regs_regs_0_sva_cse[19].CLK
+clk => reg_regs_regs_0_sva_cse[20].CLK
+clk => reg_regs_regs_0_sva_cse[21].CLK
+clk => reg_regs_regs_0_sva_cse[22].CLK
+clk => reg_regs_regs_0_sva_cse[23].CLK
+clk => reg_regs_regs_0_sva_cse[24].CLK
+clk => reg_regs_regs_0_sva_cse[25].CLK
+clk => reg_regs_regs_0_sva_cse[26].CLK
+clk => reg_regs_regs_0_sva_cse[27].CLK
+clk => reg_regs_regs_0_sva_cse[28].CLK
+clk => reg_regs_regs_0_sva_cse[29].CLK
+clk => reg_regs_regs_0_sva_cse[30].CLK
+clk => reg_regs_regs_0_sva_cse[31].CLK
+clk => reg_regs_regs_0_sva_cse[32].CLK
+clk => reg_regs_regs_0_sva_cse[33].CLK
+clk => reg_regs_regs_0_sva_cse[34].CLK
+clk => reg_regs_regs_0_sva_cse[35].CLK
+clk => reg_regs_regs_0_sva_cse[36].CLK
+clk => reg_regs_regs_0_sva_cse[37].CLK
+clk => reg_regs_regs_0_sva_cse[38].CLK
+clk => reg_regs_regs_0_sva_cse[39].CLK
+clk => reg_regs_regs_0_sva_cse[40].CLK
+clk => reg_regs_regs_0_sva_cse[41].CLK
+clk => reg_regs_regs_0_sva_cse[42].CLK
+clk => reg_regs_regs_0_sva_cse[43].CLK
+clk => reg_regs_regs_0_sva_cse[44].CLK
+clk => reg_regs_regs_0_sva_cse[45].CLK
+clk => reg_regs_regs_0_sva_cse[46].CLK
+clk => reg_regs_regs_0_sva_cse[47].CLK
+clk => reg_regs_regs_0_sva_cse[48].CLK
+clk => reg_regs_regs_0_sva_cse[49].CLK
+clk => reg_regs_regs_0_sva_cse[50].CLK
+clk => reg_regs_regs_0_sva_cse[51].CLK
+clk => reg_regs_regs_0_sva_cse[52].CLK
+clk => reg_regs_regs_0_sva_cse[53].CLK
+clk => reg_regs_regs_0_sva_cse[54].CLK
+clk => reg_regs_regs_0_sva_cse[55].CLK
+clk => reg_regs_regs_0_sva_cse[56].CLK
+clk => reg_regs_regs_0_sva_cse[57].CLK
+clk => reg_regs_regs_0_sva_cse[58].CLK
+clk => reg_regs_regs_0_sva_cse[59].CLK
+clk => reg_regs_regs_0_sva_cse[60].CLK
+clk => reg_regs_regs_0_sva_cse[61].CLK
+clk => reg_regs_regs_0_sva_cse[62].CLK
+clk => reg_regs_regs_0_sva_cse[63].CLK
+clk => reg_regs_regs_0_sva_cse[64].CLK
+clk => reg_regs_regs_0_sva_cse[65].CLK
+clk => reg_regs_regs_0_sva_cse[66].CLK
+clk => reg_regs_regs_0_sva_cse[67].CLK
+clk => reg_regs_regs_0_sva_cse[68].CLK
+clk => reg_regs_regs_0_sva_cse[69].CLK
+clk => reg_regs_regs_0_sva_cse[70].CLK
+clk => reg_regs_regs_0_sva_cse[71].CLK
+clk => reg_regs_regs_0_sva_cse[72].CLK
+clk => reg_regs_regs_0_sva_cse[73].CLK
+clk => reg_regs_regs_0_sva_cse[74].CLK
+clk => reg_regs_regs_0_sva_cse[75].CLK
+clk => reg_regs_regs_0_sva_cse[76].CLK
+clk => reg_regs_regs_0_sva_cse[77].CLK
+clk => reg_regs_regs_0_sva_cse[78].CLK
+clk => reg_regs_regs_0_sva_cse[79].CLK
+clk => reg_regs_regs_0_sva_cse[80].CLK
+clk => reg_regs_regs_0_sva_cse[81].CLK
+clk => reg_regs_regs_0_sva_cse[82].CLK
+clk => reg_regs_regs_0_sva_cse[83].CLK
+clk => reg_regs_regs_0_sva_cse[84].CLK
+clk => reg_regs_regs_0_sva_cse[85].CLK
+clk => reg_regs_regs_0_sva_cse[86].CLK
+clk => reg_regs_regs_0_sva_cse[87].CLK
+clk => reg_regs_regs_0_sva_cse[88].CLK
+clk => reg_regs_regs_0_sva_cse[89].CLK
+clk => slc_regs_regs_2_8_itm[0].CLK
+clk => slc_regs_regs_2_8_itm[1].CLK
+clk => slc_regs_regs_2_8_itm[2].CLK
+clk => slc_regs_regs_2_8_itm[3].CLK
+clk => slc_regs_regs_2_8_itm[4].CLK
+clk => slc_regs_regs_2_8_itm[5].CLK
+clk => slc_regs_regs_2_8_itm[6].CLK
+clk => slc_regs_regs_2_8_itm[7].CLK
+clk => slc_regs_regs_2_8_itm[8].CLK
+clk => slc_regs_regs_2_8_itm[9].CLK
+clk => slc_regs_regs_2_7_itm[0].CLK
+clk => slc_regs_regs_2_7_itm[1].CLK
+clk => slc_regs_regs_2_7_itm[2].CLK
+clk => slc_regs_regs_2_7_itm[3].CLK
+clk => slc_regs_regs_2_7_itm[4].CLK
+clk => slc_regs_regs_2_7_itm[5].CLK
+clk => slc_regs_regs_2_7_itm[6].CLK
+clk => slc_regs_regs_2_7_itm[7].CLK
+clk => slc_regs_regs_2_7_itm[8].CLK
+clk => slc_regs_regs_2_7_itm[9].CLK
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[0].ENA
+en => slc_regs_regs_2_7_itm[9].ENA
+en => slc_regs_regs_2_7_itm[8].ENA
+en => slc_regs_regs_2_7_itm[7].ENA
+en => slc_regs_regs_2_7_itm[6].ENA
+en => slc_regs_regs_2_7_itm[5].ENA
+en => slc_regs_regs_2_7_itm[4].ENA
+en => slc_regs_regs_2_7_itm[3].ENA
+en => slc_regs_regs_2_7_itm[2].ENA
+en => slc_regs_regs_2_7_itm[1].ENA
+en => slc_regs_regs_2_7_itm[0].ENA
+en => slc_regs_regs_2_8_itm[9].ENA
+en => slc_regs_regs_2_8_itm[8].ENA
+en => slc_regs_regs_2_8_itm[7].ENA
+en => slc_regs_regs_2_8_itm[6].ENA
+en => slc_regs_regs_2_8_itm[5].ENA
+en => slc_regs_regs_2_8_itm[4].ENA
+en => slc_regs_regs_2_8_itm[3].ENA
+en => slc_regs_regs_2_8_itm[2].ENA
+en => slc_regs_regs_2_8_itm[1].ENA
+en => slc_regs_regs_2_8_itm[0].ENA
+en => reg_regs_regs_0_sva_cse[89].ENA
+en => reg_regs_regs_0_sva_cse[88].ENA
+en => reg_regs_regs_0_sva_cse[87].ENA
+en => reg_regs_regs_0_sva_cse[86].ENA
+en => reg_regs_regs_0_sva_cse[85].ENA
+en => reg_regs_regs_0_sva_cse[84].ENA
+en => reg_regs_regs_0_sva_cse[83].ENA
+en => reg_regs_regs_0_sva_cse[82].ENA
+en => reg_regs_regs_0_sva_cse[81].ENA
+en => reg_regs_regs_0_sva_cse[80].ENA
+en => reg_regs_regs_0_sva_cse[79].ENA
+en => reg_regs_regs_0_sva_cse[78].ENA
+en => reg_regs_regs_0_sva_cse[77].ENA
+en => reg_regs_regs_0_sva_cse[76].ENA
+en => reg_regs_regs_0_sva_cse[75].ENA
+en => reg_regs_regs_0_sva_cse[74].ENA
+en => reg_regs_regs_0_sva_cse[73].ENA
+en => reg_regs_regs_0_sva_cse[72].ENA
+en => reg_regs_regs_0_sva_cse[71].ENA
+en => reg_regs_regs_0_sva_cse[70].ENA
+en => reg_regs_regs_0_sva_cse[69].ENA
+en => reg_regs_regs_0_sva_cse[68].ENA
+en => reg_regs_regs_0_sva_cse[67].ENA
+en => reg_regs_regs_0_sva_cse[66].ENA
+en => reg_regs_regs_0_sva_cse[65].ENA
+en => reg_regs_regs_0_sva_cse[64].ENA
+en => reg_regs_regs_0_sva_cse[63].ENA
+en => reg_regs_regs_0_sva_cse[62].ENA
+en => reg_regs_regs_0_sva_cse[61].ENA
+en => reg_regs_regs_0_sva_cse[60].ENA
+en => reg_regs_regs_0_sva_cse[59].ENA
+en => reg_regs_regs_0_sva_cse[58].ENA
+en => reg_regs_regs_0_sva_cse[57].ENA
+en => reg_regs_regs_0_sva_cse[56].ENA
+en => reg_regs_regs_0_sva_cse[55].ENA
+en => reg_regs_regs_0_sva_cse[54].ENA
+en => reg_regs_regs_0_sva_cse[53].ENA
+en => reg_regs_regs_0_sva_cse[52].ENA
+en => reg_regs_regs_0_sva_cse[51].ENA
+en => reg_regs_regs_0_sva_cse[50].ENA
+en => reg_regs_regs_0_sva_cse[49].ENA
+en => reg_regs_regs_0_sva_cse[48].ENA
+en => reg_regs_regs_0_sva_cse[47].ENA
+en => reg_regs_regs_0_sva_cse[46].ENA
+en => reg_regs_regs_0_sva_cse[45].ENA
+en => reg_regs_regs_0_sva_cse[44].ENA
+en => reg_regs_regs_0_sva_cse[43].ENA
+en => reg_regs_regs_0_sva_cse[42].ENA
+en => reg_regs_regs_0_sva_cse[41].ENA
+en => reg_regs_regs_0_sva_cse[40].ENA
+en => reg_regs_regs_0_sva_cse[39].ENA
+en => reg_regs_regs_0_sva_cse[38].ENA
+en => reg_regs_regs_0_sva_cse[37].ENA
+en => reg_regs_regs_0_sva_cse[36].ENA
+en => reg_regs_regs_0_sva_cse[35].ENA
+en => reg_regs_regs_0_sva_cse[34].ENA
+en => reg_regs_regs_0_sva_cse[33].ENA
+en => reg_regs_regs_0_sva_cse[32].ENA
+en => reg_regs_regs_0_sva_cse[31].ENA
+en => reg_regs_regs_0_sva_cse[30].ENA
+en => reg_regs_regs_0_sva_cse[29].ENA
+en => reg_regs_regs_0_sva_cse[28].ENA
+en => reg_regs_regs_0_sva_cse[27].ENA
+en => reg_regs_regs_0_sva_cse[26].ENA
+en => reg_regs_regs_0_sva_cse[25].ENA
+en => reg_regs_regs_0_sva_cse[24].ENA
+en => reg_regs_regs_0_sva_cse[23].ENA
+en => reg_regs_regs_0_sva_cse[22].ENA
+en => reg_regs_regs_0_sva_cse[21].ENA
+en => reg_regs_regs_0_sva_cse[20].ENA
+en => reg_regs_regs_0_sva_cse[19].ENA
+en => reg_regs_regs_0_sva_cse[18].ENA
+en => reg_regs_regs_0_sva_cse[17].ENA
+en => reg_regs_regs_0_sva_cse[16].ENA
+en => reg_regs_regs_0_sva_cse[15].ENA
+en => reg_regs_regs_0_sva_cse[14].ENA
+en => reg_regs_regs_0_sva_cse[13].ENA
+en => reg_regs_regs_0_sva_cse[12].ENA
+en => reg_regs_regs_0_sva_cse[11].ENA
+en => reg_regs_regs_0_sva_cse[10].ENA
+en => reg_regs_regs_0_sva_cse[9].ENA
+en => reg_regs_regs_0_sva_cse[8].ENA
+en => reg_regs_regs_0_sva_cse[7].ENA
+en => reg_regs_regs_0_sva_cse[6].ENA
+en => reg_regs_regs_0_sva_cse[5].ENA
+en => reg_regs_regs_0_sva_cse[4].ENA
+en => reg_regs_regs_0_sva_cse[3].ENA
+en => reg_regs_regs_0_sva_cse[2].ENA
+en => reg_regs_regs_0_sva_cse[1].ENA
+en => reg_regs_regs_0_sva_cse[0].ENA
+en => slc_regs_regs_2_6_itm[9].ENA
+en => slc_regs_regs_2_6_itm[8].ENA
+en => slc_regs_regs_2_6_itm[7].ENA
+en => slc_regs_regs_2_6_itm[6].ENA
+en => slc_regs_regs_2_6_itm[5].ENA
+en => slc_regs_regs_2_6_itm[4].ENA
+en => slc_regs_regs_2_6_itm[3].ENA
+en => slc_regs_regs_2_6_itm[2].ENA
+en => slc_regs_regs_2_6_itm[1].ENA
+en => slc_regs_regs_2_6_itm[0].ENA
+en => slc_regs_regs_2_4_itm[9].ENA
+en => slc_regs_regs_2_4_itm[8].ENA
+en => slc_regs_regs_2_4_itm[7].ENA
+en => slc_regs_regs_2_4_itm[6].ENA
+en => slc_regs_regs_2_4_itm[5].ENA
+en => slc_regs_regs_2_4_itm[4].ENA
+en => slc_regs_regs_2_4_itm[3].ENA
+en => slc_regs_regs_2_4_itm[2].ENA
+en => slc_regs_regs_2_4_itm[1].ENA
+en => slc_regs_regs_2_4_itm[0].ENA
+en => slc_regs_regs_2_5_itm[9].ENA
+en => slc_regs_regs_2_5_itm[8].ENA
+en => slc_regs_regs_2_5_itm[7].ENA
+en => slc_regs_regs_2_5_itm[6].ENA
+en => slc_regs_regs_2_5_itm[5].ENA
+en => slc_regs_regs_2_5_itm[4].ENA
+en => slc_regs_regs_2_5_itm[3].ENA
+en => slc_regs_regs_2_5_itm[2].ENA
+en => slc_regs_regs_2_5_itm[1].ENA
+en => slc_regs_regs_2_5_itm[0].ENA
+en => slc_regs_regs_2_3_itm[9].ENA
+en => slc_regs_regs_2_3_itm[8].ENA
+en => slc_regs_regs_2_3_itm[7].ENA
+en => slc_regs_regs_2_3_itm[6].ENA
+en => slc_regs_regs_2_3_itm[5].ENA
+en => slc_regs_regs_2_3_itm[4].ENA
+en => slc_regs_regs_2_3_itm[3].ENA
+en => slc_regs_regs_2_3_itm[2].ENA
+en => slc_regs_regs_2_3_itm[1].ENA
+en => slc_regs_regs_2_3_itm[0].ENA
+en => slc_regs_regs_2_1_itm[9].ENA
+en => slc_regs_regs_2_1_itm[8].ENA
+en => slc_regs_regs_2_1_itm[7].ENA
+en => slc_regs_regs_2_1_itm[6].ENA
+en => slc_regs_regs_2_1_itm[5].ENA
+en => slc_regs_regs_2_1_itm[4].ENA
+en => slc_regs_regs_2_1_itm[3].ENA
+en => slc_regs_regs_2_1_itm[2].ENA
+en => slc_regs_regs_2_1_itm[1].ENA
+en => slc_regs_regs_2_1_itm[0].ENA
+en => slc_regs_regs_2_2_itm[9].ENA
+en => slc_regs_regs_2_2_itm[8].ENA
+en => slc_regs_regs_2_2_itm[7].ENA
+en => slc_regs_regs_2_2_itm[6].ENA
+en => slc_regs_regs_2_2_itm[5].ENA
+en => slc_regs_regs_2_2_itm[4].ENA
+en => slc_regs_regs_2_2_itm[3].ENA
+en => slc_regs_regs_2_2_itm[2].ENA
+en => slc_regs_regs_2_2_itm[1].ENA
+en => slc_regs_regs_2_2_itm[0].ENA
+en => slc_regs_regs_2_itm[9].ENA
+en => slc_regs_regs_2_itm[8].ENA
+en => slc_regs_regs_2_itm[7].ENA
+en => slc_regs_regs_2_itm[6].ENA
+en => slc_regs_regs_2_itm[5].ENA
+en => slc_regs_regs_2_itm[4].ENA
+en => slc_regs_regs_2_itm[3].ENA
+en => slc_regs_regs_2_itm[2].ENA
+en => slc_regs_regs_2_itm[1].ENA
+en => slc_regs_regs_2_itm[0].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[9].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[8].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[7].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[6].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[5].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[4].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[3].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[2].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[1].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp[0].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[0].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[4].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[3].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[2].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[1].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[0].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[5].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[4].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[3].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[2].ENA
+en => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[1].ENA
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[0].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[1].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[2].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[3].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[4].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[5].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[0].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[1].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[2].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[3].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_2[4].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[0].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[0].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[1].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[2].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[3].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[4].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[5].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[6].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[7].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[8].ACLR
+arst_n => reg_vout_rsc_mgc_out_stdreg_d_tmp[9].ACLR
+arst_n => slc_regs_regs_2_itm[0].ACLR
+arst_n => slc_regs_regs_2_itm[1].ACLR
+arst_n => slc_regs_regs_2_itm[2].ACLR
+arst_n => slc_regs_regs_2_itm[3].ACLR
+arst_n => slc_regs_regs_2_itm[4].ACLR
+arst_n => slc_regs_regs_2_itm[5].ACLR
+arst_n => slc_regs_regs_2_itm[6].ACLR
+arst_n => slc_regs_regs_2_itm[7].ACLR
+arst_n => slc_regs_regs_2_itm[8].ACLR
+arst_n => slc_regs_regs_2_itm[9].ACLR
+arst_n => slc_regs_regs_2_2_itm[0].ACLR
+arst_n => slc_regs_regs_2_2_itm[1].ACLR
+arst_n => slc_regs_regs_2_2_itm[2].ACLR
+arst_n => slc_regs_regs_2_2_itm[3].ACLR
+arst_n => slc_regs_regs_2_2_itm[4].ACLR
+arst_n => slc_regs_regs_2_2_itm[5].ACLR
+arst_n => slc_regs_regs_2_2_itm[6].ACLR
+arst_n => slc_regs_regs_2_2_itm[7].ACLR
+arst_n => slc_regs_regs_2_2_itm[8].ACLR
+arst_n => slc_regs_regs_2_2_itm[9].ACLR
+arst_n => slc_regs_regs_2_1_itm[0].ACLR
+arst_n => slc_regs_regs_2_1_itm[1].ACLR
+arst_n => slc_regs_regs_2_1_itm[2].ACLR
+arst_n => slc_regs_regs_2_1_itm[3].ACLR
+arst_n => slc_regs_regs_2_1_itm[4].ACLR
+arst_n => slc_regs_regs_2_1_itm[5].ACLR
+arst_n => slc_regs_regs_2_1_itm[6].ACLR
+arst_n => slc_regs_regs_2_1_itm[7].ACLR
+arst_n => slc_regs_regs_2_1_itm[8].ACLR
+arst_n => slc_regs_regs_2_1_itm[9].ACLR
+arst_n => slc_regs_regs_2_3_itm[0].ACLR
+arst_n => slc_regs_regs_2_3_itm[1].ACLR
+arst_n => slc_regs_regs_2_3_itm[2].ACLR
+arst_n => slc_regs_regs_2_3_itm[3].ACLR
+arst_n => slc_regs_regs_2_3_itm[4].ACLR
+arst_n => slc_regs_regs_2_3_itm[5].ACLR
+arst_n => slc_regs_regs_2_3_itm[6].ACLR
+arst_n => slc_regs_regs_2_3_itm[7].ACLR
+arst_n => slc_regs_regs_2_3_itm[8].ACLR
+arst_n => slc_regs_regs_2_3_itm[9].ACLR
+arst_n => slc_regs_regs_2_5_itm[0].ACLR
+arst_n => slc_regs_regs_2_5_itm[1].ACLR
+arst_n => slc_regs_regs_2_5_itm[2].ACLR
+arst_n => slc_regs_regs_2_5_itm[3].ACLR
+arst_n => slc_regs_regs_2_5_itm[4].ACLR
+arst_n => slc_regs_regs_2_5_itm[5].ACLR
+arst_n => slc_regs_regs_2_5_itm[6].ACLR
+arst_n => slc_regs_regs_2_5_itm[7].ACLR
+arst_n => slc_regs_regs_2_5_itm[8].ACLR
+arst_n => slc_regs_regs_2_5_itm[9].ACLR
+arst_n => slc_regs_regs_2_4_itm[0].ACLR
+arst_n => slc_regs_regs_2_4_itm[1].ACLR
+arst_n => slc_regs_regs_2_4_itm[2].ACLR
+arst_n => slc_regs_regs_2_4_itm[3].ACLR
+arst_n => slc_regs_regs_2_4_itm[4].ACLR
+arst_n => slc_regs_regs_2_4_itm[5].ACLR
+arst_n => slc_regs_regs_2_4_itm[6].ACLR
+arst_n => slc_regs_regs_2_4_itm[7].ACLR
+arst_n => slc_regs_regs_2_4_itm[8].ACLR
+arst_n => slc_regs_regs_2_4_itm[9].ACLR
+arst_n => slc_regs_regs_2_6_itm[0].ACLR
+arst_n => slc_regs_regs_2_6_itm[1].ACLR
+arst_n => slc_regs_regs_2_6_itm[2].ACLR
+arst_n => slc_regs_regs_2_6_itm[3].ACLR
+arst_n => slc_regs_regs_2_6_itm[4].ACLR
+arst_n => slc_regs_regs_2_6_itm[5].ACLR
+arst_n => slc_regs_regs_2_6_itm[6].ACLR
+arst_n => slc_regs_regs_2_6_itm[7].ACLR
+arst_n => slc_regs_regs_2_6_itm[8].ACLR
+arst_n => slc_regs_regs_2_6_itm[9].ACLR
+arst_n => reg_regs_regs_0_sva_cse[0].ACLR
+arst_n => reg_regs_regs_0_sva_cse[1].ACLR
+arst_n => reg_regs_regs_0_sva_cse[2].ACLR
+arst_n => reg_regs_regs_0_sva_cse[3].ACLR
+arst_n => reg_regs_regs_0_sva_cse[4].ACLR
+arst_n => reg_regs_regs_0_sva_cse[5].ACLR
+arst_n => reg_regs_regs_0_sva_cse[6].ACLR
+arst_n => reg_regs_regs_0_sva_cse[7].ACLR
+arst_n => reg_regs_regs_0_sva_cse[8].ACLR
+arst_n => reg_regs_regs_0_sva_cse[9].ACLR
+arst_n => reg_regs_regs_0_sva_cse[10].ACLR
+arst_n => reg_regs_regs_0_sva_cse[11].ACLR
+arst_n => reg_regs_regs_0_sva_cse[12].ACLR
+arst_n => reg_regs_regs_0_sva_cse[13].ACLR
+arst_n => reg_regs_regs_0_sva_cse[14].ACLR
+arst_n => reg_regs_regs_0_sva_cse[15].ACLR
+arst_n => reg_regs_regs_0_sva_cse[16].ACLR
+arst_n => reg_regs_regs_0_sva_cse[17].ACLR
+arst_n => reg_regs_regs_0_sva_cse[18].ACLR
+arst_n => reg_regs_regs_0_sva_cse[19].ACLR
+arst_n => reg_regs_regs_0_sva_cse[20].ACLR
+arst_n => reg_regs_regs_0_sva_cse[21].ACLR
+arst_n => reg_regs_regs_0_sva_cse[22].ACLR
+arst_n => reg_regs_regs_0_sva_cse[23].ACLR
+arst_n => reg_regs_regs_0_sva_cse[24].ACLR
+arst_n => reg_regs_regs_0_sva_cse[25].ACLR
+arst_n => reg_regs_regs_0_sva_cse[26].ACLR
+arst_n => reg_regs_regs_0_sva_cse[27].ACLR
+arst_n => reg_regs_regs_0_sva_cse[28].ACLR
+arst_n => reg_regs_regs_0_sva_cse[29].ACLR
+arst_n => reg_regs_regs_0_sva_cse[30].ACLR
+arst_n => reg_regs_regs_0_sva_cse[31].ACLR
+arst_n => reg_regs_regs_0_sva_cse[32].ACLR
+arst_n => reg_regs_regs_0_sva_cse[33].ACLR
+arst_n => reg_regs_regs_0_sva_cse[34].ACLR
+arst_n => reg_regs_regs_0_sva_cse[35].ACLR
+arst_n => reg_regs_regs_0_sva_cse[36].ACLR
+arst_n => reg_regs_regs_0_sva_cse[37].ACLR
+arst_n => reg_regs_regs_0_sva_cse[38].ACLR
+arst_n => reg_regs_regs_0_sva_cse[39].ACLR
+arst_n => reg_regs_regs_0_sva_cse[40].ACLR
+arst_n => reg_regs_regs_0_sva_cse[41].ACLR
+arst_n => reg_regs_regs_0_sva_cse[42].ACLR
+arst_n => reg_regs_regs_0_sva_cse[43].ACLR
+arst_n => reg_regs_regs_0_sva_cse[44].ACLR
+arst_n => reg_regs_regs_0_sva_cse[45].ACLR
+arst_n => reg_regs_regs_0_sva_cse[46].ACLR
+arst_n => reg_regs_regs_0_sva_cse[47].ACLR
+arst_n => reg_regs_regs_0_sva_cse[48].ACLR
+arst_n => reg_regs_regs_0_sva_cse[49].ACLR
+arst_n => reg_regs_regs_0_sva_cse[50].ACLR
+arst_n => reg_regs_regs_0_sva_cse[51].ACLR
+arst_n => reg_regs_regs_0_sva_cse[52].ACLR
+arst_n => reg_regs_regs_0_sva_cse[53].ACLR
+arst_n => reg_regs_regs_0_sva_cse[54].ACLR
+arst_n => reg_regs_regs_0_sva_cse[55].ACLR
+arst_n => reg_regs_regs_0_sva_cse[56].ACLR
+arst_n => reg_regs_regs_0_sva_cse[57].ACLR
+arst_n => reg_regs_regs_0_sva_cse[58].ACLR
+arst_n => reg_regs_regs_0_sva_cse[59].ACLR
+arst_n => reg_regs_regs_0_sva_cse[60].ACLR
+arst_n => reg_regs_regs_0_sva_cse[61].ACLR
+arst_n => reg_regs_regs_0_sva_cse[62].ACLR
+arst_n => reg_regs_regs_0_sva_cse[63].ACLR
+arst_n => reg_regs_regs_0_sva_cse[64].ACLR
+arst_n => reg_regs_regs_0_sva_cse[65].ACLR
+arst_n => reg_regs_regs_0_sva_cse[66].ACLR
+arst_n => reg_regs_regs_0_sva_cse[67].ACLR
+arst_n => reg_regs_regs_0_sva_cse[68].ACLR
+arst_n => reg_regs_regs_0_sva_cse[69].ACLR
+arst_n => reg_regs_regs_0_sva_cse[70].ACLR
+arst_n => reg_regs_regs_0_sva_cse[71].ACLR
+arst_n => reg_regs_regs_0_sva_cse[72].ACLR
+arst_n => reg_regs_regs_0_sva_cse[73].ACLR
+arst_n => reg_regs_regs_0_sva_cse[74].ACLR
+arst_n => reg_regs_regs_0_sva_cse[75].ACLR
+arst_n => reg_regs_regs_0_sva_cse[76].ACLR
+arst_n => reg_regs_regs_0_sva_cse[77].ACLR
+arst_n => reg_regs_regs_0_sva_cse[78].ACLR
+arst_n => reg_regs_regs_0_sva_cse[79].ACLR
+arst_n => reg_regs_regs_0_sva_cse[80].ACLR
+arst_n => reg_regs_regs_0_sva_cse[81].ACLR
+arst_n => reg_regs_regs_0_sva_cse[82].ACLR
+arst_n => reg_regs_regs_0_sva_cse[83].ACLR
+arst_n => reg_regs_regs_0_sva_cse[84].ACLR
+arst_n => reg_regs_regs_0_sva_cse[85].ACLR
+arst_n => reg_regs_regs_0_sva_cse[86].ACLR
+arst_n => reg_regs_regs_0_sva_cse[87].ACLR
+arst_n => reg_regs_regs_0_sva_cse[88].ACLR
+arst_n => reg_regs_regs_0_sva_cse[89].ACLR
+arst_n => slc_regs_regs_2_8_itm[0].ACLR
+arst_n => slc_regs_regs_2_8_itm[1].ACLR
+arst_n => slc_regs_regs_2_8_itm[2].ACLR
+arst_n => slc_regs_regs_2_8_itm[3].ACLR
+arst_n => slc_regs_regs_2_8_itm[4].ACLR
+arst_n => slc_regs_regs_2_8_itm[5].ACLR
+arst_n => slc_regs_regs_2_8_itm[6].ACLR
+arst_n => slc_regs_regs_2_8_itm[7].ACLR
+arst_n => slc_regs_regs_2_8_itm[8].ACLR
+arst_n => slc_regs_regs_2_8_itm[9].ACLR
+arst_n => slc_regs_regs_2_7_itm[0].ACLR
+arst_n => slc_regs_regs_2_7_itm[1].ACLR
+arst_n => slc_regs_regs_2_7_itm[2].ACLR
+arst_n => slc_regs_regs_2_7_itm[3].ACLR
+arst_n => slc_regs_regs_2_7_itm[4].ACLR
+arst_n => slc_regs_regs_2_7_itm[5].ACLR
+arst_n => slc_regs_regs_2_7_itm[6].ACLR
+arst_n => slc_regs_regs_2_7_itm[7].ACLR
+arst_n => slc_regs_regs_2_7_itm[8].ACLR
+arst_n => slc_regs_regs_2_7_itm[9].ACLR
+vin_rsc_mgc_in_wire_d[0] => Add40.IN22
+vin_rsc_mgc_in_wire_d[0] => reg_regs_regs_0_sva_cse[0].DATAIN
+vin_rsc_mgc_in_wire_d[1] => Add40.IN21
+vin_rsc_mgc_in_wire_d[1] => reg_regs_regs_0_sva_cse[1].DATAIN
+vin_rsc_mgc_in_wire_d[2] => Add40.IN20
+vin_rsc_mgc_in_wire_d[2] => reg_regs_regs_0_sva_cse[2].DATAIN
+vin_rsc_mgc_in_wire_d[3] => Add40.IN19
+vin_rsc_mgc_in_wire_d[3] => reg_regs_regs_0_sva_cse[3].DATAIN
+vin_rsc_mgc_in_wire_d[4] => Add40.IN18
+vin_rsc_mgc_in_wire_d[4] => reg_regs_regs_0_sva_cse[4].DATAIN
+vin_rsc_mgc_in_wire_d[5] => Add40.IN17
+vin_rsc_mgc_in_wire_d[5] => reg_regs_regs_0_sva_cse[5].DATAIN
+vin_rsc_mgc_in_wire_d[6] => Add40.IN16
+vin_rsc_mgc_in_wire_d[6] => reg_regs_regs_0_sva_cse[6].DATAIN
+vin_rsc_mgc_in_wire_d[7] => Add40.IN15
+vin_rsc_mgc_in_wire_d[7] => reg_regs_regs_0_sva_cse[7].DATAIN
+vin_rsc_mgc_in_wire_d[8] => Add40.IN14
+vin_rsc_mgc_in_wire_d[8] => reg_regs_regs_0_sva_cse[8].DATAIN
+vin_rsc_mgc_in_wire_d[9] => Add40.IN13
+vin_rsc_mgc_in_wire_d[9] => reg_regs_regs_0_sva_cse[9].DATAIN
+vin_rsc_mgc_in_wire_d[10] => Add27.IN22
+vin_rsc_mgc_in_wire_d[10] => reg_regs_regs_0_sva_cse[10].DATAIN
+vin_rsc_mgc_in_wire_d[11] => Add27.IN21
+vin_rsc_mgc_in_wire_d[11] => reg_regs_regs_0_sva_cse[11].DATAIN
+vin_rsc_mgc_in_wire_d[12] => Add27.IN20
+vin_rsc_mgc_in_wire_d[12] => reg_regs_regs_0_sva_cse[12].DATAIN
+vin_rsc_mgc_in_wire_d[13] => Add27.IN19
+vin_rsc_mgc_in_wire_d[13] => reg_regs_regs_0_sva_cse[13].DATAIN
+vin_rsc_mgc_in_wire_d[14] => Add27.IN18
+vin_rsc_mgc_in_wire_d[14] => reg_regs_regs_0_sva_cse[14].DATAIN
+vin_rsc_mgc_in_wire_d[15] => Add27.IN17
+vin_rsc_mgc_in_wire_d[15] => reg_regs_regs_0_sva_cse[15].DATAIN
+vin_rsc_mgc_in_wire_d[16] => Add27.IN16
+vin_rsc_mgc_in_wire_d[16] => reg_regs_regs_0_sva_cse[16].DATAIN
+vin_rsc_mgc_in_wire_d[17] => Add27.IN15
+vin_rsc_mgc_in_wire_d[17] => reg_regs_regs_0_sva_cse[17].DATAIN
+vin_rsc_mgc_in_wire_d[18] => Add27.IN14
+vin_rsc_mgc_in_wire_d[18] => reg_regs_regs_0_sva_cse[18].DATAIN
+vin_rsc_mgc_in_wire_d[19] => Add27.IN13
+vin_rsc_mgc_in_wire_d[19] => reg_regs_regs_0_sva_cse[19].DATAIN
+vin_rsc_mgc_in_wire_d[20] => Add1.IN22
+vin_rsc_mgc_in_wire_d[20] => reg_regs_regs_0_sva_cse[20].DATAIN
+vin_rsc_mgc_in_wire_d[21] => Add1.IN21
+vin_rsc_mgc_in_wire_d[21] => reg_regs_regs_0_sva_cse[21].DATAIN
+vin_rsc_mgc_in_wire_d[22] => Add1.IN20
+vin_rsc_mgc_in_wire_d[22] => reg_regs_regs_0_sva_cse[22].DATAIN
+vin_rsc_mgc_in_wire_d[23] => Add1.IN19
+vin_rsc_mgc_in_wire_d[23] => reg_regs_regs_0_sva_cse[23].DATAIN
+vin_rsc_mgc_in_wire_d[24] => Add1.IN18
+vin_rsc_mgc_in_wire_d[24] => reg_regs_regs_0_sva_cse[24].DATAIN
+vin_rsc_mgc_in_wire_d[25] => Add1.IN17
+vin_rsc_mgc_in_wire_d[25] => reg_regs_regs_0_sva_cse[25].DATAIN
+vin_rsc_mgc_in_wire_d[26] => Add1.IN16
+vin_rsc_mgc_in_wire_d[26] => reg_regs_regs_0_sva_cse[26].DATAIN
+vin_rsc_mgc_in_wire_d[27] => Add1.IN15
+vin_rsc_mgc_in_wire_d[27] => reg_regs_regs_0_sva_cse[27].DATAIN
+vin_rsc_mgc_in_wire_d[28] => Add1.IN14
+vin_rsc_mgc_in_wire_d[28] => reg_regs_regs_0_sva_cse[28].DATAIN
+vin_rsc_mgc_in_wire_d[29] => Add1.IN13
+vin_rsc_mgc_in_wire_d[29] => reg_regs_regs_0_sva_cse[29].DATAIN
+vin_rsc_mgc_in_wire_d[30] => Add41.IN20
+vin_rsc_mgc_in_wire_d[30] => reg_regs_regs_0_sva_cse[30].DATAIN
+vin_rsc_mgc_in_wire_d[31] => Add41.IN19
+vin_rsc_mgc_in_wire_d[31] => reg_regs_regs_0_sva_cse[31].DATAIN
+vin_rsc_mgc_in_wire_d[32] => Add41.IN18
+vin_rsc_mgc_in_wire_d[32] => reg_regs_regs_0_sva_cse[32].DATAIN
+vin_rsc_mgc_in_wire_d[33] => Add41.IN17
+vin_rsc_mgc_in_wire_d[33] => reg_regs_regs_0_sva_cse[33].DATAIN
+vin_rsc_mgc_in_wire_d[34] => Add41.IN16
+vin_rsc_mgc_in_wire_d[34] => reg_regs_regs_0_sva_cse[34].DATAIN
+vin_rsc_mgc_in_wire_d[35] => Add41.IN15
+vin_rsc_mgc_in_wire_d[35] => reg_regs_regs_0_sva_cse[35].DATAIN
+vin_rsc_mgc_in_wire_d[36] => Add41.IN14
+vin_rsc_mgc_in_wire_d[36] => reg_regs_regs_0_sva_cse[36].DATAIN
+vin_rsc_mgc_in_wire_d[37] => Add41.IN13
+vin_rsc_mgc_in_wire_d[37] => reg_regs_regs_0_sva_cse[37].DATAIN
+vin_rsc_mgc_in_wire_d[38] => Add41.IN12
+vin_rsc_mgc_in_wire_d[38] => reg_regs_regs_0_sva_cse[38].DATAIN
+vin_rsc_mgc_in_wire_d[39] => Add41.IN11
+vin_rsc_mgc_in_wire_d[39] => reg_regs_regs_0_sva_cse[39].DATAIN
+vin_rsc_mgc_in_wire_d[40] => Add28.IN20
+vin_rsc_mgc_in_wire_d[40] => reg_regs_regs_0_sva_cse[40].DATAIN
+vin_rsc_mgc_in_wire_d[41] => Add28.IN19
+vin_rsc_mgc_in_wire_d[41] => reg_regs_regs_0_sva_cse[41].DATAIN
+vin_rsc_mgc_in_wire_d[42] => Add28.IN18
+vin_rsc_mgc_in_wire_d[42] => reg_regs_regs_0_sva_cse[42].DATAIN
+vin_rsc_mgc_in_wire_d[43] => Add28.IN17
+vin_rsc_mgc_in_wire_d[43] => reg_regs_regs_0_sva_cse[43].DATAIN
+vin_rsc_mgc_in_wire_d[44] => Add28.IN16
+vin_rsc_mgc_in_wire_d[44] => reg_regs_regs_0_sva_cse[44].DATAIN
+vin_rsc_mgc_in_wire_d[45] => Add28.IN15
+vin_rsc_mgc_in_wire_d[45] => reg_regs_regs_0_sva_cse[45].DATAIN
+vin_rsc_mgc_in_wire_d[46] => Add28.IN14
+vin_rsc_mgc_in_wire_d[46] => reg_regs_regs_0_sva_cse[46].DATAIN
+vin_rsc_mgc_in_wire_d[47] => Add28.IN13
+vin_rsc_mgc_in_wire_d[47] => reg_regs_regs_0_sva_cse[47].DATAIN
+vin_rsc_mgc_in_wire_d[48] => Add28.IN12
+vin_rsc_mgc_in_wire_d[48] => reg_regs_regs_0_sva_cse[48].DATAIN
+vin_rsc_mgc_in_wire_d[49] => Add28.IN11
+vin_rsc_mgc_in_wire_d[49] => reg_regs_regs_0_sva_cse[49].DATAIN
+vin_rsc_mgc_in_wire_d[50] => Add2.IN20
+vin_rsc_mgc_in_wire_d[50] => reg_regs_regs_0_sva_cse[50].DATAIN
+vin_rsc_mgc_in_wire_d[51] => Add2.IN19
+vin_rsc_mgc_in_wire_d[51] => reg_regs_regs_0_sva_cse[51].DATAIN
+vin_rsc_mgc_in_wire_d[52] => Add2.IN18
+vin_rsc_mgc_in_wire_d[52] => reg_regs_regs_0_sva_cse[52].DATAIN
+vin_rsc_mgc_in_wire_d[53] => Add2.IN17
+vin_rsc_mgc_in_wire_d[53] => reg_regs_regs_0_sva_cse[53].DATAIN
+vin_rsc_mgc_in_wire_d[54] => Add2.IN16
+vin_rsc_mgc_in_wire_d[54] => reg_regs_regs_0_sva_cse[54].DATAIN
+vin_rsc_mgc_in_wire_d[55] => Add2.IN15
+vin_rsc_mgc_in_wire_d[55] => reg_regs_regs_0_sva_cse[55].DATAIN
+vin_rsc_mgc_in_wire_d[56] => Add2.IN14
+vin_rsc_mgc_in_wire_d[56] => reg_regs_regs_0_sva_cse[56].DATAIN
+vin_rsc_mgc_in_wire_d[57] => Add2.IN13
+vin_rsc_mgc_in_wire_d[57] => reg_regs_regs_0_sva_cse[57].DATAIN
+vin_rsc_mgc_in_wire_d[58] => Add2.IN12
+vin_rsc_mgc_in_wire_d[58] => reg_regs_regs_0_sva_cse[58].DATAIN
+vin_rsc_mgc_in_wire_d[59] => Add2.IN11
+vin_rsc_mgc_in_wire_d[59] => reg_regs_regs_0_sva_cse[59].DATAIN
+vin_rsc_mgc_in_wire_d[60] => Add41.IN10
+vin_rsc_mgc_in_wire_d[60] => reg_regs_regs_0_sva_cse[60].DATAIN
+vin_rsc_mgc_in_wire_d[61] => Add41.IN9
+vin_rsc_mgc_in_wire_d[61] => reg_regs_regs_0_sva_cse[61].DATAIN
+vin_rsc_mgc_in_wire_d[62] => Add41.IN8
+vin_rsc_mgc_in_wire_d[62] => reg_regs_regs_0_sva_cse[62].DATAIN
+vin_rsc_mgc_in_wire_d[63] => Add41.IN7
+vin_rsc_mgc_in_wire_d[63] => reg_regs_regs_0_sva_cse[63].DATAIN
+vin_rsc_mgc_in_wire_d[64] => Add41.IN6
+vin_rsc_mgc_in_wire_d[64] => reg_regs_regs_0_sva_cse[64].DATAIN
+vin_rsc_mgc_in_wire_d[65] => Add41.IN5
+vin_rsc_mgc_in_wire_d[65] => reg_regs_regs_0_sva_cse[65].DATAIN
+vin_rsc_mgc_in_wire_d[66] => Add41.IN4
+vin_rsc_mgc_in_wire_d[66] => reg_regs_regs_0_sva_cse[66].DATAIN
+vin_rsc_mgc_in_wire_d[67] => Add41.IN3
+vin_rsc_mgc_in_wire_d[67] => reg_regs_regs_0_sva_cse[67].DATAIN
+vin_rsc_mgc_in_wire_d[68] => Add41.IN2
+vin_rsc_mgc_in_wire_d[68] => reg_regs_regs_0_sva_cse[68].DATAIN
+vin_rsc_mgc_in_wire_d[69] => Add41.IN1
+vin_rsc_mgc_in_wire_d[69] => reg_regs_regs_0_sva_cse[69].DATAIN
+vin_rsc_mgc_in_wire_d[70] => Add28.IN10
+vin_rsc_mgc_in_wire_d[70] => reg_regs_regs_0_sva_cse[70].DATAIN
+vin_rsc_mgc_in_wire_d[71] => Add28.IN9
+vin_rsc_mgc_in_wire_d[71] => reg_regs_regs_0_sva_cse[71].DATAIN
+vin_rsc_mgc_in_wire_d[72] => Add28.IN8
+vin_rsc_mgc_in_wire_d[72] => reg_regs_regs_0_sva_cse[72].DATAIN
+vin_rsc_mgc_in_wire_d[73] => Add28.IN7
+vin_rsc_mgc_in_wire_d[73] => reg_regs_regs_0_sva_cse[73].DATAIN
+vin_rsc_mgc_in_wire_d[74] => Add28.IN6
+vin_rsc_mgc_in_wire_d[74] => reg_regs_regs_0_sva_cse[74].DATAIN
+vin_rsc_mgc_in_wire_d[75] => Add28.IN5
+vin_rsc_mgc_in_wire_d[75] => reg_regs_regs_0_sva_cse[75].DATAIN
+vin_rsc_mgc_in_wire_d[76] => Add28.IN4
+vin_rsc_mgc_in_wire_d[76] => reg_regs_regs_0_sva_cse[76].DATAIN
+vin_rsc_mgc_in_wire_d[77] => Add28.IN3
+vin_rsc_mgc_in_wire_d[77] => reg_regs_regs_0_sva_cse[77].DATAIN
+vin_rsc_mgc_in_wire_d[78] => Add28.IN2
+vin_rsc_mgc_in_wire_d[78] => reg_regs_regs_0_sva_cse[78].DATAIN
+vin_rsc_mgc_in_wire_d[79] => Add28.IN1
+vin_rsc_mgc_in_wire_d[79] => reg_regs_regs_0_sva_cse[79].DATAIN
+vin_rsc_mgc_in_wire_d[80] => Add2.IN10
+vin_rsc_mgc_in_wire_d[80] => reg_regs_regs_0_sva_cse[80].DATAIN
+vin_rsc_mgc_in_wire_d[81] => Add2.IN9
+vin_rsc_mgc_in_wire_d[81] => reg_regs_regs_0_sva_cse[81].DATAIN
+vin_rsc_mgc_in_wire_d[82] => Add2.IN8
+vin_rsc_mgc_in_wire_d[82] => reg_regs_regs_0_sva_cse[82].DATAIN
+vin_rsc_mgc_in_wire_d[83] => Add2.IN7
+vin_rsc_mgc_in_wire_d[83] => reg_regs_regs_0_sva_cse[83].DATAIN
+vin_rsc_mgc_in_wire_d[84] => Add2.IN6
+vin_rsc_mgc_in_wire_d[84] => reg_regs_regs_0_sva_cse[84].DATAIN
+vin_rsc_mgc_in_wire_d[85] => Add2.IN5
+vin_rsc_mgc_in_wire_d[85] => reg_regs_regs_0_sva_cse[85].DATAIN
+vin_rsc_mgc_in_wire_d[86] => Add2.IN4
+vin_rsc_mgc_in_wire_d[86] => reg_regs_regs_0_sva_cse[86].DATAIN
+vin_rsc_mgc_in_wire_d[87] => Add2.IN3
+vin_rsc_mgc_in_wire_d[87] => reg_regs_regs_0_sva_cse[87].DATAIN
+vin_rsc_mgc_in_wire_d[88] => Add2.IN2
+vin_rsc_mgc_in_wire_d[88] => reg_regs_regs_0_sva_cse[88].DATAIN
+vin_rsc_mgc_in_wire_d[89] => Add2.IN1
+vin_rsc_mgc_in_wire_d[89] => reg_regs_regs_0_sva_cse[89].DATAIN
+vout_rsc_mgc_out_stdreg_d[0] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[0].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[1] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[1].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[2] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[2].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[3] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[3].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[4] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[4].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[5] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[5].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[6] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[7] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[8] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[9] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[10] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_2[0].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[11] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_2[1].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[12] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_2[2].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[13] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_2[3].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[14] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_2[4].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[15] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_1[0].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[16] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[17] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[18] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[19] <= reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[20] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[0].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[21] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[1].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[22] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[2].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[23] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[3].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[24] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[4].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[25] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[5].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[26] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[6].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[27] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[7].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[28] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[8].DB_MAX_OUTPUT_PORT_TYPE
+vout_rsc_mgc_out_stdreg_d[29] <= reg_vout_rsc_mgc_out_stdreg_d_tmp[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2
+shiftin[0] => shift_taps_lpm:auto_generated.shiftin[0]
+shiftin[1] => shift_taps_lpm:auto_generated.shiftin[1]
+shiftin[2] => shift_taps_lpm:auto_generated.shiftin[2]
+shiftin[3] => shift_taps_lpm:auto_generated.shiftin[3]
+shiftin[4] => shift_taps_lpm:auto_generated.shiftin[4]
+shiftin[5] => shift_taps_lpm:auto_generated.shiftin[5]
+shiftin[6] => shift_taps_lpm:auto_generated.shiftin[6]
+shiftin[7] => shift_taps_lpm:auto_generated.shiftin[7]
+shiftin[8] => shift_taps_lpm:auto_generated.shiftin[8]
+shiftin[9] => shift_taps_lpm:auto_generated.shiftin[9]
+shiftin[10] => shift_taps_lpm:auto_generated.shiftin[10]
+shiftin[11] => shift_taps_lpm:auto_generated.shiftin[11]
+shiftin[12] => shift_taps_lpm:auto_generated.shiftin[12]
+shiftin[13] => shift_taps_lpm:auto_generated.shiftin[13]
+shiftin[14] => shift_taps_lpm:auto_generated.shiftin[14]
+shiftin[15] => shift_taps_lpm:auto_generated.shiftin[15]
+shiftin[16] => shift_taps_lpm:auto_generated.shiftin[16]
+shiftin[17] => shift_taps_lpm:auto_generated.shiftin[17]
+shiftin[18] => shift_taps_lpm:auto_generated.shiftin[18]
+shiftin[19] => shift_taps_lpm:auto_generated.shiftin[19]
+shiftin[20] => shift_taps_lpm:auto_generated.shiftin[20]
+shiftin[21] => shift_taps_lpm:auto_generated.shiftin[21]
+shiftin[22] => shift_taps_lpm:auto_generated.shiftin[22]
+shiftin[23] => shift_taps_lpm:auto_generated.shiftin[23]
+shiftin[24] => shift_taps_lpm:auto_generated.shiftin[24]
+shiftin[25] => shift_taps_lpm:auto_generated.shiftin[25]
+shiftin[26] => shift_taps_lpm:auto_generated.shiftin[26]
+shiftin[27] => shift_taps_lpm:auto_generated.shiftin[27]
+shiftin[28] => shift_taps_lpm:auto_generated.shiftin[28]
+shiftin[29] => shift_taps_lpm:auto_generated.shiftin[29]
+clock => shift_taps_lpm:auto_generated.clock
+clken => shift_taps_lpm:auto_generated.clken
+shiftout[0] <= <GND>
+shiftout[1] <= <GND>
+shiftout[2] <= <GND>
+shiftout[3] <= <GND>
+shiftout[4] <= <GND>
+shiftout[5] <= <GND>
+shiftout[6] <= <GND>
+shiftout[7] <= <GND>
+shiftout[8] <= <GND>
+shiftout[9] <= <GND>
+shiftout[10] <= <GND>
+shiftout[11] <= <GND>
+shiftout[12] <= <GND>
+shiftout[13] <= <GND>
+shiftout[14] <= <GND>
+shiftout[15] <= <GND>
+shiftout[16] <= <GND>
+shiftout[17] <= <GND>
+shiftout[18] <= <GND>
+shiftout[19] <= <GND>
+shiftout[20] <= <GND>
+shiftout[21] <= <GND>
+shiftout[22] <= <GND>
+shiftout[23] <= <GND>
+shiftout[24] <= <GND>
+shiftout[25] <= <GND>
+shiftout[26] <= <GND>
+shiftout[27] <= <GND>
+shiftout[28] <= <GND>
+shiftout[29] <= <GND>
+taps[0] <= shift_taps_lpm:auto_generated.taps[0]
+taps[1] <= shift_taps_lpm:auto_generated.taps[1]
+taps[2] <= shift_taps_lpm:auto_generated.taps[2]
+taps[3] <= shift_taps_lpm:auto_generated.taps[3]
+taps[4] <= shift_taps_lpm:auto_generated.taps[4]
+taps[5] <= shift_taps_lpm:auto_generated.taps[5]
+taps[6] <= shift_taps_lpm:auto_generated.taps[6]
+taps[7] <= shift_taps_lpm:auto_generated.taps[7]
+taps[8] <= shift_taps_lpm:auto_generated.taps[8]
+taps[9] <= shift_taps_lpm:auto_generated.taps[9]
+taps[10] <= shift_taps_lpm:auto_generated.taps[10]
+taps[11] <= shift_taps_lpm:auto_generated.taps[11]
+taps[12] <= shift_taps_lpm:auto_generated.taps[12]
+taps[13] <= shift_taps_lpm:auto_generated.taps[13]
+taps[14] <= shift_taps_lpm:auto_generated.taps[14]
+taps[15] <= shift_taps_lpm:auto_generated.taps[15]
+taps[16] <= shift_taps_lpm:auto_generated.taps[16]
+taps[17] <= shift_taps_lpm:auto_generated.taps[17]
+taps[18] <= shift_taps_lpm:auto_generated.taps[18]
+taps[19] <= shift_taps_lpm:auto_generated.taps[19]
+taps[20] <= shift_taps_lpm:auto_generated.taps[20]
+taps[21] <= shift_taps_lpm:auto_generated.taps[21]
+taps[22] <= shift_taps_lpm:auto_generated.taps[22]
+taps[23] <= shift_taps_lpm:auto_generated.taps[23]
+taps[24] <= shift_taps_lpm:auto_generated.taps[24]
+taps[25] <= shift_taps_lpm:auto_generated.taps[25]
+taps[26] <= shift_taps_lpm:auto_generated.taps[26]
+taps[27] <= shift_taps_lpm:auto_generated.taps[27]
+taps[28] <= shift_taps_lpm:auto_generated.taps[28]
+taps[29] <= shift_taps_lpm:auto_generated.taps[29]
+taps[30] <= shift_taps_lpm:auto_generated.taps[30]
+taps[31] <= shift_taps_lpm:auto_generated.taps[31]
+taps[32] <= shift_taps_lpm:auto_generated.taps[32]
+taps[33] <= shift_taps_lpm:auto_generated.taps[33]
+taps[34] <= shift_taps_lpm:auto_generated.taps[34]
+taps[35] <= shift_taps_lpm:auto_generated.taps[35]
+taps[36] <= shift_taps_lpm:auto_generated.taps[36]
+taps[37] <= shift_taps_lpm:auto_generated.taps[37]
+taps[38] <= shift_taps_lpm:auto_generated.taps[38]
+taps[39] <= shift_taps_lpm:auto_generated.taps[39]
+taps[40] <= shift_taps_lpm:auto_generated.taps[40]
+taps[41] <= shift_taps_lpm:auto_generated.taps[41]
+taps[42] <= shift_taps_lpm:auto_generated.taps[42]
+taps[43] <= shift_taps_lpm:auto_generated.taps[43]
+taps[44] <= shift_taps_lpm:auto_generated.taps[44]
+taps[45] <= shift_taps_lpm:auto_generated.taps[45]
+taps[46] <= shift_taps_lpm:auto_generated.taps[46]
+taps[47] <= shift_taps_lpm:auto_generated.taps[47]
+taps[48] <= shift_taps_lpm:auto_generated.taps[48]
+taps[49] <= shift_taps_lpm:auto_generated.taps[49]
+taps[50] <= shift_taps_lpm:auto_generated.taps[50]
+taps[51] <= shift_taps_lpm:auto_generated.taps[51]
+taps[52] <= shift_taps_lpm:auto_generated.taps[52]
+taps[53] <= shift_taps_lpm:auto_generated.taps[53]
+taps[54] <= shift_taps_lpm:auto_generated.taps[54]
+taps[55] <= shift_taps_lpm:auto_generated.taps[55]
+taps[56] <= shift_taps_lpm:auto_generated.taps[56]
+taps[57] <= shift_taps_lpm:auto_generated.taps[57]
+taps[58] <= shift_taps_lpm:auto_generated.taps[58]
+taps[59] <= shift_taps_lpm:auto_generated.taps[59]
+taps[60] <= shift_taps_lpm:auto_generated.taps[60]
+taps[61] <= shift_taps_lpm:auto_generated.taps[61]
+taps[62] <= shift_taps_lpm:auto_generated.taps[62]
+taps[63] <= shift_taps_lpm:auto_generated.taps[63]
+taps[64] <= shift_taps_lpm:auto_generated.taps[64]
+taps[65] <= shift_taps_lpm:auto_generated.taps[65]
+taps[66] <= shift_taps_lpm:auto_generated.taps[66]
+taps[67] <= shift_taps_lpm:auto_generated.taps[67]
+taps[68] <= shift_taps_lpm:auto_generated.taps[68]
+taps[69] <= shift_taps_lpm:auto_generated.taps[69]
+taps[70] <= shift_taps_lpm:auto_generated.taps[70]
+taps[71] <= shift_taps_lpm:auto_generated.taps[71]
+taps[72] <= shift_taps_lpm:auto_generated.taps[72]
+taps[73] <= shift_taps_lpm:auto_generated.taps[73]
+taps[74] <= shift_taps_lpm:auto_generated.taps[74]
+taps[75] <= shift_taps_lpm:auto_generated.taps[75]
+taps[76] <= shift_taps_lpm:auto_generated.taps[76]
+taps[77] <= shift_taps_lpm:auto_generated.taps[77]
+taps[78] <= shift_taps_lpm:auto_generated.taps[78]
+taps[79] <= shift_taps_lpm:auto_generated.taps[79]
+taps[80] <= shift_taps_lpm:auto_generated.taps[80]
+taps[81] <= shift_taps_lpm:auto_generated.taps[81]
+taps[82] <= shift_taps_lpm:auto_generated.taps[82]
+taps[83] <= shift_taps_lpm:auto_generated.taps[83]
+taps[84] <= shift_taps_lpm:auto_generated.taps[84]
+taps[85] <= shift_taps_lpm:auto_generated.taps[85]
+taps[86] <= shift_taps_lpm:auto_generated.taps[86]
+taps[87] <= shift_taps_lpm:auto_generated.taps[87]
+taps[88] <= shift_taps_lpm:auto_generated.taps[88]
+taps[89] <= shift_taps_lpm:auto_generated.taps[89]
+taps[90] <= shift_taps_lpm:auto_generated.taps[90]
+taps[91] <= shift_taps_lpm:auto_generated.taps[91]
+taps[92] <= shift_taps_lpm:auto_generated.taps[92]
+taps[93] <= shift_taps_lpm:auto_generated.taps[93]
+taps[94] <= shift_taps_lpm:auto_generated.taps[94]
+taps[95] <= shift_taps_lpm:auto_generated.taps[95]
+taps[96] <= shift_taps_lpm:auto_generated.taps[96]
+taps[97] <= shift_taps_lpm:auto_generated.taps[97]
+taps[98] <= shift_taps_lpm:auto_generated.taps[98]
+taps[99] <= shift_taps_lpm:auto_generated.taps[99]
+taps[100] <= shift_taps_lpm:auto_generated.taps[100]
+taps[101] <= shift_taps_lpm:auto_generated.taps[101]
+taps[102] <= shift_taps_lpm:auto_generated.taps[102]
+taps[103] <= shift_taps_lpm:auto_generated.taps[103]
+taps[104] <= shift_taps_lpm:auto_generated.taps[104]
+taps[105] <= shift_taps_lpm:auto_generated.taps[105]
+taps[106] <= shift_taps_lpm:auto_generated.taps[106]
+taps[107] <= shift_taps_lpm:auto_generated.taps[107]
+taps[108] <= shift_taps_lpm:auto_generated.taps[108]
+taps[109] <= shift_taps_lpm:auto_generated.taps[109]
+taps[110] <= shift_taps_lpm:auto_generated.taps[110]
+taps[111] <= shift_taps_lpm:auto_generated.taps[111]
+taps[112] <= shift_taps_lpm:auto_generated.taps[112]
+taps[113] <= shift_taps_lpm:auto_generated.taps[113]
+taps[114] <= shift_taps_lpm:auto_generated.taps[114]
+taps[115] <= shift_taps_lpm:auto_generated.taps[115]
+taps[116] <= shift_taps_lpm:auto_generated.taps[116]
+taps[117] <= shift_taps_lpm:auto_generated.taps[117]
+taps[118] <= shift_taps_lpm:auto_generated.taps[118]
+taps[119] <= shift_taps_lpm:auto_generated.taps[119]
+taps[120] <= shift_taps_lpm:auto_generated.taps[120]
+taps[121] <= shift_taps_lpm:auto_generated.taps[121]
+taps[122] <= shift_taps_lpm:auto_generated.taps[122]
+taps[123] <= shift_taps_lpm:auto_generated.taps[123]
+taps[124] <= shift_taps_lpm:auto_generated.taps[124]
+taps[125] <= shift_taps_lpm:auto_generated.taps[125]
+taps[126] <= shift_taps_lpm:auto_generated.taps[126]
+taps[127] <= shift_taps_lpm:auto_generated.taps[127]
+taps[128] <= shift_taps_lpm:auto_generated.taps[128]
+taps[129] <= shift_taps_lpm:auto_generated.taps[129]
+taps[130] <= shift_taps_lpm:auto_generated.taps[130]
+taps[131] <= shift_taps_lpm:auto_generated.taps[131]
+taps[132] <= shift_taps_lpm:auto_generated.taps[132]
+taps[133] <= shift_taps_lpm:auto_generated.taps[133]
+taps[134] <= shift_taps_lpm:auto_generated.taps[134]
+taps[135] <= shift_taps_lpm:auto_generated.taps[135]
+taps[136] <= shift_taps_lpm:auto_generated.taps[136]
+taps[137] <= shift_taps_lpm:auto_generated.taps[137]
+taps[138] <= shift_taps_lpm:auto_generated.taps[138]
+taps[139] <= shift_taps_lpm:auto_generated.taps[139]
+taps[140] <= shift_taps_lpm:auto_generated.taps[140]
+taps[141] <= shift_taps_lpm:auto_generated.taps[141]
+taps[142] <= shift_taps_lpm:auto_generated.taps[142]
+taps[143] <= shift_taps_lpm:auto_generated.taps[143]
+taps[144] <= shift_taps_lpm:auto_generated.taps[144]
+taps[145] <= shift_taps_lpm:auto_generated.taps[145]
+taps[146] <= shift_taps_lpm:auto_generated.taps[146]
+taps[147] <= shift_taps_lpm:auto_generated.taps[147]
+taps[148] <= shift_taps_lpm:auto_generated.taps[148]
+taps[149] <= shift_taps_lpm:auto_generated.taps[149]
+aclr => ~NO_FANOUT~
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated
+clken => altsyncram_vp81:altsyncram2.clocken0
+clken => cntr_1tf:cntr1.clk_en
+clock => altsyncram_vp81:altsyncram2.clock0
+clock => cntr_1tf:cntr1.clock
+shiftin[0] => altsyncram_vp81:altsyncram2.data_a[0]
+shiftin[1] => altsyncram_vp81:altsyncram2.data_a[1]
+shiftin[2] => altsyncram_vp81:altsyncram2.data_a[2]
+shiftin[3] => altsyncram_vp81:altsyncram2.data_a[3]
+shiftin[4] => altsyncram_vp81:altsyncram2.data_a[4]
+shiftin[5] => altsyncram_vp81:altsyncram2.data_a[5]
+shiftin[6] => altsyncram_vp81:altsyncram2.data_a[6]
+shiftin[7] => altsyncram_vp81:altsyncram2.data_a[7]
+shiftin[8] => altsyncram_vp81:altsyncram2.data_a[8]
+shiftin[9] => altsyncram_vp81:altsyncram2.data_a[9]
+shiftin[10] => altsyncram_vp81:altsyncram2.data_a[10]
+shiftin[11] => altsyncram_vp81:altsyncram2.data_a[11]
+shiftin[12] => altsyncram_vp81:altsyncram2.data_a[12]
+shiftin[13] => altsyncram_vp81:altsyncram2.data_a[13]
+shiftin[14] => altsyncram_vp81:altsyncram2.data_a[14]
+shiftin[15] => altsyncram_vp81:altsyncram2.data_a[15]
+shiftin[16] => altsyncram_vp81:altsyncram2.data_a[16]
+shiftin[17] => altsyncram_vp81:altsyncram2.data_a[17]
+shiftin[18] => altsyncram_vp81:altsyncram2.data_a[18]
+shiftin[19] => altsyncram_vp81:altsyncram2.data_a[19]
+shiftin[20] => altsyncram_vp81:altsyncram2.data_a[20]
+shiftin[21] => altsyncram_vp81:altsyncram2.data_a[21]
+shiftin[22] => altsyncram_vp81:altsyncram2.data_a[22]
+shiftin[23] => altsyncram_vp81:altsyncram2.data_a[23]
+shiftin[24] => altsyncram_vp81:altsyncram2.data_a[24]
+shiftin[25] => altsyncram_vp81:altsyncram2.data_a[25]
+shiftin[26] => altsyncram_vp81:altsyncram2.data_a[26]
+shiftin[27] => altsyncram_vp81:altsyncram2.data_a[27]
+shiftin[28] => altsyncram_vp81:altsyncram2.data_a[28]
+shiftin[29] => altsyncram_vp81:altsyncram2.data_a[29]
+shiftout[0] <= altsyncram_vp81:altsyncram2.q_b[120]
+shiftout[1] <= altsyncram_vp81:altsyncram2.q_b[121]
+shiftout[2] <= altsyncram_vp81:altsyncram2.q_b[122]
+shiftout[3] <= altsyncram_vp81:altsyncram2.q_b[123]
+shiftout[4] <= altsyncram_vp81:altsyncram2.q_b[124]
+shiftout[5] <= altsyncram_vp81:altsyncram2.q_b[125]
+shiftout[6] <= altsyncram_vp81:altsyncram2.q_b[126]
+shiftout[7] <= altsyncram_vp81:altsyncram2.q_b[127]
+shiftout[8] <= altsyncram_vp81:altsyncram2.q_b[128]
+shiftout[9] <= altsyncram_vp81:altsyncram2.q_b[129]
+shiftout[10] <= altsyncram_vp81:altsyncram2.q_b[130]
+shiftout[11] <= altsyncram_vp81:altsyncram2.q_b[131]
+shiftout[12] <= altsyncram_vp81:altsyncram2.q_b[132]
+shiftout[13] <= altsyncram_vp81:altsyncram2.q_b[133]
+shiftout[14] <= altsyncram_vp81:altsyncram2.q_b[134]
+shiftout[15] <= altsyncram_vp81:altsyncram2.q_b[135]
+shiftout[16] <= altsyncram_vp81:altsyncram2.q_b[136]
+shiftout[17] <= altsyncram_vp81:altsyncram2.q_b[137]
+shiftout[18] <= altsyncram_vp81:altsyncram2.q_b[138]
+shiftout[19] <= altsyncram_vp81:altsyncram2.q_b[139]
+shiftout[20] <= altsyncram_vp81:altsyncram2.q_b[140]
+shiftout[21] <= altsyncram_vp81:altsyncram2.q_b[141]
+shiftout[22] <= altsyncram_vp81:altsyncram2.q_b[142]
+shiftout[23] <= altsyncram_vp81:altsyncram2.q_b[143]
+shiftout[24] <= altsyncram_vp81:altsyncram2.q_b[144]
+shiftout[25] <= altsyncram_vp81:altsyncram2.q_b[145]
+shiftout[26] <= altsyncram_vp81:altsyncram2.q_b[146]
+shiftout[27] <= altsyncram_vp81:altsyncram2.q_b[147]
+shiftout[28] <= altsyncram_vp81:altsyncram2.q_b[148]
+shiftout[29] <= altsyncram_vp81:altsyncram2.q_b[149]
+taps[0] <= altsyncram_vp81:altsyncram2.q_b[0]
+taps[1] <= altsyncram_vp81:altsyncram2.q_b[1]
+taps[2] <= altsyncram_vp81:altsyncram2.q_b[2]
+taps[3] <= altsyncram_vp81:altsyncram2.q_b[3]
+taps[4] <= altsyncram_vp81:altsyncram2.q_b[4]
+taps[5] <= altsyncram_vp81:altsyncram2.q_b[5]
+taps[6] <= altsyncram_vp81:altsyncram2.q_b[6]
+taps[7] <= altsyncram_vp81:altsyncram2.q_b[7]
+taps[8] <= altsyncram_vp81:altsyncram2.q_b[8]
+taps[9] <= altsyncram_vp81:altsyncram2.q_b[9]
+taps[10] <= altsyncram_vp81:altsyncram2.q_b[10]
+taps[11] <= altsyncram_vp81:altsyncram2.q_b[11]
+taps[12] <= altsyncram_vp81:altsyncram2.q_b[12]
+taps[13] <= altsyncram_vp81:altsyncram2.q_b[13]
+taps[14] <= altsyncram_vp81:altsyncram2.q_b[14]
+taps[15] <= altsyncram_vp81:altsyncram2.q_b[15]
+taps[16] <= altsyncram_vp81:altsyncram2.q_b[16]
+taps[17] <= altsyncram_vp81:altsyncram2.q_b[17]
+taps[18] <= altsyncram_vp81:altsyncram2.q_b[18]
+taps[19] <= altsyncram_vp81:altsyncram2.q_b[19]
+taps[20] <= altsyncram_vp81:altsyncram2.q_b[20]
+taps[21] <= altsyncram_vp81:altsyncram2.q_b[21]
+taps[22] <= altsyncram_vp81:altsyncram2.q_b[22]
+taps[23] <= altsyncram_vp81:altsyncram2.q_b[23]
+taps[24] <= altsyncram_vp81:altsyncram2.q_b[24]
+taps[25] <= altsyncram_vp81:altsyncram2.q_b[25]
+taps[26] <= altsyncram_vp81:altsyncram2.q_b[26]
+taps[27] <= altsyncram_vp81:altsyncram2.q_b[27]
+taps[28] <= altsyncram_vp81:altsyncram2.q_b[28]
+taps[29] <= altsyncram_vp81:altsyncram2.q_b[29]
+taps[30] <= altsyncram_vp81:altsyncram2.q_b[30]
+taps[31] <= altsyncram_vp81:altsyncram2.q_b[31]
+taps[32] <= altsyncram_vp81:altsyncram2.q_b[32]
+taps[33] <= altsyncram_vp81:altsyncram2.q_b[33]
+taps[34] <= altsyncram_vp81:altsyncram2.q_b[34]
+taps[35] <= altsyncram_vp81:altsyncram2.q_b[35]
+taps[36] <= altsyncram_vp81:altsyncram2.q_b[36]
+taps[37] <= altsyncram_vp81:altsyncram2.q_b[37]
+taps[38] <= altsyncram_vp81:altsyncram2.q_b[38]
+taps[39] <= altsyncram_vp81:altsyncram2.q_b[39]
+taps[40] <= altsyncram_vp81:altsyncram2.q_b[40]
+taps[41] <= altsyncram_vp81:altsyncram2.q_b[41]
+taps[42] <= altsyncram_vp81:altsyncram2.q_b[42]
+taps[43] <= altsyncram_vp81:altsyncram2.q_b[43]
+taps[44] <= altsyncram_vp81:altsyncram2.q_b[44]
+taps[45] <= altsyncram_vp81:altsyncram2.q_b[45]
+taps[46] <= altsyncram_vp81:altsyncram2.q_b[46]
+taps[47] <= altsyncram_vp81:altsyncram2.q_b[47]
+taps[48] <= altsyncram_vp81:altsyncram2.q_b[48]
+taps[49] <= altsyncram_vp81:altsyncram2.q_b[49]
+taps[50] <= altsyncram_vp81:altsyncram2.q_b[50]
+taps[51] <= altsyncram_vp81:altsyncram2.q_b[51]
+taps[52] <= altsyncram_vp81:altsyncram2.q_b[52]
+taps[53] <= altsyncram_vp81:altsyncram2.q_b[53]
+taps[54] <= altsyncram_vp81:altsyncram2.q_b[54]
+taps[55] <= altsyncram_vp81:altsyncram2.q_b[55]
+taps[56] <= altsyncram_vp81:altsyncram2.q_b[56]
+taps[57] <= altsyncram_vp81:altsyncram2.q_b[57]
+taps[58] <= altsyncram_vp81:altsyncram2.q_b[58]
+taps[59] <= altsyncram_vp81:altsyncram2.q_b[59]
+taps[60] <= altsyncram_vp81:altsyncram2.q_b[60]
+taps[61] <= altsyncram_vp81:altsyncram2.q_b[61]
+taps[62] <= altsyncram_vp81:altsyncram2.q_b[62]
+taps[63] <= altsyncram_vp81:altsyncram2.q_b[63]
+taps[64] <= altsyncram_vp81:altsyncram2.q_b[64]
+taps[65] <= altsyncram_vp81:altsyncram2.q_b[65]
+taps[66] <= altsyncram_vp81:altsyncram2.q_b[66]
+taps[67] <= altsyncram_vp81:altsyncram2.q_b[67]
+taps[68] <= altsyncram_vp81:altsyncram2.q_b[68]
+taps[69] <= altsyncram_vp81:altsyncram2.q_b[69]
+taps[70] <= altsyncram_vp81:altsyncram2.q_b[70]
+taps[71] <= altsyncram_vp81:altsyncram2.q_b[71]
+taps[72] <= altsyncram_vp81:altsyncram2.q_b[72]
+taps[73] <= altsyncram_vp81:altsyncram2.q_b[73]
+taps[74] <= altsyncram_vp81:altsyncram2.q_b[74]
+taps[75] <= altsyncram_vp81:altsyncram2.q_b[75]
+taps[76] <= altsyncram_vp81:altsyncram2.q_b[76]
+taps[77] <= altsyncram_vp81:altsyncram2.q_b[77]
+taps[78] <= altsyncram_vp81:altsyncram2.q_b[78]
+taps[79] <= altsyncram_vp81:altsyncram2.q_b[79]
+taps[80] <= altsyncram_vp81:altsyncram2.q_b[80]
+taps[81] <= altsyncram_vp81:altsyncram2.q_b[81]
+taps[82] <= altsyncram_vp81:altsyncram2.q_b[82]
+taps[83] <= altsyncram_vp81:altsyncram2.q_b[83]
+taps[84] <= altsyncram_vp81:altsyncram2.q_b[84]
+taps[85] <= altsyncram_vp81:altsyncram2.q_b[85]
+taps[86] <= altsyncram_vp81:altsyncram2.q_b[86]
+taps[87] <= altsyncram_vp81:altsyncram2.q_b[87]
+taps[88] <= altsyncram_vp81:altsyncram2.q_b[88]
+taps[89] <= altsyncram_vp81:altsyncram2.q_b[89]
+taps[90] <= altsyncram_vp81:altsyncram2.q_b[90]
+taps[91] <= altsyncram_vp81:altsyncram2.q_b[91]
+taps[92] <= altsyncram_vp81:altsyncram2.q_b[92]
+taps[93] <= altsyncram_vp81:altsyncram2.q_b[93]
+taps[94] <= altsyncram_vp81:altsyncram2.q_b[94]
+taps[95] <= altsyncram_vp81:altsyncram2.q_b[95]
+taps[96] <= altsyncram_vp81:altsyncram2.q_b[96]
+taps[97] <= altsyncram_vp81:altsyncram2.q_b[97]
+taps[98] <= altsyncram_vp81:altsyncram2.q_b[98]
+taps[99] <= altsyncram_vp81:altsyncram2.q_b[99]
+taps[100] <= altsyncram_vp81:altsyncram2.q_b[100]
+taps[101] <= altsyncram_vp81:altsyncram2.q_b[101]
+taps[102] <= altsyncram_vp81:altsyncram2.q_b[102]
+taps[103] <= altsyncram_vp81:altsyncram2.q_b[103]
+taps[104] <= altsyncram_vp81:altsyncram2.q_b[104]
+taps[105] <= altsyncram_vp81:altsyncram2.q_b[105]
+taps[106] <= altsyncram_vp81:altsyncram2.q_b[106]
+taps[107] <= altsyncram_vp81:altsyncram2.q_b[107]
+taps[108] <= altsyncram_vp81:altsyncram2.q_b[108]
+taps[109] <= altsyncram_vp81:altsyncram2.q_b[109]
+taps[110] <= altsyncram_vp81:altsyncram2.q_b[110]
+taps[111] <= altsyncram_vp81:altsyncram2.q_b[111]
+taps[112] <= altsyncram_vp81:altsyncram2.q_b[112]
+taps[113] <= altsyncram_vp81:altsyncram2.q_b[113]
+taps[114] <= altsyncram_vp81:altsyncram2.q_b[114]
+taps[115] <= altsyncram_vp81:altsyncram2.q_b[115]
+taps[116] <= altsyncram_vp81:altsyncram2.q_b[116]
+taps[117] <= altsyncram_vp81:altsyncram2.q_b[117]
+taps[118] <= altsyncram_vp81:altsyncram2.q_b[118]
+taps[119] <= altsyncram_vp81:altsyncram2.q_b[119]
+taps[120] <= altsyncram_vp81:altsyncram2.q_b[120]
+taps[121] <= altsyncram_vp81:altsyncram2.q_b[121]
+taps[122] <= altsyncram_vp81:altsyncram2.q_b[122]
+taps[123] <= altsyncram_vp81:altsyncram2.q_b[123]
+taps[124] <= altsyncram_vp81:altsyncram2.q_b[124]
+taps[125] <= altsyncram_vp81:altsyncram2.q_b[125]
+taps[126] <= altsyncram_vp81:altsyncram2.q_b[126]
+taps[127] <= altsyncram_vp81:altsyncram2.q_b[127]
+taps[128] <= altsyncram_vp81:altsyncram2.q_b[128]
+taps[129] <= altsyncram_vp81:altsyncram2.q_b[129]
+taps[130] <= altsyncram_vp81:altsyncram2.q_b[130]
+taps[131] <= altsyncram_vp81:altsyncram2.q_b[131]
+taps[132] <= altsyncram_vp81:altsyncram2.q_b[132]
+taps[133] <= altsyncram_vp81:altsyncram2.q_b[133]
+taps[134] <= altsyncram_vp81:altsyncram2.q_b[134]
+taps[135] <= altsyncram_vp81:altsyncram2.q_b[135]
+taps[136] <= altsyncram_vp81:altsyncram2.q_b[136]
+taps[137] <= altsyncram_vp81:altsyncram2.q_b[137]
+taps[138] <= altsyncram_vp81:altsyncram2.q_b[138]
+taps[139] <= altsyncram_vp81:altsyncram2.q_b[139]
+taps[140] <= altsyncram_vp81:altsyncram2.q_b[140]
+taps[141] <= altsyncram_vp81:altsyncram2.q_b[141]
+taps[142] <= altsyncram_vp81:altsyncram2.q_b[142]
+taps[143] <= altsyncram_vp81:altsyncram2.q_b[143]
+taps[144] <= altsyncram_vp81:altsyncram2.q_b[144]
+taps[145] <= altsyncram_vp81:altsyncram2.q_b[145]
+taps[146] <= altsyncram_vp81:altsyncram2.q_b[146]
+taps[147] <= altsyncram_vp81:altsyncram2.q_b[147]
+taps[148] <= altsyncram_vp81:altsyncram2.q_b[148]
+taps[149] <= altsyncram_vp81:altsyncram2.q_b[149]
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2
+address_a[0] => ram_block3a0.PORTAADDR
+address_a[0] => ram_block3a1.PORTAADDR
+address_a[0] => ram_block3a2.PORTAADDR
+address_a[0] => ram_block3a3.PORTAADDR
+address_a[0] => ram_block3a4.PORTAADDR
+address_a[0] => ram_block3a5.PORTAADDR
+address_a[0] => ram_block3a6.PORTAADDR
+address_a[0] => ram_block3a7.PORTAADDR
+address_a[0] => ram_block3a8.PORTAADDR
+address_a[0] => ram_block3a9.PORTAADDR
+address_a[0] => ram_block3a10.PORTAADDR
+address_a[0] => ram_block3a11.PORTAADDR
+address_a[0] => ram_block3a12.PORTAADDR
+address_a[0] => ram_block3a13.PORTAADDR
+address_a[0] => ram_block3a14.PORTAADDR
+address_a[0] => ram_block3a15.PORTAADDR
+address_a[0] => ram_block3a16.PORTAADDR
+address_a[0] => ram_block3a17.PORTAADDR
+address_a[0] => ram_block3a18.PORTAADDR
+address_a[0] => ram_block3a19.PORTAADDR
+address_a[0] => ram_block3a20.PORTAADDR
+address_a[0] => ram_block3a21.PORTAADDR
+address_a[0] => ram_block3a22.PORTAADDR
+address_a[0] => ram_block3a23.PORTAADDR
+address_a[0] => ram_block3a24.PORTAADDR
+address_a[0] => ram_block3a25.PORTAADDR
+address_a[0] => ram_block3a26.PORTAADDR
+address_a[0] => ram_block3a27.PORTAADDR
+address_a[0] => ram_block3a28.PORTAADDR
+address_a[0] => ram_block3a29.PORTAADDR
+address_a[0] => ram_block3a30.PORTAADDR
+address_a[0] => ram_block3a31.PORTAADDR
+address_a[0] => ram_block3a32.PORTAADDR
+address_a[0] => ram_block3a33.PORTAADDR
+address_a[0] => ram_block3a34.PORTAADDR
+address_a[0] => ram_block3a35.PORTAADDR
+address_a[0] => ram_block3a36.PORTAADDR
+address_a[0] => ram_block3a37.PORTAADDR
+address_a[0] => ram_block3a38.PORTAADDR
+address_a[0] => ram_block3a39.PORTAADDR
+address_a[0] => ram_block3a40.PORTAADDR
+address_a[0] => ram_block3a41.PORTAADDR
+address_a[0] => ram_block3a42.PORTAADDR
+address_a[0] => ram_block3a43.PORTAADDR
+address_a[0] => ram_block3a44.PORTAADDR
+address_a[0] => ram_block3a45.PORTAADDR
+address_a[0] => ram_block3a46.PORTAADDR
+address_a[0] => ram_block3a47.PORTAADDR
+address_a[0] => ram_block3a48.PORTAADDR
+address_a[0] => ram_block3a49.PORTAADDR
+address_a[0] => ram_block3a50.PORTAADDR
+address_a[0] => ram_block3a51.PORTAADDR
+address_a[0] => ram_block3a52.PORTAADDR
+address_a[0] => ram_block3a53.PORTAADDR
+address_a[0] => ram_block3a54.PORTAADDR
+address_a[0] => ram_block3a55.PORTAADDR
+address_a[0] => ram_block3a56.PORTAADDR
+address_a[0] => ram_block3a57.PORTAADDR
+address_a[0] => ram_block3a58.PORTAADDR
+address_a[0] => ram_block3a59.PORTAADDR
+address_a[0] => ram_block3a60.PORTAADDR
+address_a[0] => ram_block3a61.PORTAADDR
+address_a[0] => ram_block3a62.PORTAADDR
+address_a[0] => ram_block3a63.PORTAADDR
+address_a[0] => ram_block3a64.PORTAADDR
+address_a[0] => ram_block3a65.PORTAADDR
+address_a[0] => ram_block3a66.PORTAADDR
+address_a[0] => ram_block3a67.PORTAADDR
+address_a[0] => ram_block3a68.PORTAADDR
+address_a[0] => ram_block3a69.PORTAADDR
+address_a[0] => ram_block3a70.PORTAADDR
+address_a[0] => ram_block3a71.PORTAADDR
+address_a[0] => ram_block3a72.PORTAADDR
+address_a[0] => ram_block3a73.PORTAADDR
+address_a[0] => ram_block3a74.PORTAADDR
+address_a[0] => ram_block3a75.PORTAADDR
+address_a[0] => ram_block3a76.PORTAADDR
+address_a[0] => ram_block3a77.PORTAADDR
+address_a[0] => ram_block3a78.PORTAADDR
+address_a[0] => ram_block3a79.PORTAADDR
+address_a[0] => ram_block3a80.PORTAADDR
+address_a[0] => ram_block3a81.PORTAADDR
+address_a[0] => ram_block3a82.PORTAADDR
+address_a[0] => ram_block3a83.PORTAADDR
+address_a[0] => ram_block3a84.PORTAADDR
+address_a[0] => ram_block3a85.PORTAADDR
+address_a[0] => ram_block3a86.PORTAADDR
+address_a[0] => ram_block3a87.PORTAADDR
+address_a[0] => ram_block3a88.PORTAADDR
+address_a[0] => ram_block3a89.PORTAADDR
+address_a[0] => ram_block3a90.PORTAADDR
+address_a[0] => ram_block3a91.PORTAADDR
+address_a[0] => ram_block3a92.PORTAADDR
+address_a[0] => ram_block3a93.PORTAADDR
+address_a[0] => ram_block3a94.PORTAADDR
+address_a[0] => ram_block3a95.PORTAADDR
+address_a[0] => ram_block3a96.PORTAADDR
+address_a[0] => ram_block3a97.PORTAADDR
+address_a[0] => ram_block3a98.PORTAADDR
+address_a[0] => ram_block3a99.PORTAADDR
+address_a[0] => ram_block3a100.PORTAADDR
+address_a[0] => ram_block3a101.PORTAADDR
+address_a[0] => ram_block3a102.PORTAADDR
+address_a[0] => ram_block3a103.PORTAADDR
+address_a[0] => ram_block3a104.PORTAADDR
+address_a[0] => ram_block3a105.PORTAADDR
+address_a[0] => ram_block3a106.PORTAADDR
+address_a[0] => ram_block3a107.PORTAADDR
+address_a[0] => ram_block3a108.PORTAADDR
+address_a[0] => ram_block3a109.PORTAADDR
+address_a[0] => ram_block3a110.PORTAADDR
+address_a[0] => ram_block3a111.PORTAADDR
+address_a[0] => ram_block3a112.PORTAADDR
+address_a[0] => ram_block3a113.PORTAADDR
+address_a[0] => ram_block3a114.PORTAADDR
+address_a[0] => ram_block3a115.PORTAADDR
+address_a[0] => ram_block3a116.PORTAADDR
+address_a[0] => ram_block3a117.PORTAADDR
+address_a[0] => ram_block3a118.PORTAADDR
+address_a[0] => ram_block3a119.PORTAADDR
+address_a[0] => ram_block3a120.PORTAADDR
+address_a[0] => ram_block3a121.PORTAADDR
+address_a[0] => ram_block3a122.PORTAADDR
+address_a[0] => ram_block3a123.PORTAADDR
+address_a[0] => ram_block3a124.PORTAADDR
+address_a[0] => ram_block3a125.PORTAADDR
+address_a[0] => ram_block3a126.PORTAADDR
+address_a[0] => ram_block3a127.PORTAADDR
+address_a[0] => ram_block3a128.PORTAADDR
+address_a[0] => ram_block3a129.PORTAADDR
+address_a[0] => ram_block3a130.PORTAADDR
+address_a[0] => ram_block3a131.PORTAADDR
+address_a[0] => ram_block3a132.PORTAADDR
+address_a[0] => ram_block3a133.PORTAADDR
+address_a[0] => ram_block3a134.PORTAADDR
+address_a[0] => ram_block3a135.PORTAADDR
+address_a[0] => ram_block3a136.PORTAADDR
+address_a[0] => ram_block3a137.PORTAADDR
+address_a[0] => ram_block3a138.PORTAADDR
+address_a[0] => ram_block3a139.PORTAADDR
+address_a[0] => ram_block3a140.PORTAADDR
+address_a[0] => ram_block3a141.PORTAADDR
+address_a[0] => ram_block3a142.PORTAADDR
+address_a[0] => ram_block3a143.PORTAADDR
+address_a[0] => ram_block3a144.PORTAADDR
+address_a[0] => ram_block3a145.PORTAADDR
+address_a[0] => ram_block3a146.PORTAADDR
+address_a[0] => ram_block3a147.PORTAADDR
+address_a[0] => ram_block3a148.PORTAADDR
+address_a[0] => ram_block3a149.PORTAADDR
+address_a[1] => ram_block3a0.PORTAADDR1
+address_a[1] => ram_block3a1.PORTAADDR1
+address_a[1] => ram_block3a2.PORTAADDR1
+address_a[1] => ram_block3a3.PORTAADDR1
+address_a[1] => ram_block3a4.PORTAADDR1
+address_a[1] => ram_block3a5.PORTAADDR1
+address_a[1] => ram_block3a6.PORTAADDR1
+address_a[1] => ram_block3a7.PORTAADDR1
+address_a[1] => ram_block3a8.PORTAADDR1
+address_a[1] => ram_block3a9.PORTAADDR1
+address_a[1] => ram_block3a10.PORTAADDR1
+address_a[1] => ram_block3a11.PORTAADDR1
+address_a[1] => ram_block3a12.PORTAADDR1
+address_a[1] => ram_block3a13.PORTAADDR1
+address_a[1] => ram_block3a14.PORTAADDR1
+address_a[1] => ram_block3a15.PORTAADDR1
+address_a[1] => ram_block3a16.PORTAADDR1
+address_a[1] => ram_block3a17.PORTAADDR1
+address_a[1] => ram_block3a18.PORTAADDR1
+address_a[1] => ram_block3a19.PORTAADDR1
+address_a[1] => ram_block3a20.PORTAADDR1
+address_a[1] => ram_block3a21.PORTAADDR1
+address_a[1] => ram_block3a22.PORTAADDR1
+address_a[1] => ram_block3a23.PORTAADDR1
+address_a[1] => ram_block3a24.PORTAADDR1
+address_a[1] => ram_block3a25.PORTAADDR1
+address_a[1] => ram_block3a26.PORTAADDR1
+address_a[1] => ram_block3a27.PORTAADDR1
+address_a[1] => ram_block3a28.PORTAADDR1
+address_a[1] => ram_block3a29.PORTAADDR1
+address_a[1] => ram_block3a30.PORTAADDR1
+address_a[1] => ram_block3a31.PORTAADDR1
+address_a[1] => ram_block3a32.PORTAADDR1
+address_a[1] => ram_block3a33.PORTAADDR1
+address_a[1] => ram_block3a34.PORTAADDR1
+address_a[1] => ram_block3a35.PORTAADDR1
+address_a[1] => ram_block3a36.PORTAADDR1
+address_a[1] => ram_block3a37.PORTAADDR1
+address_a[1] => ram_block3a38.PORTAADDR1
+address_a[1] => ram_block3a39.PORTAADDR1
+address_a[1] => ram_block3a40.PORTAADDR1
+address_a[1] => ram_block3a41.PORTAADDR1
+address_a[1] => ram_block3a42.PORTAADDR1
+address_a[1] => ram_block3a43.PORTAADDR1
+address_a[1] => ram_block3a44.PORTAADDR1
+address_a[1] => ram_block3a45.PORTAADDR1
+address_a[1] => ram_block3a46.PORTAADDR1
+address_a[1] => ram_block3a47.PORTAADDR1
+address_a[1] => ram_block3a48.PORTAADDR1
+address_a[1] => ram_block3a49.PORTAADDR1
+address_a[1] => ram_block3a50.PORTAADDR1
+address_a[1] => ram_block3a51.PORTAADDR1
+address_a[1] => ram_block3a52.PORTAADDR1
+address_a[1] => ram_block3a53.PORTAADDR1
+address_a[1] => ram_block3a54.PORTAADDR1
+address_a[1] => ram_block3a55.PORTAADDR1
+address_a[1] => ram_block3a56.PORTAADDR1
+address_a[1] => ram_block3a57.PORTAADDR1
+address_a[1] => ram_block3a58.PORTAADDR1
+address_a[1] => ram_block3a59.PORTAADDR1
+address_a[1] => ram_block3a60.PORTAADDR1
+address_a[1] => ram_block3a61.PORTAADDR1
+address_a[1] => ram_block3a62.PORTAADDR1
+address_a[1] => ram_block3a63.PORTAADDR1
+address_a[1] => ram_block3a64.PORTAADDR1
+address_a[1] => ram_block3a65.PORTAADDR1
+address_a[1] => ram_block3a66.PORTAADDR1
+address_a[1] => ram_block3a67.PORTAADDR1
+address_a[1] => ram_block3a68.PORTAADDR1
+address_a[1] => ram_block3a69.PORTAADDR1
+address_a[1] => ram_block3a70.PORTAADDR1
+address_a[1] => ram_block3a71.PORTAADDR1
+address_a[1] => ram_block3a72.PORTAADDR1
+address_a[1] => ram_block3a73.PORTAADDR1
+address_a[1] => ram_block3a74.PORTAADDR1
+address_a[1] => ram_block3a75.PORTAADDR1
+address_a[1] => ram_block3a76.PORTAADDR1
+address_a[1] => ram_block3a77.PORTAADDR1
+address_a[1] => ram_block3a78.PORTAADDR1
+address_a[1] => ram_block3a79.PORTAADDR1
+address_a[1] => ram_block3a80.PORTAADDR1
+address_a[1] => ram_block3a81.PORTAADDR1
+address_a[1] => ram_block3a82.PORTAADDR1
+address_a[1] => ram_block3a83.PORTAADDR1
+address_a[1] => ram_block3a84.PORTAADDR1
+address_a[1] => ram_block3a85.PORTAADDR1
+address_a[1] => ram_block3a86.PORTAADDR1
+address_a[1] => ram_block3a87.PORTAADDR1
+address_a[1] => ram_block3a88.PORTAADDR1
+address_a[1] => ram_block3a89.PORTAADDR1
+address_a[1] => ram_block3a90.PORTAADDR1
+address_a[1] => ram_block3a91.PORTAADDR1
+address_a[1] => ram_block3a92.PORTAADDR1
+address_a[1] => ram_block3a93.PORTAADDR1
+address_a[1] => ram_block3a94.PORTAADDR1
+address_a[1] => ram_block3a95.PORTAADDR1
+address_a[1] => ram_block3a96.PORTAADDR1
+address_a[1] => ram_block3a97.PORTAADDR1
+address_a[1] => ram_block3a98.PORTAADDR1
+address_a[1] => ram_block3a99.PORTAADDR1
+address_a[1] => ram_block3a100.PORTAADDR1
+address_a[1] => ram_block3a101.PORTAADDR1
+address_a[1] => ram_block3a102.PORTAADDR1
+address_a[1] => ram_block3a103.PORTAADDR1
+address_a[1] => ram_block3a104.PORTAADDR1
+address_a[1] => ram_block3a105.PORTAADDR1
+address_a[1] => ram_block3a106.PORTAADDR1
+address_a[1] => ram_block3a107.PORTAADDR1
+address_a[1] => ram_block3a108.PORTAADDR1
+address_a[1] => ram_block3a109.PORTAADDR1
+address_a[1] => ram_block3a110.PORTAADDR1
+address_a[1] => ram_block3a111.PORTAADDR1
+address_a[1] => ram_block3a112.PORTAADDR1
+address_a[1] => ram_block3a113.PORTAADDR1
+address_a[1] => ram_block3a114.PORTAADDR1
+address_a[1] => ram_block3a115.PORTAADDR1
+address_a[1] => ram_block3a116.PORTAADDR1
+address_a[1] => ram_block3a117.PORTAADDR1
+address_a[1] => ram_block3a118.PORTAADDR1
+address_a[1] => ram_block3a119.PORTAADDR1
+address_a[1] => ram_block3a120.PORTAADDR1
+address_a[1] => ram_block3a121.PORTAADDR1
+address_a[1] => ram_block3a122.PORTAADDR1
+address_a[1] => ram_block3a123.PORTAADDR1
+address_a[1] => ram_block3a124.PORTAADDR1
+address_a[1] => ram_block3a125.PORTAADDR1
+address_a[1] => ram_block3a126.PORTAADDR1
+address_a[1] => ram_block3a127.PORTAADDR1
+address_a[1] => ram_block3a128.PORTAADDR1
+address_a[1] => ram_block3a129.PORTAADDR1
+address_a[1] => ram_block3a130.PORTAADDR1
+address_a[1] => ram_block3a131.PORTAADDR1
+address_a[1] => ram_block3a132.PORTAADDR1
+address_a[1] => ram_block3a133.PORTAADDR1
+address_a[1] => ram_block3a134.PORTAADDR1
+address_a[1] => ram_block3a135.PORTAADDR1
+address_a[1] => ram_block3a136.PORTAADDR1
+address_a[1] => ram_block3a137.PORTAADDR1
+address_a[1] => ram_block3a138.PORTAADDR1
+address_a[1] => ram_block3a139.PORTAADDR1
+address_a[1] => ram_block3a140.PORTAADDR1
+address_a[1] => ram_block3a141.PORTAADDR1
+address_a[1] => ram_block3a142.PORTAADDR1
+address_a[1] => ram_block3a143.PORTAADDR1
+address_a[1] => ram_block3a144.PORTAADDR1
+address_a[1] => ram_block3a145.PORTAADDR1
+address_a[1] => ram_block3a146.PORTAADDR1
+address_a[1] => ram_block3a147.PORTAADDR1
+address_a[1] => ram_block3a148.PORTAADDR1
+address_a[1] => ram_block3a149.PORTAADDR1
+address_a[2] => ram_block3a0.PORTAADDR2
+address_a[2] => ram_block3a1.PORTAADDR2
+address_a[2] => ram_block3a2.PORTAADDR2
+address_a[2] => ram_block3a3.PORTAADDR2
+address_a[2] => ram_block3a4.PORTAADDR2
+address_a[2] => ram_block3a5.PORTAADDR2
+address_a[2] => ram_block3a6.PORTAADDR2
+address_a[2] => ram_block3a7.PORTAADDR2
+address_a[2] => ram_block3a8.PORTAADDR2
+address_a[2] => ram_block3a9.PORTAADDR2
+address_a[2] => ram_block3a10.PORTAADDR2
+address_a[2] => ram_block3a11.PORTAADDR2
+address_a[2] => ram_block3a12.PORTAADDR2
+address_a[2] => ram_block3a13.PORTAADDR2
+address_a[2] => ram_block3a14.PORTAADDR2
+address_a[2] => ram_block3a15.PORTAADDR2
+address_a[2] => ram_block3a16.PORTAADDR2
+address_a[2] => ram_block3a17.PORTAADDR2
+address_a[2] => ram_block3a18.PORTAADDR2
+address_a[2] => ram_block3a19.PORTAADDR2
+address_a[2] => ram_block3a20.PORTAADDR2
+address_a[2] => ram_block3a21.PORTAADDR2
+address_a[2] => ram_block3a22.PORTAADDR2
+address_a[2] => ram_block3a23.PORTAADDR2
+address_a[2] => ram_block3a24.PORTAADDR2
+address_a[2] => ram_block3a25.PORTAADDR2
+address_a[2] => ram_block3a26.PORTAADDR2
+address_a[2] => ram_block3a27.PORTAADDR2
+address_a[2] => ram_block3a28.PORTAADDR2
+address_a[2] => ram_block3a29.PORTAADDR2
+address_a[2] => ram_block3a30.PORTAADDR2
+address_a[2] => ram_block3a31.PORTAADDR2
+address_a[2] => ram_block3a32.PORTAADDR2
+address_a[2] => ram_block3a33.PORTAADDR2
+address_a[2] => ram_block3a34.PORTAADDR2
+address_a[2] => ram_block3a35.PORTAADDR2
+address_a[2] => ram_block3a36.PORTAADDR2
+address_a[2] => ram_block3a37.PORTAADDR2
+address_a[2] => ram_block3a38.PORTAADDR2
+address_a[2] => ram_block3a39.PORTAADDR2
+address_a[2] => ram_block3a40.PORTAADDR2
+address_a[2] => ram_block3a41.PORTAADDR2
+address_a[2] => ram_block3a42.PORTAADDR2
+address_a[2] => ram_block3a43.PORTAADDR2
+address_a[2] => ram_block3a44.PORTAADDR2
+address_a[2] => ram_block3a45.PORTAADDR2
+address_a[2] => ram_block3a46.PORTAADDR2
+address_a[2] => ram_block3a47.PORTAADDR2
+address_a[2] => ram_block3a48.PORTAADDR2
+address_a[2] => ram_block3a49.PORTAADDR2
+address_a[2] => ram_block3a50.PORTAADDR2
+address_a[2] => ram_block3a51.PORTAADDR2
+address_a[2] => ram_block3a52.PORTAADDR2
+address_a[2] => ram_block3a53.PORTAADDR2
+address_a[2] => ram_block3a54.PORTAADDR2
+address_a[2] => ram_block3a55.PORTAADDR2
+address_a[2] => ram_block3a56.PORTAADDR2
+address_a[2] => ram_block3a57.PORTAADDR2
+address_a[2] => ram_block3a58.PORTAADDR2
+address_a[2] => ram_block3a59.PORTAADDR2
+address_a[2] => ram_block3a60.PORTAADDR2
+address_a[2] => ram_block3a61.PORTAADDR2
+address_a[2] => ram_block3a62.PORTAADDR2
+address_a[2] => ram_block3a63.PORTAADDR2
+address_a[2] => ram_block3a64.PORTAADDR2
+address_a[2] => ram_block3a65.PORTAADDR2
+address_a[2] => ram_block3a66.PORTAADDR2
+address_a[2] => ram_block3a67.PORTAADDR2
+address_a[2] => ram_block3a68.PORTAADDR2
+address_a[2] => ram_block3a69.PORTAADDR2
+address_a[2] => ram_block3a70.PORTAADDR2
+address_a[2] => ram_block3a71.PORTAADDR2
+address_a[2] => ram_block3a72.PORTAADDR2
+address_a[2] => ram_block3a73.PORTAADDR2
+address_a[2] => ram_block3a74.PORTAADDR2
+address_a[2] => ram_block3a75.PORTAADDR2
+address_a[2] => ram_block3a76.PORTAADDR2
+address_a[2] => ram_block3a77.PORTAADDR2
+address_a[2] => ram_block3a78.PORTAADDR2
+address_a[2] => ram_block3a79.PORTAADDR2
+address_a[2] => ram_block3a80.PORTAADDR2
+address_a[2] => ram_block3a81.PORTAADDR2
+address_a[2] => ram_block3a82.PORTAADDR2
+address_a[2] => ram_block3a83.PORTAADDR2
+address_a[2] => ram_block3a84.PORTAADDR2
+address_a[2] => ram_block3a85.PORTAADDR2
+address_a[2] => ram_block3a86.PORTAADDR2
+address_a[2] => ram_block3a87.PORTAADDR2
+address_a[2] => ram_block3a88.PORTAADDR2
+address_a[2] => ram_block3a89.PORTAADDR2
+address_a[2] => ram_block3a90.PORTAADDR2
+address_a[2] => ram_block3a91.PORTAADDR2
+address_a[2] => ram_block3a92.PORTAADDR2
+address_a[2] => ram_block3a93.PORTAADDR2
+address_a[2] => ram_block3a94.PORTAADDR2
+address_a[2] => ram_block3a95.PORTAADDR2
+address_a[2] => ram_block3a96.PORTAADDR2
+address_a[2] => ram_block3a97.PORTAADDR2
+address_a[2] => ram_block3a98.PORTAADDR2
+address_a[2] => ram_block3a99.PORTAADDR2
+address_a[2] => ram_block3a100.PORTAADDR2
+address_a[2] => ram_block3a101.PORTAADDR2
+address_a[2] => ram_block3a102.PORTAADDR2
+address_a[2] => ram_block3a103.PORTAADDR2
+address_a[2] => ram_block3a104.PORTAADDR2
+address_a[2] => ram_block3a105.PORTAADDR2
+address_a[2] => ram_block3a106.PORTAADDR2
+address_a[2] => ram_block3a107.PORTAADDR2
+address_a[2] => ram_block3a108.PORTAADDR2
+address_a[2] => ram_block3a109.PORTAADDR2
+address_a[2] => ram_block3a110.PORTAADDR2
+address_a[2] => ram_block3a111.PORTAADDR2
+address_a[2] => ram_block3a112.PORTAADDR2
+address_a[2] => ram_block3a113.PORTAADDR2
+address_a[2] => ram_block3a114.PORTAADDR2
+address_a[2] => ram_block3a115.PORTAADDR2
+address_a[2] => ram_block3a116.PORTAADDR2
+address_a[2] => ram_block3a117.PORTAADDR2
+address_a[2] => ram_block3a118.PORTAADDR2
+address_a[2] => ram_block3a119.PORTAADDR2
+address_a[2] => ram_block3a120.PORTAADDR2
+address_a[2] => ram_block3a121.PORTAADDR2
+address_a[2] => ram_block3a122.PORTAADDR2
+address_a[2] => ram_block3a123.PORTAADDR2
+address_a[2] => ram_block3a124.PORTAADDR2
+address_a[2] => ram_block3a125.PORTAADDR2
+address_a[2] => ram_block3a126.PORTAADDR2
+address_a[2] => ram_block3a127.PORTAADDR2
+address_a[2] => ram_block3a128.PORTAADDR2
+address_a[2] => ram_block3a129.PORTAADDR2
+address_a[2] => ram_block3a130.PORTAADDR2
+address_a[2] => ram_block3a131.PORTAADDR2
+address_a[2] => ram_block3a132.PORTAADDR2
+address_a[2] => ram_block3a133.PORTAADDR2
+address_a[2] => ram_block3a134.PORTAADDR2
+address_a[2] => ram_block3a135.PORTAADDR2
+address_a[2] => ram_block3a136.PORTAADDR2
+address_a[2] => ram_block3a137.PORTAADDR2
+address_a[2] => ram_block3a138.PORTAADDR2
+address_a[2] => ram_block3a139.PORTAADDR2
+address_a[2] => ram_block3a140.PORTAADDR2
+address_a[2] => ram_block3a141.PORTAADDR2
+address_a[2] => ram_block3a142.PORTAADDR2
+address_a[2] => ram_block3a143.PORTAADDR2
+address_a[2] => ram_block3a144.PORTAADDR2
+address_a[2] => ram_block3a145.PORTAADDR2
+address_a[2] => ram_block3a146.PORTAADDR2
+address_a[2] => ram_block3a147.PORTAADDR2
+address_a[2] => ram_block3a148.PORTAADDR2
+address_a[2] => ram_block3a149.PORTAADDR2
+address_a[3] => ram_block3a0.PORTAADDR3
+address_a[3] => ram_block3a1.PORTAADDR3
+address_a[3] => ram_block3a2.PORTAADDR3
+address_a[3] => ram_block3a3.PORTAADDR3
+address_a[3] => ram_block3a4.PORTAADDR3
+address_a[3] => ram_block3a5.PORTAADDR3
+address_a[3] => ram_block3a6.PORTAADDR3
+address_a[3] => ram_block3a7.PORTAADDR3
+address_a[3] => ram_block3a8.PORTAADDR3
+address_a[3] => ram_block3a9.PORTAADDR3
+address_a[3] => ram_block3a10.PORTAADDR3
+address_a[3] => ram_block3a11.PORTAADDR3
+address_a[3] => ram_block3a12.PORTAADDR3
+address_a[3] => ram_block3a13.PORTAADDR3
+address_a[3] => ram_block3a14.PORTAADDR3
+address_a[3] => ram_block3a15.PORTAADDR3
+address_a[3] => ram_block3a16.PORTAADDR3
+address_a[3] => ram_block3a17.PORTAADDR3
+address_a[3] => ram_block3a18.PORTAADDR3
+address_a[3] => ram_block3a19.PORTAADDR3
+address_a[3] => ram_block3a20.PORTAADDR3
+address_a[3] => ram_block3a21.PORTAADDR3
+address_a[3] => ram_block3a22.PORTAADDR3
+address_a[3] => ram_block3a23.PORTAADDR3
+address_a[3] => ram_block3a24.PORTAADDR3
+address_a[3] => ram_block3a25.PORTAADDR3
+address_a[3] => ram_block3a26.PORTAADDR3
+address_a[3] => ram_block3a27.PORTAADDR3
+address_a[3] => ram_block3a28.PORTAADDR3
+address_a[3] => ram_block3a29.PORTAADDR3
+address_a[3] => ram_block3a30.PORTAADDR3
+address_a[3] => ram_block3a31.PORTAADDR3
+address_a[3] => ram_block3a32.PORTAADDR3
+address_a[3] => ram_block3a33.PORTAADDR3
+address_a[3] => ram_block3a34.PORTAADDR3
+address_a[3] => ram_block3a35.PORTAADDR3
+address_a[3] => ram_block3a36.PORTAADDR3
+address_a[3] => ram_block3a37.PORTAADDR3
+address_a[3] => ram_block3a38.PORTAADDR3
+address_a[3] => ram_block3a39.PORTAADDR3
+address_a[3] => ram_block3a40.PORTAADDR3
+address_a[3] => ram_block3a41.PORTAADDR3
+address_a[3] => ram_block3a42.PORTAADDR3
+address_a[3] => ram_block3a43.PORTAADDR3
+address_a[3] => ram_block3a44.PORTAADDR3
+address_a[3] => ram_block3a45.PORTAADDR3
+address_a[3] => ram_block3a46.PORTAADDR3
+address_a[3] => ram_block3a47.PORTAADDR3
+address_a[3] => ram_block3a48.PORTAADDR3
+address_a[3] => ram_block3a49.PORTAADDR3
+address_a[3] => ram_block3a50.PORTAADDR3
+address_a[3] => ram_block3a51.PORTAADDR3
+address_a[3] => ram_block3a52.PORTAADDR3
+address_a[3] => ram_block3a53.PORTAADDR3
+address_a[3] => ram_block3a54.PORTAADDR3
+address_a[3] => ram_block3a55.PORTAADDR3
+address_a[3] => ram_block3a56.PORTAADDR3
+address_a[3] => ram_block3a57.PORTAADDR3
+address_a[3] => ram_block3a58.PORTAADDR3
+address_a[3] => ram_block3a59.PORTAADDR3
+address_a[3] => ram_block3a60.PORTAADDR3
+address_a[3] => ram_block3a61.PORTAADDR3
+address_a[3] => ram_block3a62.PORTAADDR3
+address_a[3] => ram_block3a63.PORTAADDR3
+address_a[3] => ram_block3a64.PORTAADDR3
+address_a[3] => ram_block3a65.PORTAADDR3
+address_a[3] => ram_block3a66.PORTAADDR3
+address_a[3] => ram_block3a67.PORTAADDR3
+address_a[3] => ram_block3a68.PORTAADDR3
+address_a[3] => ram_block3a69.PORTAADDR3
+address_a[3] => ram_block3a70.PORTAADDR3
+address_a[3] => ram_block3a71.PORTAADDR3
+address_a[3] => ram_block3a72.PORTAADDR3
+address_a[3] => ram_block3a73.PORTAADDR3
+address_a[3] => ram_block3a74.PORTAADDR3
+address_a[3] => ram_block3a75.PORTAADDR3
+address_a[3] => ram_block3a76.PORTAADDR3
+address_a[3] => ram_block3a77.PORTAADDR3
+address_a[3] => ram_block3a78.PORTAADDR3
+address_a[3] => ram_block3a79.PORTAADDR3
+address_a[3] => ram_block3a80.PORTAADDR3
+address_a[3] => ram_block3a81.PORTAADDR3
+address_a[3] => ram_block3a82.PORTAADDR3
+address_a[3] => ram_block3a83.PORTAADDR3
+address_a[3] => ram_block3a84.PORTAADDR3
+address_a[3] => ram_block3a85.PORTAADDR3
+address_a[3] => ram_block3a86.PORTAADDR3
+address_a[3] => ram_block3a87.PORTAADDR3
+address_a[3] => ram_block3a88.PORTAADDR3
+address_a[3] => ram_block3a89.PORTAADDR3
+address_a[3] => ram_block3a90.PORTAADDR3
+address_a[3] => ram_block3a91.PORTAADDR3
+address_a[3] => ram_block3a92.PORTAADDR3
+address_a[3] => ram_block3a93.PORTAADDR3
+address_a[3] => ram_block3a94.PORTAADDR3
+address_a[3] => ram_block3a95.PORTAADDR3
+address_a[3] => ram_block3a96.PORTAADDR3
+address_a[3] => ram_block3a97.PORTAADDR3
+address_a[3] => ram_block3a98.PORTAADDR3
+address_a[3] => ram_block3a99.PORTAADDR3
+address_a[3] => ram_block3a100.PORTAADDR3
+address_a[3] => ram_block3a101.PORTAADDR3
+address_a[3] => ram_block3a102.PORTAADDR3
+address_a[3] => ram_block3a103.PORTAADDR3
+address_a[3] => ram_block3a104.PORTAADDR3
+address_a[3] => ram_block3a105.PORTAADDR3
+address_a[3] => ram_block3a106.PORTAADDR3
+address_a[3] => ram_block3a107.PORTAADDR3
+address_a[3] => ram_block3a108.PORTAADDR3
+address_a[3] => ram_block3a109.PORTAADDR3
+address_a[3] => ram_block3a110.PORTAADDR3
+address_a[3] => ram_block3a111.PORTAADDR3
+address_a[3] => ram_block3a112.PORTAADDR3
+address_a[3] => ram_block3a113.PORTAADDR3
+address_a[3] => ram_block3a114.PORTAADDR3
+address_a[3] => ram_block3a115.PORTAADDR3
+address_a[3] => ram_block3a116.PORTAADDR3
+address_a[3] => ram_block3a117.PORTAADDR3
+address_a[3] => ram_block3a118.PORTAADDR3
+address_a[3] => ram_block3a119.PORTAADDR3
+address_a[3] => ram_block3a120.PORTAADDR3
+address_a[3] => ram_block3a121.PORTAADDR3
+address_a[3] => ram_block3a122.PORTAADDR3
+address_a[3] => ram_block3a123.PORTAADDR3
+address_a[3] => ram_block3a124.PORTAADDR3
+address_a[3] => ram_block3a125.PORTAADDR3
+address_a[3] => ram_block3a126.PORTAADDR3
+address_a[3] => ram_block3a127.PORTAADDR3
+address_a[3] => ram_block3a128.PORTAADDR3
+address_a[3] => ram_block3a129.PORTAADDR3
+address_a[3] => ram_block3a130.PORTAADDR3
+address_a[3] => ram_block3a131.PORTAADDR3
+address_a[3] => ram_block3a132.PORTAADDR3
+address_a[3] => ram_block3a133.PORTAADDR3
+address_a[3] => ram_block3a134.PORTAADDR3
+address_a[3] => ram_block3a135.PORTAADDR3
+address_a[3] => ram_block3a136.PORTAADDR3
+address_a[3] => ram_block3a137.PORTAADDR3
+address_a[3] => ram_block3a138.PORTAADDR3
+address_a[3] => ram_block3a139.PORTAADDR3
+address_a[3] => ram_block3a140.PORTAADDR3
+address_a[3] => ram_block3a141.PORTAADDR3
+address_a[3] => ram_block3a142.PORTAADDR3
+address_a[3] => ram_block3a143.PORTAADDR3
+address_a[3] => ram_block3a144.PORTAADDR3
+address_a[3] => ram_block3a145.PORTAADDR3
+address_a[3] => ram_block3a146.PORTAADDR3
+address_a[3] => ram_block3a147.PORTAADDR3
+address_a[3] => ram_block3a148.PORTAADDR3
+address_a[3] => ram_block3a149.PORTAADDR3
+address_a[4] => ram_block3a0.PORTAADDR4
+address_a[4] => ram_block3a1.PORTAADDR4
+address_a[4] => ram_block3a2.PORTAADDR4
+address_a[4] => ram_block3a3.PORTAADDR4
+address_a[4] => ram_block3a4.PORTAADDR4
+address_a[4] => ram_block3a5.PORTAADDR4
+address_a[4] => ram_block3a6.PORTAADDR4
+address_a[4] => ram_block3a7.PORTAADDR4
+address_a[4] => ram_block3a8.PORTAADDR4
+address_a[4] => ram_block3a9.PORTAADDR4
+address_a[4] => ram_block3a10.PORTAADDR4
+address_a[4] => ram_block3a11.PORTAADDR4
+address_a[4] => ram_block3a12.PORTAADDR4
+address_a[4] => ram_block3a13.PORTAADDR4
+address_a[4] => ram_block3a14.PORTAADDR4
+address_a[4] => ram_block3a15.PORTAADDR4
+address_a[4] => ram_block3a16.PORTAADDR4
+address_a[4] => ram_block3a17.PORTAADDR4
+address_a[4] => ram_block3a18.PORTAADDR4
+address_a[4] => ram_block3a19.PORTAADDR4
+address_a[4] => ram_block3a20.PORTAADDR4
+address_a[4] => ram_block3a21.PORTAADDR4
+address_a[4] => ram_block3a22.PORTAADDR4
+address_a[4] => ram_block3a23.PORTAADDR4
+address_a[4] => ram_block3a24.PORTAADDR4
+address_a[4] => ram_block3a25.PORTAADDR4
+address_a[4] => ram_block3a26.PORTAADDR4
+address_a[4] => ram_block3a27.PORTAADDR4
+address_a[4] => ram_block3a28.PORTAADDR4
+address_a[4] => ram_block3a29.PORTAADDR4
+address_a[4] => ram_block3a30.PORTAADDR4
+address_a[4] => ram_block3a31.PORTAADDR4
+address_a[4] => ram_block3a32.PORTAADDR4
+address_a[4] => ram_block3a33.PORTAADDR4
+address_a[4] => ram_block3a34.PORTAADDR4
+address_a[4] => ram_block3a35.PORTAADDR4
+address_a[4] => ram_block3a36.PORTAADDR4
+address_a[4] => ram_block3a37.PORTAADDR4
+address_a[4] => ram_block3a38.PORTAADDR4
+address_a[4] => ram_block3a39.PORTAADDR4
+address_a[4] => ram_block3a40.PORTAADDR4
+address_a[4] => ram_block3a41.PORTAADDR4
+address_a[4] => ram_block3a42.PORTAADDR4
+address_a[4] => ram_block3a43.PORTAADDR4
+address_a[4] => ram_block3a44.PORTAADDR4
+address_a[4] => ram_block3a45.PORTAADDR4
+address_a[4] => ram_block3a46.PORTAADDR4
+address_a[4] => ram_block3a47.PORTAADDR4
+address_a[4] => ram_block3a48.PORTAADDR4
+address_a[4] => ram_block3a49.PORTAADDR4
+address_a[4] => ram_block3a50.PORTAADDR4
+address_a[4] => ram_block3a51.PORTAADDR4
+address_a[4] => ram_block3a52.PORTAADDR4
+address_a[4] => ram_block3a53.PORTAADDR4
+address_a[4] => ram_block3a54.PORTAADDR4
+address_a[4] => ram_block3a55.PORTAADDR4
+address_a[4] => ram_block3a56.PORTAADDR4
+address_a[4] => ram_block3a57.PORTAADDR4
+address_a[4] => ram_block3a58.PORTAADDR4
+address_a[4] => ram_block3a59.PORTAADDR4
+address_a[4] => ram_block3a60.PORTAADDR4
+address_a[4] => ram_block3a61.PORTAADDR4
+address_a[4] => ram_block3a62.PORTAADDR4
+address_a[4] => ram_block3a63.PORTAADDR4
+address_a[4] => ram_block3a64.PORTAADDR4
+address_a[4] => ram_block3a65.PORTAADDR4
+address_a[4] => ram_block3a66.PORTAADDR4
+address_a[4] => ram_block3a67.PORTAADDR4
+address_a[4] => ram_block3a68.PORTAADDR4
+address_a[4] => ram_block3a69.PORTAADDR4
+address_a[4] => ram_block3a70.PORTAADDR4
+address_a[4] => ram_block3a71.PORTAADDR4
+address_a[4] => ram_block3a72.PORTAADDR4
+address_a[4] => ram_block3a73.PORTAADDR4
+address_a[4] => ram_block3a74.PORTAADDR4
+address_a[4] => ram_block3a75.PORTAADDR4
+address_a[4] => ram_block3a76.PORTAADDR4
+address_a[4] => ram_block3a77.PORTAADDR4
+address_a[4] => ram_block3a78.PORTAADDR4
+address_a[4] => ram_block3a79.PORTAADDR4
+address_a[4] => ram_block3a80.PORTAADDR4
+address_a[4] => ram_block3a81.PORTAADDR4
+address_a[4] => ram_block3a82.PORTAADDR4
+address_a[4] => ram_block3a83.PORTAADDR4
+address_a[4] => ram_block3a84.PORTAADDR4
+address_a[4] => ram_block3a85.PORTAADDR4
+address_a[4] => ram_block3a86.PORTAADDR4
+address_a[4] => ram_block3a87.PORTAADDR4
+address_a[4] => ram_block3a88.PORTAADDR4
+address_a[4] => ram_block3a89.PORTAADDR4
+address_a[4] => ram_block3a90.PORTAADDR4
+address_a[4] => ram_block3a91.PORTAADDR4
+address_a[4] => ram_block3a92.PORTAADDR4
+address_a[4] => ram_block3a93.PORTAADDR4
+address_a[4] => ram_block3a94.PORTAADDR4
+address_a[4] => ram_block3a95.PORTAADDR4
+address_a[4] => ram_block3a96.PORTAADDR4
+address_a[4] => ram_block3a97.PORTAADDR4
+address_a[4] => ram_block3a98.PORTAADDR4
+address_a[4] => ram_block3a99.PORTAADDR4
+address_a[4] => ram_block3a100.PORTAADDR4
+address_a[4] => ram_block3a101.PORTAADDR4
+address_a[4] => ram_block3a102.PORTAADDR4
+address_a[4] => ram_block3a103.PORTAADDR4
+address_a[4] => ram_block3a104.PORTAADDR4
+address_a[4] => ram_block3a105.PORTAADDR4
+address_a[4] => ram_block3a106.PORTAADDR4
+address_a[4] => ram_block3a107.PORTAADDR4
+address_a[4] => ram_block3a108.PORTAADDR4
+address_a[4] => ram_block3a109.PORTAADDR4
+address_a[4] => ram_block3a110.PORTAADDR4
+address_a[4] => ram_block3a111.PORTAADDR4
+address_a[4] => ram_block3a112.PORTAADDR4
+address_a[4] => ram_block3a113.PORTAADDR4
+address_a[4] => ram_block3a114.PORTAADDR4
+address_a[4] => ram_block3a115.PORTAADDR4
+address_a[4] => ram_block3a116.PORTAADDR4
+address_a[4] => ram_block3a117.PORTAADDR4
+address_a[4] => ram_block3a118.PORTAADDR4
+address_a[4] => ram_block3a119.PORTAADDR4
+address_a[4] => ram_block3a120.PORTAADDR4
+address_a[4] => ram_block3a121.PORTAADDR4
+address_a[4] => ram_block3a122.PORTAADDR4
+address_a[4] => ram_block3a123.PORTAADDR4
+address_a[4] => ram_block3a124.PORTAADDR4
+address_a[4] => ram_block3a125.PORTAADDR4
+address_a[4] => ram_block3a126.PORTAADDR4
+address_a[4] => ram_block3a127.PORTAADDR4
+address_a[4] => ram_block3a128.PORTAADDR4
+address_a[4] => ram_block3a129.PORTAADDR4
+address_a[4] => ram_block3a130.PORTAADDR4
+address_a[4] => ram_block3a131.PORTAADDR4
+address_a[4] => ram_block3a132.PORTAADDR4
+address_a[4] => ram_block3a133.PORTAADDR4
+address_a[4] => ram_block3a134.PORTAADDR4
+address_a[4] => ram_block3a135.PORTAADDR4
+address_a[4] => ram_block3a136.PORTAADDR4
+address_a[4] => ram_block3a137.PORTAADDR4
+address_a[4] => ram_block3a138.PORTAADDR4
+address_a[4] => ram_block3a139.PORTAADDR4
+address_a[4] => ram_block3a140.PORTAADDR4
+address_a[4] => ram_block3a141.PORTAADDR4
+address_a[4] => ram_block3a142.PORTAADDR4
+address_a[4] => ram_block3a143.PORTAADDR4
+address_a[4] => ram_block3a144.PORTAADDR4
+address_a[4] => ram_block3a145.PORTAADDR4
+address_a[4] => ram_block3a146.PORTAADDR4
+address_a[4] => ram_block3a147.PORTAADDR4
+address_a[4] => ram_block3a148.PORTAADDR4
+address_a[4] => ram_block3a149.PORTAADDR4
+address_a[5] => ram_block3a0.PORTAADDR5
+address_a[5] => ram_block3a1.PORTAADDR5
+address_a[5] => ram_block3a2.PORTAADDR5
+address_a[5] => ram_block3a3.PORTAADDR5
+address_a[5] => ram_block3a4.PORTAADDR5
+address_a[5] => ram_block3a5.PORTAADDR5
+address_a[5] => ram_block3a6.PORTAADDR5
+address_a[5] => ram_block3a7.PORTAADDR5
+address_a[5] => ram_block3a8.PORTAADDR5
+address_a[5] => ram_block3a9.PORTAADDR5
+address_a[5] => ram_block3a10.PORTAADDR5
+address_a[5] => ram_block3a11.PORTAADDR5
+address_a[5] => ram_block3a12.PORTAADDR5
+address_a[5] => ram_block3a13.PORTAADDR5
+address_a[5] => ram_block3a14.PORTAADDR5
+address_a[5] => ram_block3a15.PORTAADDR5
+address_a[5] => ram_block3a16.PORTAADDR5
+address_a[5] => ram_block3a17.PORTAADDR5
+address_a[5] => ram_block3a18.PORTAADDR5
+address_a[5] => ram_block3a19.PORTAADDR5
+address_a[5] => ram_block3a20.PORTAADDR5
+address_a[5] => ram_block3a21.PORTAADDR5
+address_a[5] => ram_block3a22.PORTAADDR5
+address_a[5] => ram_block3a23.PORTAADDR5
+address_a[5] => ram_block3a24.PORTAADDR5
+address_a[5] => ram_block3a25.PORTAADDR5
+address_a[5] => ram_block3a26.PORTAADDR5
+address_a[5] => ram_block3a27.PORTAADDR5
+address_a[5] => ram_block3a28.PORTAADDR5
+address_a[5] => ram_block3a29.PORTAADDR5
+address_a[5] => ram_block3a30.PORTAADDR5
+address_a[5] => ram_block3a31.PORTAADDR5
+address_a[5] => ram_block3a32.PORTAADDR5
+address_a[5] => ram_block3a33.PORTAADDR5
+address_a[5] => ram_block3a34.PORTAADDR5
+address_a[5] => ram_block3a35.PORTAADDR5
+address_a[5] => ram_block3a36.PORTAADDR5
+address_a[5] => ram_block3a37.PORTAADDR5
+address_a[5] => ram_block3a38.PORTAADDR5
+address_a[5] => ram_block3a39.PORTAADDR5
+address_a[5] => ram_block3a40.PORTAADDR5
+address_a[5] => ram_block3a41.PORTAADDR5
+address_a[5] => ram_block3a42.PORTAADDR5
+address_a[5] => ram_block3a43.PORTAADDR5
+address_a[5] => ram_block3a44.PORTAADDR5
+address_a[5] => ram_block3a45.PORTAADDR5
+address_a[5] => ram_block3a46.PORTAADDR5
+address_a[5] => ram_block3a47.PORTAADDR5
+address_a[5] => ram_block3a48.PORTAADDR5
+address_a[5] => ram_block3a49.PORTAADDR5
+address_a[5] => ram_block3a50.PORTAADDR5
+address_a[5] => ram_block3a51.PORTAADDR5
+address_a[5] => ram_block3a52.PORTAADDR5
+address_a[5] => ram_block3a53.PORTAADDR5
+address_a[5] => ram_block3a54.PORTAADDR5
+address_a[5] => ram_block3a55.PORTAADDR5
+address_a[5] => ram_block3a56.PORTAADDR5
+address_a[5] => ram_block3a57.PORTAADDR5
+address_a[5] => ram_block3a58.PORTAADDR5
+address_a[5] => ram_block3a59.PORTAADDR5
+address_a[5] => ram_block3a60.PORTAADDR5
+address_a[5] => ram_block3a61.PORTAADDR5
+address_a[5] => ram_block3a62.PORTAADDR5
+address_a[5] => ram_block3a63.PORTAADDR5
+address_a[5] => ram_block3a64.PORTAADDR5
+address_a[5] => ram_block3a65.PORTAADDR5
+address_a[5] => ram_block3a66.PORTAADDR5
+address_a[5] => ram_block3a67.PORTAADDR5
+address_a[5] => ram_block3a68.PORTAADDR5
+address_a[5] => ram_block3a69.PORTAADDR5
+address_a[5] => ram_block3a70.PORTAADDR5
+address_a[5] => ram_block3a71.PORTAADDR5
+address_a[5] => ram_block3a72.PORTAADDR5
+address_a[5] => ram_block3a73.PORTAADDR5
+address_a[5] => ram_block3a74.PORTAADDR5
+address_a[5] => ram_block3a75.PORTAADDR5
+address_a[5] => ram_block3a76.PORTAADDR5
+address_a[5] => ram_block3a77.PORTAADDR5
+address_a[5] => ram_block3a78.PORTAADDR5
+address_a[5] => ram_block3a79.PORTAADDR5
+address_a[5] => ram_block3a80.PORTAADDR5
+address_a[5] => ram_block3a81.PORTAADDR5
+address_a[5] => ram_block3a82.PORTAADDR5
+address_a[5] => ram_block3a83.PORTAADDR5
+address_a[5] => ram_block3a84.PORTAADDR5
+address_a[5] => ram_block3a85.PORTAADDR5
+address_a[5] => ram_block3a86.PORTAADDR5
+address_a[5] => ram_block3a87.PORTAADDR5
+address_a[5] => ram_block3a88.PORTAADDR5
+address_a[5] => ram_block3a89.PORTAADDR5
+address_a[5] => ram_block3a90.PORTAADDR5
+address_a[5] => ram_block3a91.PORTAADDR5
+address_a[5] => ram_block3a92.PORTAADDR5
+address_a[5] => ram_block3a93.PORTAADDR5
+address_a[5] => ram_block3a94.PORTAADDR5
+address_a[5] => ram_block3a95.PORTAADDR5
+address_a[5] => ram_block3a96.PORTAADDR5
+address_a[5] => ram_block3a97.PORTAADDR5
+address_a[5] => ram_block3a98.PORTAADDR5
+address_a[5] => ram_block3a99.PORTAADDR5
+address_a[5] => ram_block3a100.PORTAADDR5
+address_a[5] => ram_block3a101.PORTAADDR5
+address_a[5] => ram_block3a102.PORTAADDR5
+address_a[5] => ram_block3a103.PORTAADDR5
+address_a[5] => ram_block3a104.PORTAADDR5
+address_a[5] => ram_block3a105.PORTAADDR5
+address_a[5] => ram_block3a106.PORTAADDR5
+address_a[5] => ram_block3a107.PORTAADDR5
+address_a[5] => ram_block3a108.PORTAADDR5
+address_a[5] => ram_block3a109.PORTAADDR5
+address_a[5] => ram_block3a110.PORTAADDR5
+address_a[5] => ram_block3a111.PORTAADDR5
+address_a[5] => ram_block3a112.PORTAADDR5
+address_a[5] => ram_block3a113.PORTAADDR5
+address_a[5] => ram_block3a114.PORTAADDR5
+address_a[5] => ram_block3a115.PORTAADDR5
+address_a[5] => ram_block3a116.PORTAADDR5
+address_a[5] => ram_block3a117.PORTAADDR5
+address_a[5] => ram_block3a118.PORTAADDR5
+address_a[5] => ram_block3a119.PORTAADDR5
+address_a[5] => ram_block3a120.PORTAADDR5
+address_a[5] => ram_block3a121.PORTAADDR5
+address_a[5] => ram_block3a122.PORTAADDR5
+address_a[5] => ram_block3a123.PORTAADDR5
+address_a[5] => ram_block3a124.PORTAADDR5
+address_a[5] => ram_block3a125.PORTAADDR5
+address_a[5] => ram_block3a126.PORTAADDR5
+address_a[5] => ram_block3a127.PORTAADDR5
+address_a[5] => ram_block3a128.PORTAADDR5
+address_a[5] => ram_block3a129.PORTAADDR5
+address_a[5] => ram_block3a130.PORTAADDR5
+address_a[5] => ram_block3a131.PORTAADDR5
+address_a[5] => ram_block3a132.PORTAADDR5
+address_a[5] => ram_block3a133.PORTAADDR5
+address_a[5] => ram_block3a134.PORTAADDR5
+address_a[5] => ram_block3a135.PORTAADDR5
+address_a[5] => ram_block3a136.PORTAADDR5
+address_a[5] => ram_block3a137.PORTAADDR5
+address_a[5] => ram_block3a138.PORTAADDR5
+address_a[5] => ram_block3a139.PORTAADDR5
+address_a[5] => ram_block3a140.PORTAADDR5
+address_a[5] => ram_block3a141.PORTAADDR5
+address_a[5] => ram_block3a142.PORTAADDR5
+address_a[5] => ram_block3a143.PORTAADDR5
+address_a[5] => ram_block3a144.PORTAADDR5
+address_a[5] => ram_block3a145.PORTAADDR5
+address_a[5] => ram_block3a146.PORTAADDR5
+address_a[5] => ram_block3a147.PORTAADDR5
+address_a[5] => ram_block3a148.PORTAADDR5
+address_a[5] => ram_block3a149.PORTAADDR5
+address_a[6] => ram_block3a0.PORTAADDR6
+address_a[6] => ram_block3a1.PORTAADDR6
+address_a[6] => ram_block3a2.PORTAADDR6
+address_a[6] => ram_block3a3.PORTAADDR6
+address_a[6] => ram_block3a4.PORTAADDR6
+address_a[6] => ram_block3a5.PORTAADDR6
+address_a[6] => ram_block3a6.PORTAADDR6
+address_a[6] => ram_block3a7.PORTAADDR6
+address_a[6] => ram_block3a8.PORTAADDR6
+address_a[6] => ram_block3a9.PORTAADDR6
+address_a[6] => ram_block3a10.PORTAADDR6
+address_a[6] => ram_block3a11.PORTAADDR6
+address_a[6] => ram_block3a12.PORTAADDR6
+address_a[6] => ram_block3a13.PORTAADDR6
+address_a[6] => ram_block3a14.PORTAADDR6
+address_a[6] => ram_block3a15.PORTAADDR6
+address_a[6] => ram_block3a16.PORTAADDR6
+address_a[6] => ram_block3a17.PORTAADDR6
+address_a[6] => ram_block3a18.PORTAADDR6
+address_a[6] => ram_block3a19.PORTAADDR6
+address_a[6] => ram_block3a20.PORTAADDR6
+address_a[6] => ram_block3a21.PORTAADDR6
+address_a[6] => ram_block3a22.PORTAADDR6
+address_a[6] => ram_block3a23.PORTAADDR6
+address_a[6] => ram_block3a24.PORTAADDR6
+address_a[6] => ram_block3a25.PORTAADDR6
+address_a[6] => ram_block3a26.PORTAADDR6
+address_a[6] => ram_block3a27.PORTAADDR6
+address_a[6] => ram_block3a28.PORTAADDR6
+address_a[6] => ram_block3a29.PORTAADDR6
+address_a[6] => ram_block3a30.PORTAADDR6
+address_a[6] => ram_block3a31.PORTAADDR6
+address_a[6] => ram_block3a32.PORTAADDR6
+address_a[6] => ram_block3a33.PORTAADDR6
+address_a[6] => ram_block3a34.PORTAADDR6
+address_a[6] => ram_block3a35.PORTAADDR6
+address_a[6] => ram_block3a36.PORTAADDR6
+address_a[6] => ram_block3a37.PORTAADDR6
+address_a[6] => ram_block3a38.PORTAADDR6
+address_a[6] => ram_block3a39.PORTAADDR6
+address_a[6] => ram_block3a40.PORTAADDR6
+address_a[6] => ram_block3a41.PORTAADDR6
+address_a[6] => ram_block3a42.PORTAADDR6
+address_a[6] => ram_block3a43.PORTAADDR6
+address_a[6] => ram_block3a44.PORTAADDR6
+address_a[6] => ram_block3a45.PORTAADDR6
+address_a[6] => ram_block3a46.PORTAADDR6
+address_a[6] => ram_block3a47.PORTAADDR6
+address_a[6] => ram_block3a48.PORTAADDR6
+address_a[6] => ram_block3a49.PORTAADDR6
+address_a[6] => ram_block3a50.PORTAADDR6
+address_a[6] => ram_block3a51.PORTAADDR6
+address_a[6] => ram_block3a52.PORTAADDR6
+address_a[6] => ram_block3a53.PORTAADDR6
+address_a[6] => ram_block3a54.PORTAADDR6
+address_a[6] => ram_block3a55.PORTAADDR6
+address_a[6] => ram_block3a56.PORTAADDR6
+address_a[6] => ram_block3a57.PORTAADDR6
+address_a[6] => ram_block3a58.PORTAADDR6
+address_a[6] => ram_block3a59.PORTAADDR6
+address_a[6] => ram_block3a60.PORTAADDR6
+address_a[6] => ram_block3a61.PORTAADDR6
+address_a[6] => ram_block3a62.PORTAADDR6
+address_a[6] => ram_block3a63.PORTAADDR6
+address_a[6] => ram_block3a64.PORTAADDR6
+address_a[6] => ram_block3a65.PORTAADDR6
+address_a[6] => ram_block3a66.PORTAADDR6
+address_a[6] => ram_block3a67.PORTAADDR6
+address_a[6] => ram_block3a68.PORTAADDR6
+address_a[6] => ram_block3a69.PORTAADDR6
+address_a[6] => ram_block3a70.PORTAADDR6
+address_a[6] => ram_block3a71.PORTAADDR6
+address_a[6] => ram_block3a72.PORTAADDR6
+address_a[6] => ram_block3a73.PORTAADDR6
+address_a[6] => ram_block3a74.PORTAADDR6
+address_a[6] => ram_block3a75.PORTAADDR6
+address_a[6] => ram_block3a76.PORTAADDR6
+address_a[6] => ram_block3a77.PORTAADDR6
+address_a[6] => ram_block3a78.PORTAADDR6
+address_a[6] => ram_block3a79.PORTAADDR6
+address_a[6] => ram_block3a80.PORTAADDR6
+address_a[6] => ram_block3a81.PORTAADDR6
+address_a[6] => ram_block3a82.PORTAADDR6
+address_a[6] => ram_block3a83.PORTAADDR6
+address_a[6] => ram_block3a84.PORTAADDR6
+address_a[6] => ram_block3a85.PORTAADDR6
+address_a[6] => ram_block3a86.PORTAADDR6
+address_a[6] => ram_block3a87.PORTAADDR6
+address_a[6] => ram_block3a88.PORTAADDR6
+address_a[6] => ram_block3a89.PORTAADDR6
+address_a[6] => ram_block3a90.PORTAADDR6
+address_a[6] => ram_block3a91.PORTAADDR6
+address_a[6] => ram_block3a92.PORTAADDR6
+address_a[6] => ram_block3a93.PORTAADDR6
+address_a[6] => ram_block3a94.PORTAADDR6
+address_a[6] => ram_block3a95.PORTAADDR6
+address_a[6] => ram_block3a96.PORTAADDR6
+address_a[6] => ram_block3a97.PORTAADDR6
+address_a[6] => ram_block3a98.PORTAADDR6
+address_a[6] => ram_block3a99.PORTAADDR6
+address_a[6] => ram_block3a100.PORTAADDR6
+address_a[6] => ram_block3a101.PORTAADDR6
+address_a[6] => ram_block3a102.PORTAADDR6
+address_a[6] => ram_block3a103.PORTAADDR6
+address_a[6] => ram_block3a104.PORTAADDR6
+address_a[6] => ram_block3a105.PORTAADDR6
+address_a[6] => ram_block3a106.PORTAADDR6
+address_a[6] => ram_block3a107.PORTAADDR6
+address_a[6] => ram_block3a108.PORTAADDR6
+address_a[6] => ram_block3a109.PORTAADDR6
+address_a[6] => ram_block3a110.PORTAADDR6
+address_a[6] => ram_block3a111.PORTAADDR6
+address_a[6] => ram_block3a112.PORTAADDR6
+address_a[6] => ram_block3a113.PORTAADDR6
+address_a[6] => ram_block3a114.PORTAADDR6
+address_a[6] => ram_block3a115.PORTAADDR6
+address_a[6] => ram_block3a116.PORTAADDR6
+address_a[6] => ram_block3a117.PORTAADDR6
+address_a[6] => ram_block3a118.PORTAADDR6
+address_a[6] => ram_block3a119.PORTAADDR6
+address_a[6] => ram_block3a120.PORTAADDR6
+address_a[6] => ram_block3a121.PORTAADDR6
+address_a[6] => ram_block3a122.PORTAADDR6
+address_a[6] => ram_block3a123.PORTAADDR6
+address_a[6] => ram_block3a124.PORTAADDR6
+address_a[6] => ram_block3a125.PORTAADDR6
+address_a[6] => ram_block3a126.PORTAADDR6
+address_a[6] => ram_block3a127.PORTAADDR6
+address_a[6] => ram_block3a128.PORTAADDR6
+address_a[6] => ram_block3a129.PORTAADDR6
+address_a[6] => ram_block3a130.PORTAADDR6
+address_a[6] => ram_block3a131.PORTAADDR6
+address_a[6] => ram_block3a132.PORTAADDR6
+address_a[6] => ram_block3a133.PORTAADDR6
+address_a[6] => ram_block3a134.PORTAADDR6
+address_a[6] => ram_block3a135.PORTAADDR6
+address_a[6] => ram_block3a136.PORTAADDR6
+address_a[6] => ram_block3a137.PORTAADDR6
+address_a[6] => ram_block3a138.PORTAADDR6
+address_a[6] => ram_block3a139.PORTAADDR6
+address_a[6] => ram_block3a140.PORTAADDR6
+address_a[6] => ram_block3a141.PORTAADDR6
+address_a[6] => ram_block3a142.PORTAADDR6
+address_a[6] => ram_block3a143.PORTAADDR6
+address_a[6] => ram_block3a144.PORTAADDR6
+address_a[6] => ram_block3a145.PORTAADDR6
+address_a[6] => ram_block3a146.PORTAADDR6
+address_a[6] => ram_block3a147.PORTAADDR6
+address_a[6] => ram_block3a148.PORTAADDR6
+address_a[6] => ram_block3a149.PORTAADDR6
+address_a[7] => ram_block3a0.PORTAADDR7
+address_a[7] => ram_block3a1.PORTAADDR7
+address_a[7] => ram_block3a2.PORTAADDR7
+address_a[7] => ram_block3a3.PORTAADDR7
+address_a[7] => ram_block3a4.PORTAADDR7
+address_a[7] => ram_block3a5.PORTAADDR7
+address_a[7] => ram_block3a6.PORTAADDR7
+address_a[7] => ram_block3a7.PORTAADDR7
+address_a[7] => ram_block3a8.PORTAADDR7
+address_a[7] => ram_block3a9.PORTAADDR7
+address_a[7] => ram_block3a10.PORTAADDR7
+address_a[7] => ram_block3a11.PORTAADDR7
+address_a[7] => ram_block3a12.PORTAADDR7
+address_a[7] => ram_block3a13.PORTAADDR7
+address_a[7] => ram_block3a14.PORTAADDR7
+address_a[7] => ram_block3a15.PORTAADDR7
+address_a[7] => ram_block3a16.PORTAADDR7
+address_a[7] => ram_block3a17.PORTAADDR7
+address_a[7] => ram_block3a18.PORTAADDR7
+address_a[7] => ram_block3a19.PORTAADDR7
+address_a[7] => ram_block3a20.PORTAADDR7
+address_a[7] => ram_block3a21.PORTAADDR7
+address_a[7] => ram_block3a22.PORTAADDR7
+address_a[7] => ram_block3a23.PORTAADDR7
+address_a[7] => ram_block3a24.PORTAADDR7
+address_a[7] => ram_block3a25.PORTAADDR7
+address_a[7] => ram_block3a26.PORTAADDR7
+address_a[7] => ram_block3a27.PORTAADDR7
+address_a[7] => ram_block3a28.PORTAADDR7
+address_a[7] => ram_block3a29.PORTAADDR7
+address_a[7] => ram_block3a30.PORTAADDR7
+address_a[7] => ram_block3a31.PORTAADDR7
+address_a[7] => ram_block3a32.PORTAADDR7
+address_a[7] => ram_block3a33.PORTAADDR7
+address_a[7] => ram_block3a34.PORTAADDR7
+address_a[7] => ram_block3a35.PORTAADDR7
+address_a[7] => ram_block3a36.PORTAADDR7
+address_a[7] => ram_block3a37.PORTAADDR7
+address_a[7] => ram_block3a38.PORTAADDR7
+address_a[7] => ram_block3a39.PORTAADDR7
+address_a[7] => ram_block3a40.PORTAADDR7
+address_a[7] => ram_block3a41.PORTAADDR7
+address_a[7] => ram_block3a42.PORTAADDR7
+address_a[7] => ram_block3a43.PORTAADDR7
+address_a[7] => ram_block3a44.PORTAADDR7
+address_a[7] => ram_block3a45.PORTAADDR7
+address_a[7] => ram_block3a46.PORTAADDR7
+address_a[7] => ram_block3a47.PORTAADDR7
+address_a[7] => ram_block3a48.PORTAADDR7
+address_a[7] => ram_block3a49.PORTAADDR7
+address_a[7] => ram_block3a50.PORTAADDR7
+address_a[7] => ram_block3a51.PORTAADDR7
+address_a[7] => ram_block3a52.PORTAADDR7
+address_a[7] => ram_block3a53.PORTAADDR7
+address_a[7] => ram_block3a54.PORTAADDR7
+address_a[7] => ram_block3a55.PORTAADDR7
+address_a[7] => ram_block3a56.PORTAADDR7
+address_a[7] => ram_block3a57.PORTAADDR7
+address_a[7] => ram_block3a58.PORTAADDR7
+address_a[7] => ram_block3a59.PORTAADDR7
+address_a[7] => ram_block3a60.PORTAADDR7
+address_a[7] => ram_block3a61.PORTAADDR7
+address_a[7] => ram_block3a62.PORTAADDR7
+address_a[7] => ram_block3a63.PORTAADDR7
+address_a[7] => ram_block3a64.PORTAADDR7
+address_a[7] => ram_block3a65.PORTAADDR7
+address_a[7] => ram_block3a66.PORTAADDR7
+address_a[7] => ram_block3a67.PORTAADDR7
+address_a[7] => ram_block3a68.PORTAADDR7
+address_a[7] => ram_block3a69.PORTAADDR7
+address_a[7] => ram_block3a70.PORTAADDR7
+address_a[7] => ram_block3a71.PORTAADDR7
+address_a[7] => ram_block3a72.PORTAADDR7
+address_a[7] => ram_block3a73.PORTAADDR7
+address_a[7] => ram_block3a74.PORTAADDR7
+address_a[7] => ram_block3a75.PORTAADDR7
+address_a[7] => ram_block3a76.PORTAADDR7
+address_a[7] => ram_block3a77.PORTAADDR7
+address_a[7] => ram_block3a78.PORTAADDR7
+address_a[7] => ram_block3a79.PORTAADDR7
+address_a[7] => ram_block3a80.PORTAADDR7
+address_a[7] => ram_block3a81.PORTAADDR7
+address_a[7] => ram_block3a82.PORTAADDR7
+address_a[7] => ram_block3a83.PORTAADDR7
+address_a[7] => ram_block3a84.PORTAADDR7
+address_a[7] => ram_block3a85.PORTAADDR7
+address_a[7] => ram_block3a86.PORTAADDR7
+address_a[7] => ram_block3a87.PORTAADDR7
+address_a[7] => ram_block3a88.PORTAADDR7
+address_a[7] => ram_block3a89.PORTAADDR7
+address_a[7] => ram_block3a90.PORTAADDR7
+address_a[7] => ram_block3a91.PORTAADDR7
+address_a[7] => ram_block3a92.PORTAADDR7
+address_a[7] => ram_block3a93.PORTAADDR7
+address_a[7] => ram_block3a94.PORTAADDR7
+address_a[7] => ram_block3a95.PORTAADDR7
+address_a[7] => ram_block3a96.PORTAADDR7
+address_a[7] => ram_block3a97.PORTAADDR7
+address_a[7] => ram_block3a98.PORTAADDR7
+address_a[7] => ram_block3a99.PORTAADDR7
+address_a[7] => ram_block3a100.PORTAADDR7
+address_a[7] => ram_block3a101.PORTAADDR7
+address_a[7] => ram_block3a102.PORTAADDR7
+address_a[7] => ram_block3a103.PORTAADDR7
+address_a[7] => ram_block3a104.PORTAADDR7
+address_a[7] => ram_block3a105.PORTAADDR7
+address_a[7] => ram_block3a106.PORTAADDR7
+address_a[7] => ram_block3a107.PORTAADDR7
+address_a[7] => ram_block3a108.PORTAADDR7
+address_a[7] => ram_block3a109.PORTAADDR7
+address_a[7] => ram_block3a110.PORTAADDR7
+address_a[7] => ram_block3a111.PORTAADDR7
+address_a[7] => ram_block3a112.PORTAADDR7
+address_a[7] => ram_block3a113.PORTAADDR7
+address_a[7] => ram_block3a114.PORTAADDR7
+address_a[7] => ram_block3a115.PORTAADDR7
+address_a[7] => ram_block3a116.PORTAADDR7
+address_a[7] => ram_block3a117.PORTAADDR7
+address_a[7] => ram_block3a118.PORTAADDR7
+address_a[7] => ram_block3a119.PORTAADDR7
+address_a[7] => ram_block3a120.PORTAADDR7
+address_a[7] => ram_block3a121.PORTAADDR7
+address_a[7] => ram_block3a122.PORTAADDR7
+address_a[7] => ram_block3a123.PORTAADDR7
+address_a[7] => ram_block3a124.PORTAADDR7
+address_a[7] => ram_block3a125.PORTAADDR7
+address_a[7] => ram_block3a126.PORTAADDR7
+address_a[7] => ram_block3a127.PORTAADDR7
+address_a[7] => ram_block3a128.PORTAADDR7
+address_a[7] => ram_block3a129.PORTAADDR7
+address_a[7] => ram_block3a130.PORTAADDR7
+address_a[7] => ram_block3a131.PORTAADDR7
+address_a[7] => ram_block3a132.PORTAADDR7
+address_a[7] => ram_block3a133.PORTAADDR7
+address_a[7] => ram_block3a134.PORTAADDR7
+address_a[7] => ram_block3a135.PORTAADDR7
+address_a[7] => ram_block3a136.PORTAADDR7
+address_a[7] => ram_block3a137.PORTAADDR7
+address_a[7] => ram_block3a138.PORTAADDR7
+address_a[7] => ram_block3a139.PORTAADDR7
+address_a[7] => ram_block3a140.PORTAADDR7
+address_a[7] => ram_block3a141.PORTAADDR7
+address_a[7] => ram_block3a142.PORTAADDR7
+address_a[7] => ram_block3a143.PORTAADDR7
+address_a[7] => ram_block3a144.PORTAADDR7
+address_a[7] => ram_block3a145.PORTAADDR7
+address_a[7] => ram_block3a146.PORTAADDR7
+address_a[7] => ram_block3a147.PORTAADDR7
+address_a[7] => ram_block3a148.PORTAADDR7
+address_a[7] => ram_block3a149.PORTAADDR7
+address_a[8] => ram_block3a0.PORTAADDR8
+address_a[8] => ram_block3a1.PORTAADDR8
+address_a[8] => ram_block3a2.PORTAADDR8
+address_a[8] => ram_block3a3.PORTAADDR8
+address_a[8] => ram_block3a4.PORTAADDR8
+address_a[8] => ram_block3a5.PORTAADDR8
+address_a[8] => ram_block3a6.PORTAADDR8
+address_a[8] => ram_block3a7.PORTAADDR8
+address_a[8] => ram_block3a8.PORTAADDR8
+address_a[8] => ram_block3a9.PORTAADDR8
+address_a[8] => ram_block3a10.PORTAADDR8
+address_a[8] => ram_block3a11.PORTAADDR8
+address_a[8] => ram_block3a12.PORTAADDR8
+address_a[8] => ram_block3a13.PORTAADDR8
+address_a[8] => ram_block3a14.PORTAADDR8
+address_a[8] => ram_block3a15.PORTAADDR8
+address_a[8] => ram_block3a16.PORTAADDR8
+address_a[8] => ram_block3a17.PORTAADDR8
+address_a[8] => ram_block3a18.PORTAADDR8
+address_a[8] => ram_block3a19.PORTAADDR8
+address_a[8] => ram_block3a20.PORTAADDR8
+address_a[8] => ram_block3a21.PORTAADDR8
+address_a[8] => ram_block3a22.PORTAADDR8
+address_a[8] => ram_block3a23.PORTAADDR8
+address_a[8] => ram_block3a24.PORTAADDR8
+address_a[8] => ram_block3a25.PORTAADDR8
+address_a[8] => ram_block3a26.PORTAADDR8
+address_a[8] => ram_block3a27.PORTAADDR8
+address_a[8] => ram_block3a28.PORTAADDR8
+address_a[8] => ram_block3a29.PORTAADDR8
+address_a[8] => ram_block3a30.PORTAADDR8
+address_a[8] => ram_block3a31.PORTAADDR8
+address_a[8] => ram_block3a32.PORTAADDR8
+address_a[8] => ram_block3a33.PORTAADDR8
+address_a[8] => ram_block3a34.PORTAADDR8
+address_a[8] => ram_block3a35.PORTAADDR8
+address_a[8] => ram_block3a36.PORTAADDR8
+address_a[8] => ram_block3a37.PORTAADDR8
+address_a[8] => ram_block3a38.PORTAADDR8
+address_a[8] => ram_block3a39.PORTAADDR8
+address_a[8] => ram_block3a40.PORTAADDR8
+address_a[8] => ram_block3a41.PORTAADDR8
+address_a[8] => ram_block3a42.PORTAADDR8
+address_a[8] => ram_block3a43.PORTAADDR8
+address_a[8] => ram_block3a44.PORTAADDR8
+address_a[8] => ram_block3a45.PORTAADDR8
+address_a[8] => ram_block3a46.PORTAADDR8
+address_a[8] => ram_block3a47.PORTAADDR8
+address_a[8] => ram_block3a48.PORTAADDR8
+address_a[8] => ram_block3a49.PORTAADDR8
+address_a[8] => ram_block3a50.PORTAADDR8
+address_a[8] => ram_block3a51.PORTAADDR8
+address_a[8] => ram_block3a52.PORTAADDR8
+address_a[8] => ram_block3a53.PORTAADDR8
+address_a[8] => ram_block3a54.PORTAADDR8
+address_a[8] => ram_block3a55.PORTAADDR8
+address_a[8] => ram_block3a56.PORTAADDR8
+address_a[8] => ram_block3a57.PORTAADDR8
+address_a[8] => ram_block3a58.PORTAADDR8
+address_a[8] => ram_block3a59.PORTAADDR8
+address_a[8] => ram_block3a60.PORTAADDR8
+address_a[8] => ram_block3a61.PORTAADDR8
+address_a[8] => ram_block3a62.PORTAADDR8
+address_a[8] => ram_block3a63.PORTAADDR8
+address_a[8] => ram_block3a64.PORTAADDR8
+address_a[8] => ram_block3a65.PORTAADDR8
+address_a[8] => ram_block3a66.PORTAADDR8
+address_a[8] => ram_block3a67.PORTAADDR8
+address_a[8] => ram_block3a68.PORTAADDR8
+address_a[8] => ram_block3a69.PORTAADDR8
+address_a[8] => ram_block3a70.PORTAADDR8
+address_a[8] => ram_block3a71.PORTAADDR8
+address_a[8] => ram_block3a72.PORTAADDR8
+address_a[8] => ram_block3a73.PORTAADDR8
+address_a[8] => ram_block3a74.PORTAADDR8
+address_a[8] => ram_block3a75.PORTAADDR8
+address_a[8] => ram_block3a76.PORTAADDR8
+address_a[8] => ram_block3a77.PORTAADDR8
+address_a[8] => ram_block3a78.PORTAADDR8
+address_a[8] => ram_block3a79.PORTAADDR8
+address_a[8] => ram_block3a80.PORTAADDR8
+address_a[8] => ram_block3a81.PORTAADDR8
+address_a[8] => ram_block3a82.PORTAADDR8
+address_a[8] => ram_block3a83.PORTAADDR8
+address_a[8] => ram_block3a84.PORTAADDR8
+address_a[8] => ram_block3a85.PORTAADDR8
+address_a[8] => ram_block3a86.PORTAADDR8
+address_a[8] => ram_block3a87.PORTAADDR8
+address_a[8] => ram_block3a88.PORTAADDR8
+address_a[8] => ram_block3a89.PORTAADDR8
+address_a[8] => ram_block3a90.PORTAADDR8
+address_a[8] => ram_block3a91.PORTAADDR8
+address_a[8] => ram_block3a92.PORTAADDR8
+address_a[8] => ram_block3a93.PORTAADDR8
+address_a[8] => ram_block3a94.PORTAADDR8
+address_a[8] => ram_block3a95.PORTAADDR8
+address_a[8] => ram_block3a96.PORTAADDR8
+address_a[8] => ram_block3a97.PORTAADDR8
+address_a[8] => ram_block3a98.PORTAADDR8
+address_a[8] => ram_block3a99.PORTAADDR8
+address_a[8] => ram_block3a100.PORTAADDR8
+address_a[8] => ram_block3a101.PORTAADDR8
+address_a[8] => ram_block3a102.PORTAADDR8
+address_a[8] => ram_block3a103.PORTAADDR8
+address_a[8] => ram_block3a104.PORTAADDR8
+address_a[8] => ram_block3a105.PORTAADDR8
+address_a[8] => ram_block3a106.PORTAADDR8
+address_a[8] => ram_block3a107.PORTAADDR8
+address_a[8] => ram_block3a108.PORTAADDR8
+address_a[8] => ram_block3a109.PORTAADDR8
+address_a[8] => ram_block3a110.PORTAADDR8
+address_a[8] => ram_block3a111.PORTAADDR8
+address_a[8] => ram_block3a112.PORTAADDR8
+address_a[8] => ram_block3a113.PORTAADDR8
+address_a[8] => ram_block3a114.PORTAADDR8
+address_a[8] => ram_block3a115.PORTAADDR8
+address_a[8] => ram_block3a116.PORTAADDR8
+address_a[8] => ram_block3a117.PORTAADDR8
+address_a[8] => ram_block3a118.PORTAADDR8
+address_a[8] => ram_block3a119.PORTAADDR8
+address_a[8] => ram_block3a120.PORTAADDR8
+address_a[8] => ram_block3a121.PORTAADDR8
+address_a[8] => ram_block3a122.PORTAADDR8
+address_a[8] => ram_block3a123.PORTAADDR8
+address_a[8] => ram_block3a124.PORTAADDR8
+address_a[8] => ram_block3a125.PORTAADDR8
+address_a[8] => ram_block3a126.PORTAADDR8
+address_a[8] => ram_block3a127.PORTAADDR8
+address_a[8] => ram_block3a128.PORTAADDR8
+address_a[8] => ram_block3a129.PORTAADDR8
+address_a[8] => ram_block3a130.PORTAADDR8
+address_a[8] => ram_block3a131.PORTAADDR8
+address_a[8] => ram_block3a132.PORTAADDR8
+address_a[8] => ram_block3a133.PORTAADDR8
+address_a[8] => ram_block3a134.PORTAADDR8
+address_a[8] => ram_block3a135.PORTAADDR8
+address_a[8] => ram_block3a136.PORTAADDR8
+address_a[8] => ram_block3a137.PORTAADDR8
+address_a[8] => ram_block3a138.PORTAADDR8
+address_a[8] => ram_block3a139.PORTAADDR8
+address_a[8] => ram_block3a140.PORTAADDR8
+address_a[8] => ram_block3a141.PORTAADDR8
+address_a[8] => ram_block3a142.PORTAADDR8
+address_a[8] => ram_block3a143.PORTAADDR8
+address_a[8] => ram_block3a144.PORTAADDR8
+address_a[8] => ram_block3a145.PORTAADDR8
+address_a[8] => ram_block3a146.PORTAADDR8
+address_a[8] => ram_block3a147.PORTAADDR8
+address_a[8] => ram_block3a148.PORTAADDR8
+address_a[8] => ram_block3a149.PORTAADDR8
+address_a[9] => ram_block3a0.PORTAADDR9
+address_a[9] => ram_block3a1.PORTAADDR9
+address_a[9] => ram_block3a2.PORTAADDR9
+address_a[9] => ram_block3a3.PORTAADDR9
+address_a[9] => ram_block3a4.PORTAADDR9
+address_a[9] => ram_block3a5.PORTAADDR9
+address_a[9] => ram_block3a6.PORTAADDR9
+address_a[9] => ram_block3a7.PORTAADDR9
+address_a[9] => ram_block3a8.PORTAADDR9
+address_a[9] => ram_block3a9.PORTAADDR9
+address_a[9] => ram_block3a10.PORTAADDR9
+address_a[9] => ram_block3a11.PORTAADDR9
+address_a[9] => ram_block3a12.PORTAADDR9
+address_a[9] => ram_block3a13.PORTAADDR9
+address_a[9] => ram_block3a14.PORTAADDR9
+address_a[9] => ram_block3a15.PORTAADDR9
+address_a[9] => ram_block3a16.PORTAADDR9
+address_a[9] => ram_block3a17.PORTAADDR9
+address_a[9] => ram_block3a18.PORTAADDR9
+address_a[9] => ram_block3a19.PORTAADDR9
+address_a[9] => ram_block3a20.PORTAADDR9
+address_a[9] => ram_block3a21.PORTAADDR9
+address_a[9] => ram_block3a22.PORTAADDR9
+address_a[9] => ram_block3a23.PORTAADDR9
+address_a[9] => ram_block3a24.PORTAADDR9
+address_a[9] => ram_block3a25.PORTAADDR9
+address_a[9] => ram_block3a26.PORTAADDR9
+address_a[9] => ram_block3a27.PORTAADDR9
+address_a[9] => ram_block3a28.PORTAADDR9
+address_a[9] => ram_block3a29.PORTAADDR9
+address_a[9] => ram_block3a30.PORTAADDR9
+address_a[9] => ram_block3a31.PORTAADDR9
+address_a[9] => ram_block3a32.PORTAADDR9
+address_a[9] => ram_block3a33.PORTAADDR9
+address_a[9] => ram_block3a34.PORTAADDR9
+address_a[9] => ram_block3a35.PORTAADDR9
+address_a[9] => ram_block3a36.PORTAADDR9
+address_a[9] => ram_block3a37.PORTAADDR9
+address_a[9] => ram_block3a38.PORTAADDR9
+address_a[9] => ram_block3a39.PORTAADDR9
+address_a[9] => ram_block3a40.PORTAADDR9
+address_a[9] => ram_block3a41.PORTAADDR9
+address_a[9] => ram_block3a42.PORTAADDR9
+address_a[9] => ram_block3a43.PORTAADDR9
+address_a[9] => ram_block3a44.PORTAADDR9
+address_a[9] => ram_block3a45.PORTAADDR9
+address_a[9] => ram_block3a46.PORTAADDR9
+address_a[9] => ram_block3a47.PORTAADDR9
+address_a[9] => ram_block3a48.PORTAADDR9
+address_a[9] => ram_block3a49.PORTAADDR9
+address_a[9] => ram_block3a50.PORTAADDR9
+address_a[9] => ram_block3a51.PORTAADDR9
+address_a[9] => ram_block3a52.PORTAADDR9
+address_a[9] => ram_block3a53.PORTAADDR9
+address_a[9] => ram_block3a54.PORTAADDR9
+address_a[9] => ram_block3a55.PORTAADDR9
+address_a[9] => ram_block3a56.PORTAADDR9
+address_a[9] => ram_block3a57.PORTAADDR9
+address_a[9] => ram_block3a58.PORTAADDR9
+address_a[9] => ram_block3a59.PORTAADDR9
+address_a[9] => ram_block3a60.PORTAADDR9
+address_a[9] => ram_block3a61.PORTAADDR9
+address_a[9] => ram_block3a62.PORTAADDR9
+address_a[9] => ram_block3a63.PORTAADDR9
+address_a[9] => ram_block3a64.PORTAADDR9
+address_a[9] => ram_block3a65.PORTAADDR9
+address_a[9] => ram_block3a66.PORTAADDR9
+address_a[9] => ram_block3a67.PORTAADDR9
+address_a[9] => ram_block3a68.PORTAADDR9
+address_a[9] => ram_block3a69.PORTAADDR9
+address_a[9] => ram_block3a70.PORTAADDR9
+address_a[9] => ram_block3a71.PORTAADDR9
+address_a[9] => ram_block3a72.PORTAADDR9
+address_a[9] => ram_block3a73.PORTAADDR9
+address_a[9] => ram_block3a74.PORTAADDR9
+address_a[9] => ram_block3a75.PORTAADDR9
+address_a[9] => ram_block3a76.PORTAADDR9
+address_a[9] => ram_block3a77.PORTAADDR9
+address_a[9] => ram_block3a78.PORTAADDR9
+address_a[9] => ram_block3a79.PORTAADDR9
+address_a[9] => ram_block3a80.PORTAADDR9
+address_a[9] => ram_block3a81.PORTAADDR9
+address_a[9] => ram_block3a82.PORTAADDR9
+address_a[9] => ram_block3a83.PORTAADDR9
+address_a[9] => ram_block3a84.PORTAADDR9
+address_a[9] => ram_block3a85.PORTAADDR9
+address_a[9] => ram_block3a86.PORTAADDR9
+address_a[9] => ram_block3a87.PORTAADDR9
+address_a[9] => ram_block3a88.PORTAADDR9
+address_a[9] => ram_block3a89.PORTAADDR9
+address_a[9] => ram_block3a90.PORTAADDR9
+address_a[9] => ram_block3a91.PORTAADDR9
+address_a[9] => ram_block3a92.PORTAADDR9
+address_a[9] => ram_block3a93.PORTAADDR9
+address_a[9] => ram_block3a94.PORTAADDR9
+address_a[9] => ram_block3a95.PORTAADDR9
+address_a[9] => ram_block3a96.PORTAADDR9
+address_a[9] => ram_block3a97.PORTAADDR9
+address_a[9] => ram_block3a98.PORTAADDR9
+address_a[9] => ram_block3a99.PORTAADDR9
+address_a[9] => ram_block3a100.PORTAADDR9
+address_a[9] => ram_block3a101.PORTAADDR9
+address_a[9] => ram_block3a102.PORTAADDR9
+address_a[9] => ram_block3a103.PORTAADDR9
+address_a[9] => ram_block3a104.PORTAADDR9
+address_a[9] => ram_block3a105.PORTAADDR9
+address_a[9] => ram_block3a106.PORTAADDR9
+address_a[9] => ram_block3a107.PORTAADDR9
+address_a[9] => ram_block3a108.PORTAADDR9
+address_a[9] => ram_block3a109.PORTAADDR9
+address_a[9] => ram_block3a110.PORTAADDR9
+address_a[9] => ram_block3a111.PORTAADDR9
+address_a[9] => ram_block3a112.PORTAADDR9
+address_a[9] => ram_block3a113.PORTAADDR9
+address_a[9] => ram_block3a114.PORTAADDR9
+address_a[9] => ram_block3a115.PORTAADDR9
+address_a[9] => ram_block3a116.PORTAADDR9
+address_a[9] => ram_block3a117.PORTAADDR9
+address_a[9] => ram_block3a118.PORTAADDR9
+address_a[9] => ram_block3a119.PORTAADDR9
+address_a[9] => ram_block3a120.PORTAADDR9
+address_a[9] => ram_block3a121.PORTAADDR9
+address_a[9] => ram_block3a122.PORTAADDR9
+address_a[9] => ram_block3a123.PORTAADDR9
+address_a[9] => ram_block3a124.PORTAADDR9
+address_a[9] => ram_block3a125.PORTAADDR9
+address_a[9] => ram_block3a126.PORTAADDR9
+address_a[9] => ram_block3a127.PORTAADDR9
+address_a[9] => ram_block3a128.PORTAADDR9
+address_a[9] => ram_block3a129.PORTAADDR9
+address_a[9] => ram_block3a130.PORTAADDR9
+address_a[9] => ram_block3a131.PORTAADDR9
+address_a[9] => ram_block3a132.PORTAADDR9
+address_a[9] => ram_block3a133.PORTAADDR9
+address_a[9] => ram_block3a134.PORTAADDR9
+address_a[9] => ram_block3a135.PORTAADDR9
+address_a[9] => ram_block3a136.PORTAADDR9
+address_a[9] => ram_block3a137.PORTAADDR9
+address_a[9] => ram_block3a138.PORTAADDR9
+address_a[9] => ram_block3a139.PORTAADDR9
+address_a[9] => ram_block3a140.PORTAADDR9
+address_a[9] => ram_block3a141.PORTAADDR9
+address_a[9] => ram_block3a142.PORTAADDR9
+address_a[9] => ram_block3a143.PORTAADDR9
+address_a[9] => ram_block3a144.PORTAADDR9
+address_a[9] => ram_block3a145.PORTAADDR9
+address_a[9] => ram_block3a146.PORTAADDR9
+address_a[9] => ram_block3a147.PORTAADDR9
+address_a[9] => ram_block3a148.PORTAADDR9
+address_a[9] => ram_block3a149.PORTAADDR9
+address_b[0] => ram_block3a0.PORTBADDR
+address_b[0] => ram_block3a1.PORTBADDR
+address_b[0] => ram_block3a2.PORTBADDR
+address_b[0] => ram_block3a3.PORTBADDR
+address_b[0] => ram_block3a4.PORTBADDR
+address_b[0] => ram_block3a5.PORTBADDR
+address_b[0] => ram_block3a6.PORTBADDR
+address_b[0] => ram_block3a7.PORTBADDR
+address_b[0] => ram_block3a8.PORTBADDR
+address_b[0] => ram_block3a9.PORTBADDR
+address_b[0] => ram_block3a10.PORTBADDR
+address_b[0] => ram_block3a11.PORTBADDR
+address_b[0] => ram_block3a12.PORTBADDR
+address_b[0] => ram_block3a13.PORTBADDR
+address_b[0] => ram_block3a14.PORTBADDR
+address_b[0] => ram_block3a15.PORTBADDR
+address_b[0] => ram_block3a16.PORTBADDR
+address_b[0] => ram_block3a17.PORTBADDR
+address_b[0] => ram_block3a18.PORTBADDR
+address_b[0] => ram_block3a19.PORTBADDR
+address_b[0] => ram_block3a20.PORTBADDR
+address_b[0] => ram_block3a21.PORTBADDR
+address_b[0] => ram_block3a22.PORTBADDR
+address_b[0] => ram_block3a23.PORTBADDR
+address_b[0] => ram_block3a24.PORTBADDR
+address_b[0] => ram_block3a25.PORTBADDR
+address_b[0] => ram_block3a26.PORTBADDR
+address_b[0] => ram_block3a27.PORTBADDR
+address_b[0] => ram_block3a28.PORTBADDR
+address_b[0] => ram_block3a29.PORTBADDR
+address_b[0] => ram_block3a30.PORTBADDR
+address_b[0] => ram_block3a31.PORTBADDR
+address_b[0] => ram_block3a32.PORTBADDR
+address_b[0] => ram_block3a33.PORTBADDR
+address_b[0] => ram_block3a34.PORTBADDR
+address_b[0] => ram_block3a35.PORTBADDR
+address_b[0] => ram_block3a36.PORTBADDR
+address_b[0] => ram_block3a37.PORTBADDR
+address_b[0] => ram_block3a38.PORTBADDR
+address_b[0] => ram_block3a39.PORTBADDR
+address_b[0] => ram_block3a40.PORTBADDR
+address_b[0] => ram_block3a41.PORTBADDR
+address_b[0] => ram_block3a42.PORTBADDR
+address_b[0] => ram_block3a43.PORTBADDR
+address_b[0] => ram_block3a44.PORTBADDR
+address_b[0] => ram_block3a45.PORTBADDR
+address_b[0] => ram_block3a46.PORTBADDR
+address_b[0] => ram_block3a47.PORTBADDR
+address_b[0] => ram_block3a48.PORTBADDR
+address_b[0] => ram_block3a49.PORTBADDR
+address_b[0] => ram_block3a50.PORTBADDR
+address_b[0] => ram_block3a51.PORTBADDR
+address_b[0] => ram_block3a52.PORTBADDR
+address_b[0] => ram_block3a53.PORTBADDR
+address_b[0] => ram_block3a54.PORTBADDR
+address_b[0] => ram_block3a55.PORTBADDR
+address_b[0] => ram_block3a56.PORTBADDR
+address_b[0] => ram_block3a57.PORTBADDR
+address_b[0] => ram_block3a58.PORTBADDR
+address_b[0] => ram_block3a59.PORTBADDR
+address_b[0] => ram_block3a60.PORTBADDR
+address_b[0] => ram_block3a61.PORTBADDR
+address_b[0] => ram_block3a62.PORTBADDR
+address_b[0] => ram_block3a63.PORTBADDR
+address_b[0] => ram_block3a64.PORTBADDR
+address_b[0] => ram_block3a65.PORTBADDR
+address_b[0] => ram_block3a66.PORTBADDR
+address_b[0] => ram_block3a67.PORTBADDR
+address_b[0] => ram_block3a68.PORTBADDR
+address_b[0] => ram_block3a69.PORTBADDR
+address_b[0] => ram_block3a70.PORTBADDR
+address_b[0] => ram_block3a71.PORTBADDR
+address_b[0] => ram_block3a72.PORTBADDR
+address_b[0] => ram_block3a73.PORTBADDR
+address_b[0] => ram_block3a74.PORTBADDR
+address_b[0] => ram_block3a75.PORTBADDR
+address_b[0] => ram_block3a76.PORTBADDR
+address_b[0] => ram_block3a77.PORTBADDR
+address_b[0] => ram_block3a78.PORTBADDR
+address_b[0] => ram_block3a79.PORTBADDR
+address_b[0] => ram_block3a80.PORTBADDR
+address_b[0] => ram_block3a81.PORTBADDR
+address_b[0] => ram_block3a82.PORTBADDR
+address_b[0] => ram_block3a83.PORTBADDR
+address_b[0] => ram_block3a84.PORTBADDR
+address_b[0] => ram_block3a85.PORTBADDR
+address_b[0] => ram_block3a86.PORTBADDR
+address_b[0] => ram_block3a87.PORTBADDR
+address_b[0] => ram_block3a88.PORTBADDR
+address_b[0] => ram_block3a89.PORTBADDR
+address_b[0] => ram_block3a90.PORTBADDR
+address_b[0] => ram_block3a91.PORTBADDR
+address_b[0] => ram_block3a92.PORTBADDR
+address_b[0] => ram_block3a93.PORTBADDR
+address_b[0] => ram_block3a94.PORTBADDR
+address_b[0] => ram_block3a95.PORTBADDR
+address_b[0] => ram_block3a96.PORTBADDR
+address_b[0] => ram_block3a97.PORTBADDR
+address_b[0] => ram_block3a98.PORTBADDR
+address_b[0] => ram_block3a99.PORTBADDR
+address_b[0] => ram_block3a100.PORTBADDR
+address_b[0] => ram_block3a101.PORTBADDR
+address_b[0] => ram_block3a102.PORTBADDR
+address_b[0] => ram_block3a103.PORTBADDR
+address_b[0] => ram_block3a104.PORTBADDR
+address_b[0] => ram_block3a105.PORTBADDR
+address_b[0] => ram_block3a106.PORTBADDR
+address_b[0] => ram_block3a107.PORTBADDR
+address_b[0] => ram_block3a108.PORTBADDR
+address_b[0] => ram_block3a109.PORTBADDR
+address_b[0] => ram_block3a110.PORTBADDR
+address_b[0] => ram_block3a111.PORTBADDR
+address_b[0] => ram_block3a112.PORTBADDR
+address_b[0] => ram_block3a113.PORTBADDR
+address_b[0] => ram_block3a114.PORTBADDR
+address_b[0] => ram_block3a115.PORTBADDR
+address_b[0] => ram_block3a116.PORTBADDR
+address_b[0] => ram_block3a117.PORTBADDR
+address_b[0] => ram_block3a118.PORTBADDR
+address_b[0] => ram_block3a119.PORTBADDR
+address_b[0] => ram_block3a120.PORTBADDR
+address_b[0] => ram_block3a121.PORTBADDR
+address_b[0] => ram_block3a122.PORTBADDR
+address_b[0] => ram_block3a123.PORTBADDR
+address_b[0] => ram_block3a124.PORTBADDR
+address_b[0] => ram_block3a125.PORTBADDR
+address_b[0] => ram_block3a126.PORTBADDR
+address_b[0] => ram_block3a127.PORTBADDR
+address_b[0] => ram_block3a128.PORTBADDR
+address_b[0] => ram_block3a129.PORTBADDR
+address_b[0] => ram_block3a130.PORTBADDR
+address_b[0] => ram_block3a131.PORTBADDR
+address_b[0] => ram_block3a132.PORTBADDR
+address_b[0] => ram_block3a133.PORTBADDR
+address_b[0] => ram_block3a134.PORTBADDR
+address_b[0] => ram_block3a135.PORTBADDR
+address_b[0] => ram_block3a136.PORTBADDR
+address_b[0] => ram_block3a137.PORTBADDR
+address_b[0] => ram_block3a138.PORTBADDR
+address_b[0] => ram_block3a139.PORTBADDR
+address_b[0] => ram_block3a140.PORTBADDR
+address_b[0] => ram_block3a141.PORTBADDR
+address_b[0] => ram_block3a142.PORTBADDR
+address_b[0] => ram_block3a143.PORTBADDR
+address_b[0] => ram_block3a144.PORTBADDR
+address_b[0] => ram_block3a145.PORTBADDR
+address_b[0] => ram_block3a146.PORTBADDR
+address_b[0] => ram_block3a147.PORTBADDR
+address_b[0] => ram_block3a148.PORTBADDR
+address_b[0] => ram_block3a149.PORTBADDR
+address_b[1] => ram_block3a0.PORTBADDR1
+address_b[1] => ram_block3a1.PORTBADDR1
+address_b[1] => ram_block3a2.PORTBADDR1
+address_b[1] => ram_block3a3.PORTBADDR1
+address_b[1] => ram_block3a4.PORTBADDR1
+address_b[1] => ram_block3a5.PORTBADDR1
+address_b[1] => ram_block3a6.PORTBADDR1
+address_b[1] => ram_block3a7.PORTBADDR1
+address_b[1] => ram_block3a8.PORTBADDR1
+address_b[1] => ram_block3a9.PORTBADDR1
+address_b[1] => ram_block3a10.PORTBADDR1
+address_b[1] => ram_block3a11.PORTBADDR1
+address_b[1] => ram_block3a12.PORTBADDR1
+address_b[1] => ram_block3a13.PORTBADDR1
+address_b[1] => ram_block3a14.PORTBADDR1
+address_b[1] => ram_block3a15.PORTBADDR1
+address_b[1] => ram_block3a16.PORTBADDR1
+address_b[1] => ram_block3a17.PORTBADDR1
+address_b[1] => ram_block3a18.PORTBADDR1
+address_b[1] => ram_block3a19.PORTBADDR1
+address_b[1] => ram_block3a20.PORTBADDR1
+address_b[1] => ram_block3a21.PORTBADDR1
+address_b[1] => ram_block3a22.PORTBADDR1
+address_b[1] => ram_block3a23.PORTBADDR1
+address_b[1] => ram_block3a24.PORTBADDR1
+address_b[1] => ram_block3a25.PORTBADDR1
+address_b[1] => ram_block3a26.PORTBADDR1
+address_b[1] => ram_block3a27.PORTBADDR1
+address_b[1] => ram_block3a28.PORTBADDR1
+address_b[1] => ram_block3a29.PORTBADDR1
+address_b[1] => ram_block3a30.PORTBADDR1
+address_b[1] => ram_block3a31.PORTBADDR1
+address_b[1] => ram_block3a32.PORTBADDR1
+address_b[1] => ram_block3a33.PORTBADDR1
+address_b[1] => ram_block3a34.PORTBADDR1
+address_b[1] => ram_block3a35.PORTBADDR1
+address_b[1] => ram_block3a36.PORTBADDR1
+address_b[1] => ram_block3a37.PORTBADDR1
+address_b[1] => ram_block3a38.PORTBADDR1
+address_b[1] => ram_block3a39.PORTBADDR1
+address_b[1] => ram_block3a40.PORTBADDR1
+address_b[1] => ram_block3a41.PORTBADDR1
+address_b[1] => ram_block3a42.PORTBADDR1
+address_b[1] => ram_block3a43.PORTBADDR1
+address_b[1] => ram_block3a44.PORTBADDR1
+address_b[1] => ram_block3a45.PORTBADDR1
+address_b[1] => ram_block3a46.PORTBADDR1
+address_b[1] => ram_block3a47.PORTBADDR1
+address_b[1] => ram_block3a48.PORTBADDR1
+address_b[1] => ram_block3a49.PORTBADDR1
+address_b[1] => ram_block3a50.PORTBADDR1
+address_b[1] => ram_block3a51.PORTBADDR1
+address_b[1] => ram_block3a52.PORTBADDR1
+address_b[1] => ram_block3a53.PORTBADDR1
+address_b[1] => ram_block3a54.PORTBADDR1
+address_b[1] => ram_block3a55.PORTBADDR1
+address_b[1] => ram_block3a56.PORTBADDR1
+address_b[1] => ram_block3a57.PORTBADDR1
+address_b[1] => ram_block3a58.PORTBADDR1
+address_b[1] => ram_block3a59.PORTBADDR1
+address_b[1] => ram_block3a60.PORTBADDR1
+address_b[1] => ram_block3a61.PORTBADDR1
+address_b[1] => ram_block3a62.PORTBADDR1
+address_b[1] => ram_block3a63.PORTBADDR1
+address_b[1] => ram_block3a64.PORTBADDR1
+address_b[1] => ram_block3a65.PORTBADDR1
+address_b[1] => ram_block3a66.PORTBADDR1
+address_b[1] => ram_block3a67.PORTBADDR1
+address_b[1] => ram_block3a68.PORTBADDR1
+address_b[1] => ram_block3a69.PORTBADDR1
+address_b[1] => ram_block3a70.PORTBADDR1
+address_b[1] => ram_block3a71.PORTBADDR1
+address_b[1] => ram_block3a72.PORTBADDR1
+address_b[1] => ram_block3a73.PORTBADDR1
+address_b[1] => ram_block3a74.PORTBADDR1
+address_b[1] => ram_block3a75.PORTBADDR1
+address_b[1] => ram_block3a76.PORTBADDR1
+address_b[1] => ram_block3a77.PORTBADDR1
+address_b[1] => ram_block3a78.PORTBADDR1
+address_b[1] => ram_block3a79.PORTBADDR1
+address_b[1] => ram_block3a80.PORTBADDR1
+address_b[1] => ram_block3a81.PORTBADDR1
+address_b[1] => ram_block3a82.PORTBADDR1
+address_b[1] => ram_block3a83.PORTBADDR1
+address_b[1] => ram_block3a84.PORTBADDR1
+address_b[1] => ram_block3a85.PORTBADDR1
+address_b[1] => ram_block3a86.PORTBADDR1
+address_b[1] => ram_block3a87.PORTBADDR1
+address_b[1] => ram_block3a88.PORTBADDR1
+address_b[1] => ram_block3a89.PORTBADDR1
+address_b[1] => ram_block3a90.PORTBADDR1
+address_b[1] => ram_block3a91.PORTBADDR1
+address_b[1] => ram_block3a92.PORTBADDR1
+address_b[1] => ram_block3a93.PORTBADDR1
+address_b[1] => ram_block3a94.PORTBADDR1
+address_b[1] => ram_block3a95.PORTBADDR1
+address_b[1] => ram_block3a96.PORTBADDR1
+address_b[1] => ram_block3a97.PORTBADDR1
+address_b[1] => ram_block3a98.PORTBADDR1
+address_b[1] => ram_block3a99.PORTBADDR1
+address_b[1] => ram_block3a100.PORTBADDR1
+address_b[1] => ram_block3a101.PORTBADDR1
+address_b[1] => ram_block3a102.PORTBADDR1
+address_b[1] => ram_block3a103.PORTBADDR1
+address_b[1] => ram_block3a104.PORTBADDR1
+address_b[1] => ram_block3a105.PORTBADDR1
+address_b[1] => ram_block3a106.PORTBADDR1
+address_b[1] => ram_block3a107.PORTBADDR1
+address_b[1] => ram_block3a108.PORTBADDR1
+address_b[1] => ram_block3a109.PORTBADDR1
+address_b[1] => ram_block3a110.PORTBADDR1
+address_b[1] => ram_block3a111.PORTBADDR1
+address_b[1] => ram_block3a112.PORTBADDR1
+address_b[1] => ram_block3a113.PORTBADDR1
+address_b[1] => ram_block3a114.PORTBADDR1
+address_b[1] => ram_block3a115.PORTBADDR1
+address_b[1] => ram_block3a116.PORTBADDR1
+address_b[1] => ram_block3a117.PORTBADDR1
+address_b[1] => ram_block3a118.PORTBADDR1
+address_b[1] => ram_block3a119.PORTBADDR1
+address_b[1] => ram_block3a120.PORTBADDR1
+address_b[1] => ram_block3a121.PORTBADDR1
+address_b[1] => ram_block3a122.PORTBADDR1
+address_b[1] => ram_block3a123.PORTBADDR1
+address_b[1] => ram_block3a124.PORTBADDR1
+address_b[1] => ram_block3a125.PORTBADDR1
+address_b[1] => ram_block3a126.PORTBADDR1
+address_b[1] => ram_block3a127.PORTBADDR1
+address_b[1] => ram_block3a128.PORTBADDR1
+address_b[1] => ram_block3a129.PORTBADDR1
+address_b[1] => ram_block3a130.PORTBADDR1
+address_b[1] => ram_block3a131.PORTBADDR1
+address_b[1] => ram_block3a132.PORTBADDR1
+address_b[1] => ram_block3a133.PORTBADDR1
+address_b[1] => ram_block3a134.PORTBADDR1
+address_b[1] => ram_block3a135.PORTBADDR1
+address_b[1] => ram_block3a136.PORTBADDR1
+address_b[1] => ram_block3a137.PORTBADDR1
+address_b[1] => ram_block3a138.PORTBADDR1
+address_b[1] => ram_block3a139.PORTBADDR1
+address_b[1] => ram_block3a140.PORTBADDR1
+address_b[1] => ram_block3a141.PORTBADDR1
+address_b[1] => ram_block3a142.PORTBADDR1
+address_b[1] => ram_block3a143.PORTBADDR1
+address_b[1] => ram_block3a144.PORTBADDR1
+address_b[1] => ram_block3a145.PORTBADDR1
+address_b[1] => ram_block3a146.PORTBADDR1
+address_b[1] => ram_block3a147.PORTBADDR1
+address_b[1] => ram_block3a148.PORTBADDR1
+address_b[1] => ram_block3a149.PORTBADDR1
+address_b[2] => ram_block3a0.PORTBADDR2
+address_b[2] => ram_block3a1.PORTBADDR2
+address_b[2] => ram_block3a2.PORTBADDR2
+address_b[2] => ram_block3a3.PORTBADDR2
+address_b[2] => ram_block3a4.PORTBADDR2
+address_b[2] => ram_block3a5.PORTBADDR2
+address_b[2] => ram_block3a6.PORTBADDR2
+address_b[2] => ram_block3a7.PORTBADDR2
+address_b[2] => ram_block3a8.PORTBADDR2
+address_b[2] => ram_block3a9.PORTBADDR2
+address_b[2] => ram_block3a10.PORTBADDR2
+address_b[2] => ram_block3a11.PORTBADDR2
+address_b[2] => ram_block3a12.PORTBADDR2
+address_b[2] => ram_block3a13.PORTBADDR2
+address_b[2] => ram_block3a14.PORTBADDR2
+address_b[2] => ram_block3a15.PORTBADDR2
+address_b[2] => ram_block3a16.PORTBADDR2
+address_b[2] => ram_block3a17.PORTBADDR2
+address_b[2] => ram_block3a18.PORTBADDR2
+address_b[2] => ram_block3a19.PORTBADDR2
+address_b[2] => ram_block3a20.PORTBADDR2
+address_b[2] => ram_block3a21.PORTBADDR2
+address_b[2] => ram_block3a22.PORTBADDR2
+address_b[2] => ram_block3a23.PORTBADDR2
+address_b[2] => ram_block3a24.PORTBADDR2
+address_b[2] => ram_block3a25.PORTBADDR2
+address_b[2] => ram_block3a26.PORTBADDR2
+address_b[2] => ram_block3a27.PORTBADDR2
+address_b[2] => ram_block3a28.PORTBADDR2
+address_b[2] => ram_block3a29.PORTBADDR2
+address_b[2] => ram_block3a30.PORTBADDR2
+address_b[2] => ram_block3a31.PORTBADDR2
+address_b[2] => ram_block3a32.PORTBADDR2
+address_b[2] => ram_block3a33.PORTBADDR2
+address_b[2] => ram_block3a34.PORTBADDR2
+address_b[2] => ram_block3a35.PORTBADDR2
+address_b[2] => ram_block3a36.PORTBADDR2
+address_b[2] => ram_block3a37.PORTBADDR2
+address_b[2] => ram_block3a38.PORTBADDR2
+address_b[2] => ram_block3a39.PORTBADDR2
+address_b[2] => ram_block3a40.PORTBADDR2
+address_b[2] => ram_block3a41.PORTBADDR2
+address_b[2] => ram_block3a42.PORTBADDR2
+address_b[2] => ram_block3a43.PORTBADDR2
+address_b[2] => ram_block3a44.PORTBADDR2
+address_b[2] => ram_block3a45.PORTBADDR2
+address_b[2] => ram_block3a46.PORTBADDR2
+address_b[2] => ram_block3a47.PORTBADDR2
+address_b[2] => ram_block3a48.PORTBADDR2
+address_b[2] => ram_block3a49.PORTBADDR2
+address_b[2] => ram_block3a50.PORTBADDR2
+address_b[2] => ram_block3a51.PORTBADDR2
+address_b[2] => ram_block3a52.PORTBADDR2
+address_b[2] => ram_block3a53.PORTBADDR2
+address_b[2] => ram_block3a54.PORTBADDR2
+address_b[2] => ram_block3a55.PORTBADDR2
+address_b[2] => ram_block3a56.PORTBADDR2
+address_b[2] => ram_block3a57.PORTBADDR2
+address_b[2] => ram_block3a58.PORTBADDR2
+address_b[2] => ram_block3a59.PORTBADDR2
+address_b[2] => ram_block3a60.PORTBADDR2
+address_b[2] => ram_block3a61.PORTBADDR2
+address_b[2] => ram_block3a62.PORTBADDR2
+address_b[2] => ram_block3a63.PORTBADDR2
+address_b[2] => ram_block3a64.PORTBADDR2
+address_b[2] => ram_block3a65.PORTBADDR2
+address_b[2] => ram_block3a66.PORTBADDR2
+address_b[2] => ram_block3a67.PORTBADDR2
+address_b[2] => ram_block3a68.PORTBADDR2
+address_b[2] => ram_block3a69.PORTBADDR2
+address_b[2] => ram_block3a70.PORTBADDR2
+address_b[2] => ram_block3a71.PORTBADDR2
+address_b[2] => ram_block3a72.PORTBADDR2
+address_b[2] => ram_block3a73.PORTBADDR2
+address_b[2] => ram_block3a74.PORTBADDR2
+address_b[2] => ram_block3a75.PORTBADDR2
+address_b[2] => ram_block3a76.PORTBADDR2
+address_b[2] => ram_block3a77.PORTBADDR2
+address_b[2] => ram_block3a78.PORTBADDR2
+address_b[2] => ram_block3a79.PORTBADDR2
+address_b[2] => ram_block3a80.PORTBADDR2
+address_b[2] => ram_block3a81.PORTBADDR2
+address_b[2] => ram_block3a82.PORTBADDR2
+address_b[2] => ram_block3a83.PORTBADDR2
+address_b[2] => ram_block3a84.PORTBADDR2
+address_b[2] => ram_block3a85.PORTBADDR2
+address_b[2] => ram_block3a86.PORTBADDR2
+address_b[2] => ram_block3a87.PORTBADDR2
+address_b[2] => ram_block3a88.PORTBADDR2
+address_b[2] => ram_block3a89.PORTBADDR2
+address_b[2] => ram_block3a90.PORTBADDR2
+address_b[2] => ram_block3a91.PORTBADDR2
+address_b[2] => ram_block3a92.PORTBADDR2
+address_b[2] => ram_block3a93.PORTBADDR2
+address_b[2] => ram_block3a94.PORTBADDR2
+address_b[2] => ram_block3a95.PORTBADDR2
+address_b[2] => ram_block3a96.PORTBADDR2
+address_b[2] => ram_block3a97.PORTBADDR2
+address_b[2] => ram_block3a98.PORTBADDR2
+address_b[2] => ram_block3a99.PORTBADDR2
+address_b[2] => ram_block3a100.PORTBADDR2
+address_b[2] => ram_block3a101.PORTBADDR2
+address_b[2] => ram_block3a102.PORTBADDR2
+address_b[2] => ram_block3a103.PORTBADDR2
+address_b[2] => ram_block3a104.PORTBADDR2
+address_b[2] => ram_block3a105.PORTBADDR2
+address_b[2] => ram_block3a106.PORTBADDR2
+address_b[2] => ram_block3a107.PORTBADDR2
+address_b[2] => ram_block3a108.PORTBADDR2
+address_b[2] => ram_block3a109.PORTBADDR2
+address_b[2] => ram_block3a110.PORTBADDR2
+address_b[2] => ram_block3a111.PORTBADDR2
+address_b[2] => ram_block3a112.PORTBADDR2
+address_b[2] => ram_block3a113.PORTBADDR2
+address_b[2] => ram_block3a114.PORTBADDR2
+address_b[2] => ram_block3a115.PORTBADDR2
+address_b[2] => ram_block3a116.PORTBADDR2
+address_b[2] => ram_block3a117.PORTBADDR2
+address_b[2] => ram_block3a118.PORTBADDR2
+address_b[2] => ram_block3a119.PORTBADDR2
+address_b[2] => ram_block3a120.PORTBADDR2
+address_b[2] => ram_block3a121.PORTBADDR2
+address_b[2] => ram_block3a122.PORTBADDR2
+address_b[2] => ram_block3a123.PORTBADDR2
+address_b[2] => ram_block3a124.PORTBADDR2
+address_b[2] => ram_block3a125.PORTBADDR2
+address_b[2] => ram_block3a126.PORTBADDR2
+address_b[2] => ram_block3a127.PORTBADDR2
+address_b[2] => ram_block3a128.PORTBADDR2
+address_b[2] => ram_block3a129.PORTBADDR2
+address_b[2] => ram_block3a130.PORTBADDR2
+address_b[2] => ram_block3a131.PORTBADDR2
+address_b[2] => ram_block3a132.PORTBADDR2
+address_b[2] => ram_block3a133.PORTBADDR2
+address_b[2] => ram_block3a134.PORTBADDR2
+address_b[2] => ram_block3a135.PORTBADDR2
+address_b[2] => ram_block3a136.PORTBADDR2
+address_b[2] => ram_block3a137.PORTBADDR2
+address_b[2] => ram_block3a138.PORTBADDR2
+address_b[2] => ram_block3a139.PORTBADDR2
+address_b[2] => ram_block3a140.PORTBADDR2
+address_b[2] => ram_block3a141.PORTBADDR2
+address_b[2] => ram_block3a142.PORTBADDR2
+address_b[2] => ram_block3a143.PORTBADDR2
+address_b[2] => ram_block3a144.PORTBADDR2
+address_b[2] => ram_block3a145.PORTBADDR2
+address_b[2] => ram_block3a146.PORTBADDR2
+address_b[2] => ram_block3a147.PORTBADDR2
+address_b[2] => ram_block3a148.PORTBADDR2
+address_b[2] => ram_block3a149.PORTBADDR2
+address_b[3] => ram_block3a0.PORTBADDR3
+address_b[3] => ram_block3a1.PORTBADDR3
+address_b[3] => ram_block3a2.PORTBADDR3
+address_b[3] => ram_block3a3.PORTBADDR3
+address_b[3] => ram_block3a4.PORTBADDR3
+address_b[3] => ram_block3a5.PORTBADDR3
+address_b[3] => ram_block3a6.PORTBADDR3
+address_b[3] => ram_block3a7.PORTBADDR3
+address_b[3] => ram_block3a8.PORTBADDR3
+address_b[3] => ram_block3a9.PORTBADDR3
+address_b[3] => ram_block3a10.PORTBADDR3
+address_b[3] => ram_block3a11.PORTBADDR3
+address_b[3] => ram_block3a12.PORTBADDR3
+address_b[3] => ram_block3a13.PORTBADDR3
+address_b[3] => ram_block3a14.PORTBADDR3
+address_b[3] => ram_block3a15.PORTBADDR3
+address_b[3] => ram_block3a16.PORTBADDR3
+address_b[3] => ram_block3a17.PORTBADDR3
+address_b[3] => ram_block3a18.PORTBADDR3
+address_b[3] => ram_block3a19.PORTBADDR3
+address_b[3] => ram_block3a20.PORTBADDR3
+address_b[3] => ram_block3a21.PORTBADDR3
+address_b[3] => ram_block3a22.PORTBADDR3
+address_b[3] => ram_block3a23.PORTBADDR3
+address_b[3] => ram_block3a24.PORTBADDR3
+address_b[3] => ram_block3a25.PORTBADDR3
+address_b[3] => ram_block3a26.PORTBADDR3
+address_b[3] => ram_block3a27.PORTBADDR3
+address_b[3] => ram_block3a28.PORTBADDR3
+address_b[3] => ram_block3a29.PORTBADDR3
+address_b[3] => ram_block3a30.PORTBADDR3
+address_b[3] => ram_block3a31.PORTBADDR3
+address_b[3] => ram_block3a32.PORTBADDR3
+address_b[3] => ram_block3a33.PORTBADDR3
+address_b[3] => ram_block3a34.PORTBADDR3
+address_b[3] => ram_block3a35.PORTBADDR3
+address_b[3] => ram_block3a36.PORTBADDR3
+address_b[3] => ram_block3a37.PORTBADDR3
+address_b[3] => ram_block3a38.PORTBADDR3
+address_b[3] => ram_block3a39.PORTBADDR3
+address_b[3] => ram_block3a40.PORTBADDR3
+address_b[3] => ram_block3a41.PORTBADDR3
+address_b[3] => ram_block3a42.PORTBADDR3
+address_b[3] => ram_block3a43.PORTBADDR3
+address_b[3] => ram_block3a44.PORTBADDR3
+address_b[3] => ram_block3a45.PORTBADDR3
+address_b[3] => ram_block3a46.PORTBADDR3
+address_b[3] => ram_block3a47.PORTBADDR3
+address_b[3] => ram_block3a48.PORTBADDR3
+address_b[3] => ram_block3a49.PORTBADDR3
+address_b[3] => ram_block3a50.PORTBADDR3
+address_b[3] => ram_block3a51.PORTBADDR3
+address_b[3] => ram_block3a52.PORTBADDR3
+address_b[3] => ram_block3a53.PORTBADDR3
+address_b[3] => ram_block3a54.PORTBADDR3
+address_b[3] => ram_block3a55.PORTBADDR3
+address_b[3] => ram_block3a56.PORTBADDR3
+address_b[3] => ram_block3a57.PORTBADDR3
+address_b[3] => ram_block3a58.PORTBADDR3
+address_b[3] => ram_block3a59.PORTBADDR3
+address_b[3] => ram_block3a60.PORTBADDR3
+address_b[3] => ram_block3a61.PORTBADDR3
+address_b[3] => ram_block3a62.PORTBADDR3
+address_b[3] => ram_block3a63.PORTBADDR3
+address_b[3] => ram_block3a64.PORTBADDR3
+address_b[3] => ram_block3a65.PORTBADDR3
+address_b[3] => ram_block3a66.PORTBADDR3
+address_b[3] => ram_block3a67.PORTBADDR3
+address_b[3] => ram_block3a68.PORTBADDR3
+address_b[3] => ram_block3a69.PORTBADDR3
+address_b[3] => ram_block3a70.PORTBADDR3
+address_b[3] => ram_block3a71.PORTBADDR3
+address_b[3] => ram_block3a72.PORTBADDR3
+address_b[3] => ram_block3a73.PORTBADDR3
+address_b[3] => ram_block3a74.PORTBADDR3
+address_b[3] => ram_block3a75.PORTBADDR3
+address_b[3] => ram_block3a76.PORTBADDR3
+address_b[3] => ram_block3a77.PORTBADDR3
+address_b[3] => ram_block3a78.PORTBADDR3
+address_b[3] => ram_block3a79.PORTBADDR3
+address_b[3] => ram_block3a80.PORTBADDR3
+address_b[3] => ram_block3a81.PORTBADDR3
+address_b[3] => ram_block3a82.PORTBADDR3
+address_b[3] => ram_block3a83.PORTBADDR3
+address_b[3] => ram_block3a84.PORTBADDR3
+address_b[3] => ram_block3a85.PORTBADDR3
+address_b[3] => ram_block3a86.PORTBADDR3
+address_b[3] => ram_block3a87.PORTBADDR3
+address_b[3] => ram_block3a88.PORTBADDR3
+address_b[3] => ram_block3a89.PORTBADDR3
+address_b[3] => ram_block3a90.PORTBADDR3
+address_b[3] => ram_block3a91.PORTBADDR3
+address_b[3] => ram_block3a92.PORTBADDR3
+address_b[3] => ram_block3a93.PORTBADDR3
+address_b[3] => ram_block3a94.PORTBADDR3
+address_b[3] => ram_block3a95.PORTBADDR3
+address_b[3] => ram_block3a96.PORTBADDR3
+address_b[3] => ram_block3a97.PORTBADDR3
+address_b[3] => ram_block3a98.PORTBADDR3
+address_b[3] => ram_block3a99.PORTBADDR3
+address_b[3] => ram_block3a100.PORTBADDR3
+address_b[3] => ram_block3a101.PORTBADDR3
+address_b[3] => ram_block3a102.PORTBADDR3
+address_b[3] => ram_block3a103.PORTBADDR3
+address_b[3] => ram_block3a104.PORTBADDR3
+address_b[3] => ram_block3a105.PORTBADDR3
+address_b[3] => ram_block3a106.PORTBADDR3
+address_b[3] => ram_block3a107.PORTBADDR3
+address_b[3] => ram_block3a108.PORTBADDR3
+address_b[3] => ram_block3a109.PORTBADDR3
+address_b[3] => ram_block3a110.PORTBADDR3
+address_b[3] => ram_block3a111.PORTBADDR3
+address_b[3] => ram_block3a112.PORTBADDR3
+address_b[3] => ram_block3a113.PORTBADDR3
+address_b[3] => ram_block3a114.PORTBADDR3
+address_b[3] => ram_block3a115.PORTBADDR3
+address_b[3] => ram_block3a116.PORTBADDR3
+address_b[3] => ram_block3a117.PORTBADDR3
+address_b[3] => ram_block3a118.PORTBADDR3
+address_b[3] => ram_block3a119.PORTBADDR3
+address_b[3] => ram_block3a120.PORTBADDR3
+address_b[3] => ram_block3a121.PORTBADDR3
+address_b[3] => ram_block3a122.PORTBADDR3
+address_b[3] => ram_block3a123.PORTBADDR3
+address_b[3] => ram_block3a124.PORTBADDR3
+address_b[3] => ram_block3a125.PORTBADDR3
+address_b[3] => ram_block3a126.PORTBADDR3
+address_b[3] => ram_block3a127.PORTBADDR3
+address_b[3] => ram_block3a128.PORTBADDR3
+address_b[3] => ram_block3a129.PORTBADDR3
+address_b[3] => ram_block3a130.PORTBADDR3
+address_b[3] => ram_block3a131.PORTBADDR3
+address_b[3] => ram_block3a132.PORTBADDR3
+address_b[3] => ram_block3a133.PORTBADDR3
+address_b[3] => ram_block3a134.PORTBADDR3
+address_b[3] => ram_block3a135.PORTBADDR3
+address_b[3] => ram_block3a136.PORTBADDR3
+address_b[3] => ram_block3a137.PORTBADDR3
+address_b[3] => ram_block3a138.PORTBADDR3
+address_b[3] => ram_block3a139.PORTBADDR3
+address_b[3] => ram_block3a140.PORTBADDR3
+address_b[3] => ram_block3a141.PORTBADDR3
+address_b[3] => ram_block3a142.PORTBADDR3
+address_b[3] => ram_block3a143.PORTBADDR3
+address_b[3] => ram_block3a144.PORTBADDR3
+address_b[3] => ram_block3a145.PORTBADDR3
+address_b[3] => ram_block3a146.PORTBADDR3
+address_b[3] => ram_block3a147.PORTBADDR3
+address_b[3] => ram_block3a148.PORTBADDR3
+address_b[3] => ram_block3a149.PORTBADDR3
+address_b[4] => ram_block3a0.PORTBADDR4
+address_b[4] => ram_block3a1.PORTBADDR4
+address_b[4] => ram_block3a2.PORTBADDR4
+address_b[4] => ram_block3a3.PORTBADDR4
+address_b[4] => ram_block3a4.PORTBADDR4
+address_b[4] => ram_block3a5.PORTBADDR4
+address_b[4] => ram_block3a6.PORTBADDR4
+address_b[4] => ram_block3a7.PORTBADDR4
+address_b[4] => ram_block3a8.PORTBADDR4
+address_b[4] => ram_block3a9.PORTBADDR4
+address_b[4] => ram_block3a10.PORTBADDR4
+address_b[4] => ram_block3a11.PORTBADDR4
+address_b[4] => ram_block3a12.PORTBADDR4
+address_b[4] => ram_block3a13.PORTBADDR4
+address_b[4] => ram_block3a14.PORTBADDR4
+address_b[4] => ram_block3a15.PORTBADDR4
+address_b[4] => ram_block3a16.PORTBADDR4
+address_b[4] => ram_block3a17.PORTBADDR4
+address_b[4] => ram_block3a18.PORTBADDR4
+address_b[4] => ram_block3a19.PORTBADDR4
+address_b[4] => ram_block3a20.PORTBADDR4
+address_b[4] => ram_block3a21.PORTBADDR4
+address_b[4] => ram_block3a22.PORTBADDR4
+address_b[4] => ram_block3a23.PORTBADDR4
+address_b[4] => ram_block3a24.PORTBADDR4
+address_b[4] => ram_block3a25.PORTBADDR4
+address_b[4] => ram_block3a26.PORTBADDR4
+address_b[4] => ram_block3a27.PORTBADDR4
+address_b[4] => ram_block3a28.PORTBADDR4
+address_b[4] => ram_block3a29.PORTBADDR4
+address_b[4] => ram_block3a30.PORTBADDR4
+address_b[4] => ram_block3a31.PORTBADDR4
+address_b[4] => ram_block3a32.PORTBADDR4
+address_b[4] => ram_block3a33.PORTBADDR4
+address_b[4] => ram_block3a34.PORTBADDR4
+address_b[4] => ram_block3a35.PORTBADDR4
+address_b[4] => ram_block3a36.PORTBADDR4
+address_b[4] => ram_block3a37.PORTBADDR4
+address_b[4] => ram_block3a38.PORTBADDR4
+address_b[4] => ram_block3a39.PORTBADDR4
+address_b[4] => ram_block3a40.PORTBADDR4
+address_b[4] => ram_block3a41.PORTBADDR4
+address_b[4] => ram_block3a42.PORTBADDR4
+address_b[4] => ram_block3a43.PORTBADDR4
+address_b[4] => ram_block3a44.PORTBADDR4
+address_b[4] => ram_block3a45.PORTBADDR4
+address_b[4] => ram_block3a46.PORTBADDR4
+address_b[4] => ram_block3a47.PORTBADDR4
+address_b[4] => ram_block3a48.PORTBADDR4
+address_b[4] => ram_block3a49.PORTBADDR4
+address_b[4] => ram_block3a50.PORTBADDR4
+address_b[4] => ram_block3a51.PORTBADDR4
+address_b[4] => ram_block3a52.PORTBADDR4
+address_b[4] => ram_block3a53.PORTBADDR4
+address_b[4] => ram_block3a54.PORTBADDR4
+address_b[4] => ram_block3a55.PORTBADDR4
+address_b[4] => ram_block3a56.PORTBADDR4
+address_b[4] => ram_block3a57.PORTBADDR4
+address_b[4] => ram_block3a58.PORTBADDR4
+address_b[4] => ram_block3a59.PORTBADDR4
+address_b[4] => ram_block3a60.PORTBADDR4
+address_b[4] => ram_block3a61.PORTBADDR4
+address_b[4] => ram_block3a62.PORTBADDR4
+address_b[4] => ram_block3a63.PORTBADDR4
+address_b[4] => ram_block3a64.PORTBADDR4
+address_b[4] => ram_block3a65.PORTBADDR4
+address_b[4] => ram_block3a66.PORTBADDR4
+address_b[4] => ram_block3a67.PORTBADDR4
+address_b[4] => ram_block3a68.PORTBADDR4
+address_b[4] => ram_block3a69.PORTBADDR4
+address_b[4] => ram_block3a70.PORTBADDR4
+address_b[4] => ram_block3a71.PORTBADDR4
+address_b[4] => ram_block3a72.PORTBADDR4
+address_b[4] => ram_block3a73.PORTBADDR4
+address_b[4] => ram_block3a74.PORTBADDR4
+address_b[4] => ram_block3a75.PORTBADDR4
+address_b[4] => ram_block3a76.PORTBADDR4
+address_b[4] => ram_block3a77.PORTBADDR4
+address_b[4] => ram_block3a78.PORTBADDR4
+address_b[4] => ram_block3a79.PORTBADDR4
+address_b[4] => ram_block3a80.PORTBADDR4
+address_b[4] => ram_block3a81.PORTBADDR4
+address_b[4] => ram_block3a82.PORTBADDR4
+address_b[4] => ram_block3a83.PORTBADDR4
+address_b[4] => ram_block3a84.PORTBADDR4
+address_b[4] => ram_block3a85.PORTBADDR4
+address_b[4] => ram_block3a86.PORTBADDR4
+address_b[4] => ram_block3a87.PORTBADDR4
+address_b[4] => ram_block3a88.PORTBADDR4
+address_b[4] => ram_block3a89.PORTBADDR4
+address_b[4] => ram_block3a90.PORTBADDR4
+address_b[4] => ram_block3a91.PORTBADDR4
+address_b[4] => ram_block3a92.PORTBADDR4
+address_b[4] => ram_block3a93.PORTBADDR4
+address_b[4] => ram_block3a94.PORTBADDR4
+address_b[4] => ram_block3a95.PORTBADDR4
+address_b[4] => ram_block3a96.PORTBADDR4
+address_b[4] => ram_block3a97.PORTBADDR4
+address_b[4] => ram_block3a98.PORTBADDR4
+address_b[4] => ram_block3a99.PORTBADDR4
+address_b[4] => ram_block3a100.PORTBADDR4
+address_b[4] => ram_block3a101.PORTBADDR4
+address_b[4] => ram_block3a102.PORTBADDR4
+address_b[4] => ram_block3a103.PORTBADDR4
+address_b[4] => ram_block3a104.PORTBADDR4
+address_b[4] => ram_block3a105.PORTBADDR4
+address_b[4] => ram_block3a106.PORTBADDR4
+address_b[4] => ram_block3a107.PORTBADDR4
+address_b[4] => ram_block3a108.PORTBADDR4
+address_b[4] => ram_block3a109.PORTBADDR4
+address_b[4] => ram_block3a110.PORTBADDR4
+address_b[4] => ram_block3a111.PORTBADDR4
+address_b[4] => ram_block3a112.PORTBADDR4
+address_b[4] => ram_block3a113.PORTBADDR4
+address_b[4] => ram_block3a114.PORTBADDR4
+address_b[4] => ram_block3a115.PORTBADDR4
+address_b[4] => ram_block3a116.PORTBADDR4
+address_b[4] => ram_block3a117.PORTBADDR4
+address_b[4] => ram_block3a118.PORTBADDR4
+address_b[4] => ram_block3a119.PORTBADDR4
+address_b[4] => ram_block3a120.PORTBADDR4
+address_b[4] => ram_block3a121.PORTBADDR4
+address_b[4] => ram_block3a122.PORTBADDR4
+address_b[4] => ram_block3a123.PORTBADDR4
+address_b[4] => ram_block3a124.PORTBADDR4
+address_b[4] => ram_block3a125.PORTBADDR4
+address_b[4] => ram_block3a126.PORTBADDR4
+address_b[4] => ram_block3a127.PORTBADDR4
+address_b[4] => ram_block3a128.PORTBADDR4
+address_b[4] => ram_block3a129.PORTBADDR4
+address_b[4] => ram_block3a130.PORTBADDR4
+address_b[4] => ram_block3a131.PORTBADDR4
+address_b[4] => ram_block3a132.PORTBADDR4
+address_b[4] => ram_block3a133.PORTBADDR4
+address_b[4] => ram_block3a134.PORTBADDR4
+address_b[4] => ram_block3a135.PORTBADDR4
+address_b[4] => ram_block3a136.PORTBADDR4
+address_b[4] => ram_block3a137.PORTBADDR4
+address_b[4] => ram_block3a138.PORTBADDR4
+address_b[4] => ram_block3a139.PORTBADDR4
+address_b[4] => ram_block3a140.PORTBADDR4
+address_b[4] => ram_block3a141.PORTBADDR4
+address_b[4] => ram_block3a142.PORTBADDR4
+address_b[4] => ram_block3a143.PORTBADDR4
+address_b[4] => ram_block3a144.PORTBADDR4
+address_b[4] => ram_block3a145.PORTBADDR4
+address_b[4] => ram_block3a146.PORTBADDR4
+address_b[4] => ram_block3a147.PORTBADDR4
+address_b[4] => ram_block3a148.PORTBADDR4
+address_b[4] => ram_block3a149.PORTBADDR4
+address_b[5] => ram_block3a0.PORTBADDR5
+address_b[5] => ram_block3a1.PORTBADDR5
+address_b[5] => ram_block3a2.PORTBADDR5
+address_b[5] => ram_block3a3.PORTBADDR5
+address_b[5] => ram_block3a4.PORTBADDR5
+address_b[5] => ram_block3a5.PORTBADDR5
+address_b[5] => ram_block3a6.PORTBADDR5
+address_b[5] => ram_block3a7.PORTBADDR5
+address_b[5] => ram_block3a8.PORTBADDR5
+address_b[5] => ram_block3a9.PORTBADDR5
+address_b[5] => ram_block3a10.PORTBADDR5
+address_b[5] => ram_block3a11.PORTBADDR5
+address_b[5] => ram_block3a12.PORTBADDR5
+address_b[5] => ram_block3a13.PORTBADDR5
+address_b[5] => ram_block3a14.PORTBADDR5
+address_b[5] => ram_block3a15.PORTBADDR5
+address_b[5] => ram_block3a16.PORTBADDR5
+address_b[5] => ram_block3a17.PORTBADDR5
+address_b[5] => ram_block3a18.PORTBADDR5
+address_b[5] => ram_block3a19.PORTBADDR5
+address_b[5] => ram_block3a20.PORTBADDR5
+address_b[5] => ram_block3a21.PORTBADDR5
+address_b[5] => ram_block3a22.PORTBADDR5
+address_b[5] => ram_block3a23.PORTBADDR5
+address_b[5] => ram_block3a24.PORTBADDR5
+address_b[5] => ram_block3a25.PORTBADDR5
+address_b[5] => ram_block3a26.PORTBADDR5
+address_b[5] => ram_block3a27.PORTBADDR5
+address_b[5] => ram_block3a28.PORTBADDR5
+address_b[5] => ram_block3a29.PORTBADDR5
+address_b[5] => ram_block3a30.PORTBADDR5
+address_b[5] => ram_block3a31.PORTBADDR5
+address_b[5] => ram_block3a32.PORTBADDR5
+address_b[5] => ram_block3a33.PORTBADDR5
+address_b[5] => ram_block3a34.PORTBADDR5
+address_b[5] => ram_block3a35.PORTBADDR5
+address_b[5] => ram_block3a36.PORTBADDR5
+address_b[5] => ram_block3a37.PORTBADDR5
+address_b[5] => ram_block3a38.PORTBADDR5
+address_b[5] => ram_block3a39.PORTBADDR5
+address_b[5] => ram_block3a40.PORTBADDR5
+address_b[5] => ram_block3a41.PORTBADDR5
+address_b[5] => ram_block3a42.PORTBADDR5
+address_b[5] => ram_block3a43.PORTBADDR5
+address_b[5] => ram_block3a44.PORTBADDR5
+address_b[5] => ram_block3a45.PORTBADDR5
+address_b[5] => ram_block3a46.PORTBADDR5
+address_b[5] => ram_block3a47.PORTBADDR5
+address_b[5] => ram_block3a48.PORTBADDR5
+address_b[5] => ram_block3a49.PORTBADDR5
+address_b[5] => ram_block3a50.PORTBADDR5
+address_b[5] => ram_block3a51.PORTBADDR5
+address_b[5] => ram_block3a52.PORTBADDR5
+address_b[5] => ram_block3a53.PORTBADDR5
+address_b[5] => ram_block3a54.PORTBADDR5
+address_b[5] => ram_block3a55.PORTBADDR5
+address_b[5] => ram_block3a56.PORTBADDR5
+address_b[5] => ram_block3a57.PORTBADDR5
+address_b[5] => ram_block3a58.PORTBADDR5
+address_b[5] => ram_block3a59.PORTBADDR5
+address_b[5] => ram_block3a60.PORTBADDR5
+address_b[5] => ram_block3a61.PORTBADDR5
+address_b[5] => ram_block3a62.PORTBADDR5
+address_b[5] => ram_block3a63.PORTBADDR5
+address_b[5] => ram_block3a64.PORTBADDR5
+address_b[5] => ram_block3a65.PORTBADDR5
+address_b[5] => ram_block3a66.PORTBADDR5
+address_b[5] => ram_block3a67.PORTBADDR5
+address_b[5] => ram_block3a68.PORTBADDR5
+address_b[5] => ram_block3a69.PORTBADDR5
+address_b[5] => ram_block3a70.PORTBADDR5
+address_b[5] => ram_block3a71.PORTBADDR5
+address_b[5] => ram_block3a72.PORTBADDR5
+address_b[5] => ram_block3a73.PORTBADDR5
+address_b[5] => ram_block3a74.PORTBADDR5
+address_b[5] => ram_block3a75.PORTBADDR5
+address_b[5] => ram_block3a76.PORTBADDR5
+address_b[5] => ram_block3a77.PORTBADDR5
+address_b[5] => ram_block3a78.PORTBADDR5
+address_b[5] => ram_block3a79.PORTBADDR5
+address_b[5] => ram_block3a80.PORTBADDR5
+address_b[5] => ram_block3a81.PORTBADDR5
+address_b[5] => ram_block3a82.PORTBADDR5
+address_b[5] => ram_block3a83.PORTBADDR5
+address_b[5] => ram_block3a84.PORTBADDR5
+address_b[5] => ram_block3a85.PORTBADDR5
+address_b[5] => ram_block3a86.PORTBADDR5
+address_b[5] => ram_block3a87.PORTBADDR5
+address_b[5] => ram_block3a88.PORTBADDR5
+address_b[5] => ram_block3a89.PORTBADDR5
+address_b[5] => ram_block3a90.PORTBADDR5
+address_b[5] => ram_block3a91.PORTBADDR5
+address_b[5] => ram_block3a92.PORTBADDR5
+address_b[5] => ram_block3a93.PORTBADDR5
+address_b[5] => ram_block3a94.PORTBADDR5
+address_b[5] => ram_block3a95.PORTBADDR5
+address_b[5] => ram_block3a96.PORTBADDR5
+address_b[5] => ram_block3a97.PORTBADDR5
+address_b[5] => ram_block3a98.PORTBADDR5
+address_b[5] => ram_block3a99.PORTBADDR5
+address_b[5] => ram_block3a100.PORTBADDR5
+address_b[5] => ram_block3a101.PORTBADDR5
+address_b[5] => ram_block3a102.PORTBADDR5
+address_b[5] => ram_block3a103.PORTBADDR5
+address_b[5] => ram_block3a104.PORTBADDR5
+address_b[5] => ram_block3a105.PORTBADDR5
+address_b[5] => ram_block3a106.PORTBADDR5
+address_b[5] => ram_block3a107.PORTBADDR5
+address_b[5] => ram_block3a108.PORTBADDR5
+address_b[5] => ram_block3a109.PORTBADDR5
+address_b[5] => ram_block3a110.PORTBADDR5
+address_b[5] => ram_block3a111.PORTBADDR5
+address_b[5] => ram_block3a112.PORTBADDR5
+address_b[5] => ram_block3a113.PORTBADDR5
+address_b[5] => ram_block3a114.PORTBADDR5
+address_b[5] => ram_block3a115.PORTBADDR5
+address_b[5] => ram_block3a116.PORTBADDR5
+address_b[5] => ram_block3a117.PORTBADDR5
+address_b[5] => ram_block3a118.PORTBADDR5
+address_b[5] => ram_block3a119.PORTBADDR5
+address_b[5] => ram_block3a120.PORTBADDR5
+address_b[5] => ram_block3a121.PORTBADDR5
+address_b[5] => ram_block3a122.PORTBADDR5
+address_b[5] => ram_block3a123.PORTBADDR5
+address_b[5] => ram_block3a124.PORTBADDR5
+address_b[5] => ram_block3a125.PORTBADDR5
+address_b[5] => ram_block3a126.PORTBADDR5
+address_b[5] => ram_block3a127.PORTBADDR5
+address_b[5] => ram_block3a128.PORTBADDR5
+address_b[5] => ram_block3a129.PORTBADDR5
+address_b[5] => ram_block3a130.PORTBADDR5
+address_b[5] => ram_block3a131.PORTBADDR5
+address_b[5] => ram_block3a132.PORTBADDR5
+address_b[5] => ram_block3a133.PORTBADDR5
+address_b[5] => ram_block3a134.PORTBADDR5
+address_b[5] => ram_block3a135.PORTBADDR5
+address_b[5] => ram_block3a136.PORTBADDR5
+address_b[5] => ram_block3a137.PORTBADDR5
+address_b[5] => ram_block3a138.PORTBADDR5
+address_b[5] => ram_block3a139.PORTBADDR5
+address_b[5] => ram_block3a140.PORTBADDR5
+address_b[5] => ram_block3a141.PORTBADDR5
+address_b[5] => ram_block3a142.PORTBADDR5
+address_b[5] => ram_block3a143.PORTBADDR5
+address_b[5] => ram_block3a144.PORTBADDR5
+address_b[5] => ram_block3a145.PORTBADDR5
+address_b[5] => ram_block3a146.PORTBADDR5
+address_b[5] => ram_block3a147.PORTBADDR5
+address_b[5] => ram_block3a148.PORTBADDR5
+address_b[5] => ram_block3a149.PORTBADDR5
+address_b[6] => ram_block3a0.PORTBADDR6
+address_b[6] => ram_block3a1.PORTBADDR6
+address_b[6] => ram_block3a2.PORTBADDR6
+address_b[6] => ram_block3a3.PORTBADDR6
+address_b[6] => ram_block3a4.PORTBADDR6
+address_b[6] => ram_block3a5.PORTBADDR6
+address_b[6] => ram_block3a6.PORTBADDR6
+address_b[6] => ram_block3a7.PORTBADDR6
+address_b[6] => ram_block3a8.PORTBADDR6
+address_b[6] => ram_block3a9.PORTBADDR6
+address_b[6] => ram_block3a10.PORTBADDR6
+address_b[6] => ram_block3a11.PORTBADDR6
+address_b[6] => ram_block3a12.PORTBADDR6
+address_b[6] => ram_block3a13.PORTBADDR6
+address_b[6] => ram_block3a14.PORTBADDR6
+address_b[6] => ram_block3a15.PORTBADDR6
+address_b[6] => ram_block3a16.PORTBADDR6
+address_b[6] => ram_block3a17.PORTBADDR6
+address_b[6] => ram_block3a18.PORTBADDR6
+address_b[6] => ram_block3a19.PORTBADDR6
+address_b[6] => ram_block3a20.PORTBADDR6
+address_b[6] => ram_block3a21.PORTBADDR6
+address_b[6] => ram_block3a22.PORTBADDR6
+address_b[6] => ram_block3a23.PORTBADDR6
+address_b[6] => ram_block3a24.PORTBADDR6
+address_b[6] => ram_block3a25.PORTBADDR6
+address_b[6] => ram_block3a26.PORTBADDR6
+address_b[6] => ram_block3a27.PORTBADDR6
+address_b[6] => ram_block3a28.PORTBADDR6
+address_b[6] => ram_block3a29.PORTBADDR6
+address_b[6] => ram_block3a30.PORTBADDR6
+address_b[6] => ram_block3a31.PORTBADDR6
+address_b[6] => ram_block3a32.PORTBADDR6
+address_b[6] => ram_block3a33.PORTBADDR6
+address_b[6] => ram_block3a34.PORTBADDR6
+address_b[6] => ram_block3a35.PORTBADDR6
+address_b[6] => ram_block3a36.PORTBADDR6
+address_b[6] => ram_block3a37.PORTBADDR6
+address_b[6] => ram_block3a38.PORTBADDR6
+address_b[6] => ram_block3a39.PORTBADDR6
+address_b[6] => ram_block3a40.PORTBADDR6
+address_b[6] => ram_block3a41.PORTBADDR6
+address_b[6] => ram_block3a42.PORTBADDR6
+address_b[6] => ram_block3a43.PORTBADDR6
+address_b[6] => ram_block3a44.PORTBADDR6
+address_b[6] => ram_block3a45.PORTBADDR6
+address_b[6] => ram_block3a46.PORTBADDR6
+address_b[6] => ram_block3a47.PORTBADDR6
+address_b[6] => ram_block3a48.PORTBADDR6
+address_b[6] => ram_block3a49.PORTBADDR6
+address_b[6] => ram_block3a50.PORTBADDR6
+address_b[6] => ram_block3a51.PORTBADDR6
+address_b[6] => ram_block3a52.PORTBADDR6
+address_b[6] => ram_block3a53.PORTBADDR6
+address_b[6] => ram_block3a54.PORTBADDR6
+address_b[6] => ram_block3a55.PORTBADDR6
+address_b[6] => ram_block3a56.PORTBADDR6
+address_b[6] => ram_block3a57.PORTBADDR6
+address_b[6] => ram_block3a58.PORTBADDR6
+address_b[6] => ram_block3a59.PORTBADDR6
+address_b[6] => ram_block3a60.PORTBADDR6
+address_b[6] => ram_block3a61.PORTBADDR6
+address_b[6] => ram_block3a62.PORTBADDR6
+address_b[6] => ram_block3a63.PORTBADDR6
+address_b[6] => ram_block3a64.PORTBADDR6
+address_b[6] => ram_block3a65.PORTBADDR6
+address_b[6] => ram_block3a66.PORTBADDR6
+address_b[6] => ram_block3a67.PORTBADDR6
+address_b[6] => ram_block3a68.PORTBADDR6
+address_b[6] => ram_block3a69.PORTBADDR6
+address_b[6] => ram_block3a70.PORTBADDR6
+address_b[6] => ram_block3a71.PORTBADDR6
+address_b[6] => ram_block3a72.PORTBADDR6
+address_b[6] => ram_block3a73.PORTBADDR6
+address_b[6] => ram_block3a74.PORTBADDR6
+address_b[6] => ram_block3a75.PORTBADDR6
+address_b[6] => ram_block3a76.PORTBADDR6
+address_b[6] => ram_block3a77.PORTBADDR6
+address_b[6] => ram_block3a78.PORTBADDR6
+address_b[6] => ram_block3a79.PORTBADDR6
+address_b[6] => ram_block3a80.PORTBADDR6
+address_b[6] => ram_block3a81.PORTBADDR6
+address_b[6] => ram_block3a82.PORTBADDR6
+address_b[6] => ram_block3a83.PORTBADDR6
+address_b[6] => ram_block3a84.PORTBADDR6
+address_b[6] => ram_block3a85.PORTBADDR6
+address_b[6] => ram_block3a86.PORTBADDR6
+address_b[6] => ram_block3a87.PORTBADDR6
+address_b[6] => ram_block3a88.PORTBADDR6
+address_b[6] => ram_block3a89.PORTBADDR6
+address_b[6] => ram_block3a90.PORTBADDR6
+address_b[6] => ram_block3a91.PORTBADDR6
+address_b[6] => ram_block3a92.PORTBADDR6
+address_b[6] => ram_block3a93.PORTBADDR6
+address_b[6] => ram_block3a94.PORTBADDR6
+address_b[6] => ram_block3a95.PORTBADDR6
+address_b[6] => ram_block3a96.PORTBADDR6
+address_b[6] => ram_block3a97.PORTBADDR6
+address_b[6] => ram_block3a98.PORTBADDR6
+address_b[6] => ram_block3a99.PORTBADDR6
+address_b[6] => ram_block3a100.PORTBADDR6
+address_b[6] => ram_block3a101.PORTBADDR6
+address_b[6] => ram_block3a102.PORTBADDR6
+address_b[6] => ram_block3a103.PORTBADDR6
+address_b[6] => ram_block3a104.PORTBADDR6
+address_b[6] => ram_block3a105.PORTBADDR6
+address_b[6] => ram_block3a106.PORTBADDR6
+address_b[6] => ram_block3a107.PORTBADDR6
+address_b[6] => ram_block3a108.PORTBADDR6
+address_b[6] => ram_block3a109.PORTBADDR6
+address_b[6] => ram_block3a110.PORTBADDR6
+address_b[6] => ram_block3a111.PORTBADDR6
+address_b[6] => ram_block3a112.PORTBADDR6
+address_b[6] => ram_block3a113.PORTBADDR6
+address_b[6] => ram_block3a114.PORTBADDR6
+address_b[6] => ram_block3a115.PORTBADDR6
+address_b[6] => ram_block3a116.PORTBADDR6
+address_b[6] => ram_block3a117.PORTBADDR6
+address_b[6] => ram_block3a118.PORTBADDR6
+address_b[6] => ram_block3a119.PORTBADDR6
+address_b[6] => ram_block3a120.PORTBADDR6
+address_b[6] => ram_block3a121.PORTBADDR6
+address_b[6] => ram_block3a122.PORTBADDR6
+address_b[6] => ram_block3a123.PORTBADDR6
+address_b[6] => ram_block3a124.PORTBADDR6
+address_b[6] => ram_block3a125.PORTBADDR6
+address_b[6] => ram_block3a126.PORTBADDR6
+address_b[6] => ram_block3a127.PORTBADDR6
+address_b[6] => ram_block3a128.PORTBADDR6
+address_b[6] => ram_block3a129.PORTBADDR6
+address_b[6] => ram_block3a130.PORTBADDR6
+address_b[6] => ram_block3a131.PORTBADDR6
+address_b[6] => ram_block3a132.PORTBADDR6
+address_b[6] => ram_block3a133.PORTBADDR6
+address_b[6] => ram_block3a134.PORTBADDR6
+address_b[6] => ram_block3a135.PORTBADDR6
+address_b[6] => ram_block3a136.PORTBADDR6
+address_b[6] => ram_block3a137.PORTBADDR6
+address_b[6] => ram_block3a138.PORTBADDR6
+address_b[6] => ram_block3a139.PORTBADDR6
+address_b[6] => ram_block3a140.PORTBADDR6
+address_b[6] => ram_block3a141.PORTBADDR6
+address_b[6] => ram_block3a142.PORTBADDR6
+address_b[6] => ram_block3a143.PORTBADDR6
+address_b[6] => ram_block3a144.PORTBADDR6
+address_b[6] => ram_block3a145.PORTBADDR6
+address_b[6] => ram_block3a146.PORTBADDR6
+address_b[6] => ram_block3a147.PORTBADDR6
+address_b[6] => ram_block3a148.PORTBADDR6
+address_b[6] => ram_block3a149.PORTBADDR6
+address_b[7] => ram_block3a0.PORTBADDR7
+address_b[7] => ram_block3a1.PORTBADDR7
+address_b[7] => ram_block3a2.PORTBADDR7
+address_b[7] => ram_block3a3.PORTBADDR7
+address_b[7] => ram_block3a4.PORTBADDR7
+address_b[7] => ram_block3a5.PORTBADDR7
+address_b[7] => ram_block3a6.PORTBADDR7
+address_b[7] => ram_block3a7.PORTBADDR7
+address_b[7] => ram_block3a8.PORTBADDR7
+address_b[7] => ram_block3a9.PORTBADDR7
+address_b[7] => ram_block3a10.PORTBADDR7
+address_b[7] => ram_block3a11.PORTBADDR7
+address_b[7] => ram_block3a12.PORTBADDR7
+address_b[7] => ram_block3a13.PORTBADDR7
+address_b[7] => ram_block3a14.PORTBADDR7
+address_b[7] => ram_block3a15.PORTBADDR7
+address_b[7] => ram_block3a16.PORTBADDR7
+address_b[7] => ram_block3a17.PORTBADDR7
+address_b[7] => ram_block3a18.PORTBADDR7
+address_b[7] => ram_block3a19.PORTBADDR7
+address_b[7] => ram_block3a20.PORTBADDR7
+address_b[7] => ram_block3a21.PORTBADDR7
+address_b[7] => ram_block3a22.PORTBADDR7
+address_b[7] => ram_block3a23.PORTBADDR7
+address_b[7] => ram_block3a24.PORTBADDR7
+address_b[7] => ram_block3a25.PORTBADDR7
+address_b[7] => ram_block3a26.PORTBADDR7
+address_b[7] => ram_block3a27.PORTBADDR7
+address_b[7] => ram_block3a28.PORTBADDR7
+address_b[7] => ram_block3a29.PORTBADDR7
+address_b[7] => ram_block3a30.PORTBADDR7
+address_b[7] => ram_block3a31.PORTBADDR7
+address_b[7] => ram_block3a32.PORTBADDR7
+address_b[7] => ram_block3a33.PORTBADDR7
+address_b[7] => ram_block3a34.PORTBADDR7
+address_b[7] => ram_block3a35.PORTBADDR7
+address_b[7] => ram_block3a36.PORTBADDR7
+address_b[7] => ram_block3a37.PORTBADDR7
+address_b[7] => ram_block3a38.PORTBADDR7
+address_b[7] => ram_block3a39.PORTBADDR7
+address_b[7] => ram_block3a40.PORTBADDR7
+address_b[7] => ram_block3a41.PORTBADDR7
+address_b[7] => ram_block3a42.PORTBADDR7
+address_b[7] => ram_block3a43.PORTBADDR7
+address_b[7] => ram_block3a44.PORTBADDR7
+address_b[7] => ram_block3a45.PORTBADDR7
+address_b[7] => ram_block3a46.PORTBADDR7
+address_b[7] => ram_block3a47.PORTBADDR7
+address_b[7] => ram_block3a48.PORTBADDR7
+address_b[7] => ram_block3a49.PORTBADDR7
+address_b[7] => ram_block3a50.PORTBADDR7
+address_b[7] => ram_block3a51.PORTBADDR7
+address_b[7] => ram_block3a52.PORTBADDR7
+address_b[7] => ram_block3a53.PORTBADDR7
+address_b[7] => ram_block3a54.PORTBADDR7
+address_b[7] => ram_block3a55.PORTBADDR7
+address_b[7] => ram_block3a56.PORTBADDR7
+address_b[7] => ram_block3a57.PORTBADDR7
+address_b[7] => ram_block3a58.PORTBADDR7
+address_b[7] => ram_block3a59.PORTBADDR7
+address_b[7] => ram_block3a60.PORTBADDR7
+address_b[7] => ram_block3a61.PORTBADDR7
+address_b[7] => ram_block3a62.PORTBADDR7
+address_b[7] => ram_block3a63.PORTBADDR7
+address_b[7] => ram_block3a64.PORTBADDR7
+address_b[7] => ram_block3a65.PORTBADDR7
+address_b[7] => ram_block3a66.PORTBADDR7
+address_b[7] => ram_block3a67.PORTBADDR7
+address_b[7] => ram_block3a68.PORTBADDR7
+address_b[7] => ram_block3a69.PORTBADDR7
+address_b[7] => ram_block3a70.PORTBADDR7
+address_b[7] => ram_block3a71.PORTBADDR7
+address_b[7] => ram_block3a72.PORTBADDR7
+address_b[7] => ram_block3a73.PORTBADDR7
+address_b[7] => ram_block3a74.PORTBADDR7
+address_b[7] => ram_block3a75.PORTBADDR7
+address_b[7] => ram_block3a76.PORTBADDR7
+address_b[7] => ram_block3a77.PORTBADDR7
+address_b[7] => ram_block3a78.PORTBADDR7
+address_b[7] => ram_block3a79.PORTBADDR7
+address_b[7] => ram_block3a80.PORTBADDR7
+address_b[7] => ram_block3a81.PORTBADDR7
+address_b[7] => ram_block3a82.PORTBADDR7
+address_b[7] => ram_block3a83.PORTBADDR7
+address_b[7] => ram_block3a84.PORTBADDR7
+address_b[7] => ram_block3a85.PORTBADDR7
+address_b[7] => ram_block3a86.PORTBADDR7
+address_b[7] => ram_block3a87.PORTBADDR7
+address_b[7] => ram_block3a88.PORTBADDR7
+address_b[7] => ram_block3a89.PORTBADDR7
+address_b[7] => ram_block3a90.PORTBADDR7
+address_b[7] => ram_block3a91.PORTBADDR7
+address_b[7] => ram_block3a92.PORTBADDR7
+address_b[7] => ram_block3a93.PORTBADDR7
+address_b[7] => ram_block3a94.PORTBADDR7
+address_b[7] => ram_block3a95.PORTBADDR7
+address_b[7] => ram_block3a96.PORTBADDR7
+address_b[7] => ram_block3a97.PORTBADDR7
+address_b[7] => ram_block3a98.PORTBADDR7
+address_b[7] => ram_block3a99.PORTBADDR7
+address_b[7] => ram_block3a100.PORTBADDR7
+address_b[7] => ram_block3a101.PORTBADDR7
+address_b[7] => ram_block3a102.PORTBADDR7
+address_b[7] => ram_block3a103.PORTBADDR7
+address_b[7] => ram_block3a104.PORTBADDR7
+address_b[7] => ram_block3a105.PORTBADDR7
+address_b[7] => ram_block3a106.PORTBADDR7
+address_b[7] => ram_block3a107.PORTBADDR7
+address_b[7] => ram_block3a108.PORTBADDR7
+address_b[7] => ram_block3a109.PORTBADDR7
+address_b[7] => ram_block3a110.PORTBADDR7
+address_b[7] => ram_block3a111.PORTBADDR7
+address_b[7] => ram_block3a112.PORTBADDR7
+address_b[7] => ram_block3a113.PORTBADDR7
+address_b[7] => ram_block3a114.PORTBADDR7
+address_b[7] => ram_block3a115.PORTBADDR7
+address_b[7] => ram_block3a116.PORTBADDR7
+address_b[7] => ram_block3a117.PORTBADDR7
+address_b[7] => ram_block3a118.PORTBADDR7
+address_b[7] => ram_block3a119.PORTBADDR7
+address_b[7] => ram_block3a120.PORTBADDR7
+address_b[7] => ram_block3a121.PORTBADDR7
+address_b[7] => ram_block3a122.PORTBADDR7
+address_b[7] => ram_block3a123.PORTBADDR7
+address_b[7] => ram_block3a124.PORTBADDR7
+address_b[7] => ram_block3a125.PORTBADDR7
+address_b[7] => ram_block3a126.PORTBADDR7
+address_b[7] => ram_block3a127.PORTBADDR7
+address_b[7] => ram_block3a128.PORTBADDR7
+address_b[7] => ram_block3a129.PORTBADDR7
+address_b[7] => ram_block3a130.PORTBADDR7
+address_b[7] => ram_block3a131.PORTBADDR7
+address_b[7] => ram_block3a132.PORTBADDR7
+address_b[7] => ram_block3a133.PORTBADDR7
+address_b[7] => ram_block3a134.PORTBADDR7
+address_b[7] => ram_block3a135.PORTBADDR7
+address_b[7] => ram_block3a136.PORTBADDR7
+address_b[7] => ram_block3a137.PORTBADDR7
+address_b[7] => ram_block3a138.PORTBADDR7
+address_b[7] => ram_block3a139.PORTBADDR7
+address_b[7] => ram_block3a140.PORTBADDR7
+address_b[7] => ram_block3a141.PORTBADDR7
+address_b[7] => ram_block3a142.PORTBADDR7
+address_b[7] => ram_block3a143.PORTBADDR7
+address_b[7] => ram_block3a144.PORTBADDR7
+address_b[7] => ram_block3a145.PORTBADDR7
+address_b[7] => ram_block3a146.PORTBADDR7
+address_b[7] => ram_block3a147.PORTBADDR7
+address_b[7] => ram_block3a148.PORTBADDR7
+address_b[7] => ram_block3a149.PORTBADDR7
+address_b[8] => ram_block3a0.PORTBADDR8
+address_b[8] => ram_block3a1.PORTBADDR8
+address_b[8] => ram_block3a2.PORTBADDR8
+address_b[8] => ram_block3a3.PORTBADDR8
+address_b[8] => ram_block3a4.PORTBADDR8
+address_b[8] => ram_block3a5.PORTBADDR8
+address_b[8] => ram_block3a6.PORTBADDR8
+address_b[8] => ram_block3a7.PORTBADDR8
+address_b[8] => ram_block3a8.PORTBADDR8
+address_b[8] => ram_block3a9.PORTBADDR8
+address_b[8] => ram_block3a10.PORTBADDR8
+address_b[8] => ram_block3a11.PORTBADDR8
+address_b[8] => ram_block3a12.PORTBADDR8
+address_b[8] => ram_block3a13.PORTBADDR8
+address_b[8] => ram_block3a14.PORTBADDR8
+address_b[8] => ram_block3a15.PORTBADDR8
+address_b[8] => ram_block3a16.PORTBADDR8
+address_b[8] => ram_block3a17.PORTBADDR8
+address_b[8] => ram_block3a18.PORTBADDR8
+address_b[8] => ram_block3a19.PORTBADDR8
+address_b[8] => ram_block3a20.PORTBADDR8
+address_b[8] => ram_block3a21.PORTBADDR8
+address_b[8] => ram_block3a22.PORTBADDR8
+address_b[8] => ram_block3a23.PORTBADDR8
+address_b[8] => ram_block3a24.PORTBADDR8
+address_b[8] => ram_block3a25.PORTBADDR8
+address_b[8] => ram_block3a26.PORTBADDR8
+address_b[8] => ram_block3a27.PORTBADDR8
+address_b[8] => ram_block3a28.PORTBADDR8
+address_b[8] => ram_block3a29.PORTBADDR8
+address_b[8] => ram_block3a30.PORTBADDR8
+address_b[8] => ram_block3a31.PORTBADDR8
+address_b[8] => ram_block3a32.PORTBADDR8
+address_b[8] => ram_block3a33.PORTBADDR8
+address_b[8] => ram_block3a34.PORTBADDR8
+address_b[8] => ram_block3a35.PORTBADDR8
+address_b[8] => ram_block3a36.PORTBADDR8
+address_b[8] => ram_block3a37.PORTBADDR8
+address_b[8] => ram_block3a38.PORTBADDR8
+address_b[8] => ram_block3a39.PORTBADDR8
+address_b[8] => ram_block3a40.PORTBADDR8
+address_b[8] => ram_block3a41.PORTBADDR8
+address_b[8] => ram_block3a42.PORTBADDR8
+address_b[8] => ram_block3a43.PORTBADDR8
+address_b[8] => ram_block3a44.PORTBADDR8
+address_b[8] => ram_block3a45.PORTBADDR8
+address_b[8] => ram_block3a46.PORTBADDR8
+address_b[8] => ram_block3a47.PORTBADDR8
+address_b[8] => ram_block3a48.PORTBADDR8
+address_b[8] => ram_block3a49.PORTBADDR8
+address_b[8] => ram_block3a50.PORTBADDR8
+address_b[8] => ram_block3a51.PORTBADDR8
+address_b[8] => ram_block3a52.PORTBADDR8
+address_b[8] => ram_block3a53.PORTBADDR8
+address_b[8] => ram_block3a54.PORTBADDR8
+address_b[8] => ram_block3a55.PORTBADDR8
+address_b[8] => ram_block3a56.PORTBADDR8
+address_b[8] => ram_block3a57.PORTBADDR8
+address_b[8] => ram_block3a58.PORTBADDR8
+address_b[8] => ram_block3a59.PORTBADDR8
+address_b[8] => ram_block3a60.PORTBADDR8
+address_b[8] => ram_block3a61.PORTBADDR8
+address_b[8] => ram_block3a62.PORTBADDR8
+address_b[8] => ram_block3a63.PORTBADDR8
+address_b[8] => ram_block3a64.PORTBADDR8
+address_b[8] => ram_block3a65.PORTBADDR8
+address_b[8] => ram_block3a66.PORTBADDR8
+address_b[8] => ram_block3a67.PORTBADDR8
+address_b[8] => ram_block3a68.PORTBADDR8
+address_b[8] => ram_block3a69.PORTBADDR8
+address_b[8] => ram_block3a70.PORTBADDR8
+address_b[8] => ram_block3a71.PORTBADDR8
+address_b[8] => ram_block3a72.PORTBADDR8
+address_b[8] => ram_block3a73.PORTBADDR8
+address_b[8] => ram_block3a74.PORTBADDR8
+address_b[8] => ram_block3a75.PORTBADDR8
+address_b[8] => ram_block3a76.PORTBADDR8
+address_b[8] => ram_block3a77.PORTBADDR8
+address_b[8] => ram_block3a78.PORTBADDR8
+address_b[8] => ram_block3a79.PORTBADDR8
+address_b[8] => ram_block3a80.PORTBADDR8
+address_b[8] => ram_block3a81.PORTBADDR8
+address_b[8] => ram_block3a82.PORTBADDR8
+address_b[8] => ram_block3a83.PORTBADDR8
+address_b[8] => ram_block3a84.PORTBADDR8
+address_b[8] => ram_block3a85.PORTBADDR8
+address_b[8] => ram_block3a86.PORTBADDR8
+address_b[8] => ram_block3a87.PORTBADDR8
+address_b[8] => ram_block3a88.PORTBADDR8
+address_b[8] => ram_block3a89.PORTBADDR8
+address_b[8] => ram_block3a90.PORTBADDR8
+address_b[8] => ram_block3a91.PORTBADDR8
+address_b[8] => ram_block3a92.PORTBADDR8
+address_b[8] => ram_block3a93.PORTBADDR8
+address_b[8] => ram_block3a94.PORTBADDR8
+address_b[8] => ram_block3a95.PORTBADDR8
+address_b[8] => ram_block3a96.PORTBADDR8
+address_b[8] => ram_block3a97.PORTBADDR8
+address_b[8] => ram_block3a98.PORTBADDR8
+address_b[8] => ram_block3a99.PORTBADDR8
+address_b[8] => ram_block3a100.PORTBADDR8
+address_b[8] => ram_block3a101.PORTBADDR8
+address_b[8] => ram_block3a102.PORTBADDR8
+address_b[8] => ram_block3a103.PORTBADDR8
+address_b[8] => ram_block3a104.PORTBADDR8
+address_b[8] => ram_block3a105.PORTBADDR8
+address_b[8] => ram_block3a106.PORTBADDR8
+address_b[8] => ram_block3a107.PORTBADDR8
+address_b[8] => ram_block3a108.PORTBADDR8
+address_b[8] => ram_block3a109.PORTBADDR8
+address_b[8] => ram_block3a110.PORTBADDR8
+address_b[8] => ram_block3a111.PORTBADDR8
+address_b[8] => ram_block3a112.PORTBADDR8
+address_b[8] => ram_block3a113.PORTBADDR8
+address_b[8] => ram_block3a114.PORTBADDR8
+address_b[8] => ram_block3a115.PORTBADDR8
+address_b[8] => ram_block3a116.PORTBADDR8
+address_b[8] => ram_block3a117.PORTBADDR8
+address_b[8] => ram_block3a118.PORTBADDR8
+address_b[8] => ram_block3a119.PORTBADDR8
+address_b[8] => ram_block3a120.PORTBADDR8
+address_b[8] => ram_block3a121.PORTBADDR8
+address_b[8] => ram_block3a122.PORTBADDR8
+address_b[8] => ram_block3a123.PORTBADDR8
+address_b[8] => ram_block3a124.PORTBADDR8
+address_b[8] => ram_block3a125.PORTBADDR8
+address_b[8] => ram_block3a126.PORTBADDR8
+address_b[8] => ram_block3a127.PORTBADDR8
+address_b[8] => ram_block3a128.PORTBADDR8
+address_b[8] => ram_block3a129.PORTBADDR8
+address_b[8] => ram_block3a130.PORTBADDR8
+address_b[8] => ram_block3a131.PORTBADDR8
+address_b[8] => ram_block3a132.PORTBADDR8
+address_b[8] => ram_block3a133.PORTBADDR8
+address_b[8] => ram_block3a134.PORTBADDR8
+address_b[8] => ram_block3a135.PORTBADDR8
+address_b[8] => ram_block3a136.PORTBADDR8
+address_b[8] => ram_block3a137.PORTBADDR8
+address_b[8] => ram_block3a138.PORTBADDR8
+address_b[8] => ram_block3a139.PORTBADDR8
+address_b[8] => ram_block3a140.PORTBADDR8
+address_b[8] => ram_block3a141.PORTBADDR8
+address_b[8] => ram_block3a142.PORTBADDR8
+address_b[8] => ram_block3a143.PORTBADDR8
+address_b[8] => ram_block3a144.PORTBADDR8
+address_b[8] => ram_block3a145.PORTBADDR8
+address_b[8] => ram_block3a146.PORTBADDR8
+address_b[8] => ram_block3a147.PORTBADDR8
+address_b[8] => ram_block3a148.PORTBADDR8
+address_b[8] => ram_block3a149.PORTBADDR8
+address_b[9] => ram_block3a0.PORTBADDR9
+address_b[9] => ram_block3a1.PORTBADDR9
+address_b[9] => ram_block3a2.PORTBADDR9
+address_b[9] => ram_block3a3.PORTBADDR9
+address_b[9] => ram_block3a4.PORTBADDR9
+address_b[9] => ram_block3a5.PORTBADDR9
+address_b[9] => ram_block3a6.PORTBADDR9
+address_b[9] => ram_block3a7.PORTBADDR9
+address_b[9] => ram_block3a8.PORTBADDR9
+address_b[9] => ram_block3a9.PORTBADDR9
+address_b[9] => ram_block3a10.PORTBADDR9
+address_b[9] => ram_block3a11.PORTBADDR9
+address_b[9] => ram_block3a12.PORTBADDR9
+address_b[9] => ram_block3a13.PORTBADDR9
+address_b[9] => ram_block3a14.PORTBADDR9
+address_b[9] => ram_block3a15.PORTBADDR9
+address_b[9] => ram_block3a16.PORTBADDR9
+address_b[9] => ram_block3a17.PORTBADDR9
+address_b[9] => ram_block3a18.PORTBADDR9
+address_b[9] => ram_block3a19.PORTBADDR9
+address_b[9] => ram_block3a20.PORTBADDR9
+address_b[9] => ram_block3a21.PORTBADDR9
+address_b[9] => ram_block3a22.PORTBADDR9
+address_b[9] => ram_block3a23.PORTBADDR9
+address_b[9] => ram_block3a24.PORTBADDR9
+address_b[9] => ram_block3a25.PORTBADDR9
+address_b[9] => ram_block3a26.PORTBADDR9
+address_b[9] => ram_block3a27.PORTBADDR9
+address_b[9] => ram_block3a28.PORTBADDR9
+address_b[9] => ram_block3a29.PORTBADDR9
+address_b[9] => ram_block3a30.PORTBADDR9
+address_b[9] => ram_block3a31.PORTBADDR9
+address_b[9] => ram_block3a32.PORTBADDR9
+address_b[9] => ram_block3a33.PORTBADDR9
+address_b[9] => ram_block3a34.PORTBADDR9
+address_b[9] => ram_block3a35.PORTBADDR9
+address_b[9] => ram_block3a36.PORTBADDR9
+address_b[9] => ram_block3a37.PORTBADDR9
+address_b[9] => ram_block3a38.PORTBADDR9
+address_b[9] => ram_block3a39.PORTBADDR9
+address_b[9] => ram_block3a40.PORTBADDR9
+address_b[9] => ram_block3a41.PORTBADDR9
+address_b[9] => ram_block3a42.PORTBADDR9
+address_b[9] => ram_block3a43.PORTBADDR9
+address_b[9] => ram_block3a44.PORTBADDR9
+address_b[9] => ram_block3a45.PORTBADDR9
+address_b[9] => ram_block3a46.PORTBADDR9
+address_b[9] => ram_block3a47.PORTBADDR9
+address_b[9] => ram_block3a48.PORTBADDR9
+address_b[9] => ram_block3a49.PORTBADDR9
+address_b[9] => ram_block3a50.PORTBADDR9
+address_b[9] => ram_block3a51.PORTBADDR9
+address_b[9] => ram_block3a52.PORTBADDR9
+address_b[9] => ram_block3a53.PORTBADDR9
+address_b[9] => ram_block3a54.PORTBADDR9
+address_b[9] => ram_block3a55.PORTBADDR9
+address_b[9] => ram_block3a56.PORTBADDR9
+address_b[9] => ram_block3a57.PORTBADDR9
+address_b[9] => ram_block3a58.PORTBADDR9
+address_b[9] => ram_block3a59.PORTBADDR9
+address_b[9] => ram_block3a60.PORTBADDR9
+address_b[9] => ram_block3a61.PORTBADDR9
+address_b[9] => ram_block3a62.PORTBADDR9
+address_b[9] => ram_block3a63.PORTBADDR9
+address_b[9] => ram_block3a64.PORTBADDR9
+address_b[9] => ram_block3a65.PORTBADDR9
+address_b[9] => ram_block3a66.PORTBADDR9
+address_b[9] => ram_block3a67.PORTBADDR9
+address_b[9] => ram_block3a68.PORTBADDR9
+address_b[9] => ram_block3a69.PORTBADDR9
+address_b[9] => ram_block3a70.PORTBADDR9
+address_b[9] => ram_block3a71.PORTBADDR9
+address_b[9] => ram_block3a72.PORTBADDR9
+address_b[9] => ram_block3a73.PORTBADDR9
+address_b[9] => ram_block3a74.PORTBADDR9
+address_b[9] => ram_block3a75.PORTBADDR9
+address_b[9] => ram_block3a76.PORTBADDR9
+address_b[9] => ram_block3a77.PORTBADDR9
+address_b[9] => ram_block3a78.PORTBADDR9
+address_b[9] => ram_block3a79.PORTBADDR9
+address_b[9] => ram_block3a80.PORTBADDR9
+address_b[9] => ram_block3a81.PORTBADDR9
+address_b[9] => ram_block3a82.PORTBADDR9
+address_b[9] => ram_block3a83.PORTBADDR9
+address_b[9] => ram_block3a84.PORTBADDR9
+address_b[9] => ram_block3a85.PORTBADDR9
+address_b[9] => ram_block3a86.PORTBADDR9
+address_b[9] => ram_block3a87.PORTBADDR9
+address_b[9] => ram_block3a88.PORTBADDR9
+address_b[9] => ram_block3a89.PORTBADDR9
+address_b[9] => ram_block3a90.PORTBADDR9
+address_b[9] => ram_block3a91.PORTBADDR9
+address_b[9] => ram_block3a92.PORTBADDR9
+address_b[9] => ram_block3a93.PORTBADDR9
+address_b[9] => ram_block3a94.PORTBADDR9
+address_b[9] => ram_block3a95.PORTBADDR9
+address_b[9] => ram_block3a96.PORTBADDR9
+address_b[9] => ram_block3a97.PORTBADDR9
+address_b[9] => ram_block3a98.PORTBADDR9
+address_b[9] => ram_block3a99.PORTBADDR9
+address_b[9] => ram_block3a100.PORTBADDR9
+address_b[9] => ram_block3a101.PORTBADDR9
+address_b[9] => ram_block3a102.PORTBADDR9
+address_b[9] => ram_block3a103.PORTBADDR9
+address_b[9] => ram_block3a104.PORTBADDR9
+address_b[9] => ram_block3a105.PORTBADDR9
+address_b[9] => ram_block3a106.PORTBADDR9
+address_b[9] => ram_block3a107.PORTBADDR9
+address_b[9] => ram_block3a108.PORTBADDR9
+address_b[9] => ram_block3a109.PORTBADDR9
+address_b[9] => ram_block3a110.PORTBADDR9
+address_b[9] => ram_block3a111.PORTBADDR9
+address_b[9] => ram_block3a112.PORTBADDR9
+address_b[9] => ram_block3a113.PORTBADDR9
+address_b[9] => ram_block3a114.PORTBADDR9
+address_b[9] => ram_block3a115.PORTBADDR9
+address_b[9] => ram_block3a116.PORTBADDR9
+address_b[9] => ram_block3a117.PORTBADDR9
+address_b[9] => ram_block3a118.PORTBADDR9
+address_b[9] => ram_block3a119.PORTBADDR9
+address_b[9] => ram_block3a120.PORTBADDR9
+address_b[9] => ram_block3a121.PORTBADDR9
+address_b[9] => ram_block3a122.PORTBADDR9
+address_b[9] => ram_block3a123.PORTBADDR9
+address_b[9] => ram_block3a124.PORTBADDR9
+address_b[9] => ram_block3a125.PORTBADDR9
+address_b[9] => ram_block3a126.PORTBADDR9
+address_b[9] => ram_block3a127.PORTBADDR9
+address_b[9] => ram_block3a128.PORTBADDR9
+address_b[9] => ram_block3a129.PORTBADDR9
+address_b[9] => ram_block3a130.PORTBADDR9
+address_b[9] => ram_block3a131.PORTBADDR9
+address_b[9] => ram_block3a132.PORTBADDR9
+address_b[9] => ram_block3a133.PORTBADDR9
+address_b[9] => ram_block3a134.PORTBADDR9
+address_b[9] => ram_block3a135.PORTBADDR9
+address_b[9] => ram_block3a136.PORTBADDR9
+address_b[9] => ram_block3a137.PORTBADDR9
+address_b[9] => ram_block3a138.PORTBADDR9
+address_b[9] => ram_block3a139.PORTBADDR9
+address_b[9] => ram_block3a140.PORTBADDR9
+address_b[9] => ram_block3a141.PORTBADDR9
+address_b[9] => ram_block3a142.PORTBADDR9
+address_b[9] => ram_block3a143.PORTBADDR9
+address_b[9] => ram_block3a144.PORTBADDR9
+address_b[9] => ram_block3a145.PORTBADDR9
+address_b[9] => ram_block3a146.PORTBADDR9
+address_b[9] => ram_block3a147.PORTBADDR9
+address_b[9] => ram_block3a148.PORTBADDR9
+address_b[9] => ram_block3a149.PORTBADDR9
+clock0 => ram_block3a0.CLK0
+clock0 => ram_block3a1.CLK0
+clock0 => ram_block3a2.CLK0
+clock0 => ram_block3a3.CLK0
+clock0 => ram_block3a4.CLK0
+clock0 => ram_block3a5.CLK0
+clock0 => ram_block3a6.CLK0
+clock0 => ram_block3a7.CLK0
+clock0 => ram_block3a8.CLK0
+clock0 => ram_block3a9.CLK0
+clock0 => ram_block3a10.CLK0
+clock0 => ram_block3a11.CLK0
+clock0 => ram_block3a12.CLK0
+clock0 => ram_block3a13.CLK0
+clock0 => ram_block3a14.CLK0
+clock0 => ram_block3a15.CLK0
+clock0 => ram_block3a16.CLK0
+clock0 => ram_block3a17.CLK0
+clock0 => ram_block3a18.CLK0
+clock0 => ram_block3a19.CLK0
+clock0 => ram_block3a20.CLK0
+clock0 => ram_block3a21.CLK0
+clock0 => ram_block3a22.CLK0
+clock0 => ram_block3a23.CLK0
+clock0 => ram_block3a24.CLK0
+clock0 => ram_block3a25.CLK0
+clock0 => ram_block3a26.CLK0
+clock0 => ram_block3a27.CLK0
+clock0 => ram_block3a28.CLK0
+clock0 => ram_block3a29.CLK0
+clock0 => ram_block3a30.CLK0
+clock0 => ram_block3a31.CLK0
+clock0 => ram_block3a32.CLK0
+clock0 => ram_block3a33.CLK0
+clock0 => ram_block3a34.CLK0
+clock0 => ram_block3a35.CLK0
+clock0 => ram_block3a36.CLK0
+clock0 => ram_block3a37.CLK0
+clock0 => ram_block3a38.CLK0
+clock0 => ram_block3a39.CLK0
+clock0 => ram_block3a40.CLK0
+clock0 => ram_block3a41.CLK0
+clock0 => ram_block3a42.CLK0
+clock0 => ram_block3a43.CLK0
+clock0 => ram_block3a44.CLK0
+clock0 => ram_block3a45.CLK0
+clock0 => ram_block3a46.CLK0
+clock0 => ram_block3a47.CLK0
+clock0 => ram_block3a48.CLK0
+clock0 => ram_block3a49.CLK0
+clock0 => ram_block3a50.CLK0
+clock0 => ram_block3a51.CLK0
+clock0 => ram_block3a52.CLK0
+clock0 => ram_block3a53.CLK0
+clock0 => ram_block3a54.CLK0
+clock0 => ram_block3a55.CLK0
+clock0 => ram_block3a56.CLK0
+clock0 => ram_block3a57.CLK0
+clock0 => ram_block3a58.CLK0
+clock0 => ram_block3a59.CLK0
+clock0 => ram_block3a60.CLK0
+clock0 => ram_block3a61.CLK0
+clock0 => ram_block3a62.CLK0
+clock0 => ram_block3a63.CLK0
+clock0 => ram_block3a64.CLK0
+clock0 => ram_block3a65.CLK0
+clock0 => ram_block3a66.CLK0
+clock0 => ram_block3a67.CLK0
+clock0 => ram_block3a68.CLK0
+clock0 => ram_block3a69.CLK0
+clock0 => ram_block3a70.CLK0
+clock0 => ram_block3a71.CLK0
+clock0 => ram_block3a72.CLK0
+clock0 => ram_block3a73.CLK0
+clock0 => ram_block3a74.CLK0
+clock0 => ram_block3a75.CLK0
+clock0 => ram_block3a76.CLK0
+clock0 => ram_block3a77.CLK0
+clock0 => ram_block3a78.CLK0
+clock0 => ram_block3a79.CLK0
+clock0 => ram_block3a80.CLK0
+clock0 => ram_block3a81.CLK0
+clock0 => ram_block3a82.CLK0
+clock0 => ram_block3a83.CLK0
+clock0 => ram_block3a84.CLK0
+clock0 => ram_block3a85.CLK0
+clock0 => ram_block3a86.CLK0
+clock0 => ram_block3a87.CLK0
+clock0 => ram_block3a88.CLK0
+clock0 => ram_block3a89.CLK0
+clock0 => ram_block3a90.CLK0
+clock0 => ram_block3a91.CLK0
+clock0 => ram_block3a92.CLK0
+clock0 => ram_block3a93.CLK0
+clock0 => ram_block3a94.CLK0
+clock0 => ram_block3a95.CLK0
+clock0 => ram_block3a96.CLK0
+clock0 => ram_block3a97.CLK0
+clock0 => ram_block3a98.CLK0
+clock0 => ram_block3a99.CLK0
+clock0 => ram_block3a100.CLK0
+clock0 => ram_block3a101.CLK0
+clock0 => ram_block3a102.CLK0
+clock0 => ram_block3a103.CLK0
+clock0 => ram_block3a104.CLK0
+clock0 => ram_block3a105.CLK0
+clock0 => ram_block3a106.CLK0
+clock0 => ram_block3a107.CLK0
+clock0 => ram_block3a108.CLK0
+clock0 => ram_block3a109.CLK0
+clock0 => ram_block3a110.CLK0
+clock0 => ram_block3a111.CLK0
+clock0 => ram_block3a112.CLK0
+clock0 => ram_block3a113.CLK0
+clock0 => ram_block3a114.CLK0
+clock0 => ram_block3a115.CLK0
+clock0 => ram_block3a116.CLK0
+clock0 => ram_block3a117.CLK0
+clock0 => ram_block3a118.CLK0
+clock0 => ram_block3a119.CLK0
+clock0 => ram_block3a120.CLK0
+clock0 => ram_block3a121.CLK0
+clock0 => ram_block3a122.CLK0
+clock0 => ram_block3a123.CLK0
+clock0 => ram_block3a124.CLK0
+clock0 => ram_block3a125.CLK0
+clock0 => ram_block3a126.CLK0
+clock0 => ram_block3a127.CLK0
+clock0 => ram_block3a128.CLK0
+clock0 => ram_block3a129.CLK0
+clock0 => ram_block3a130.CLK0
+clock0 => ram_block3a131.CLK0
+clock0 => ram_block3a132.CLK0
+clock0 => ram_block3a133.CLK0
+clock0 => ram_block3a134.CLK0
+clock0 => ram_block3a135.CLK0
+clock0 => ram_block3a136.CLK0
+clock0 => ram_block3a137.CLK0
+clock0 => ram_block3a138.CLK0
+clock0 => ram_block3a139.CLK0
+clock0 => ram_block3a140.CLK0
+clock0 => ram_block3a141.CLK0
+clock0 => ram_block3a142.CLK0
+clock0 => ram_block3a143.CLK0
+clock0 => ram_block3a144.CLK0
+clock0 => ram_block3a145.CLK0
+clock0 => ram_block3a146.CLK0
+clock0 => ram_block3a147.CLK0
+clock0 => ram_block3a148.CLK0
+clock0 => ram_block3a149.CLK0
+clocken0 => ram_block3a0.ENA0
+clocken0 => ram_block3a1.ENA0
+clocken0 => ram_block3a2.ENA0
+clocken0 => ram_block3a3.ENA0
+clocken0 => ram_block3a4.ENA0
+clocken0 => ram_block3a5.ENA0
+clocken0 => ram_block3a6.ENA0
+clocken0 => ram_block3a7.ENA0
+clocken0 => ram_block3a8.ENA0
+clocken0 => ram_block3a9.ENA0
+clocken0 => ram_block3a10.ENA0
+clocken0 => ram_block3a11.ENA0
+clocken0 => ram_block3a12.ENA0
+clocken0 => ram_block3a13.ENA0
+clocken0 => ram_block3a14.ENA0
+clocken0 => ram_block3a15.ENA0
+clocken0 => ram_block3a16.ENA0
+clocken0 => ram_block3a17.ENA0
+clocken0 => ram_block3a18.ENA0
+clocken0 => ram_block3a19.ENA0
+clocken0 => ram_block3a20.ENA0
+clocken0 => ram_block3a21.ENA0
+clocken0 => ram_block3a22.ENA0
+clocken0 => ram_block3a23.ENA0
+clocken0 => ram_block3a24.ENA0
+clocken0 => ram_block3a25.ENA0
+clocken0 => ram_block3a26.ENA0
+clocken0 => ram_block3a27.ENA0
+clocken0 => ram_block3a28.ENA0
+clocken0 => ram_block3a29.ENA0
+clocken0 => ram_block3a30.ENA0
+clocken0 => ram_block3a31.ENA0
+clocken0 => ram_block3a32.ENA0
+clocken0 => ram_block3a33.ENA0
+clocken0 => ram_block3a34.ENA0
+clocken0 => ram_block3a35.ENA0
+clocken0 => ram_block3a36.ENA0
+clocken0 => ram_block3a37.ENA0
+clocken0 => ram_block3a38.ENA0
+clocken0 => ram_block3a39.ENA0
+clocken0 => ram_block3a40.ENA0
+clocken0 => ram_block3a41.ENA0
+clocken0 => ram_block3a42.ENA0
+clocken0 => ram_block3a43.ENA0
+clocken0 => ram_block3a44.ENA0
+clocken0 => ram_block3a45.ENA0
+clocken0 => ram_block3a46.ENA0
+clocken0 => ram_block3a47.ENA0
+clocken0 => ram_block3a48.ENA0
+clocken0 => ram_block3a49.ENA0
+clocken0 => ram_block3a50.ENA0
+clocken0 => ram_block3a51.ENA0
+clocken0 => ram_block3a52.ENA0
+clocken0 => ram_block3a53.ENA0
+clocken0 => ram_block3a54.ENA0
+clocken0 => ram_block3a55.ENA0
+clocken0 => ram_block3a56.ENA0
+clocken0 => ram_block3a57.ENA0
+clocken0 => ram_block3a58.ENA0
+clocken0 => ram_block3a59.ENA0
+clocken0 => ram_block3a60.ENA0
+clocken0 => ram_block3a61.ENA0
+clocken0 => ram_block3a62.ENA0
+clocken0 => ram_block3a63.ENA0
+clocken0 => ram_block3a64.ENA0
+clocken0 => ram_block3a65.ENA0
+clocken0 => ram_block3a66.ENA0
+clocken0 => ram_block3a67.ENA0
+clocken0 => ram_block3a68.ENA0
+clocken0 => ram_block3a69.ENA0
+clocken0 => ram_block3a70.ENA0
+clocken0 => ram_block3a71.ENA0
+clocken0 => ram_block3a72.ENA0
+clocken0 => ram_block3a73.ENA0
+clocken0 => ram_block3a74.ENA0
+clocken0 => ram_block3a75.ENA0
+clocken0 => ram_block3a76.ENA0
+clocken0 => ram_block3a77.ENA0
+clocken0 => ram_block3a78.ENA0
+clocken0 => ram_block3a79.ENA0
+clocken0 => ram_block3a80.ENA0
+clocken0 => ram_block3a81.ENA0
+clocken0 => ram_block3a82.ENA0
+clocken0 => ram_block3a83.ENA0
+clocken0 => ram_block3a84.ENA0
+clocken0 => ram_block3a85.ENA0
+clocken0 => ram_block3a86.ENA0
+clocken0 => ram_block3a87.ENA0
+clocken0 => ram_block3a88.ENA0
+clocken0 => ram_block3a89.ENA0
+clocken0 => ram_block3a90.ENA0
+clocken0 => ram_block3a91.ENA0
+clocken0 => ram_block3a92.ENA0
+clocken0 => ram_block3a93.ENA0
+clocken0 => ram_block3a94.ENA0
+clocken0 => ram_block3a95.ENA0
+clocken0 => ram_block3a96.ENA0
+clocken0 => ram_block3a97.ENA0
+clocken0 => ram_block3a98.ENA0
+clocken0 => ram_block3a99.ENA0
+clocken0 => ram_block3a100.ENA0
+clocken0 => ram_block3a101.ENA0
+clocken0 => ram_block3a102.ENA0
+clocken0 => ram_block3a103.ENA0
+clocken0 => ram_block3a104.ENA0
+clocken0 => ram_block3a105.ENA0
+clocken0 => ram_block3a106.ENA0
+clocken0 => ram_block3a107.ENA0
+clocken0 => ram_block3a108.ENA0
+clocken0 => ram_block3a109.ENA0
+clocken0 => ram_block3a110.ENA0
+clocken0 => ram_block3a111.ENA0
+clocken0 => ram_block3a112.ENA0
+clocken0 => ram_block3a113.ENA0
+clocken0 => ram_block3a114.ENA0
+clocken0 => ram_block3a115.ENA0
+clocken0 => ram_block3a116.ENA0
+clocken0 => ram_block3a117.ENA0
+clocken0 => ram_block3a118.ENA0
+clocken0 => ram_block3a119.ENA0
+clocken0 => ram_block3a120.ENA0
+clocken0 => ram_block3a121.ENA0
+clocken0 => ram_block3a122.ENA0
+clocken0 => ram_block3a123.ENA0
+clocken0 => ram_block3a124.ENA0
+clocken0 => ram_block3a125.ENA0
+clocken0 => ram_block3a126.ENA0
+clocken0 => ram_block3a127.ENA0
+clocken0 => ram_block3a128.ENA0
+clocken0 => ram_block3a129.ENA0
+clocken0 => ram_block3a130.ENA0
+clocken0 => ram_block3a131.ENA0
+clocken0 => ram_block3a132.ENA0
+clocken0 => ram_block3a133.ENA0
+clocken0 => ram_block3a134.ENA0
+clocken0 => ram_block3a135.ENA0
+clocken0 => ram_block3a136.ENA0
+clocken0 => ram_block3a137.ENA0
+clocken0 => ram_block3a138.ENA0
+clocken0 => ram_block3a139.ENA0
+clocken0 => ram_block3a140.ENA0
+clocken0 => ram_block3a141.ENA0
+clocken0 => ram_block3a142.ENA0
+clocken0 => ram_block3a143.ENA0
+clocken0 => ram_block3a144.ENA0
+clocken0 => ram_block3a145.ENA0
+clocken0 => ram_block3a146.ENA0
+clocken0 => ram_block3a147.ENA0
+clocken0 => ram_block3a148.ENA0
+clocken0 => ram_block3a149.ENA0
+data_a[0] => ram_block3a0.PORTADATAIN
+data_a[1] => ram_block3a1.PORTADATAIN
+data_a[2] => ram_block3a2.PORTADATAIN
+data_a[3] => ram_block3a3.PORTADATAIN
+data_a[4] => ram_block3a4.PORTADATAIN
+data_a[5] => ram_block3a5.PORTADATAIN
+data_a[6] => ram_block3a6.PORTADATAIN
+data_a[7] => ram_block3a7.PORTADATAIN
+data_a[8] => ram_block3a8.PORTADATAIN
+data_a[9] => ram_block3a9.PORTADATAIN
+data_a[10] => ram_block3a10.PORTADATAIN
+data_a[11] => ram_block3a11.PORTADATAIN
+data_a[12] => ram_block3a12.PORTADATAIN
+data_a[13] => ram_block3a13.PORTADATAIN
+data_a[14] => ram_block3a14.PORTADATAIN
+data_a[15] => ram_block3a15.PORTADATAIN
+data_a[16] => ram_block3a16.PORTADATAIN
+data_a[17] => ram_block3a17.PORTADATAIN
+data_a[18] => ram_block3a18.PORTADATAIN
+data_a[19] => ram_block3a19.PORTADATAIN
+data_a[20] => ram_block3a20.PORTADATAIN
+data_a[21] => ram_block3a21.PORTADATAIN
+data_a[22] => ram_block3a22.PORTADATAIN
+data_a[23] => ram_block3a23.PORTADATAIN
+data_a[24] => ram_block3a24.PORTADATAIN
+data_a[25] => ram_block3a25.PORTADATAIN
+data_a[26] => ram_block3a26.PORTADATAIN
+data_a[27] => ram_block3a27.PORTADATAIN
+data_a[28] => ram_block3a28.PORTADATAIN
+data_a[29] => ram_block3a29.PORTADATAIN
+data_a[30] => ram_block3a30.PORTADATAIN
+data_a[31] => ram_block3a31.PORTADATAIN
+data_a[32] => ram_block3a32.PORTADATAIN
+data_a[33] => ram_block3a33.PORTADATAIN
+data_a[34] => ram_block3a34.PORTADATAIN
+data_a[35] => ram_block3a35.PORTADATAIN
+data_a[36] => ram_block3a36.PORTADATAIN
+data_a[37] => ram_block3a37.PORTADATAIN
+data_a[38] => ram_block3a38.PORTADATAIN
+data_a[39] => ram_block3a39.PORTADATAIN
+data_a[40] => ram_block3a40.PORTADATAIN
+data_a[41] => ram_block3a41.PORTADATAIN
+data_a[42] => ram_block3a42.PORTADATAIN
+data_a[43] => ram_block3a43.PORTADATAIN
+data_a[44] => ram_block3a44.PORTADATAIN
+data_a[45] => ram_block3a45.PORTADATAIN
+data_a[46] => ram_block3a46.PORTADATAIN
+data_a[47] => ram_block3a47.PORTADATAIN
+data_a[48] => ram_block3a48.PORTADATAIN
+data_a[49] => ram_block3a49.PORTADATAIN
+data_a[50] => ram_block3a50.PORTADATAIN
+data_a[51] => ram_block3a51.PORTADATAIN
+data_a[52] => ram_block3a52.PORTADATAIN
+data_a[53] => ram_block3a53.PORTADATAIN
+data_a[54] => ram_block3a54.PORTADATAIN
+data_a[55] => ram_block3a55.PORTADATAIN
+data_a[56] => ram_block3a56.PORTADATAIN
+data_a[57] => ram_block3a57.PORTADATAIN
+data_a[58] => ram_block3a58.PORTADATAIN
+data_a[59] => ram_block3a59.PORTADATAIN
+data_a[60] => ram_block3a60.PORTADATAIN
+data_a[61] => ram_block3a61.PORTADATAIN
+data_a[62] => ram_block3a62.PORTADATAIN
+data_a[63] => ram_block3a63.PORTADATAIN
+data_a[64] => ram_block3a64.PORTADATAIN
+data_a[65] => ram_block3a65.PORTADATAIN
+data_a[66] => ram_block3a66.PORTADATAIN
+data_a[67] => ram_block3a67.PORTADATAIN
+data_a[68] => ram_block3a68.PORTADATAIN
+data_a[69] => ram_block3a69.PORTADATAIN
+data_a[70] => ram_block3a70.PORTADATAIN
+data_a[71] => ram_block3a71.PORTADATAIN
+data_a[72] => ram_block3a72.PORTADATAIN
+data_a[73] => ram_block3a73.PORTADATAIN
+data_a[74] => ram_block3a74.PORTADATAIN
+data_a[75] => ram_block3a75.PORTADATAIN
+data_a[76] => ram_block3a76.PORTADATAIN
+data_a[77] => ram_block3a77.PORTADATAIN
+data_a[78] => ram_block3a78.PORTADATAIN
+data_a[79] => ram_block3a79.PORTADATAIN
+data_a[80] => ram_block3a80.PORTADATAIN
+data_a[81] => ram_block3a81.PORTADATAIN
+data_a[82] => ram_block3a82.PORTADATAIN
+data_a[83] => ram_block3a83.PORTADATAIN
+data_a[84] => ram_block3a84.PORTADATAIN
+data_a[85] => ram_block3a85.PORTADATAIN
+data_a[86] => ram_block3a86.PORTADATAIN
+data_a[87] => ram_block3a87.PORTADATAIN
+data_a[88] => ram_block3a88.PORTADATAIN
+data_a[89] => ram_block3a89.PORTADATAIN
+data_a[90] => ram_block3a90.PORTADATAIN
+data_a[91] => ram_block3a91.PORTADATAIN
+data_a[92] => ram_block3a92.PORTADATAIN
+data_a[93] => ram_block3a93.PORTADATAIN
+data_a[94] => ram_block3a94.PORTADATAIN
+data_a[95] => ram_block3a95.PORTADATAIN
+data_a[96] => ram_block3a96.PORTADATAIN
+data_a[97] => ram_block3a97.PORTADATAIN
+data_a[98] => ram_block3a98.PORTADATAIN
+data_a[99] => ram_block3a99.PORTADATAIN
+data_a[100] => ram_block3a100.PORTADATAIN
+data_a[101] => ram_block3a101.PORTADATAIN
+data_a[102] => ram_block3a102.PORTADATAIN
+data_a[103] => ram_block3a103.PORTADATAIN
+data_a[104] => ram_block3a104.PORTADATAIN
+data_a[105] => ram_block3a105.PORTADATAIN
+data_a[106] => ram_block3a106.PORTADATAIN
+data_a[107] => ram_block3a107.PORTADATAIN
+data_a[108] => ram_block3a108.PORTADATAIN
+data_a[109] => ram_block3a109.PORTADATAIN
+data_a[110] => ram_block3a110.PORTADATAIN
+data_a[111] => ram_block3a111.PORTADATAIN
+data_a[112] => ram_block3a112.PORTADATAIN
+data_a[113] => ram_block3a113.PORTADATAIN
+data_a[114] => ram_block3a114.PORTADATAIN
+data_a[115] => ram_block3a115.PORTADATAIN
+data_a[116] => ram_block3a116.PORTADATAIN
+data_a[117] => ram_block3a117.PORTADATAIN
+data_a[118] => ram_block3a118.PORTADATAIN
+data_a[119] => ram_block3a119.PORTADATAIN
+data_a[120] => ram_block3a120.PORTADATAIN
+data_a[121] => ram_block3a121.PORTADATAIN
+data_a[122] => ram_block3a122.PORTADATAIN
+data_a[123] => ram_block3a123.PORTADATAIN
+data_a[124] => ram_block3a124.PORTADATAIN
+data_a[125] => ram_block3a125.PORTADATAIN
+data_a[126] => ram_block3a126.PORTADATAIN
+data_a[127] => ram_block3a127.PORTADATAIN
+data_a[128] => ram_block3a128.PORTADATAIN
+data_a[129] => ram_block3a129.PORTADATAIN
+data_a[130] => ram_block3a130.PORTADATAIN
+data_a[131] => ram_block3a131.PORTADATAIN
+data_a[132] => ram_block3a132.PORTADATAIN
+data_a[133] => ram_block3a133.PORTADATAIN
+data_a[134] => ram_block3a134.PORTADATAIN
+data_a[135] => ram_block3a135.PORTADATAIN
+data_a[136] => ram_block3a136.PORTADATAIN
+data_a[137] => ram_block3a137.PORTADATAIN
+data_a[138] => ram_block3a138.PORTADATAIN
+data_a[139] => ram_block3a139.PORTADATAIN
+data_a[140] => ram_block3a140.PORTADATAIN
+data_a[141] => ram_block3a141.PORTADATAIN
+data_a[142] => ram_block3a142.PORTADATAIN
+data_a[143] => ram_block3a143.PORTADATAIN
+data_a[144] => ram_block3a144.PORTADATAIN
+data_a[145] => ram_block3a145.PORTADATAIN
+data_a[146] => ram_block3a146.PORTADATAIN
+data_a[147] => ram_block3a147.PORTADATAIN
+data_a[148] => ram_block3a148.PORTADATAIN
+data_a[149] => ram_block3a149.PORTADATAIN
+q_b[0] <= ram_block3a0.PORTBDATAOUT
+q_b[1] <= ram_block3a1.PORTBDATAOUT
+q_b[2] <= ram_block3a2.PORTBDATAOUT
+q_b[3] <= ram_block3a3.PORTBDATAOUT
+q_b[4] <= ram_block3a4.PORTBDATAOUT
+q_b[5] <= ram_block3a5.PORTBDATAOUT
+q_b[6] <= ram_block3a6.PORTBDATAOUT
+q_b[7] <= ram_block3a7.PORTBDATAOUT
+q_b[8] <= ram_block3a8.PORTBDATAOUT
+q_b[9] <= ram_block3a9.PORTBDATAOUT
+q_b[10] <= ram_block3a10.PORTBDATAOUT
+q_b[11] <= ram_block3a11.PORTBDATAOUT
+q_b[12] <= ram_block3a12.PORTBDATAOUT
+q_b[13] <= ram_block3a13.PORTBDATAOUT
+q_b[14] <= ram_block3a14.PORTBDATAOUT
+q_b[15] <= ram_block3a15.PORTBDATAOUT
+q_b[16] <= ram_block3a16.PORTBDATAOUT
+q_b[17] <= ram_block3a17.PORTBDATAOUT
+q_b[18] <= ram_block3a18.PORTBDATAOUT
+q_b[19] <= ram_block3a19.PORTBDATAOUT
+q_b[20] <= ram_block3a20.PORTBDATAOUT
+q_b[21] <= ram_block3a21.PORTBDATAOUT
+q_b[22] <= ram_block3a22.PORTBDATAOUT
+q_b[23] <= ram_block3a23.PORTBDATAOUT
+q_b[24] <= ram_block3a24.PORTBDATAOUT
+q_b[25] <= ram_block3a25.PORTBDATAOUT
+q_b[26] <= ram_block3a26.PORTBDATAOUT
+q_b[27] <= ram_block3a27.PORTBDATAOUT
+q_b[28] <= ram_block3a28.PORTBDATAOUT
+q_b[29] <= ram_block3a29.PORTBDATAOUT
+q_b[30] <= ram_block3a30.PORTBDATAOUT
+q_b[31] <= ram_block3a31.PORTBDATAOUT
+q_b[32] <= ram_block3a32.PORTBDATAOUT
+q_b[33] <= ram_block3a33.PORTBDATAOUT
+q_b[34] <= ram_block3a34.PORTBDATAOUT
+q_b[35] <= ram_block3a35.PORTBDATAOUT
+q_b[36] <= ram_block3a36.PORTBDATAOUT
+q_b[37] <= ram_block3a37.PORTBDATAOUT
+q_b[38] <= ram_block3a38.PORTBDATAOUT
+q_b[39] <= ram_block3a39.PORTBDATAOUT
+q_b[40] <= ram_block3a40.PORTBDATAOUT
+q_b[41] <= ram_block3a41.PORTBDATAOUT
+q_b[42] <= ram_block3a42.PORTBDATAOUT
+q_b[43] <= ram_block3a43.PORTBDATAOUT
+q_b[44] <= ram_block3a44.PORTBDATAOUT
+q_b[45] <= ram_block3a45.PORTBDATAOUT
+q_b[46] <= ram_block3a46.PORTBDATAOUT
+q_b[47] <= ram_block3a47.PORTBDATAOUT
+q_b[48] <= ram_block3a48.PORTBDATAOUT
+q_b[49] <= ram_block3a49.PORTBDATAOUT
+q_b[50] <= ram_block3a50.PORTBDATAOUT
+q_b[51] <= ram_block3a51.PORTBDATAOUT
+q_b[52] <= ram_block3a52.PORTBDATAOUT
+q_b[53] <= ram_block3a53.PORTBDATAOUT
+q_b[54] <= ram_block3a54.PORTBDATAOUT
+q_b[55] <= ram_block3a55.PORTBDATAOUT
+q_b[56] <= ram_block3a56.PORTBDATAOUT
+q_b[57] <= ram_block3a57.PORTBDATAOUT
+q_b[58] <= ram_block3a58.PORTBDATAOUT
+q_b[59] <= ram_block3a59.PORTBDATAOUT
+q_b[60] <= ram_block3a60.PORTBDATAOUT
+q_b[61] <= ram_block3a61.PORTBDATAOUT
+q_b[62] <= ram_block3a62.PORTBDATAOUT
+q_b[63] <= ram_block3a63.PORTBDATAOUT
+q_b[64] <= ram_block3a64.PORTBDATAOUT
+q_b[65] <= ram_block3a65.PORTBDATAOUT
+q_b[66] <= ram_block3a66.PORTBDATAOUT
+q_b[67] <= ram_block3a67.PORTBDATAOUT
+q_b[68] <= ram_block3a68.PORTBDATAOUT
+q_b[69] <= ram_block3a69.PORTBDATAOUT
+q_b[70] <= ram_block3a70.PORTBDATAOUT
+q_b[71] <= ram_block3a71.PORTBDATAOUT
+q_b[72] <= ram_block3a72.PORTBDATAOUT
+q_b[73] <= ram_block3a73.PORTBDATAOUT
+q_b[74] <= ram_block3a74.PORTBDATAOUT
+q_b[75] <= ram_block3a75.PORTBDATAOUT
+q_b[76] <= ram_block3a76.PORTBDATAOUT
+q_b[77] <= ram_block3a77.PORTBDATAOUT
+q_b[78] <= ram_block3a78.PORTBDATAOUT
+q_b[79] <= ram_block3a79.PORTBDATAOUT
+q_b[80] <= ram_block3a80.PORTBDATAOUT
+q_b[81] <= ram_block3a81.PORTBDATAOUT
+q_b[82] <= ram_block3a82.PORTBDATAOUT
+q_b[83] <= ram_block3a83.PORTBDATAOUT
+q_b[84] <= ram_block3a84.PORTBDATAOUT
+q_b[85] <= ram_block3a85.PORTBDATAOUT
+q_b[86] <= ram_block3a86.PORTBDATAOUT
+q_b[87] <= ram_block3a87.PORTBDATAOUT
+q_b[88] <= ram_block3a88.PORTBDATAOUT
+q_b[89] <= ram_block3a89.PORTBDATAOUT
+q_b[90] <= ram_block3a90.PORTBDATAOUT
+q_b[91] <= ram_block3a91.PORTBDATAOUT
+q_b[92] <= ram_block3a92.PORTBDATAOUT
+q_b[93] <= ram_block3a93.PORTBDATAOUT
+q_b[94] <= ram_block3a94.PORTBDATAOUT
+q_b[95] <= ram_block3a95.PORTBDATAOUT
+q_b[96] <= ram_block3a96.PORTBDATAOUT
+q_b[97] <= ram_block3a97.PORTBDATAOUT
+q_b[98] <= ram_block3a98.PORTBDATAOUT
+q_b[99] <= ram_block3a99.PORTBDATAOUT
+q_b[100] <= ram_block3a100.PORTBDATAOUT
+q_b[101] <= ram_block3a101.PORTBDATAOUT
+q_b[102] <= ram_block3a102.PORTBDATAOUT
+q_b[103] <= ram_block3a103.PORTBDATAOUT
+q_b[104] <= ram_block3a104.PORTBDATAOUT
+q_b[105] <= ram_block3a105.PORTBDATAOUT
+q_b[106] <= ram_block3a106.PORTBDATAOUT
+q_b[107] <= ram_block3a107.PORTBDATAOUT
+q_b[108] <= ram_block3a108.PORTBDATAOUT
+q_b[109] <= ram_block3a109.PORTBDATAOUT
+q_b[110] <= ram_block3a110.PORTBDATAOUT
+q_b[111] <= ram_block3a111.PORTBDATAOUT
+q_b[112] <= ram_block3a112.PORTBDATAOUT
+q_b[113] <= ram_block3a113.PORTBDATAOUT
+q_b[114] <= ram_block3a114.PORTBDATAOUT
+q_b[115] <= ram_block3a115.PORTBDATAOUT
+q_b[116] <= ram_block3a116.PORTBDATAOUT
+q_b[117] <= ram_block3a117.PORTBDATAOUT
+q_b[118] <= ram_block3a118.PORTBDATAOUT
+q_b[119] <= ram_block3a119.PORTBDATAOUT
+q_b[120] <= ram_block3a120.PORTBDATAOUT
+q_b[121] <= ram_block3a121.PORTBDATAOUT
+q_b[122] <= ram_block3a122.PORTBDATAOUT
+q_b[123] <= ram_block3a123.PORTBDATAOUT
+q_b[124] <= ram_block3a124.PORTBDATAOUT
+q_b[125] <= ram_block3a125.PORTBDATAOUT
+q_b[126] <= ram_block3a126.PORTBDATAOUT
+q_b[127] <= ram_block3a127.PORTBDATAOUT
+q_b[128] <= ram_block3a128.PORTBDATAOUT
+q_b[129] <= ram_block3a129.PORTBDATAOUT
+q_b[130] <= ram_block3a130.PORTBDATAOUT
+q_b[131] <= ram_block3a131.PORTBDATAOUT
+q_b[132] <= ram_block3a132.PORTBDATAOUT
+q_b[133] <= ram_block3a133.PORTBDATAOUT
+q_b[134] <= ram_block3a134.PORTBDATAOUT
+q_b[135] <= ram_block3a135.PORTBDATAOUT
+q_b[136] <= ram_block3a136.PORTBDATAOUT
+q_b[137] <= ram_block3a137.PORTBDATAOUT
+q_b[138] <= ram_block3a138.PORTBDATAOUT
+q_b[139] <= ram_block3a139.PORTBDATAOUT
+q_b[140] <= ram_block3a140.PORTBDATAOUT
+q_b[141] <= ram_block3a141.PORTBDATAOUT
+q_b[142] <= ram_block3a142.PORTBDATAOUT
+q_b[143] <= ram_block3a143.PORTBDATAOUT
+q_b[144] <= ram_block3a144.PORTBDATAOUT
+q_b[145] <= ram_block3a145.PORTBDATAOUT
+q_b[146] <= ram_block3a146.PORTBDATAOUT
+q_b[147] <= ram_block3a147.PORTBDATAOUT
+q_b[148] <= ram_block3a148.PORTBDATAOUT
+q_b[149] <= ram_block3a149.PORTBDATAOUT
+wren_a => ram_block3a0.PORTAWE
+wren_a => ram_block3a1.PORTAWE
+wren_a => ram_block3a2.PORTAWE
+wren_a => ram_block3a3.PORTAWE
+wren_a => ram_block3a4.PORTAWE
+wren_a => ram_block3a5.PORTAWE
+wren_a => ram_block3a6.PORTAWE
+wren_a => ram_block3a7.PORTAWE
+wren_a => ram_block3a8.PORTAWE
+wren_a => ram_block3a9.PORTAWE
+wren_a => ram_block3a10.PORTAWE
+wren_a => ram_block3a11.PORTAWE
+wren_a => ram_block3a12.PORTAWE
+wren_a => ram_block3a13.PORTAWE
+wren_a => ram_block3a14.PORTAWE
+wren_a => ram_block3a15.PORTAWE
+wren_a => ram_block3a16.PORTAWE
+wren_a => ram_block3a17.PORTAWE
+wren_a => ram_block3a18.PORTAWE
+wren_a => ram_block3a19.PORTAWE
+wren_a => ram_block3a20.PORTAWE
+wren_a => ram_block3a21.PORTAWE
+wren_a => ram_block3a22.PORTAWE
+wren_a => ram_block3a23.PORTAWE
+wren_a => ram_block3a24.PORTAWE
+wren_a => ram_block3a25.PORTAWE
+wren_a => ram_block3a26.PORTAWE
+wren_a => ram_block3a27.PORTAWE
+wren_a => ram_block3a28.PORTAWE
+wren_a => ram_block3a29.PORTAWE
+wren_a => ram_block3a30.PORTAWE
+wren_a => ram_block3a31.PORTAWE
+wren_a => ram_block3a32.PORTAWE
+wren_a => ram_block3a33.PORTAWE
+wren_a => ram_block3a34.PORTAWE
+wren_a => ram_block3a35.PORTAWE
+wren_a => ram_block3a36.PORTAWE
+wren_a => ram_block3a37.PORTAWE
+wren_a => ram_block3a38.PORTAWE
+wren_a => ram_block3a39.PORTAWE
+wren_a => ram_block3a40.PORTAWE
+wren_a => ram_block3a41.PORTAWE
+wren_a => ram_block3a42.PORTAWE
+wren_a => ram_block3a43.PORTAWE
+wren_a => ram_block3a44.PORTAWE
+wren_a => ram_block3a45.PORTAWE
+wren_a => ram_block3a46.PORTAWE
+wren_a => ram_block3a47.PORTAWE
+wren_a => ram_block3a48.PORTAWE
+wren_a => ram_block3a49.PORTAWE
+wren_a => ram_block3a50.PORTAWE
+wren_a => ram_block3a51.PORTAWE
+wren_a => ram_block3a52.PORTAWE
+wren_a => ram_block3a53.PORTAWE
+wren_a => ram_block3a54.PORTAWE
+wren_a => ram_block3a55.PORTAWE
+wren_a => ram_block3a56.PORTAWE
+wren_a => ram_block3a57.PORTAWE
+wren_a => ram_block3a58.PORTAWE
+wren_a => ram_block3a59.PORTAWE
+wren_a => ram_block3a60.PORTAWE
+wren_a => ram_block3a61.PORTAWE
+wren_a => ram_block3a62.PORTAWE
+wren_a => ram_block3a63.PORTAWE
+wren_a => ram_block3a64.PORTAWE
+wren_a => ram_block3a65.PORTAWE
+wren_a => ram_block3a66.PORTAWE
+wren_a => ram_block3a67.PORTAWE
+wren_a => ram_block3a68.PORTAWE
+wren_a => ram_block3a69.PORTAWE
+wren_a => ram_block3a70.PORTAWE
+wren_a => ram_block3a71.PORTAWE
+wren_a => ram_block3a72.PORTAWE
+wren_a => ram_block3a73.PORTAWE
+wren_a => ram_block3a74.PORTAWE
+wren_a => ram_block3a75.PORTAWE
+wren_a => ram_block3a76.PORTAWE
+wren_a => ram_block3a77.PORTAWE
+wren_a => ram_block3a78.PORTAWE
+wren_a => ram_block3a79.PORTAWE
+wren_a => ram_block3a80.PORTAWE
+wren_a => ram_block3a81.PORTAWE
+wren_a => ram_block3a82.PORTAWE
+wren_a => ram_block3a83.PORTAWE
+wren_a => ram_block3a84.PORTAWE
+wren_a => ram_block3a85.PORTAWE
+wren_a => ram_block3a86.PORTAWE
+wren_a => ram_block3a87.PORTAWE
+wren_a => ram_block3a88.PORTAWE
+wren_a => ram_block3a89.PORTAWE
+wren_a => ram_block3a90.PORTAWE
+wren_a => ram_block3a91.PORTAWE
+wren_a => ram_block3a92.PORTAWE
+wren_a => ram_block3a93.PORTAWE
+wren_a => ram_block3a94.PORTAWE
+wren_a => ram_block3a95.PORTAWE
+wren_a => ram_block3a96.PORTAWE
+wren_a => ram_block3a97.PORTAWE
+wren_a => ram_block3a98.PORTAWE
+wren_a => ram_block3a99.PORTAWE
+wren_a => ram_block3a100.PORTAWE
+wren_a => ram_block3a101.PORTAWE
+wren_a => ram_block3a102.PORTAWE
+wren_a => ram_block3a103.PORTAWE
+wren_a => ram_block3a104.PORTAWE
+wren_a => ram_block3a105.PORTAWE
+wren_a => ram_block3a106.PORTAWE
+wren_a => ram_block3a107.PORTAWE
+wren_a => ram_block3a108.PORTAWE
+wren_a => ram_block3a109.PORTAWE
+wren_a => ram_block3a110.PORTAWE
+wren_a => ram_block3a111.PORTAWE
+wren_a => ram_block3a112.PORTAWE
+wren_a => ram_block3a113.PORTAWE
+wren_a => ram_block3a114.PORTAWE
+wren_a => ram_block3a115.PORTAWE
+wren_a => ram_block3a116.PORTAWE
+wren_a => ram_block3a117.PORTAWE
+wren_a => ram_block3a118.PORTAWE
+wren_a => ram_block3a119.PORTAWE
+wren_a => ram_block3a120.PORTAWE
+wren_a => ram_block3a121.PORTAWE
+wren_a => ram_block3a122.PORTAWE
+wren_a => ram_block3a123.PORTAWE
+wren_a => ram_block3a124.PORTAWE
+wren_a => ram_block3a125.PORTAWE
+wren_a => ram_block3a126.PORTAWE
+wren_a => ram_block3a127.PORTAWE
+wren_a => ram_block3a128.PORTAWE
+wren_a => ram_block3a129.PORTAWE
+wren_a => ram_block3a130.PORTAWE
+wren_a => ram_block3a131.PORTAWE
+wren_a => ram_block3a132.PORTAWE
+wren_a => ram_block3a133.PORTAWE
+wren_a => ram_block3a134.PORTAWE
+wren_a => ram_block3a135.PORTAWE
+wren_a => ram_block3a136.PORTAWE
+wren_a => ram_block3a137.PORTAWE
+wren_a => ram_block3a138.PORTAWE
+wren_a => ram_block3a139.PORTAWE
+wren_a => ram_block3a140.PORTAWE
+wren_a => ram_block3a141.PORTAWE
+wren_a => ram_block3a142.PORTAWE
+wren_a => ram_block3a143.PORTAWE
+wren_a => ram_block3a144.PORTAWE
+wren_a => ram_block3a145.PORTAWE
+wren_a => ram_block3a146.PORTAWE
+wren_a => ram_block3a147.PORTAWE
+wren_a => ram_block3a148.PORTAWE
+wren_a => ram_block3a149.PORTAWE
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1
+clk_en => counter_reg_bit[9].IN0
+clock => counter_reg_bit[9].CLK
+clock => counter_reg_bit[8].CLK
+clock => counter_reg_bit[7].CLK
+clock => counter_reg_bit[6].CLK
+clock => counter_reg_bit[5].CLK
+clock => counter_reg_bit[4].CLK
+clock => counter_reg_bit[3].CLK
+clock => counter_reg_bit[2].CLK
+clock => counter_reg_bit[1].CLK
+clock => counter_reg_bit[0].CLK
+q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE
+q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE
+q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE
+q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE
+q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE
+q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE
+q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE
+q[7] <= counter_reg_bit[7].DB_MAX_OUTPUT_PORT_TYPE
+q[8] <= counter_reg_bit[8].DB_MAX_OUTPUT_PORT_TYPE
+q[9] <= counter_reg_bit[9].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4
+aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
+dataa[0] => data_wire[2].IN0
+dataa[1] => data_wire[2].IN0
+dataa[2] => data_wire[3].IN0
+dataa[3] => data_wire[3].IN0
+dataa[4] => data_wire[4].IN0
+dataa[5] => data_wire[4].IN0
+dataa[6] => data_wire[5].IN0
+dataa[7] => data_wire[5].IN0
+dataa[8] => data_wire[6].IN0
+dataa[9] => data_wire[6].IN0
+datab[0] => data_wire[2].IN1
+datab[1] => data_wire[2].IN1
+datab[2] => data_wire[3].IN1
+datab[3] => data_wire[3].IN1
+datab[4] => data_wire[4].IN1
+datab[5] => data_wire[4].IN1
+datab[6] => data_wire[5].IN1
+datab[7] => data_wire[5].IN1
+datab[8] => data_wire[6].IN1
+datab[9] => data_wire[6].IN1
+
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hif b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hif
new file mode 100644
index 0000000..196f1e3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.hif
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ipinfo b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ipinfo
new file mode 100644
index 0000000..554cafa
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.ipinfo
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.html b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.html
new file mode 100644
index 0000000..114da62
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.html
@@ -0,0 +1,2018 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated|cntr1|cmpr4</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated|cntr1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated|altsyncram2</TD>
+<TD >173</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >150</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >fifo_inst2|auto_generated</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >150</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_blur_catapult_inst|mean_vga_core_inst</TD>
+<TD >93</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_blur_catapult_inst|vout_rsc_mgc_out_stdreg</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_blur_catapult_inst|vin_rsc_mgc_in_wire</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >90</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_blur_catapult_inst</TD>
+<TD >93</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >30</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|vga_mouse_square_core_inst</TD>
+<TD >81</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|video_out_rsc_mgc_out_stdreg</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|video_in_rsc_mgc_in_wire</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|cursor_size_rsc_mgc_in_wire</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|mouse_xy_rsc_mgc_in_wire</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst|vga_xy_rsc_mgc_in_wire</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >vga_mouse_catapult_inst</TD>
+<TD >81</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >30</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst10|LPM_MUX_component|auto_generated</TD>
+<TD >122</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst10</TD>
+<TD >122</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >30</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst6|U4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst6|U3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst6|U2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst6|U1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst6</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >47</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u8|u0</TD>
+<TD >35</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u8</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe13</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|fifo_ram</TD>
+<TD >40</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2|dcfifo_component|auto_generated</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >36</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo2</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >25</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|fifo_ram</TD>
+<TD >40</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1|dcfifo_component|auto_generated</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >36</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|read_fifo1</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >25</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe13</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|fifo_ram</TD>
+<TD >40</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2|dcfifo_component|auto_generated</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >36</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo2</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >25</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_bwp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_brp</TD>
+<TD >12</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|fifo_ram</TD>
+<TD >40</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >10</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1|dcfifo_component|auto_generated</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >36</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|write_fifo1</TD>
+<TD >21</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >25</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|data_path1</TD>
+<TD >20</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >18</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|command1</TD>
+<TD >35</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >23</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7|control1</TD>
+<TD >30</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >32</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u7</TD>
+<TD >267</TD>
+<TD >224</TD>
+<TD >1</TD>
+<TD >224</TD>
+<TD >54</TD>
+<TD >224</TD>
+<TD >224</TD>
+<TD >224</TD>
+<TD >16</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u6|altpll_component|auto_generated</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >5</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u6</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u7</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u6</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u5</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u4</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u3</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u2</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u1</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5|u0</TD>
+<TD >4</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >7</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u5</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >28</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated|cntr1|cmpr4</TD>
+<TD >22</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated|cntr1</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >11</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated|altsyncram2</TD>
+<TD >49</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >1</TD>
+<TD >24</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >1</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0|altshift_taps_component|auto_generated</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >36</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4|u0</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >24</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u4</TD>
+<TD >37</TD>
+<TD >0</TD>
+<TD >20</TD>
+<TD >0</TD>
+<TD >37</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u3</TD>
+<TD >18</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >77</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u2</TD>
+<TD >2</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >3</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|u1</TD>
+<TD >32</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >58</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >16</TD>
+<TD >39</TD>
+<TD >8</TD>
+<TD >39</TD>
+<TD >120</TD>
+<TD >39</TD>
+<TD >39</TD>
+<TD >39</TD>
+<TD >48</TD>
+<TD >0</TD>
+<TD >14</TD>
+<TD >0</TD>
+<TD >14</TD>
+</TR>
+</TABLE>
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.rdb
new file mode 100644
index 0000000..eafab9a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.txt
new file mode 100644
index 0000000..053ddb1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.lpc.txt
@@ -0,0 +1,131 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                                                                 ;
++-----------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                                                             ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; fifo_inst2|auto_generated|cntr1|cmpr4                                 ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fifo_inst2|auto_generated|cntr1                                       ; 2     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fifo_inst2|auto_generated|altsyncram2                                 ; 173   ; 1              ; 0            ; 1              ; 150    ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; fifo_inst2|auto_generated                                             ; 32    ; 0              ; 0            ; 0              ; 150    ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_blur_catapult_inst|mean_vga_core_inst                             ; 93    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_blur_catapult_inst|vout_rsc_mgc_out_stdreg                        ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_blur_catapult_inst|vin_rsc_mgc_in_wire                            ; 90    ; 0              ; 0            ; 0              ; 90     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_blur_catapult_inst                                                ; 93    ; 1              ; 0            ; 1              ; 30     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|vga_mouse_square_core_inst                    ; 81    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|video_out_rsc_mgc_out_stdreg                  ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|video_in_rsc_mgc_in_wire                      ; 30    ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|cursor_size_rsc_mgc_in_wire                   ; 8     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|mouse_xy_rsc_mgc_in_wire                      ; 20    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst|vga_xy_rsc_mgc_in_wire                        ; 20    ; 0              ; 0            ; 0              ; 20     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; vga_mouse_catapult_inst                                               ; 81    ; 3              ; 0            ; 3              ; 30     ; 3               ; 3             ; 3               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst10|LPM_MUX_component|auto_generated                               ; 122   ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst10                                                                ; 122   ; 0              ; 0            ; 0              ; 30     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U4                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U3                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U2                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6|U1                                                              ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst6                                                                 ; 3     ; 0              ; 0            ; 0              ; 47     ; 0               ; 0             ; 0               ; 2     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u8|u0                                                            ; 35    ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 1     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u8                                                               ; 5     ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 1     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp     ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe13  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|fifo_ram           ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2|dcfifo_component|auto_generated                    ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo2                                                    ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp     ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13  ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_bwp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_brp             ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|fifo_ram           ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p          ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin   ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1|dcfifo_component|auto_generated                    ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|read_fifo1                                                    ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp   ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe13 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|fifo_ram          ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2|dcfifo_component|auto_generated                   ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo2                                                   ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp    ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp   ; 20    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe13 ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp           ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_bwp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_brp            ; 12    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|fifo_ram          ; 40    ; 0              ; 0            ; 0              ; 16     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p         ; 3     ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin  ; 10    ; 0              ; 0            ; 0              ; 10     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1|dcfifo_component|auto_generated                   ; 21    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|write_fifo1                                                   ; 21    ; 0              ; 0            ; 0              ; 25     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|data_path1                                                    ; 20    ; 2              ; 0            ; 2              ; 18     ; 2               ; 2             ; 2               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|command1                                                      ; 35    ; 0              ; 2            ; 0              ; 23     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7|control1                                                      ; 30    ; 1              ; 0            ; 1              ; 32     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u7                                                               ; 267   ; 224            ; 1            ; 224            ; 54     ; 224             ; 224           ; 224             ; 16    ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u6|altpll_component|auto_generated                               ; 2     ; 0              ; 0            ; 0              ; 5      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u6                                                               ; 1     ; 0              ; 0            ; 0              ; 2      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u7                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u6                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u5                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u4                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u3                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u2                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u1                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5|u0                                                            ; 4     ; 0              ; 0            ; 0              ; 7      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u5                                                               ; 32    ; 0              ; 0            ; 0              ; 28     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated|cntr1|cmpr4         ; 22    ; 0              ; 0            ; 0              ; 1      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated|cntr1               ; 2     ; 0              ; 0            ; 0              ; 11     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated|altsyncram2         ; 49    ; 1              ; 0            ; 1              ; 24     ; 1               ; 1             ; 1               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0|altshift_taps_component|auto_generated                     ; 14    ; 0              ; 0            ; 0              ; 36     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4|u0                                                            ; 14    ; 0              ; 0            ; 0              ; 24     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u4                                                               ; 37    ; 0              ; 20           ; 0              ; 37     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u3                                                               ; 18    ; 0              ; 0            ; 0              ; 77     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u2                                                               ; 2     ; 0              ; 0            ; 0              ; 3      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|u1                                                               ; 32    ; 0              ; 0            ; 0              ; 58     ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst                                                                  ; 16    ; 39             ; 8            ; 39             ; 120    ; 39              ; 39            ; 39              ; 48    ; 0              ; 14           ; 0                ; 14                ;
++-----------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.ammdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.ammdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.bpm b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.bpm
new file mode 100644
index 0000000..2cb535e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.bpm
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.cdb
new file mode 100644
index 0000000..4f0ec60
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.hdb
new file mode 100644
index 0000000..88e66b3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.kpt
new file mode 100644
index 0000000..ecca6ad
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.qmsg
new file mode 100644
index 0000000..ee8eb1a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.qmsg
@@ -0,0 +1,286 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456854056900 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456854056902 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 17:40:56 2016 " "Processing started: Tue Mar 01 17:40:56 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456854056902 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456854056902 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M " "Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456854056902 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456854057135 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/blur3x3/rtl.v 2 2 " "Found 2 design units, including 2 entities, in source file catapult_ip/blur3x3/rtl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mean_vga_core " "Found entity 1: mean_vga_core" {  } { { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057173 ""} { "Info" "ISGN_ENTITY_NAME" "2 mean_vga " "Found entity 2: mean_vga" {  } { { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 393 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057173 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057173 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ps2.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ps2.v" { { "Info" "ISGN_ENTITY_NAME" "1 ps2 " "Found entity 1: ps2" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057175 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057175 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/command.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v" { { "Info" "ISGN_ENTITY_NAME" "1 command " "Found entity 1: command" {  } { { "Sdram_Control_4Port/command.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057178 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057178 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/control_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 control_interface " "Found entity 1: control_interface" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057181 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057181 ""}
+{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 sdr_data_path.v(68) " "Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Quartus II" 0 -1 1456854057183 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdr_data_path.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdr_data_path " "Found entity 1: sdr_data_path" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057184 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057184 ""}
+{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "Sdram_Control_4Port Sdram_Control_4Port.v(90) " "Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"Sdram_Control_4Port\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 90 0 0 } }  } 0 10238 "Verilog Module Declaration warning at %2!s!: ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854057186 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_control_4port.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_Control_4Port " "Found entity 1: Sdram_Control_4Port" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057187 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057187 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sdram_control_4port/sdram_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 Sdram_FIFO " "Found entity 1: Sdram_FIFO" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057189 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057189 ""}
+{ "Warning" "WSGN_FILE_IS_MISSING" "V/async_receiver.v " "Can't analyze file -- file V/async_receiver.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Quartus II" 0 -1 1456854057191 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/ccd_capture.v 1 1 " "Found 1 design units, including 1 entities, in source file v/ccd_capture.v" { { "Info" "ISGN_ENTITY_NAME" "1 CCD_Capture " "Found entity 1: CCD_Capture" {  } { { "V/CCD_Capture.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057192 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057192 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_ccd_config.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_CCD_Config " "Found entity 1: I2C_CCD_Config" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057194 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057194 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/i2c_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/i2c_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_Controller " "Found entity 1: I2C_Controller" {  } { { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057196 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057196 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/line_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file v/line_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Line_Buffer " "Found entity 1: Line_Buffer" {  } { { "V/Line_Buffer.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057198 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057198 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/raw2rgb.v 1 1 " "Found 1 design units, including 1 entities, in source file v/raw2rgb.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAW2RGB " "Found entity 1: RAW2RGB" {  } { { "V/RAW2RGB.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057200 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057200 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/reset_delay.v 1 1 " "Found 1 design units, including 1 entities, in source file v/reset_delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Found entity 1: Reset_Delay" {  } { { "V/Reset_Delay.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057202 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057202 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/sdram_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file v/sdram_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 sdram_pll " "Found entity 1: sdram_pll" {  } { { "V/sdram_pll.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057205 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057205 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Found entity 1: SEG7_LUT" {  } { { "V/SEG7_LUT.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057208 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057208 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/seg7_lut_8.v 1 1 " "Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_8 " "Found entity 1: SEG7_LUT_8" {  } { { "V/SEG7_LUT_8.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057209 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057209 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/vga_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file v/vga_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 VGA_Controller " "Found entity 1: VGA_Controller" {  } { { "V/VGA_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057211 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057211 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_d5m.v 1 1 " "Found 1 design units, including 1 entities, in source file de0_d5m.v" { { "Info" "ISGN_ENTITY_NAME" "1 DE0_D5M " "Found entity 1: DE0_D5M" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 44 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057213 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057213 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "v/top_de0_camera_mouse.bdf 1 1 " "Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TOP_DE0_CAMERA_MOUSE " "Found entity 1: TOP_DE0_CAMERA_MOUSE" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057216 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057216 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga_mux.vhd 2 1 " "Found 2 design units, including 1 entities, in source file vga_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga_mux-SYN " "Found design unit 1: vga_mux-SYN" {  } { { "vga_mux.vhd" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 55 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057624 ""} { "Info" "ISGN_ENTITY_NAME" "1 vga_mux " "Found entity 1: vga_mux" {  } { { "vga_mux.vhd" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057624 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057624 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport_v2001.v 7 7 " "Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "catapult_ip/mouse/rtl_mgc_ioport_v2001.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057627 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl_mgc_ioport.v 20 20 " "Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "catapult_ip/mouse/rtl_mgc_ioport.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057630 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catapult_ip/mouse/rtl.v 2 2 " "Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga_mouse_square_core " "Found entity 1: vga_mouse_square_core" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057633 ""} { "Info" "ISGN_ENTITY_NAME" "2 vga_mouse_square " "Found entity 2: vga_mouse_square" {  } { { "catapult_ip/mouse/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 110 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057633 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057633 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "TOP_DE0_CAMERA_MOUSE " "Elaborating entity \"TOP_DE0_CAMERA_MOUSE\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456854057669 ""}
+{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "No superset bus at connection" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 912 1008 1120 928 "MOUSE_X\[1..0\]" "" } { 928 1008 1120 944 "MOUSE_Y\[1..0\]" "" } { 928 1008 1008 944 "" "" } { 944 1008 1008 952 "" "" } } } }  } 0 275002 "No superset bus at connection" 0 0 "Quartus II" 0 -1 1456854057676 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DE0_D5M DE0_D5M:inst " "Elaborating entity \"DE0_D5M\" for hierarchy \"DE0_D5M:inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057685 ""}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_R DE0_D5M.v(118) " "Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port \"VGA_R\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 118 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1456854057685 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_R DE0_D5M.v(166) " "HDL warning at DE0_D5M.v(166): see declaration for object \"VGA_R\"" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 166 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854057686 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_G DE0_D5M.v(119) " "Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port \"VGA_G\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 119 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1456854057686 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_G DE0_D5M.v(167) " "HDL warning at DE0_D5M.v(167): see declaration for object \"VGA_G\"" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 167 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854057686 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Critical Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "VGA_B DE0_D5M.v(120) " "Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port \"VGA_B\" do not specify the same range for each dimension" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 120 0 0 } }  } 1 10169 "Verilog HDL warning at %2!s!: the port and data declarations for array port \"%1!s!\" do not specify the same range for each dimension" 0 0 "Quartus II" 0 -1 1456854057686 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_HDL_SEE_DECLARATION" "VGA_B DE0_D5M.v(168) " "HDL warning at DE0_D5M.v(168): see declaration for object \"VGA_B\"" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 168 0 0 } }  } 0 10359 "HDL warning at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854057686 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 10 DE0_D5M.v(197) " "Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057686 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 DE0_D5M.v(202) " "Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 202 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057687 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "GPIO_1_CLKOUT\[1\] DE0_D5M.v(128) " "Output port \"GPIO_1_CLKOUT\[1\]\" at DE0_D5M.v(128) has no driver" {  } { { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 128 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1456854057691 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGA_Controller DE0_D5M:inst\|VGA_Controller:u1 " "Elaborating entity \"VGA_Controller\" for hierarchy \"DE0_D5M:inst\|VGA_Controller:u1\"" {  } { { "DE0_D5M.v" "u1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 253 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057704 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(70) " "Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057705 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(73) " "Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057705 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 VGA_Controller.v(76) " "Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)" {  } { { "V/VGA_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057705 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(115) " "Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057706 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 VGA_Controller.v(146) " "Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)" {  } { { "V/VGA_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057706 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay DE0_D5M:inst\|Reset_Delay:u2 " "Elaborating entity \"Reset_Delay\" for hierarchy \"DE0_D5M:inst\|Reset_Delay:u2\"" {  } { { "DE0_D5M.v" "u2" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 262 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057713 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CCD_Capture DE0_D5M:inst\|CCD_Capture:u3 " "Elaborating entity \"CCD_Capture\" for hierarchy \"DE0_D5M:inst\|CCD_Capture:u3\"" {  } { { "DE0_D5M.v" "u3" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 277 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057720 ""}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ifval_fedge CCD_Capture.v(162) " "Verilog HDL or VHDL warning at CCD_Capture.v(162): object \"ifval_fedge\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 162 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1456854057721 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "y_cnt_d CCD_Capture.v(163) " "Verilog HDL or VHDL warning at CCD_Capture.v(163): object \"y_cnt_d\" assigned a value but never read" {  } { { "V/CCD_Capture.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 163 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1456854057721 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(123) " "Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057722 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 CCD_Capture.v(127) " "Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)" {  } { { "V/CCD_Capture.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057722 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CCD_Capture.v(183) " "Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)" {  } { { "V/CCD_Capture.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854057723 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAW2RGB DE0_D5M:inst\|RAW2RGB:u4 " "Elaborating entity \"RAW2RGB\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\"" {  } { { "DE0_D5M.v" "u4" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 290 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057733 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Line_Buffer DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0 " "Elaborating entity \"Line_Buffer\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\"" {  } { { "V/RAW2RGB.v" "u0" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v" 83 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057747 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborating entity \"altshift_taps\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "altshift_taps_component" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057882 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\"" {  } { { "V/Line_Buffer.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854057886 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component " "Instantiated megafunction \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altshift_taps " "Parameter \"lpm_type\" = \"altshift_taps\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057886 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_taps 2 " "Parameter \"number_of_taps\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057886 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "tap_distance 1280 " "Parameter \"tap_distance\" = \"1280\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057886 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 12 " "Parameter \"width\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057886 ""}  } { { "V/Line_Buffer.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v" 67 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456854057886 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_rnn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_rnn " "Found entity 1: shift_taps_rnn" {  } { { "db/shift_taps_rnn.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057934 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057934 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_rnn DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated " "Elaborating entity \"shift_taps_rnn\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057935 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_lp81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_lp81 " "Found entity 1: altsyncram_lp81" {  } { { "db/altsyncram_lp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854057992 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854057992 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_lp81 DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2 " "Elaborating entity \"altsyncram_lp81\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|altsyncram_lp81:altsyncram2\"" {  } { { "db/shift_taps_rnn.tdf" "altsyncram2" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854057993 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cuf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cuf " "Found entity 1: cntr_cuf" {  } { { "db/cntr_cuf.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058075 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058075 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cuf DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1 " "Elaborating entity \"cntr_cuf\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\"" {  } { { "db/shift_taps_rnn.tdf" "cntr1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058076 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_vgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_vgc " "Found entity 1: cmpr_vgc" {  } { { "db/cmpr_vgc.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058130 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058130 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_vgc DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4 " "Elaborating entity \"cmpr_vgc\" for hierarchy \"DE0_D5M:inst\|RAW2RGB:u4\|Line_Buffer:u0\|altshift_taps:altshift_taps_component\|shift_taps_rnn:auto_generated\|cntr_cuf:cntr1\|cmpr_vgc:cmpr4\"" {  } { { "db/cntr_cuf.tdf" "cmpr4" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf" 90 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058131 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_8 DE0_D5M:inst\|SEG7_LUT_8:u5 " "Elaborating entity \"SEG7_LUT_8\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\"" {  } { { "DE0_D5M.v" "u5" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 302 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058138 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0 " "Elaborating entity \"SEG7_LUT\" for hierarchy \"DE0_D5M:inst\|SEG7_LUT_8:u5\|SEG7_LUT:u0\"" {  } { { "V/SEG7_LUT_8.v" "u0" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v" 47 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058144 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdram_pll DE0_D5M:inst\|sdram_pll:u6 " "Elaborating entity \"sdram_pll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\"" {  } { { "DE0_D5M.v" "u6" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 308 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058157 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "altpll_component" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058227 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\"" {  } { { "V/sdram_pll.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component " "Instantiated megafunction \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 2 " "Parameter \"clk0_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 2 " "Parameter \"clk1_divide_by\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 5 " "Parameter \"clk1_multiply_by\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -2600 " "Parameter \"clk1_phase_shift\" = \"-2600\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone III " "Parameter \"intended_device_family\" = \"Cyclone III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058242 ""}  } { { "V/sdram_pll.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456854058242 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_9ee2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_9ee2 " "Found entity 1: altpll_9ee2" {  } { { "db/altpll_9ee2.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058298 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058298 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_9ee2 DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated " "Elaborating entity \"altpll_9ee2\" for hierarchy \"DE0_D5M:inst\|sdram_pll:u6\|altpll:altpll_component\|altpll_9ee2:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058299 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_Control_4Port DE0_D5M:inst\|Sdram_Control_4Port:u7 " "Elaborating entity \"Sdram_Control_4Port\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\"" {  } { { "DE0_D5M.v" "u7" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058310 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 Sdram_Control_4Port.v(385) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058314 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(431) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058315 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(432) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 432 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058315 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(433) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058315 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 Sdram_Control_4Port.v(434) " "Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058315 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058317 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rWR2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rWR2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058317 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD1_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD1_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058317 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "rRD2_MAX_ADDR Sdram_Control_4Port.v(423) " "Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable \"rRD2_MAX_ADDR\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058317 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058324 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058325 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058326 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rRD1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rRD1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058327 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058328 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR2_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR2_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[0\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[0\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[1\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[1\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[2\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[2\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[3\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[3\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[4\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[4\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[5\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[5\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[6\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[6\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[7\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[7\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[8\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[8\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[9\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[9\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[10\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[10\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[11\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[11\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058329 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[12\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[12\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[13\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[13\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[14\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[14\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[15\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[15\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[16\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[16\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[17\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[17\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[18\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[18\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[19\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[19\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[20\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[20\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[21\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[21\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "rWR1_MAX_ADDR\[22\] Sdram_Control_4Port.v(423) " "Inferred latch for \"rWR1_MAX_ADDR\[22\]\" at Sdram_Control_4Port.v(423)" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 423 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1456854058330 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_interface DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1 " "Elaborating entity \"control_interface\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|control_interface:control1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "control1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 237 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058358 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(162) " "Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058359 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(167) " "Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058359 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 control_interface.v(192) " "Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)" {  } { { "Sdram_Control_4Port/control_interface.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058360 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "command DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1 " "Elaborating entity \"command\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|command:command1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "command1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 263 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058369 ""}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe_shift command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe_shift\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058372 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe1 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe1\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058372 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "oe2 command.v(275) " "Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable \"oe2\", which holds its previous value in one or more paths through the always construct" {  } { { "Sdram_Control_4Port/command.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v" 275 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1456854058372 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sdr_data_path DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1 " "Elaborating entity \"sdr_data_path\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|sdr_data_path:data_path1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "data_path1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 272 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058382 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 sdr_data_path.v(68) " "Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)" {  } { { "Sdram_Control_4Port/sdr_data_path.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854058383 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Sdram_FIFO DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1 " "Elaborating entity \"Sdram_FIFO\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\"" {  } { { "Sdram_Control_4Port/Sdram_Control_4Port.v" "write_fifo1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 283 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058390 ""}
+{ "Warning" "WCBX_DCFIFO_CBX_DCFIFO_NO_SYNCHRO_REGISTERS" "" "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 272007 "Warning message" 0 0 "Quartus II" 0 -1 1456854058524 ""}
+{ "Warning" "WCBX_ALTSYNCRAM_ALTSYNCRAM_MRAM_UNAVAILABLE" "" "Device family Cyclone III does not have M4K blocks -- using available memory blocks" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 272007 "Warning message" 0 0 "Quartus II" 0 -1 1456854058524 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborating entity \"dcfifo\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "dcfifo_component" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058527 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Elaborated megafunction instantiation \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\"" {  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component " "Instantiated megafunction \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clocks_are_synchronized FALSE " "Parameter \"clocks_are_synchronized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=M4K " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=M4K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 512 " "Parameter \"lpm_numwords\" = \"512\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type dcfifo " "Parameter \"lpm_type\" = \"dcfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Parameter \"lpm_width\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 9 " "Parameter \"lpm_widthu\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking ON " "Parameter \"overflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking ON " "Parameter \"underflow_checking\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058534 ""}  } { { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456854058534 ""}
+{ "Warning" "WTDFX_ASSERTION" "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 " "Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 161 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1456854058581 ""}
+{ "Warning" "WTDFX_ASSERTION" "Device family Cyclone III does not have M4K blocks -- using available memory blocks " "Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 164 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Quartus II" 0 -1 1456854058581 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dcfifo_v5o1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dcfifo_v5o1 " "Found entity 1: dcfifo_v5o1" {  } { { "db/dcfifo_v5o1.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 40 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058582 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058582 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dcfifo_v5o1 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated " "Elaborating entity \"dcfifo_v5o1\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\"" {  } { { "dcfifo.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058583 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_gray2bin_tgb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_gray2bin_tgb " "Found entity 1: a_gray2bin_tgb" {  } { { "db/a_gray2bin_tgb.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058598 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058598 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_gray2bin_tgb DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin " "Elaborating entity \"a_gray2bin_tgb\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_gray2bin_tgb:rdptr_g_gray2bin\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g_gray2bin" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058599 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_s57.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_s57 " "Found entity 1: a_graycounter_s57" {  } { { "db/a_graycounter_s57.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058656 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058656 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_s57 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p " "Elaborating entity \"a_graycounter_s57\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_s57:rdptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "rdptr_g1p" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 59 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058657 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_graycounter_ojc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_graycounter_ojc " "Found entity 1: a_graycounter_ojc" {  } { { "db/a_graycounter_ojc.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058708 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058708 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_graycounter_ojc DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p " "Elaborating entity \"a_graycounter_ojc\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|a_graycounter_ojc:wrptr_g1p\"" {  } { { "db/dcfifo_v5o1.tdf" "wrptr_g1p" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 60 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058709 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_de51.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_de51 " "Found entity 1: altsyncram_de51" {  } { { "db/altsyncram_de51.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058764 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058764 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_de51 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram " "Elaborating entity \"altsyncram_de51\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\"" {  } { { "db/dcfifo_v5o1.tdf" "fifo_ram" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058766 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_oe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_oe9 " "Found entity 1: dffpipe_oe9" {  } { { "db/dffpipe_oe9.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058791 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058791 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_oe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp " "Elaborating entity \"dffpipe_oe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|dffpipe_oe9:rs_brp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_brp" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 68 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058793 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_qld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_qld " "Found entity 1: alt_synch_pipe_qld" {  } { { "db/alt_synch_pipe_qld.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058804 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058804 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_qld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp " "Elaborating entity \"alt_synch_pipe_qld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\"" {  } { { "db/dcfifo_v5o1.tdf" "rs_dgwp" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 70 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058805 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_pe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_pe9 " "Found entity 1: dffpipe_pe9" {  } { { "db/dffpipe_pe9.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058814 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058814 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_pe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13 " "Elaborating entity \"dffpipe_pe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_qld:rs_dgwp\|dffpipe_pe9:dffpipe13\"" {  } { { "db/alt_synch_pipe_qld.tdf" "dffpipe13" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058816 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_synch_pipe_rld.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_synch_pipe_rld " "Found entity 1: alt_synch_pipe_rld" {  } { { "db/alt_synch_pipe_rld.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058831 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058831 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_synch_pipe_rld DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp " "Elaborating entity \"alt_synch_pipe_rld\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\"" {  } { { "db/dcfifo_v5o1.tdf" "ws_dgrp" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 73 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058832 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_qe9.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_qe9 " "Found entity 1: dffpipe_qe9" {  } { { "db/dffpipe_qe9.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058843 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058843 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_qe9 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16 " "Elaborating entity \"dffpipe_qe9\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|alt_synch_pipe_rld:ws_dgrp\|dffpipe_qe9:dffpipe16\"" {  } { { "db/alt_synch_pipe_rld.tdf" "dffpipe16" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf" 34 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058844 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_e66.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_e66 " "Found entity 1: cmpr_e66" {  } { { "db/cmpr_e66.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854058894 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854058894 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_e66 DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp " "Elaborating entity \"cmpr_e66\" for hierarchy \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:write_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|cmpr_e66:rdempty_eq_comp\"" {  } { { "db/dcfifo_v5o1.tdf" "rdempty_eq_comp" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 80 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854058895 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_CCD_Config DE0_D5M:inst\|I2C_CCD_Config:u8 " "Elaborating entity \"I2C_CCD_Config\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\"" {  } { { "DE0_D5M.v" "u8" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 377 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059108 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(126) " "Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059109 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(127) " "Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059109 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 25 I2C_CCD_Config.v(160) " "Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059110 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_CCD_Config.v(165) " "Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059111 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 I2C_CCD_Config.v(190) " "Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059111 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 I2C_CCD_Config.v(240) " "Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)" {  } { { "V/I2C_CCD_Config.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059112 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "I2C_Controller DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0 " "Elaborating entity \"I2C_Controller\" for hierarchy \"DE0_D5M:inst\|I2C_CCD_Config:u8\|I2C_Controller:u0\"" {  } { { "V/I2C_CCD_Config.v" "u0" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v" 207 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059131 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(70) " "Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059131 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(69) " "Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)" {  } { { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059131 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 I2C_Controller.v(82) " "Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)" {  } { { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059131 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ps2 ps2:inst6 " "Elaborating entity \"ps2\" for hierarchy \"ps2:inst6\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst6" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 704 760 968 944 "inst6" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059144 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 ps2.v(120) " "Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059145 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ps2.v(188) " "Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059146 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 ps2.v(195) " "Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 195 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059146 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 ps2.v(201) " "Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059146 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(229) " "Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 229 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059146 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ps2.v(245) " "Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)" {  } { { "V/ps2.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059146 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mux vga_mux:inst10 " "Elaborating entity \"vga_mux\" for hierarchy \"vga_mux:inst10\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "inst10" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1056 2304 2448 1168 "inst10" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059163 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_MUX vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborating entity \"LPM_MUX\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "LPM_MUX_component" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059203 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Elaborated megafunction instantiation \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\"" {  } { { "vga_mux.vhd" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "vga_mux:inst10\|LPM_MUX:LPM_MUX_component " "Instantiated megafunction \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 30 " "Parameter \"LPM_WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Parameter \"LPM_SIZE\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Parameter \"LPM_WIDTHS\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 0 " "Parameter \"LPM_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_MUX " "Parameter \"LPM_TYPE\" = \"LPM_MUX\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT UNUSED " "Parameter \"LPM_HINT\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059210 ""}  } { { "vga_mux.vhd" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd" 193 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456854059210 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_u7e.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_u7e " "Found entity 1: mux_u7e" {  } { { "db/mux_u7e.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854059258 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854059258 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_u7e vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated " "Elaborating entity \"mux_u7e\" for hierarchy \"vga_mux:inst10\|LPM_MUX:LPM_MUX_component\|mux_u7e:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.tdf" 86 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059259 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square vga_mouse_square:vga_mouse_catapult_inst " "Elaborating entity \"vga_mouse_square\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "vga_mouse_catapult_inst" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 848 1672 1960 1024 "vga_mouse_catapult_inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059273 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:vga_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_xy_rsc_mgc_in_wire" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 137 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059282 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:mouse_xy_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "mouse_xy_rsc_mgc_in_wire" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 142 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059288 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:cursor_size_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "cursor_size_rsc_mgc_in_wire" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059293 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_in_wire:video_in_rsc_mgc_in_wire\"" {  } { { "catapult_ip/mouse/rtl.v" "video_in_rsc_mgc_in_wire" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 152 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059298 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg\"" {  } { { "catapult_ip/mouse/rtl.v" "video_out_rsc_mgc_out_stdreg" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 157 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059302 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_mouse_square_core vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst " "Elaborating entity \"vga_mouse_square_core\" for hierarchy \"vga_mouse_square:vga_mouse_catapult_inst\|vga_mouse_square_core:vga_mouse_square_core_inst\"" {  } { { "catapult_ip/mouse/rtl.v" "vga_mouse_square_core_inst" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v" 167 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059307 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mean_vga mean_vga:vga_blur_catapult_inst " "Elaborating entity \"mean_vga\" for hierarchy \"mean_vga:vga_blur_catapult_inst\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "vga_blur_catapult_inst" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 1080 1704 1944 1192 "vga_blur_catapult_inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059317 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire mean_vga:vga_blur_catapult_inst\|mgc_in_wire:vin_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"mean_vga:vga_blur_catapult_inst\|mgc_in_wire:vin_rsc_mgc_in_wire\"" {  } { { "catapult_ip/blur3x3/rtl.v" "vin_rsc_mgc_in_wire" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 413 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059326 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg mean_vga:vga_blur_catapult_inst\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"mean_vga:vga_blur_catapult_inst\|mgc_out_stdreg:vout_rsc_mgc_out_stdreg\"" {  } { { "catapult_ip/blur3x3/rtl.v" "vout_rsc_mgc_out_stdreg" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 418 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059331 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mean_vga_core mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst " "Elaborating entity \"mean_vga_core\" for hierarchy \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\"" {  } { { "catapult_ip/blur3x3/rtl.v" "mean_vga_core_inst" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 425 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059336 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "11 10 rtl.v(153) " "Verilog HDL assignment warning at rtl.v(153): truncated value with size 11 to match size of target (10)" {  } { { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 153 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1456854059342 "|TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift_taps altshift_taps:fifo_inst2 " "Elaborating entity \"altshift_taps\" for hierarchy \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "fifo_inst2" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059500 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "altshift_taps:fifo_inst2 " "Elaborated megafunction instantiation \"altshift_taps:fifo_inst2\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854059505 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altshift_taps:fifo_inst2 " "Instantiated megafunction \"altshift_taps:fifo_inst2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMBER_OF_TAPS 5 " "Parameter \"NUMBER_OF_TAPS\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059505 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "TAP_DISTANCE 800 " "Parameter \"TAP_DISTANCE\" = \"800\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059505 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH 30 " "Parameter \"WIDTH\" = \"30\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059505 ""}  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456854059505 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/shift_taps_lpm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/shift_taps_lpm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 shift_taps_lpm " "Found entity 1: shift_taps_lpm" {  } { { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 26 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854059549 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854059549 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_taps_lpm altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated " "Elaborating entity \"shift_taps_lpm\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\"" {  } { { "altshift_taps.tdf" "auto_generated" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059550 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vp81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_vp81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vp81 " "Found entity 1: altsyncram_vp81" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854059624 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854059624 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vp81 altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2 " "Elaborating entity \"altsyncram_vp81\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\"" {  } { { "db/shift_taps_lpm.tdf" "altsyncram2" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059625 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1tf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1tf " "Found entity 1: cntr_1tf" {  } { { "db/cntr_1tf.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854059824 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854059824 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1tf altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|cntr_1tf:cntr1 " "Elaborating entity \"cntr_1tf\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|cntr_1tf:cntr1\"" {  } { { "db/shift_taps_lpm.tdf" "cntr1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 36 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059826 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ugc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ugc " "Found entity 1: cmpr_ugc" {  } { { "db/cmpr_ugc.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456854059876 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456854059876 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ugc altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4 " "Elaborating entity \"cmpr_ugc\" for hierarchy \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|cntr_1tf:cntr1\|cmpr_ugc:cmpr4\"" {  } { { "db/cntr_1tf.tdf" "cmpr4" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf" 85 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854059878 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[120\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[120\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3638 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a120"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[121\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[121\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3668 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a121"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[122\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[122\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3698 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a122"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[123\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[123\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3728 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a123"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[124\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[124\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3758 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a124"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[125\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[125\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3788 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a125"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[126\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[126\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3818 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a126"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[127\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[127\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3848 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a127"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[128\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[128\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3878 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a128"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[129\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[129\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3908 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a129"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[130\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[130\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3938 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a130"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[131\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[131\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3968 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a131"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[132\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[132\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3998 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a132"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[133\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[133\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4028 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a133"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[134\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[134\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4058 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a134"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[135\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[135\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4088 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a135"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[136\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[136\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4118 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a136"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[137\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[137\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4148 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a137"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[138\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[138\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4178 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a138"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[139\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[139\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4208 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a139"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[140\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[140\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4238 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a140"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[141\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[141\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4268 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a141"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[142\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[142\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4298 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a142"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[143\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[143\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4328 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a143"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[144\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[144\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4358 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a144"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[145\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[145\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4388 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a145"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[146\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[146\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4418 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a146"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[147\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[147\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4448 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a147"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[148\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[148\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4478 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a148"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[149\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[149\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 4508 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a149"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo2\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 319 0 0 } } { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\] " "Synthesized away node \"DE0_D5M:inst\|Sdram_Control_4Port:u7\|Sdram_FIFO:read_fifo1\|dcfifo:dcfifo_component\|dcfifo_v5o1:auto_generated\|altsyncram_de51:fifo_ram\|q_b\[15\]\"" {  } { { "db/altsyncram_de51.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf" 521 2 0 } } { "db/dcfifo_v5o1.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf" 61 2 0 } } { "dcfifo.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf" 188 3 0 } } { "Sdram_Control_4Port/Sdram_FIFO.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v" 95 0 0 } } { "Sdram_Control_4Port/Sdram_Control_4Port.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v" 308 0 0 } } { "DE0_D5M.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v" 364 0 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 64 760 1048 560 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[90\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[90\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2738 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a90"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[91\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[91\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2768 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a91"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[92\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[92\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2798 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a92"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[93\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[93\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2828 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a93"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[94\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[94\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2858 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a94"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[95\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[95\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2888 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a95"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[96\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[96\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2918 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a96"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[97\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[97\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2948 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a97"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[98\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[98\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 2978 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a98"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[99\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[99\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3008 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a99"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[100\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[100\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3038 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a100"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[101\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[101\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3068 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a101"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[102\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[102\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3098 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a102"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[103\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[103\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3128 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a103"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[104\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[104\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3158 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a104"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[105\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[105\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3188 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a105"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[106\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[106\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3218 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a106"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[107\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[107\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3248 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a107"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[108\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[108\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3278 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a108"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[109\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[109\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3308 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a109"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[110\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[110\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3338 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a110"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[111\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[111\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3368 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a111"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[112\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[112\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3398 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a112"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[113\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[113\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3428 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a113"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[114\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[114\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3458 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a114"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[115\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[115\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3488 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a115"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[116\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[116\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3518 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a116"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[117\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[117\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3548 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a117"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[118\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[118\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3578 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a118"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[119\] " "Synthesized away node \"altshift_taps:fifo_inst2\|shift_taps_lpm:auto_generated\|altsyncram_vp81:altsyncram2\|q_b\[119\]\"" {  } { { "db/altsyncram_vp81.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf" 3608 2 0 } } { "db/shift_taps_lpm.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf" 35 2 0 } } { "altshift_taps.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift_taps.tdf" 103 3 0 } } { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 456 1896 2040 560 "fifo_inst2" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854060188 "|TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ram_block3a119"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1456854060188 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1456854060188 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|Mult1\"" {  } { { "catapult_ip/blur3x3/rtl.v" "Mult1" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 88 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854061514 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|Mult0\"" {  } { { "catapult_ip/blur3x3/rtl.v" "Mult0" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 80 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854061514 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|Mult2\"" {  } { { "catapult_ip/blur3x3/rtl.v" "Mult2" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 153 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854061514 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1456854061514 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\"" {  } { { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 88 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1 " "Instantiated megafunction \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 3 " "Parameter \"LPM_WIDTHA\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 6 " "Parameter \"LPM_WIDTHB\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 9 " "Parameter \"LPM_WIDTHP\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 9 " "Parameter \"LPM_WIDTHR\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061556 ""}  } { { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 88 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456854061556 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\|multcore:mult_core mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\|multcore:mult_core\", which is child of megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 88 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061590 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\"" {  } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 88 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061605 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1 " "Elaborated megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"mean_vga:vga_blur_catapult_inst\|mean_vga_core:mean_vga_core_inst\|lpm_mult:Mult1\"" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "catapult_ip/blur3x3/rtl.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v" 88 -1 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456854061617 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "10 " "10 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1456854061999 ""}
+{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[20\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[20\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1456854062081 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[14\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[14\]\" and its non-tri-state driver." {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "Quartus II" 0 -1 1456854062081 ""}  } {  } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "Quartus II" 0 -1 1456854062081 ""}
+{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1 " "Bidir \"GPIO_1\" has no driver" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 -1 1456854062082 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 -1 1456854062082 ""}
+{ "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI_HDR" "" "The following tri-state nodes are fed by constants" { { "Warning" "WMLS_OPT_REPLACED_VCC_OR_GND_WITH_TRI" "GPIO_1\[15\] VCC pin " "The pin \"GPIO_1\[15\]\" is fed by VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13033 "The %3!s! \"%1!s!\" is fed by %2!s!" 0 0 "Quartus II" 0 -1 1456854062083 ""}  } {  } 0 13032 "The following tri-state nodes are fed by constants" 0 0 "Quartus II" 0 -1 1456854062083 ""}
+{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "db/a_graycounter_s57.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 32 2 0 } } { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 64 -1 0 } } { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 79 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 32 2 0 } } { "db/a_graycounter_s57.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 63 -1 0 } } { "db/a_graycounter_ojc.tdf" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf" 45 2 0 } } { "V/I2C_Controller.v" "" { Text "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v" 59 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1456854062133 ""}
+{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1456854062133 ""}
+{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854062678 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854062678 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1~synth " "Node \"GPIO_1~synth\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 520 1144 1320 536 "GPIO_1\[31..0\]" "" } } } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854062678 ""}  } {  } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "Quartus II" 0 -1 1456854062678 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 344 1144 1320 360 "DRAM_CKE" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|DRAM_CKE"} { "Warning" "WMLS_MLS_STUCK_PIN" "GPIO_1_CLKOUT\[1\] GND " "Pin \"GPIO_1_CLKOUT\[1\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 504 1144 1354 520 "GPIO_1_CLKOUT\[1..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKOUT[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[9\] GND " "Pin \"LEDG\[9\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[8\] GND " "Pin \"LEDG\[8\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[7\] GND " "Pin \"LEDG\[7\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[6\] GND " "Pin \"LEDG\[6\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[5\] GND " "Pin \"LEDG\[5\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[4\] GND " "Pin \"LEDG\[4\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[3\] GND " "Pin \"LEDG\[3\]\" is stuck at GND" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 24 504 680 40 "LEDG\[9..0\]" "" } { 752 968 1096 768 "LEDG\[2\]" "" } { 768 968 1096 784 "LEDG\[0\]" "" } { 784 968 1096 800 "LEDG\[1\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456854062678 "|TOP_DE0_CAMERA_MOUSE|LEDG[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456854062678 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456854062898 ""}
+{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "29 " "29 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1456854063913 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456854064431 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854064431 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "GPIO_1_CLKIN\[1\] " "No output dependent on input pin \"GPIO_1_CLKIN\[1\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 136 480 704 152 "GPIO_1_CLKIN" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854064677 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854064677 "|TOP_DE0_CAMERA_MOUSE|SW[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "No output dependent on input pin \"SW\[8\]\"" {  } { { "V/TOP_DE0_CAMERA_MOUSE.bdf" "" { Schematic "C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf" { { 120 512 680 136 "SW" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456854064677 "|TOP_DE0_CAMERA_MOUSE|SW[8]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1456854064677 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "2857 " "Implemented 2857 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "16 " "Implemented 16 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456854064678 ""} { "Info" "ICUT_CUT_TM_OPINS" "77 " "Implemented 77 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456854064678 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "50 " "Implemented 50 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1456854064678 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2537 " "Implemented 2537 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456854064678 ""} { "Info" "ICUT_CUT_TM_RAMS" "176 " "Implemented 176 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1456854064678 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1456854064678 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456854064678 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 176 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 176 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "558 " "Peak virtual memory: 558 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456854064718 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 17:41:04 2016 " "Processing ended: Tue Mar 01 17:41:04 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456854064718 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456854064718 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456854064718 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456854064718 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.rdb
new file mode 100644
index 0000000..0da5b81
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.cdb
new file mode 100644
index 0000000..37504a7
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.hdb
new file mode 100644
index 0000000..3d04020
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pre_map.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pre_map.hdb
new file mode 100644
index 0000000..f899e5a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pre_map.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pti_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.pti_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.root_partition.map.reg_db.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..c951a94
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.root_partition.map.reg_db.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.routing.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.routing.rdb
new file mode 100644
index 0000000..cb6c7dc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.routing.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv.hdb
new file mode 100644
index 0000000..729c6e2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg.cdb
new file mode 100644
index 0000000..f33b99f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg_swap.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..86f8d9d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.rtlv_sg_swap.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.cdb
new file mode 100644
index 0000000..f020834
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.hdb
new file mode 100644
index 0000000..f46e981
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sgdiff.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry.sci b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry.sci
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry_dsc.sci b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sld_design_entry_dsc.sci
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smart_action.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smp_dump.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smp_dump.txt
new file mode 100644
index 0000000..5e0f7e1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.smp_dump.txt
@@ -0,0 +1,13 @@
+
+State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state
+Name cur_state.trans cur_state.pulldat cur_state.pullclk cur_state.listen 
+cur_state.listen 0 0 0 0 
+cur_state.pullclk 0 0 1 1 
+cur_state.pulldat 0 1 0 1 
+cur_state.trans 1 0 0 1 
+
+State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+Name mSetup_ST.0000 mSetup_ST.0010 mSetup_ST.0001 
+mSetup_ST.0000 0 0 0 
+mSetup_ST.0001 1 0 1 
+mSetup_ST.0010 1 1 0 
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.qmsg
new file mode 100644
index 0000000..b13f4d3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.qmsg
@@ -0,0 +1,57 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456854083671 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456854083672 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 17:41:23 2016 " "Processing started: Tue Mar 01 17:41:23 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456854083672 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456854083672 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DE0_D5M -c DE0_D5M " "Command: quartus_sta DE0_D5M -c DE0_D5M" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456854083672 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456854083729 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456854083892 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456854083935 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456854083935 ""}
+{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "dcfifo_v5o1 " "Entity dcfifo_v5o1" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a*  " "set_false_path -from *rdptr_g* -to *ws_dgrp\|dffpipe_qe9:dffpipe16\|dffe17a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084270 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a*  " "set_false_path -from *delayed_wrptr_g* -to *rs_dgwp\|dffpipe_pe9:dffpipe13\|dffe14a* " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084270 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1456854084270 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1456854084270 ""}
+{ "Info" "ISTA_SDC_FOUND" "DE0_D5M.sdc " "Reading SDC File: 'DE0_D5M.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1456854084282 ""}
+{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084283 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst\|u6\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084283 ""}  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084283 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854084290 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854084290 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854084290 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854084290 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854084290 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854084400 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854084400 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854084400 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1456854084400 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456854084401 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456854084411 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456854084434 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456854084434 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.619 " "Worst-case setup slack is -0.619" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.619       -28.860 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.619       -28.860 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084436 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.570         0.000 CLOCK_50  " "   15.570         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084436 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854084436 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.283 " "Worst-case hold slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.283         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.358         0.000 CLOCK_50  " "    0.358         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084441 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854084441 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -1.405 " "Worst-case recovery slack is -1.405" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084444 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084444 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.405      -338.209 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -1.405      -338.209 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084444 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.249         0.000 CLOCK_50  " "   14.249         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084444 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854084444 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.496 " "Worst-case removal slack is 1.496" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.496         0.000 CLOCK_50  " "    1.496         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.024         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    4.024         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084447 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854084447 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.735 " "Worst-case minimum pulse width slack is 3.735" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084449 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084449 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.735         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.735         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084449 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.580         0.000 CLOCK_50  " "    9.580         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084449 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854084449 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 10.811 ns " "Worst Case Available Settling Time: 10.811 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854084573 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456854084580 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456854084606 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456854085126 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085252 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085252 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085252 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085252 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085252 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854085258 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854085258 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854085258 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1456854085258 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456854085272 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456854085272 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.084 " "Worst-case setup slack is -0.084" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.084        -1.260 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.084        -1.260 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   15.983         0.000 CLOCK_50  " "   15.983         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085277 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085277 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.283 " "Worst-case hold slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.283         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.283         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.312         0.000 CLOCK_50  " "    0.312         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085285 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085285 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.758 " "Worst-case recovery slack is -0.758" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.758      -148.233 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "   -0.758      -148.233 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085291 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   14.888         0.000 CLOCK_50  " "   14.888         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085291 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085291 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.358 " "Worst-case removal slack is 1.358" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.358         0.000 CLOCK_50  " "    1.358         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085297 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.530         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.530         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085297 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085297 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.740 " "Worst-case minimum pulse width slack is 3.740" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.740         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.740         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.562         0.000 CLOCK_50  " "    9.562         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085301 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085301 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.374 ns " "Worst Case Available Settling Time: 11.374 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085436 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456854085445 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|clk_div\[8\] " "Node: ps2:inst6\|clk_div\[8\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085630 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|clk_div[8]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ps2:inst6\|ps2_clk_in " "Node: ps2:inst6\|ps2_clk_in was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085630 "|TOP_DE0_CAMERA_MOUSE|ps2:inst6|ps2_clk_in"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|rClk\[0\] " "Node: DE0_D5M:inst\|rClk\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085630 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|rClk[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "GPIO_1_CLKIN\[0\] " "Node: GPIO_1_CLKIN\[0\] was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085630 "|TOP_DE0_CAMERA_MOUSE|GPIO_1_CLKIN[0]"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK " "Node: DE0_D5M:inst\|I2C_CCD_Config:u8\|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment." {  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1456854085630 "|TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK"}
+{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) CLOCK_50 (Rise) setup and hold " "From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854085636 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "CLOCK_50 (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From CLOCK_50 (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854085636 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) to inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1456854085636 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1456854085636 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.379 " "Worst-case setup slack is 1.379" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.379         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    1.379         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085648 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   17.476         0.000 CLOCK_50  " "   17.476         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085648 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085648 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.135 " "Worst-case hold slack is 0.135" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085659 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085659 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.135         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.135         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085659 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.187         0.000 CLOCK_50  " "    0.187         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085659 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085659 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.842 " "Worst-case recovery slack is 0.842" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.842         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    0.842         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085667 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   16.628         0.000 CLOCK_50  " "   16.628         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085667 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085667 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.814 " "Worst-case removal slack is 0.814" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.814         0.000 CLOCK_50  " "    0.814         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.346         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    2.346         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085676 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085676 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 3.746 " "Worst-case minimum pulse width slack is 3.746" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\]  " "    3.746         0.000 inst\|u6\|altpll_component\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085684 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.264         0.000 CLOCK_50  " "    9.264         0.000 CLOCK_50 " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085684 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456854085684 ""}
+{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 40 synchronizer chains. " "Report Metastability: Found 40 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 40 " "Number of Synchronizer Chains Found: 40" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.000" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 13.104 ns " "Worst Case Available Settling Time: 13.104 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9" {  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""}  } {  } 0 332114 "%1!s!" 0 0 "Quartus II" 0 -1 1456854085856 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456854086109 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456854086110 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 29 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "525 " "Peak virtual memory: 525 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456854086283 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 17:41:26 2016 " "Processing ended: Tue Mar 01 17:41:26 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456854086283 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456854086283 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456854086283 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456854086283 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.rdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.rdb
new file mode 100644
index 0000000..bf2b23a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta.rdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta_cmp.6_slow_1200mv_85c.tdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..fa2ae4d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.syn_hier_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.syn_hier_info
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tis_db_list.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.fast_1200mv_0c.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..fdd9338
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.fast_1200mv_0c.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_0c.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..a60c66f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_0c.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_85c.ddb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..58a6f2e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tiscmp.slow_1200mv_85c.ddb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tmw_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tmw_info
new file mode 100644
index 0000000..f484d27
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:01
+start_analysis_synthesis:s:00:00:01-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:00-start_full_compilation
+start_assembler:s:00:00:00-start_full_compilation
+start_timing_analyzer:s:00:00:00-start_full_compilation
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.vpr.ammdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.vpr.ammdb
new file mode 100644
index 0000000..ed379e8
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/DE0_D5M.vpr.ammdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf
new file mode 100644
index 0000000..3e96f62
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf
@@ -0,0 +1,50 @@
+--a_gray2bin carry_chain="MANUAL" carry_chain_length=48 device_family="Cyclone III" ignore_carry_buffers="OFF" WIDTH=10 bin gray
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN a_gray2bin_tgb
+( 
+	bin[9..0]	:	output;
+	gray[9..0]	:	input;
+) 
+VARIABLE 
+	xor0	: WIRE;
+	xor1	: WIRE;
+	xor2	: WIRE;
+	xor3	: WIRE;
+	xor4	: WIRE;
+	xor5	: WIRE;
+	xor6	: WIRE;
+	xor7	: WIRE;
+	xor8	: WIRE;
+
+BEGIN 
+	bin[] = ( gray[9..9], xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0);
+	xor0 = (gray[0..0] $ xor1);
+	xor1 = (gray[1..1] $ xor2);
+	xor2 = (gray[2..2] $ xor3);
+	xor3 = (gray[3..3] $ xor4);
+	xor4 = (gray[4..4] $ xor5);
+	xor5 = (gray[5..5] $ xor6);
+	xor6 = (gray[6..6] $ xor7);
+	xor7 = (gray[7..7] $ xor8);
+	xor8 = (gray[9..9] $ gray[8..8]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf
new file mode 100644
index 0000000..a69d388
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf
@@ -0,0 +1,75 @@
+--a_graycounter DEVICE_FAMILY="Cyclone III" PVALUE=1 WIDTH=10 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=S102
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 14 
+OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=S102;{-to counter8a0} POWER_UP_LEVEL=HIGH;{-to parity9} POWER_UP_LEVEL=HIGH";
+
+SUBDESIGN a_graycounter_ojc
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	counter8a0 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	counter8a1 : dffeas;
+	counter8a2 : dffeas;
+	counter8a3 : dffeas;
+	counter8a4 : dffeas;
+	counter8a5 : dffeas;
+	counter8a6 : dffeas;
+	counter8a7 : dffeas;
+	counter8a8 : dffeas;
+	counter8a9 : dffeas;
+	parity9 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	sub_parity10a[2..0] : dffeas;
+	cntr_cout[9..0]	: WIRE;
+	parity_cout	: WIRE;
+	sclr	: NODE;
+	updown	: NODE;
+
+BEGIN 
+	counter8a[9..0].clk = clock;
+	counter8a[9..1].clrn = (! aclr);
+	counter8a[9..0].d = ( (counter8a[9].q $ cntr_cout[8..8]), (counter8a[8].q $ (counter8a[7].q & cntr_cout[7..7])), (counter8a[7].q $ (counter8a[6].q & cntr_cout[6..6])), (counter8a[6].q $ (counter8a[5].q & cntr_cout[5..5])), (counter8a[5].q $ (counter8a[4].q & cntr_cout[4..4])), (counter8a[4].q $ (counter8a[3].q & cntr_cout[3..3])), (counter8a[3].q $ (counter8a[2].q & cntr_cout[2..2])), (counter8a[2].q $ (counter8a[1].q & cntr_cout[1..1])), (counter8a[1].q $ (counter8a[0].q & cntr_cout[0..0])), ((cnt_en & (counter8a[0].q $ (! parity_cout))) # ((! cnt_en) & counter8a[0].q)));
+	counter8a[0].prn = (! aclr);
+	counter8a[9..0].sclr = sclr;
+	parity9.clk = clock;
+	parity9.d = ((cnt_en & ((sub_parity10a[0..0].q $ sub_parity10a[1..1].q) $ sub_parity10a[2..2].q)) # ((! cnt_en) & parity9.q));
+	parity9.prn = (! aclr);
+	parity9.sclr = sclr;
+	sub_parity10a[].clk = ( clock, clock, clock);
+	sub_parity10a[].clrn = ( (! aclr), (! aclr), (! aclr));
+	sub_parity10a[].d = ( ((cnt_en & (counter8a[8..8].q $ counter8a[9..9].q)) # ((! cnt_en) & sub_parity10a[2].q)), ((cnt_en & (((counter8a[4..4].q $ counter8a[5..5].q) $ counter8a[6..6].q) $ counter8a[7..7].q)) # ((! cnt_en) & sub_parity10a[1].q)), ((cnt_en & (((counter8a[0..0].q $ counter8a[1..1].q) $ counter8a[2..2].q) $ counter8a[3..3].q)) # ((! cnt_en) & sub_parity10a[0].q)));
+	sub_parity10a[].sclr = ( sclr, sclr, sclr);
+	cntr_cout[] = ( B"0", (cntr_cout[7..7] & (! counter8a[7].q)), (cntr_cout[6..6] & (! counter8a[6].q)), (cntr_cout[5..5] & (! counter8a[5].q)), (cntr_cout[4..4] & (! counter8a[4].q)), (cntr_cout[3..3] & (! counter8a[3].q)), (cntr_cout[2..2] & (! counter8a[2].q)), (cntr_cout[1..1] & (! counter8a[1].q)), (cntr_cout[0..0] & (! counter8a[0].q)), (cnt_en & parity_cout));
+	parity_cout = (((! parity9.q) $ updown) & cnt_en);
+	q[] = counter8a[9..0].q;
+	sclr = GND;
+	updown = VCC;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf
new file mode 100644
index 0000000..776938d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf
@@ -0,0 +1,75 @@
+--a_graycounter DEVICE_FAMILY="Cyclone III" PVALUE=1 WIDTH=10 aclr clock cnt_en q
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 14 
+OPTIONS ALTERA_INTERNAL_OPTION = "{-to counter5a0} POWER_UP_LEVEL=HIGH;{-to parity6} POWER_UP_LEVEL=HIGH";
+
+SUBDESIGN a_graycounter_s57
+( 
+	aclr	:	input;
+	clock	:	input;
+	cnt_en	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	counter5a0 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	counter5a1 : dffeas;
+	counter5a2 : dffeas;
+	counter5a3 : dffeas;
+	counter5a4 : dffeas;
+	counter5a5 : dffeas;
+	counter5a6 : dffeas;
+	counter5a7 : dffeas;
+	counter5a8 : dffeas;
+	counter5a9 : dffeas;
+	parity6 : dffeas
+		WITH (
+			power_up = "high"
+		);
+	sub_parity7a[2..0] : dffeas;
+	cntr_cout[9..0]	: WIRE;
+	parity_cout	: WIRE;
+	sclr	: NODE;
+	updown	: NODE;
+
+BEGIN 
+	counter5a[9..0].clk = clock;
+	counter5a[9..1].clrn = (! aclr);
+	counter5a[9..0].d = ( (counter5a[9].q $ cntr_cout[8..8]), (counter5a[8].q $ (counter5a[7].q & cntr_cout[7..7])), (counter5a[7].q $ (counter5a[6].q & cntr_cout[6..6])), (counter5a[6].q $ (counter5a[5].q & cntr_cout[5..5])), (counter5a[5].q $ (counter5a[4].q & cntr_cout[4..4])), (counter5a[4].q $ (counter5a[3].q & cntr_cout[3..3])), (counter5a[3].q $ (counter5a[2].q & cntr_cout[2..2])), (counter5a[2].q $ (counter5a[1].q & cntr_cout[1..1])), (counter5a[1].q $ (counter5a[0].q & cntr_cout[0..0])), ((cnt_en & (counter5a[0].q $ (! parity_cout))) # ((! cnt_en) & counter5a[0].q)));
+	counter5a[0].prn = (! aclr);
+	counter5a[9..0].sclr = sclr;
+	parity6.clk = clock;
+	parity6.d = ((cnt_en & ((sub_parity7a[0..0].q $ sub_parity7a[1..1].q) $ sub_parity7a[2..2].q)) # ((! cnt_en) & parity6.q));
+	parity6.prn = (! aclr);
+	parity6.sclr = sclr;
+	sub_parity7a[].clk = ( clock, clock, clock);
+	sub_parity7a[].clrn = ( (! aclr), (! aclr), (! aclr));
+	sub_parity7a[].d = ( ((cnt_en & (counter5a[8..8].q $ counter5a[9..9].q)) # ((! cnt_en) & sub_parity7a[2].q)), ((cnt_en & (((counter5a[4..4].q $ counter5a[5..5].q) $ counter5a[6..6].q) $ counter5a[7..7].q)) # ((! cnt_en) & sub_parity7a[1].q)), ((cnt_en & (((counter5a[0..0].q $ counter5a[1..1].q) $ counter5a[2..2].q) $ counter5a[3..3].q)) # ((! cnt_en) & sub_parity7a[0].q)));
+	sub_parity7a[].sclr = ( sclr, sclr, sclr);
+	cntr_cout[] = ( B"0", (cntr_cout[7..7] & (! counter5a[7].q)), (cntr_cout[6..6] & (! counter5a[6].q)), (cntr_cout[5..5] & (! counter5a[5].q)), (cntr_cout[4..4] & (! counter5a[4].q)), (cntr_cout[3..3] & (! counter5a[3].q)), (cntr_cout[2..2] & (! counter5a[2].q)), (cntr_cout[1..1] & (! counter5a[1].q)), (cntr_cout[0..0] & (! counter5a[0].q)), (cnt_en & parity_cout));
+	parity_cout = (((! parity6.q) $ updown) & cnt_en);
+	q[] = counter5a[9..0].q;
+	sclr = GND;
+	updown = VCC;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf
new file mode 100644
index 0000000..cc60ec9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf
@@ -0,0 +1,42 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_dcfifo 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION dffpipe_pe9 (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS";
+
+SUBDESIGN alt_synch_pipe_qld
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffpipe13 : dffpipe_pe9;
+
+BEGIN 
+	dffpipe13.clock = clock;
+	dffpipe13.clrn = clrn;
+	dffpipe13.d[] = d[];
+	q[] = dffpipe13.q[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf
new file mode 100644
index 0000000..0870b23
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf
@@ -0,0 +1,42 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_dcfifo 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION dffpipe_qe9 (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF;SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS";
+
+SUBDESIGN alt_synch_pipe_rld
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffpipe16 : dffpipe_qe9;
+
+BEGIN 
+	dffpipe16.clock = clock;
+	dffpipe16.clrn = clrn;
+	dffpipe16.d[] = d[];
+	q[] = dffpipe16.q[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf
new file mode 100644
index 0000000..dfc7a42
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf
@@ -0,0 +1,53 @@
+--altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=2 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" clk1_divide_by=2 clk1_duty_cycle=50 clk1_multiply_by=5 clk1_phase_shift="-2600" compensate_clock="CLK0" device_family="Cyclone III" inclk0_input_frequency=20000 intended_device_family="Cyclone III" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:43:SJ cbx_altiobuf_bidir 2013:06:12:18:03:43:SJ cbx_altiobuf_in 2013:06:12:18:03:43:SJ cbx_altiobuf_out 2013:06:12:18:03:43:SJ cbx_altpll 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_pll (areset, clkswitch, configupdate, fbin, inclk[1..0], pfdena, phasecounterselect[phasecounterselect_width-1..0], phasestep, phaseupdown, scanclk, scanclkena, scandata)
+WITH ( AUTO_SETTINGS, BANDWIDTH, BANDWIDTH_TYPE, C0_HIGH, C0_INITIAL, C0_LOW, C0_MODE, C0_PH, C0_TEST_SOURCE, C1_HIGH, C1_INITIAL, C1_LOW, C1_MODE, C1_PH, C1_TEST_SOURCE, C1_USE_CASC_IN, C2_HIGH, C2_INITIAL, C2_LOW, C2_MODE, C2_PH, C2_TEST_SOURCE, C2_USE_CASC_IN, C3_HIGH, C3_INITIAL, C3_LOW, C3_MODE, C3_PH, C3_TEST_SOURCE, C3_USE_CASC_IN, C4_HIGH, C4_INITIAL, C4_LOW, C4_MODE, C4_PH, C4_TEST_SOURCE, C4_USE_CASC_IN, CHARGE_PUMP_CURRENT, CHARGE_PUMP_CURRENT_BITS, CLK0_COUNTER, CLK0_DIVIDE_BY, CLK0_DUTY_CYCLE, CLK0_MULTIPLY_BY, CLK0_OUTPUT_FREQUENCY, CLK0_PHASE_SHIFT, CLK0_PHASE_SHIFT_NUM, clk0_use_even_counter_mode, clk0_use_even_counter_value, CLK1_COUNTER, CLK1_DIVIDE_BY, CLK1_DUTY_CYCLE, CLK1_MULTIPLY_BY, CLK1_OUTPUT_FREQUENCY, CLK1_PHASE_SHIFT, CLK1_PHASE_SHIFT_NUM, clk1_use_even_counter_mode, clk1_use_even_counter_value, CLK2_COUNTER, CLK2_DIVIDE_BY, CLK2_DUTY_CYCLE, CLK2_MULTIPLY_BY, CLK2_OUTPUT_FREQUENCY, CLK2_PHASE_SHIFT, CLK2_PHASE_SHIFT_NUM, clk2_use_even_counter_mode, clk2_use_even_counter_value, CLK3_COUNTER, CLK3_DIVIDE_BY, CLK3_DUTY_CYCLE, CLK3_MULTIPLY_BY, CLK3_OUTPUT_FREQUENCY, CLK3_PHASE_SHIFT, CLK3_PHASE_SHIFT_NUM, clk3_use_even_counter_mode, clk3_use_even_counter_value, CLK4_COUNTER, CLK4_DIVIDE_BY, CLK4_DUTY_CYCLE, CLK4_MULTIPLY_BY, CLK4_OUTPUT_FREQUENCY, CLK4_PHASE_SHIFT, CLK4_PHASE_SHIFT_NUM, clk4_use_even_counter_mode, clk4_use_even_counter_value, CLKOUT_WIDTH = 5, COMPENSATE_CLOCK, ENABLE_SWITCH_OVER_COUNTER, INCLK0_INPUT_FREQUENCY, INCLK1_INPUT_FREQUENCY, LOCK_HIGH, LOCK_LOW, lock_window_ui, lock_window_ui_bits, LOOP_FILTER_C, LOOP_FILTER_C_BITS, LOOP_FILTER_R, LOOP_FILTER_R_BITS, M, M_INITIAL, M_PH, M_TEST_SOURCE, N, OPERATION_MODE, PFD_MAX, PFD_MIN, PHASECOUNTERSELECT_WIDTH = 3, PLL_COMPENSATION_DELAY, PLL_TYPE, SCAN_CHAIN_MIF_FILE, self_reset_on_loss_lock, SIMULATION_TYPE, SWITCH_OVER_COUNTER, SWITCH_OVER_TYPE, TEST_BYPASS_LOCK_DETECT, USE_DC_COUPLING, VCO_CENTER, VCO_DIVIDE_BY, vco_frequency_control, VCO_MAX, VCO_MIN, VCO_MULTIPLY_BY, vco_phase_shift_step, VCO_POST_SCALE, VCO_RANGE_DETECTOR_HIGH_BITS, VCO_RANGE_DETECTOR_LOW_BITS)
+RETURNS ( activeclock, clk[CLKOUT_WIDTH-1..0], clkbad[1..0], fbout, locked, phasedone, scandataout, scandone, vcooverrange, vcounderrange);
+
+--synthesis_resources = cycloneiii_pll 1 
+SUBDESIGN altpll_9ee2
+( 
+	clk[4..0]	:	output;
+	inclk[1..0]	:	input;
+) 
+VARIABLE 
+	pll1 : cycloneiii_pll
+		WITH (
+			BANDWIDTH_TYPE = "auto",
+			CLK0_DIVIDE_BY = 2,
+			CLK0_DUTY_CYCLE = 50,
+			CLK0_MULTIPLY_BY = 5,
+			CLK0_PHASE_SHIFT = "0",
+			CLK1_DIVIDE_BY = 2,
+			CLK1_DUTY_CYCLE = 50,
+			CLK1_MULTIPLY_BY = 5,
+			CLK1_PHASE_SHIFT = "-2600",
+			COMPENSATE_CLOCK = "clk0",
+			INCLK0_INPUT_FREQUENCY = 20000,
+			OPERATION_MODE = "normal",
+			PLL_TYPE = "auto"
+		);
+
+BEGIN 
+	pll1.fbin = pll1.fbout;
+	pll1.inclk[] = inclk[];
+	clk[] = ( pll1.clk[4..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf
new file mode 100644
index 0000000..2195635
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf
@@ -0,0 +1,587 @@
+--altsyncram ADDRESS_ACLR_B="CLEAR1" ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=9 WIDTHAD_B=9 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a
+--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 1 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_de51
+( 
+	aclr1	:	input;
+	address_a[8..0]	:	input;
+	address_b[8..0]	:	input;
+	addressstall_b	:	input;
+	clock0	:	input;
+	clock1	:	input;
+	clocken1	:	input;
+	data_a[15..0]	:	input;
+	q_b[15..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block11a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a9 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a10 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a11 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a12 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 12,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 12,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a13 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 13,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 13,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a14 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 14,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 14,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block11a15 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "none",
+			CLK1_CORE_CLOCK_ENABLE = "none",
+			CLK1_INPUT_CLOCK_ENABLE = "none",
+			CLK1_OUTPUT_CLOCK_ENABLE = "ena1",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 9,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 15,
+			PORT_A_LAST_ADDRESS = 511,
+			PORT_A_LOGICAL_RAM_DEPTH = 512,
+			PORT_A_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_ADDRESS_CLEAR = "clear1",
+			PORT_B_ADDRESS_CLOCK = "clock1",
+			PORT_B_ADDRESS_WIDTH = 9,
+			PORT_B_DATA_OUT_CLEAR = "clear1",
+			PORT_B_DATA_OUT_CLOCK = "clock1",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 15,
+			PORT_B_LAST_ADDRESS = 511,
+			PORT_B_LOGICAL_RAM_DEPTH = 512,
+			PORT_B_LOGICAL_RAM_WIDTH = 16,
+			PORT_B_READ_ENABLE_CLOCK = "clock1",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[8..0]	: WIRE;
+	address_b_wire[8..0]	: WIRE;
+
+BEGIN 
+	ram_block11a[15..0].clk0 = clock0;
+	ram_block11a[15..0].clk1 = clock1;
+	ram_block11a[15..0].clr1 = aclr1;
+	ram_block11a[15..0].ena0 = wren_a;
+	ram_block11a[15..0].ena1 = clocken1;
+	ram_block11a[15..0].portaaddr[] = ( address_a_wire[8..0]);
+	ram_block11a[0].portadatain[] = ( data_a[0..0]);
+	ram_block11a[1].portadatain[] = ( data_a[1..1]);
+	ram_block11a[2].portadatain[] = ( data_a[2..2]);
+	ram_block11a[3].portadatain[] = ( data_a[3..3]);
+	ram_block11a[4].portadatain[] = ( data_a[4..4]);
+	ram_block11a[5].portadatain[] = ( data_a[5..5]);
+	ram_block11a[6].portadatain[] = ( data_a[6..6]);
+	ram_block11a[7].portadatain[] = ( data_a[7..7]);
+	ram_block11a[8].portadatain[] = ( data_a[8..8]);
+	ram_block11a[9].portadatain[] = ( data_a[9..9]);
+	ram_block11a[10].portadatain[] = ( data_a[10..10]);
+	ram_block11a[11].portadatain[] = ( data_a[11..11]);
+	ram_block11a[12].portadatain[] = ( data_a[12..12]);
+	ram_block11a[13].portadatain[] = ( data_a[13..13]);
+	ram_block11a[14].portadatain[] = ( data_a[14..14]);
+	ram_block11a[15].portadatain[] = ( data_a[15..15]);
+	ram_block11a[15..0].portawe = wren_a;
+	ram_block11a[15..0].portbaddr[] = ( address_b_wire[8..0]);
+	ram_block11a[15..0].portbaddrstall = addressstall_b;
+	ram_block11a[15..0].portbre = B"1111111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block11a[15..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf
new file mode 100644
index 0000000..b09ad92
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf
@@ -0,0 +1,796 @@
+--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" NUMWORDS_A=1278 NUMWORDS_B=1278 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=24 WIDTH_B=24 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clocken0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 6 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_lp81
+( 
+	address_a[10..0]	:	input;
+	address_b[10..0]	:	input;
+	clock0	:	input;
+	clocken0	:	input;
+	data_a[23..0]	:	input;
+	q_b[23..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block3a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a9 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a10 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a11 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a12 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 12,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 12,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a13 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 13,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 13,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a14 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 14,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 14,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a15 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 15,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 15,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a16 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 16,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 16,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a17 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 17,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 17,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a18 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 18,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 18,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a19 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 19,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 19,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a20 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 20,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 20,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a21 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 21,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 21,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a22 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 22,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 22,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a23 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 11,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 23,
+			PORT_A_LAST_ADDRESS = 1277,
+			PORT_A_LOGICAL_RAM_DEPTH = 1278,
+			PORT_A_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 11,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 23,
+			PORT_B_LAST_ADDRESS = 1277,
+			PORT_B_LOGICAL_RAM_DEPTH = 1278,
+			PORT_B_LOGICAL_RAM_WIDTH = 24,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[10..0]	: WIRE;
+	address_b_wire[10..0]	: WIRE;
+
+BEGIN 
+	ram_block3a[23..0].clk0 = clock0;
+	ram_block3a[23..0].ena0 = clocken0;
+	ram_block3a[23..0].portaaddr[] = ( address_a_wire[10..0]);
+	ram_block3a[0].portadatain[] = ( data_a[0..0]);
+	ram_block3a[1].portadatain[] = ( data_a[1..1]);
+	ram_block3a[2].portadatain[] = ( data_a[2..2]);
+	ram_block3a[3].portadatain[] = ( data_a[3..3]);
+	ram_block3a[4].portadatain[] = ( data_a[4..4]);
+	ram_block3a[5].portadatain[] = ( data_a[5..5]);
+	ram_block3a[6].portadatain[] = ( data_a[6..6]);
+	ram_block3a[7].portadatain[] = ( data_a[7..7]);
+	ram_block3a[8].portadatain[] = ( data_a[8..8]);
+	ram_block3a[9].portadatain[] = ( data_a[9..9]);
+	ram_block3a[10].portadatain[] = ( data_a[10..10]);
+	ram_block3a[11].portadatain[] = ( data_a[11..11]);
+	ram_block3a[12].portadatain[] = ( data_a[12..12]);
+	ram_block3a[13].portadatain[] = ( data_a[13..13]);
+	ram_block3a[14].portadatain[] = ( data_a[14..14]);
+	ram_block3a[15].portadatain[] = ( data_a[15..15]);
+	ram_block3a[16].portadatain[] = ( data_a[16..16]);
+	ram_block3a[17].portadatain[] = ( data_a[17..17]);
+	ram_block3a[18].portadatain[] = ( data_a[18..18]);
+	ram_block3a[19].portadatain[] = ( data_a[19..19]);
+	ram_block3a[20].portadatain[] = ( data_a[20..20]);
+	ram_block3a[21].portadatain[] = ( data_a[21..21]);
+	ram_block3a[22].portadatain[] = ( data_a[22..22]);
+	ram_block3a[23].portadatain[] = ( data_a[23..23]);
+	ram_block3a[23..0].portawe = wren_a;
+	ram_block3a[23..0].portbaddr[] = ( address_b_wire[10..0]);
+	ram_block3a[23..0].portbre = B"111111111111111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block3a[23..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf
new file mode 100644
index 0000000..e9f57b1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf
@@ -0,0 +1,4702 @@
+--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" NUMWORDS_A=798 NUMWORDS_B=798 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=150 WIDTH_B=150 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b clock0 clocken0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
+WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = M9K 17 
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_vp81
+( 
+	address_a[9..0]	:	input;
+	address_b[9..0]	:	input;
+	clock0	:	input;
+	clocken0	:	input;
+	data_a[149..0]	:	input;
+	q_b[149..0]	:	output;
+	wren_a	:	input;
+) 
+VARIABLE 
+	ram_block3a0 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 0,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 0,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a1 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 1,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 1,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a2 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 2,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 2,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a3 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 3,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 3,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a4 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 4,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 4,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a5 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 5,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 5,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a6 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 6,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 6,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a7 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 7,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 7,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a8 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 8,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 8,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a9 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 9,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 9,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a10 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 10,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 10,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a11 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 11,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 11,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a12 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 12,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 12,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a13 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 13,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 13,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a14 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 14,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 14,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a15 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 15,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 15,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a16 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 16,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 16,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a17 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 17,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 17,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a18 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 18,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 18,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a19 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 19,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 19,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a20 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 20,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 20,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a21 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 21,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 21,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a22 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 22,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 22,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a23 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 23,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 23,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a24 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 24,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 24,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a25 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 25,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 25,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a26 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 26,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 26,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a27 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 27,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 27,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a28 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 28,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 28,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a29 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 29,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 29,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a30 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 30,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 30,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a31 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 31,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 31,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a32 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 32,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 32,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a33 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 33,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 33,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a34 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 34,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 34,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a35 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 35,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 35,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a36 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 36,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 36,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a37 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 37,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 37,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a38 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 38,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 38,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a39 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 39,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 39,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a40 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 40,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 40,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a41 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 41,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 41,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a42 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 42,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 42,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a43 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 43,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 43,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a44 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 44,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 44,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a45 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 45,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 45,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a46 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 46,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 46,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a47 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 47,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 47,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a48 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 48,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 48,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a49 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 49,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 49,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a50 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 50,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 50,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a51 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 51,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 51,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a52 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 52,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 52,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a53 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 53,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 53,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a54 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 54,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 54,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a55 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 55,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 55,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a56 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 56,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 56,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a57 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 57,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 57,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a58 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 58,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 58,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a59 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 59,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 59,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a60 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 60,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 60,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a61 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 61,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 61,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a62 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 62,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 62,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a63 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 63,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 63,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a64 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 64,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 64,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a65 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 65,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 65,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a66 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 66,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 66,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a67 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 67,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 67,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a68 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 68,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 68,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a69 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 69,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 69,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a70 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 70,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 70,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a71 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 71,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 71,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a72 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 72,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 72,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a73 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 73,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 73,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a74 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 74,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 74,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a75 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 75,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 75,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a76 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 76,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 76,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a77 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 77,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 77,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a78 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 78,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 78,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a79 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 79,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 79,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a80 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 80,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 80,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a81 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 81,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 81,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a82 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 82,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 82,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a83 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 83,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 83,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a84 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 84,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 84,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a85 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 85,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 85,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a86 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 86,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 86,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a87 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 87,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 87,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a88 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 88,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 88,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a89 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 89,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 89,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a90 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 90,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 90,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a91 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 91,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 91,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a92 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 92,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 92,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a93 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 93,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 93,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a94 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 94,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 94,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a95 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 95,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 95,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a96 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 96,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 96,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a97 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 97,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 97,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a98 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 98,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 98,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a99 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 99,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 99,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a100 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 100,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 100,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a101 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 101,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 101,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a102 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 102,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 102,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a103 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 103,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 103,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a104 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 104,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 104,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a105 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 105,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 105,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a106 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 106,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 106,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a107 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 107,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 107,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a108 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 108,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 108,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a109 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 109,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 109,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a110 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 110,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 110,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a111 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 111,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 111,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a112 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 112,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 112,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a113 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 113,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 113,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a114 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 114,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 114,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a115 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 115,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 115,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a116 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 116,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 116,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a117 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 117,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 117,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a118 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 118,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 118,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a119 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 119,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 119,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a120 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 120,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 120,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a121 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 121,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 121,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a122 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 122,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 122,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a123 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 123,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 123,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a124 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 124,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 124,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a125 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 125,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 125,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a126 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 126,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 126,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a127 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 127,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 127,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a128 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 128,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 128,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a129 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 129,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 129,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a130 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 130,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 130,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a131 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 131,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 131,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a132 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 132,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 132,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a133 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 133,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 133,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a134 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 134,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 134,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a135 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 135,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 135,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a136 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 136,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 136,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a137 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 137,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 137,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a138 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 138,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 138,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a139 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 139,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 139,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a140 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 140,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 140,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a141 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 141,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 141,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a142 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 142,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 142,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a143 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 143,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 143,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a144 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 144,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 144,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a145 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 145,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 145,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a146 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 146,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 146,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a147 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 147,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 147,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a148 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 148,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 148,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	ram_block3a149 : cycloneiii_ram_block
+		WITH (
+			CLK0_CORE_CLOCK_ENABLE = "ena0",
+			CLK0_INPUT_CLOCK_ENABLE = "ena0",
+			CLK0_OUTPUT_CLOCK_ENABLE = "ena0",
+			CONNECTIVITY_CHECKING = "OFF",
+			LOGICAL_RAM_NAME = "ALTSYNCRAM",
+			MIXED_PORT_FEED_THROUGH_MODE = "old",
+			OPERATION_MODE = "dual_port",
+			PORT_A_ADDRESS_WIDTH = 10,
+			PORT_A_DATA_WIDTH = 1,
+			PORT_A_FIRST_ADDRESS = 0,
+			PORT_A_FIRST_BIT_NUMBER = 149,
+			PORT_A_LAST_ADDRESS = 797,
+			PORT_A_LOGICAL_RAM_DEPTH = 798,
+			PORT_A_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_ADDRESS_CLEAR = "none",
+			PORT_B_ADDRESS_CLOCK = "clock0",
+			PORT_B_ADDRESS_WIDTH = 10,
+			PORT_B_DATA_OUT_CLEAR = "none",
+			PORT_B_DATA_OUT_CLOCK = "clock0",
+			PORT_B_DATA_WIDTH = 1,
+			PORT_B_FIRST_ADDRESS = 0,
+			PORT_B_FIRST_BIT_NUMBER = 149,
+			PORT_B_LAST_ADDRESS = 797,
+			PORT_B_LOGICAL_RAM_DEPTH = 798,
+			PORT_B_LOGICAL_RAM_WIDTH = 150,
+			PORT_B_READ_ENABLE_CLOCK = "clock0",
+			RAM_BLOCK_TYPE = "AUTO"
+		);
+	address_a_wire[9..0]	: WIRE;
+	address_b_wire[9..0]	: WIRE;
+
+BEGIN 
+	ram_block3a[149..0].clk0 = clock0;
+	ram_block3a[149..0].ena0 = clocken0;
+	ram_block3a[149..0].portaaddr[] = ( address_a_wire[9..0]);
+	ram_block3a[0].portadatain[] = ( data_a[0..0]);
+	ram_block3a[1].portadatain[] = ( data_a[1..1]);
+	ram_block3a[2].portadatain[] = ( data_a[2..2]);
+	ram_block3a[3].portadatain[] = ( data_a[3..3]);
+	ram_block3a[4].portadatain[] = ( data_a[4..4]);
+	ram_block3a[5].portadatain[] = ( data_a[5..5]);
+	ram_block3a[6].portadatain[] = ( data_a[6..6]);
+	ram_block3a[7].portadatain[] = ( data_a[7..7]);
+	ram_block3a[8].portadatain[] = ( data_a[8..8]);
+	ram_block3a[9].portadatain[] = ( data_a[9..9]);
+	ram_block3a[10].portadatain[] = ( data_a[10..10]);
+	ram_block3a[11].portadatain[] = ( data_a[11..11]);
+	ram_block3a[12].portadatain[] = ( data_a[12..12]);
+	ram_block3a[13].portadatain[] = ( data_a[13..13]);
+	ram_block3a[14].portadatain[] = ( data_a[14..14]);
+	ram_block3a[15].portadatain[] = ( data_a[15..15]);
+	ram_block3a[16].portadatain[] = ( data_a[16..16]);
+	ram_block3a[17].portadatain[] = ( data_a[17..17]);
+	ram_block3a[18].portadatain[] = ( data_a[18..18]);
+	ram_block3a[19].portadatain[] = ( data_a[19..19]);
+	ram_block3a[20].portadatain[] = ( data_a[20..20]);
+	ram_block3a[21].portadatain[] = ( data_a[21..21]);
+	ram_block3a[22].portadatain[] = ( data_a[22..22]);
+	ram_block3a[23].portadatain[] = ( data_a[23..23]);
+	ram_block3a[24].portadatain[] = ( data_a[24..24]);
+	ram_block3a[25].portadatain[] = ( data_a[25..25]);
+	ram_block3a[26].portadatain[] = ( data_a[26..26]);
+	ram_block3a[27].portadatain[] = ( data_a[27..27]);
+	ram_block3a[28].portadatain[] = ( data_a[28..28]);
+	ram_block3a[29].portadatain[] = ( data_a[29..29]);
+	ram_block3a[30].portadatain[] = ( data_a[30..30]);
+	ram_block3a[31].portadatain[] = ( data_a[31..31]);
+	ram_block3a[32].portadatain[] = ( data_a[32..32]);
+	ram_block3a[33].portadatain[] = ( data_a[33..33]);
+	ram_block3a[34].portadatain[] = ( data_a[34..34]);
+	ram_block3a[35].portadatain[] = ( data_a[35..35]);
+	ram_block3a[36].portadatain[] = ( data_a[36..36]);
+	ram_block3a[37].portadatain[] = ( data_a[37..37]);
+	ram_block3a[38].portadatain[] = ( data_a[38..38]);
+	ram_block3a[39].portadatain[] = ( data_a[39..39]);
+	ram_block3a[40].portadatain[] = ( data_a[40..40]);
+	ram_block3a[41].portadatain[] = ( data_a[41..41]);
+	ram_block3a[42].portadatain[] = ( data_a[42..42]);
+	ram_block3a[43].portadatain[] = ( data_a[43..43]);
+	ram_block3a[44].portadatain[] = ( data_a[44..44]);
+	ram_block3a[45].portadatain[] = ( data_a[45..45]);
+	ram_block3a[46].portadatain[] = ( data_a[46..46]);
+	ram_block3a[47].portadatain[] = ( data_a[47..47]);
+	ram_block3a[48].portadatain[] = ( data_a[48..48]);
+	ram_block3a[49].portadatain[] = ( data_a[49..49]);
+	ram_block3a[50].portadatain[] = ( data_a[50..50]);
+	ram_block3a[51].portadatain[] = ( data_a[51..51]);
+	ram_block3a[52].portadatain[] = ( data_a[52..52]);
+	ram_block3a[53].portadatain[] = ( data_a[53..53]);
+	ram_block3a[54].portadatain[] = ( data_a[54..54]);
+	ram_block3a[55].portadatain[] = ( data_a[55..55]);
+	ram_block3a[56].portadatain[] = ( data_a[56..56]);
+	ram_block3a[57].portadatain[] = ( data_a[57..57]);
+	ram_block3a[58].portadatain[] = ( data_a[58..58]);
+	ram_block3a[59].portadatain[] = ( data_a[59..59]);
+	ram_block3a[60].portadatain[] = ( data_a[60..60]);
+	ram_block3a[61].portadatain[] = ( data_a[61..61]);
+	ram_block3a[62].portadatain[] = ( data_a[62..62]);
+	ram_block3a[63].portadatain[] = ( data_a[63..63]);
+	ram_block3a[64].portadatain[] = ( data_a[64..64]);
+	ram_block3a[65].portadatain[] = ( data_a[65..65]);
+	ram_block3a[66].portadatain[] = ( data_a[66..66]);
+	ram_block3a[67].portadatain[] = ( data_a[67..67]);
+	ram_block3a[68].portadatain[] = ( data_a[68..68]);
+	ram_block3a[69].portadatain[] = ( data_a[69..69]);
+	ram_block3a[70].portadatain[] = ( data_a[70..70]);
+	ram_block3a[71].portadatain[] = ( data_a[71..71]);
+	ram_block3a[72].portadatain[] = ( data_a[72..72]);
+	ram_block3a[73].portadatain[] = ( data_a[73..73]);
+	ram_block3a[74].portadatain[] = ( data_a[74..74]);
+	ram_block3a[75].portadatain[] = ( data_a[75..75]);
+	ram_block3a[76].portadatain[] = ( data_a[76..76]);
+	ram_block3a[77].portadatain[] = ( data_a[77..77]);
+	ram_block3a[78].portadatain[] = ( data_a[78..78]);
+	ram_block3a[79].portadatain[] = ( data_a[79..79]);
+	ram_block3a[80].portadatain[] = ( data_a[80..80]);
+	ram_block3a[81].portadatain[] = ( data_a[81..81]);
+	ram_block3a[82].portadatain[] = ( data_a[82..82]);
+	ram_block3a[83].portadatain[] = ( data_a[83..83]);
+	ram_block3a[84].portadatain[] = ( data_a[84..84]);
+	ram_block3a[85].portadatain[] = ( data_a[85..85]);
+	ram_block3a[86].portadatain[] = ( data_a[86..86]);
+	ram_block3a[87].portadatain[] = ( data_a[87..87]);
+	ram_block3a[88].portadatain[] = ( data_a[88..88]);
+	ram_block3a[89].portadatain[] = ( data_a[89..89]);
+	ram_block3a[90].portadatain[] = ( data_a[90..90]);
+	ram_block3a[91].portadatain[] = ( data_a[91..91]);
+	ram_block3a[92].portadatain[] = ( data_a[92..92]);
+	ram_block3a[93].portadatain[] = ( data_a[93..93]);
+	ram_block3a[94].portadatain[] = ( data_a[94..94]);
+	ram_block3a[95].portadatain[] = ( data_a[95..95]);
+	ram_block3a[96].portadatain[] = ( data_a[96..96]);
+	ram_block3a[97].portadatain[] = ( data_a[97..97]);
+	ram_block3a[98].portadatain[] = ( data_a[98..98]);
+	ram_block3a[99].portadatain[] = ( data_a[99..99]);
+	ram_block3a[100].portadatain[] = ( data_a[100..100]);
+	ram_block3a[101].portadatain[] = ( data_a[101..101]);
+	ram_block3a[102].portadatain[] = ( data_a[102..102]);
+	ram_block3a[103].portadatain[] = ( data_a[103..103]);
+	ram_block3a[104].portadatain[] = ( data_a[104..104]);
+	ram_block3a[105].portadatain[] = ( data_a[105..105]);
+	ram_block3a[106].portadatain[] = ( data_a[106..106]);
+	ram_block3a[107].portadatain[] = ( data_a[107..107]);
+	ram_block3a[108].portadatain[] = ( data_a[108..108]);
+	ram_block3a[109].portadatain[] = ( data_a[109..109]);
+	ram_block3a[110].portadatain[] = ( data_a[110..110]);
+	ram_block3a[111].portadatain[] = ( data_a[111..111]);
+	ram_block3a[112].portadatain[] = ( data_a[112..112]);
+	ram_block3a[113].portadatain[] = ( data_a[113..113]);
+	ram_block3a[114].portadatain[] = ( data_a[114..114]);
+	ram_block3a[115].portadatain[] = ( data_a[115..115]);
+	ram_block3a[116].portadatain[] = ( data_a[116..116]);
+	ram_block3a[117].portadatain[] = ( data_a[117..117]);
+	ram_block3a[118].portadatain[] = ( data_a[118..118]);
+	ram_block3a[119].portadatain[] = ( data_a[119..119]);
+	ram_block3a[120].portadatain[] = ( data_a[120..120]);
+	ram_block3a[121].portadatain[] = ( data_a[121..121]);
+	ram_block3a[122].portadatain[] = ( data_a[122..122]);
+	ram_block3a[123].portadatain[] = ( data_a[123..123]);
+	ram_block3a[124].portadatain[] = ( data_a[124..124]);
+	ram_block3a[125].portadatain[] = ( data_a[125..125]);
+	ram_block3a[126].portadatain[] = ( data_a[126..126]);
+	ram_block3a[127].portadatain[] = ( data_a[127..127]);
+	ram_block3a[128].portadatain[] = ( data_a[128..128]);
+	ram_block3a[129].portadatain[] = ( data_a[129..129]);
+	ram_block3a[130].portadatain[] = ( data_a[130..130]);
+	ram_block3a[131].portadatain[] = ( data_a[131..131]);
+	ram_block3a[132].portadatain[] = ( data_a[132..132]);
+	ram_block3a[133].portadatain[] = ( data_a[133..133]);
+	ram_block3a[134].portadatain[] = ( data_a[134..134]);
+	ram_block3a[135].portadatain[] = ( data_a[135..135]);
+	ram_block3a[136].portadatain[] = ( data_a[136..136]);
+	ram_block3a[137].portadatain[] = ( data_a[137..137]);
+	ram_block3a[138].portadatain[] = ( data_a[138..138]);
+	ram_block3a[139].portadatain[] = ( data_a[139..139]);
+	ram_block3a[140].portadatain[] = ( data_a[140..140]);
+	ram_block3a[141].portadatain[] = ( data_a[141..141]);
+	ram_block3a[142].portadatain[] = ( data_a[142..142]);
+	ram_block3a[143].portadatain[] = ( data_a[143..143]);
+	ram_block3a[144].portadatain[] = ( data_a[144..144]);
+	ram_block3a[145].portadatain[] = ( data_a[145..145]);
+	ram_block3a[146].portadatain[] = ( data_a[146..146]);
+	ram_block3a[147].portadatain[] = ( data_a[147..147]);
+	ram_block3a[148].portadatain[] = ( data_a[148..148]);
+	ram_block3a[149].portadatain[] = ( data_a[149..149]);
+	ram_block3a[149..0].portawe = wren_a;
+	ram_block3a[149..0].portbaddr[] = ( address_b_wire[9..0]);
+	ram_block3a[149..0].portbre = B"111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";
+	address_a_wire[] = address_a[];
+	address_b_wire[] = address_b[];
+	q_b[] = ( ram_block3a[149..0].portbdataout[0..0]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf
new file mode 100644
index 0000000..c752b2f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf
@@ -0,0 +1,41 @@
+--lpm_compare DEVICE_FAMILY="Cyclone III" LPM_WIDTH=10 aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_e66
+( 
+	aeb	:	output;
+	dataa[9..0]	:	input;
+	datab[9..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[26..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[23..23] $ data_wire[24..24]) # (data_wire[25..25] $ data_wire[26..26])), ((data_wire[19..19] $ data_wire[20..20]) # (data_wire[21..21] $ data_wire[22..22])), ((data_wire[15..15] $ data_wire[16..16]) # (data_wire[17..17] $ data_wire[18..18])), ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), data_wire[6..6], (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf
new file mode 100644
index 0000000..52d3129
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf
@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" LPM_WIDTH=10 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_ugc
+( 
+	aeb	:	output;
+	dataa[9..0]	:	input;
+	datab[9..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[26..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], ((data_wire[23..23] $ data_wire[24..24]) # (data_wire[25..25] $ data_wire[26..26])), ((data_wire[19..19] $ data_wire[20..20]) # (data_wire[21..21] $ data_wire[22..22])), ((data_wire[15..15] $ data_wire[16..16]) # (data_wire[17..17] $ data_wire[18..18])), ((data_wire[11..11] $ data_wire[12..12]) # (data_wire[13..13] $ data_wire[14..14])), ((data_wire[7..7] $ data_wire[8..8]) # (data_wire[9..9] $ data_wire[10..10])), data_wire[6..6], (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf
new file mode 100644
index 0000000..835c6a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf
@@ -0,0 +1,41 @@
+--lpm_compare CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" LPM_WIDTH=11 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = 
+SUBDESIGN cmpr_vgc
+( 
+	aeb	:	output;
+	dataa[10..0]	:	input;
+	datab[10..0]	:	input;
+) 
+VARIABLE 
+	aeb_result_wire[0..0]	: WIRE;
+	aneb_result_wire[0..0]	: WIRE;
+	data_wire[29..0]	: WIRE;
+	eq_wire	: WIRE;
+
+BEGIN 
+	aeb = eq_wire;
+	aeb_result_wire[] = (! aneb_result_wire[]);
+	aneb_result_wire[] = (data_wire[0..0] # data_wire[1..1]);
+	data_wire[] = ( datab[10..10], dataa[10..10], datab[9..9], dataa[9..9], datab[8..8], dataa[8..8], datab[7..7], dataa[7..7], datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[28..28] $ data_wire[29..29]), ((data_wire[24..24] $ data_wire[25..25]) # (data_wire[26..26] $ data_wire[27..27])), ((data_wire[20..20] $ data_wire[21..21]) # (data_wire[22..22] $ data_wire[23..23])), ((data_wire[16..16] $ data_wire[17..17]) # (data_wire[18..18] $ data_wire[19..19])), ((data_wire[12..12] $ data_wire[13..13]) # (data_wire[14..14] $ data_wire[15..15])), ((data_wire[8..8] $ data_wire[9..9]) # (data_wire[10..10] $ data_wire[11..11])), (data_wire[6..6] # data_wire[7..7]), (((data_wire[2..2] # data_wire[3..3]) # data_wire[4..4]) # data_wire[5..5]));
+	eq_wire = aeb_result_wire[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf
new file mode 100644
index 0000000..ffc210e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf
@@ -0,0 +1,132 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" lpm_direction="UP" lpm_modulus=798 lpm_port_updown="PORT_UNUSED" lpm_width=10 clk_en clock q
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_ugc (dataa[9..0], datab[9..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 10 reg 10 
+SUBDESIGN cntr_1tf
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita6 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita7 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita8 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita9 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[9..0] : dffeas;
+	cmpr4 : cmpr_ugc;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[9..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[9..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[9..0]	: WIRE;
+	safe_q[9..0]	: WIRE;
+	sclr	: NODE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[9..0].cin = ( counter_comb_bita[8..0].cout, external_cin);
+	counter_comb_bita[9..0].dataa = ( counter_reg_bit[9..0].q);
+	counter_comb_bita[9..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[9..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[9..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr4.dataa[] = safe_q[];
+	cmpr4.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	compare_result = cmpr4.aeb;
+	cout_actual = (counter_comb_bita[9].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"1100011101";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"1111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sclr = GND;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf
new file mode 100644
index 0000000..3790661
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf
@@ -0,0 +1,137 @@
+--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" lpm_direction="UP" lpm_modulus=1278 lpm_port_updown="PORT_UNUSED" lpm_width=11 clk_en clock q
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION cmpr_vgc (dataa[10..0], datab[10..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 11 reg 11 
+SUBDESIGN cntr_cuf
+( 
+	clk_en	:	input;
+	clock	:	input;
+	q[10..0]	:	output;
+) 
+VARIABLE 
+	counter_comb_bita0 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita1 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita2 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita3 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita4 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita5 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita6 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita7 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita8 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita9 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_comb_bita10 : cycloneiii_lcell_comb
+		WITH (
+			LUT_MASK = "5A90",
+			SUM_LUTC_INPUT = "cin"
+		);
+	counter_reg_bit[10..0] : dffeas;
+	cmpr4 : cmpr_vgc;
+	aclr_actual	: WIRE;
+	cnt_en	: NODE;
+	compare_result	: WIRE;
+	cout_actual	: WIRE;
+	data[10..0]	: NODE;
+	external_cin	: WIRE;
+	modulus_bus[10..0]	: WIRE;
+	modulus_trigger	: WIRE;
+	s_val[10..0]	: WIRE;
+	safe_q[10..0]	: WIRE;
+	sclr	: NODE;
+	sload	: NODE;
+	sset	: NODE;
+	time_to_clear	: WIRE;
+	updown_dir	: WIRE;
+
+BEGIN 
+	counter_comb_bita[10..0].cin = ( counter_comb_bita[9..0].cout, external_cin);
+	counter_comb_bita[10..0].dataa = ( counter_reg_bit[10..0].q);
+	counter_comb_bita[10..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
+	counter_comb_bita[10..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
+	counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
+	counter_reg_bit[].clk = clock;
+	counter_reg_bit[].clrn = (! aclr_actual);
+	counter_reg_bit[].d = ( counter_comb_bita[10..0].combout);
+	counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
+	counter_reg_bit[].sload = (((sclr # sset) # sload) # modulus_trigger);
+	cmpr4.dataa[] = safe_q[];
+	cmpr4.datab[] = modulus_bus[];
+	aclr_actual = B"0";
+	cnt_en = VCC;
+	compare_result = cmpr4.aeb;
+	cout_actual = (counter_comb_bita[10].cout # (time_to_clear & updown_dir));
+	data[] = GND;
+	external_cin = B"1";
+	modulus_bus[] = B"10011111101";
+	modulus_trigger = cout_actual;
+	q[] = safe_q[];
+	s_val[] = B"11111111111";
+	safe_q[] = counter_reg_bit[].q;
+	sclr = GND;
+	sload = GND;
+	sset = GND;
+	time_to_clear = compare_result;
+	updown_dir = B"1";
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf
new file mode 100644
index 0000000..c54465a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf
@@ -0,0 +1,168 @@
+--dcfifo_mixed_widths ADD_RAM_OUTPUT_REGISTER="OFF" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone III" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=512 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTH_R=16 LPM_WIDTHU=9 LPM_WIDTHU_R=9 OVERFLOW_CHECKING="ON" RAM_BLOCK_TYPE="M4K" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_dcfifo 2013:06:12:18:03:43:SJ cbx_fifo_common 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_scfifo 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION a_gray2bin_tgb (gray[9..0])
+RETURNS ( bin[9..0]);
+FUNCTION a_graycounter_s57 (aclr, clock, cnt_en)
+RETURNS ( q[9..0]);
+FUNCTION a_graycounter_ojc (aclr, clock, cnt_en)
+RETURNS ( q[9..0]);
+FUNCTION altsyncram_de51 (aclr1, address_a[8..0], address_b[8..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
+RETURNS ( q_b[15..0]);
+FUNCTION dffpipe_oe9 (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+FUNCTION alt_synch_pipe_qld (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+FUNCTION alt_synch_pipe_rld (clock, clrn, d[9..0])
+RETURNS ( q[9..0]);
+FUNCTION cmpr_e66 (dataa[9..0], datab[9..0])
+RETURNS ( aeb);
+
+--synthesis_resources = lut 22 M9K 1 reg 138 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 2;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* """;
+
+SUBDESIGN dcfifo_v5o1
+( 
+	aclr	:	input;
+	data[15..0]	:	input;
+	q[15..0]	:	output;
+	rdclk	:	input;
+	rdempty	:	output;
+	rdreq	:	input;
+	rdusedw[8..0]	:	output;
+	wrclk	:	input;
+	wrfull	:	output;
+	wrreq	:	input;
+	wrusedw[8..0]	:	output;
+) 
+VARIABLE 
+	rdptr_g_gray2bin : a_gray2bin_tgb;
+	rs_dgwp_gray2bin : a_gray2bin_tgb;
+	wrptr_g_gray2bin : a_gray2bin_tgb;
+	ws_dgrp_gray2bin : a_gray2bin_tgb;
+	rdptr_g1p : a_graycounter_s57;
+	wrptr_g1p : a_graycounter_ojc;
+	fifo_ram : altsyncram_de51;
+	delayed_wrptr_g[9..0] : dffe;
+	rdptr_g[9..0] : dffe;
+	wrptr_g[9..0] : dffe
+		WITH (
+			power_up = "low"
+		);
+	rs_brp : dffpipe_oe9;
+	rs_bwp : dffpipe_oe9;
+	rs_dgwp : alt_synch_pipe_qld;
+	ws_brp : dffpipe_oe9;
+	ws_bwp : dffpipe_oe9;
+	ws_dgrp : alt_synch_pipe_rld;
+	rdusedw_sub_dataa[9..0]	:	WIRE;
+	rdusedw_sub_datab[9..0]	:	WIRE;
+	rdusedw_sub_result[9..0]	:	WIRE;
+	wrusedw_sub_dataa[9..0]	:	WIRE;
+	wrusedw_sub_datab[9..0]	:	WIRE;
+	wrusedw_sub_result[9..0]	:	WIRE;
+	rdempty_eq_comp : cmpr_e66;
+	wrfull_eq_comp : cmpr_e66;
+	int_rdempty	: WIRE;
+	int_wrfull	: WIRE;
+	ram_address_a[8..0]	: WIRE;
+	ram_address_b[8..0]	: WIRE;
+	valid_rdreq	: WIRE;
+	valid_wrreq	: WIRE;
+	wrptr_gs[9..0]	: WIRE;
+
+BEGIN 
+	rdptr_g_gray2bin.gray[9..0] = rdptr_g[9..0].q;
+	rs_dgwp_gray2bin.gray[9..0] = rs_dgwp.q[9..0];
+	wrptr_g_gray2bin.gray[9..0] = wrptr_g[9..0].q;
+	ws_dgrp_gray2bin.gray[9..0] = ws_dgrp.q[9..0];
+	rdptr_g1p.aclr = aclr;
+	rdptr_g1p.clock = rdclk;
+	rdptr_g1p.cnt_en = valid_rdreq;
+	wrptr_g1p.aclr = aclr;
+	wrptr_g1p.clock = wrclk;
+	wrptr_g1p.cnt_en = valid_wrreq;
+	fifo_ram.aclr1 = aclr;
+	fifo_ram.address_a[] = ram_address_a[];
+	fifo_ram.address_b[] = ram_address_b[];
+	fifo_ram.addressstall_b = (! valid_rdreq);
+	fifo_ram.clock0 = wrclk;
+	fifo_ram.clock1 = rdclk;
+	fifo_ram.clocken1 = valid_rdreq;
+	fifo_ram.data_a[] = data[];
+	fifo_ram.wren_a = valid_wrreq;
+	delayed_wrptr_g[].clk = wrclk;
+	delayed_wrptr_g[].clrn = (! aclr);
+	delayed_wrptr_g[].d = wrptr_g[].q;
+	rdptr_g[].clk = rdclk;
+	rdptr_g[].clrn = (! aclr);
+	rdptr_g[].d = rdptr_g1p.q[];
+	rdptr_g[].ena = valid_rdreq;
+	wrptr_g[].clk = wrclk;
+	wrptr_g[].clrn = (! aclr);
+	wrptr_g[].d = wrptr_g1p.q[];
+	wrptr_g[].ena = valid_wrreq;
+	rs_brp.clock = rdclk;
+	rs_brp.clrn = (! aclr);
+	rs_brp.d[] = rdptr_g_gray2bin.bin[];
+	rs_bwp.clock = rdclk;
+	rs_bwp.clrn = (! aclr);
+	rs_bwp.d[] = rs_dgwp_gray2bin.bin[];
+	rs_dgwp.clock = rdclk;
+	rs_dgwp.clrn = (! aclr);
+	rs_dgwp.d[] = delayed_wrptr_g[].q;
+	ws_brp.clock = wrclk;
+	ws_brp.clrn = (! aclr);
+	ws_brp.d[] = ws_dgrp_gray2bin.bin[];
+	ws_bwp.clock = wrclk;
+	ws_bwp.clrn = (! aclr);
+	ws_bwp.d[] = wrptr_g_gray2bin.bin[];
+	ws_dgrp.clock = wrclk;
+	ws_dgrp.clrn = (! aclr);
+	ws_dgrp.d[] = rdptr_g[].q;
+	rdusedw_sub_result[] = rdusedw_sub_dataa[] - rdusedw_sub_datab[];
+	rdusedw_sub_dataa[] = rs_bwp.q[];
+	rdusedw_sub_datab[] = rs_brp.q[];
+	wrusedw_sub_result[] = wrusedw_sub_dataa[] - wrusedw_sub_datab[];
+	wrusedw_sub_dataa[] = ws_bwp.q[];
+	wrusedw_sub_datab[] = ws_brp.q[];
+	rdempty_eq_comp.dataa[] = rs_dgwp.q[];
+	rdempty_eq_comp.datab[] = rdptr_g[].q;
+	wrfull_eq_comp.dataa[] = ws_dgrp.q[];
+	wrfull_eq_comp.datab[] = wrptr_gs[];
+	int_rdempty = rdempty_eq_comp.aeb;
+	int_wrfull = wrfull_eq_comp.aeb;
+	q[] = fifo_ram.q_b[];
+	ram_address_a[] = ( (wrptr_g[9..9].q $ wrptr_g[8..8].q), wrptr_g[7..0].q);
+	ram_address_b[] = ( (rdptr_g1p.q[9..9] $ rdptr_g1p.q[8..8]), rdptr_g1p.q[7..0]);
+	rdempty = int_rdempty;
+	rdusedw[] = ( rdusedw_sub_result[8..0]);
+	valid_rdreq = (rdreq & (! int_rdempty));
+	valid_wrreq = (wrreq & (! int_wrfull));
+	wrfull = int_wrfull;
+	wrptr_gs[] = ( (! wrptr_g[9..9].q), (! wrptr_g[8..8].q), wrptr_g[7..0].q);
+	wrusedw[] = ( wrusedw_sub_result[8..0]);
+	ASSERT (0) 
+	REPORT "Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2"
+	SEVERITY WARNING;
+	ASSERT (0) 
+	REPORT "Device family Cyclone III does not have M4K blocks -- using available memory blocks"
+	SEVERITY WARNING;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf
new file mode 100644
index 0000000..b1ad734
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf
@@ -0,0 +1,48 @@
+--dffpipe DELAY=1 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 10 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
+
+SUBDESIGN dffpipe_oe9
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffe12a[9..0] : dffe;
+	ena	: NODE;
+	prn	: NODE;
+	sclr	: NODE;
+
+BEGIN 
+	dffe12a[].clk = clock;
+	dffe12a[].clrn = clrn;
+	dffe12a[].d = (d[] & (! sclr));
+	dffe12a[].ena = ena;
+	dffe12a[].prn = prn;
+	ena = VCC;
+	prn = VCC;
+	q[] = dffe12a[].q;
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf
new file mode 100644
index 0000000..5bd8385
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf
@@ -0,0 +1,54 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
+
+SUBDESIGN dffpipe_pe9
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffe14a[9..0] : dffe;
+	dffe15a[9..0] : dffe;
+	ena	: NODE;
+	prn	: NODE;
+	sclr	: NODE;
+
+BEGIN 
+	dffe14a[].clk = clock;
+	dffe14a[].clrn = clrn;
+	dffe14a[].d = (d[] & (! sclr));
+	dffe14a[].ena = ena;
+	dffe14a[].prn = prn;
+	dffe15a[].clk = clock;
+	dffe15a[].clrn = clrn;
+	dffe15a[].d = (dffe14a[].q & (! sclr));
+	dffe15a[].ena = ena;
+	dffe15a[].prn = prn;
+	ena = VCC;
+	prn = VCC;
+	q[] = dffe15a[].q;
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf
new file mode 100644
index 0000000..3971343
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf
@@ -0,0 +1,54 @@
+--dffpipe DELAY=2 WIDTH=10 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+--VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = reg 20 
+OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF";
+
+SUBDESIGN dffpipe_qe9
+( 
+	clock	:	input;
+	clrn	:	input;
+	d[9..0]	:	input;
+	q[9..0]	:	output;
+) 
+VARIABLE 
+	dffe17a[9..0] : dffe;
+	dffe18a[9..0] : dffe;
+	ena	: NODE;
+	prn	: NODE;
+	sclr	: NODE;
+
+BEGIN 
+	dffe17a[].clk = clock;
+	dffe17a[].clrn = clrn;
+	dffe17a[].d = (d[] & (! sclr));
+	dffe17a[].ena = ena;
+	dffe17a[].prn = prn;
+	dffe18a[].clk = clock;
+	dffe18a[].clrn = clrn;
+	dffe18a[].d = (dffe17a[].q & (! sclr));
+	dffe18a[].ena = ena;
+	dffe18a[].prn = prn;
+	ena = VCC;
+	prn = VCC;
+	q[] = dffe18a[].q;
+	sclr = GND;
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/logic_util_heursitic.dat b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..0fe5a0a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/logic_util_heursitic.dat
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf
new file mode 100644
index 0000000..95c482a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf
@@ -0,0 +1,97 @@
+--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone III" IGNORE_CASCADE_BUFFERS="OFF" LPM_PIPELINE=0 LPM_SIZE=4 LPM_WIDTH=30 LPM_WIDTHS=2 data result sel
+--VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+
+--synthesis_resources = lut 60 
+SUBDESIGN mux_u7e
+( 
+	data[119..0]	:	input;
+	result[29..0]	:	output;
+	sel[1..0]	:	input;
+) 
+VARIABLE 
+	result_node[29..0]	: WIRE;
+	sel_node[1..0]	: WIRE;
+	w_data109w[3..0]	: WIRE;
+	w_data134w[3..0]	: WIRE;
+	w_data159w[3..0]	: WIRE;
+	w_data184w[3..0]	: WIRE;
+	w_data209w[3..0]	: WIRE;
+	w_data234w[3..0]	: WIRE;
+	w_data259w[3..0]	: WIRE;
+	w_data284w[3..0]	: WIRE;
+	w_data309w[3..0]	: WIRE;
+	w_data334w[3..0]	: WIRE;
+	w_data34w[3..0]	: WIRE;
+	w_data359w[3..0]	: WIRE;
+	w_data384w[3..0]	: WIRE;
+	w_data409w[3..0]	: WIRE;
+	w_data434w[3..0]	: WIRE;
+	w_data459w[3..0]	: WIRE;
+	w_data484w[3..0]	: WIRE;
+	w_data4w[3..0]	: WIRE;
+	w_data509w[3..0]	: WIRE;
+	w_data534w[3..0]	: WIRE;
+	w_data559w[3..0]	: WIRE;
+	w_data584w[3..0]	: WIRE;
+	w_data59w[3..0]	: WIRE;
+	w_data609w[3..0]	: WIRE;
+	w_data634w[3..0]	: WIRE;
+	w_data659w[3..0]	: WIRE;
+	w_data684w[3..0]	: WIRE;
+	w_data709w[3..0]	: WIRE;
+	w_data734w[3..0]	: WIRE;
+	w_data84w[3..0]	: WIRE;
+
+BEGIN 
+	result[] = result_node[];
+	result_node[] = ( (((w_data734w[1..1] & sel_node[0..0]) & (! (((w_data734w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data734w[2..2]))))) # ((((w_data734w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data734w[2..2]))) & (w_data734w[3..3] # (! sel_node[0..0])))), (((w_data709w[1..1] & sel_node[0..0]) & (! (((w_data709w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data709w[2..2]))))) # ((((w_data709w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data709w[2..2]))) & (w_data709w[3..3] # (! sel_node[0..0])))), (((w_data684w[1..1] & sel_node[0..0]) & (! (((w_data684w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data684w[2..2]))))) # ((((w_data684w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data684w[2..2]))) & (w_data684w[3..3] # (! sel_node[0..0])))), (((w_data659w[1..1] & sel_node[0..0]) & (! (((w_data659w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data659w[2..2]))))) # ((((w_data659w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data659w[2..2]))) & (w_data659w[3..3] # (! sel_node[0..0])))), (((w_data634w[1..1] & sel_node[0..0]) & (! (((w_data634w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data634w[2..2]))))) # ((((w_data634w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data634w[2..2]))) & (w_data634w[3..3] # (! sel_node[0..0])))), (((w_data609w[1..1] & sel_node[0..0]) & (! (((w_data609w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data609w[2..2]))))) # ((((w_data609w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data609w[2..2]))) & (w_data609w[3..3] # (! sel_node[0..0])))), (((w_data584w[1..1] & sel_node[0..0]) & (! (((w_data584w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data584w[2..2]))))) # ((((w_data584w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data584w[2..2]))) & (w_data584w[3..3] # (! sel_node[0..0])))), (((w_data559w[1..1] & sel_node[0..0]) & (! (((w_data559w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data559w[2..2]))))) # ((((w_data559w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data559w[2..2]))) & (w_data559w[3..3] # (! sel_node[0..0])))), (((w_data534w[1..1] & sel_node[0..0]) & (! (((w_data534w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data534w[2..2]))))) # ((((w_data534w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data534w[2..2]))) & (w_data534w[3..3] # (! sel_node[0..0])))), (((w_data509w[1..1] & sel_node[0..0]) & (! (((w_data509w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data509w[2..2]))))) # ((((w_data509w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data509w[2..2]))) & (w_data509w[3..3] # (! sel_node[0..0])))), (((w_data484w[1..1] & sel_node[0..0]) & (! (((w_data484w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data484w[2..2]))))) # ((((w_data484w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data484w[2..2]))) & (w_data484w[3..3] # (! sel_node[0..0])))), (((w_data459w[1..1] & sel_node[0..0]) & (! (((w_data459w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data459w[2..2]))))) # ((((w_data459w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data459w[2..2]))) & (w_data459w[3..3] # (! sel_node[0..0])))), (((w_data434w[1..1] & sel_node[0..0]) & (! (((w_data434w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data434w[2..2]))))) # ((((w_data434w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data434w[2..2]))) & (w_data434w[3..3] # (! sel_node[0..0])))), (((w_data409w[1..1] & sel_node[0..0]) & (! (((w_data409w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data409w[2..2]))))) # ((((w_data409w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data409w[2..2]))) & (w_data409w[3..3] # (! sel_node[0..0])))), (((w_data384w[1..1] & sel_node[0..0]) & (! (((w_data384w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data384w[2..2]))))) # ((((w_data384w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data384w[2..2]))) & (w_data384w[3..3] # (! sel_node[0..0])))), (((w_data359w[1..1] & sel_node[0..0]) & (! (((w_data359w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data359w[2..2]))))) # ((((w_data359w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data359w[2..2]))) & (w_data359w[3..3] # (! sel_node[0..0])))), (((w_data334w[1..1] & sel_node[0..0]) & (! (((w_data334w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data334w[2..2]))))) # ((((w_data334w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data334w[2..2]))) & (w_data334w[3..3] # (! sel_node[0..0])))), (((w_data309w[1..1] & sel_node[0..0]) & (! (((w_data309w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data309w[2..2]))))) # ((((w_data309w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data309w[2..2]))) & (w_data309w[3..3] # (! sel_node[0..0])))), (((w_data284w[1..1] & sel_node[0..0]) & (! (((w_data284w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data284w[2..2]))))) # ((((w_data284w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data284w[2..2]))) & (w_data284w[3..3] # (! sel_node[0..0])))), (((w_data259w[1..1] & sel_node[0..0]) & (! (((w_data259w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data259w[2..2]))))) # ((((w_data259w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data259w[2..2]))) & (w_data259w[3..3] # (! sel_node[0..0])))), (((w_data234w[1..1] & sel_node[0..0]) & (! (((w_data234w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data234w[2..2]))))) # ((((w_data234w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data234w[2..2]))) & (w_data234w[3..3] # (! sel_node[0..0])))), (((w_data209w[1..1] & sel_node[0..0]) & (! (((w_data209w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data209w[2..2]))))) # ((((w_data209w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data209w[2..2]))) & (w_data209w[3..3] # (! sel_node[0..0])))), (((w_data184w[1..1] & sel_node[0..0]) & (! (((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2]))))) # ((((w_data184w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data184w[2..2]))) & (w_data184w[3..3] # (! sel_node[0..0])))), (((w_data159w[1..1] & sel_node[0..0]) & (! (((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2]))))) # ((((w_data159w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data159w[2..2]))) & (w_data159w[3..3] # (! sel_node[0..0])))), (((w_data134w[1..1] & sel_node[0..0]) & (! (((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2]))))) # ((((w_data134w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data134w[2..2]))) & (w_data134w[3..3] # (! sel_node[0..0])))), (((w_data109w[1..1] & sel_node[0..0]) & (! (((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2]))))) # ((((w_data109w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data109w[2..2]))) & (w_data109w[3..3] # (! sel_node[0..0])))), (((w_data84w[1..1] & sel_node[0..0]) & (! (((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2]))))) # ((((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2]))) & (w_data84w[3..3] # (! sel_node[0..0])))), (((w_data59w[1..1] & sel_node[0..0]) & (! (((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2]))))) # ((((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2]))) & (w_data59w[3..3] # (! sel_node[0..0])))), (((w_data34w[1..1] & sel_node[0..0]) & (! (((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2]))))) # ((((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2]))) & (w_data34w[3..3] # (! sel_node[0..0])))), (((w_data4w[1..1] & sel_node[0..0]) & (! (((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2]))))) # ((((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2]))) & (w_data4w[3..3] # (! sel_node[0..0])))));
+	sel_node[] = ( sel[1..0]);
+	w_data109w[] = ( data[94..94], data[64..64], data[34..34], data[4..4]);
+	w_data134w[] = ( data[95..95], data[65..65], data[35..35], data[5..5]);
+	w_data159w[] = ( data[96..96], data[66..66], data[36..36], data[6..6]);
+	w_data184w[] = ( data[97..97], data[67..67], data[37..37], data[7..7]);
+	w_data209w[] = ( data[98..98], data[68..68], data[38..38], data[8..8]);
+	w_data234w[] = ( data[99..99], data[69..69], data[39..39], data[9..9]);
+	w_data259w[] = ( data[100..100], data[70..70], data[40..40], data[10..10]);
+	w_data284w[] = ( data[101..101], data[71..71], data[41..41], data[11..11]);
+	w_data309w[] = ( data[102..102], data[72..72], data[42..42], data[12..12]);
+	w_data334w[] = ( data[103..103], data[73..73], data[43..43], data[13..13]);
+	w_data34w[] = ( data[91..91], data[61..61], data[31..31], data[1..1]);
+	w_data359w[] = ( data[104..104], data[74..74], data[44..44], data[14..14]);
+	w_data384w[] = ( data[105..105], data[75..75], data[45..45], data[15..15]);
+	w_data409w[] = ( data[106..106], data[76..76], data[46..46], data[16..16]);
+	w_data434w[] = ( data[107..107], data[77..77], data[47..47], data[17..17]);
+	w_data459w[] = ( data[108..108], data[78..78], data[48..48], data[18..18]);
+	w_data484w[] = ( data[109..109], data[79..79], data[49..49], data[19..19]);
+	w_data4w[] = ( data[90..90], data[60..60], data[30..30], data[0..0]);
+	w_data509w[] = ( data[110..110], data[80..80], data[50..50], data[20..20]);
+	w_data534w[] = ( data[111..111], data[81..81], data[51..51], data[21..21]);
+	w_data559w[] = ( data[112..112], data[82..82], data[52..52], data[22..22]);
+	w_data584w[] = ( data[113..113], data[83..83], data[53..53], data[23..23]);
+	w_data59w[] = ( data[92..92], data[62..62], data[32..32], data[2..2]);
+	w_data609w[] = ( data[114..114], data[84..84], data[54..54], data[24..24]);
+	w_data634w[] = ( data[115..115], data[85..85], data[55..55], data[25..25]);
+	w_data659w[] = ( data[116..116], data[86..86], data[56..56], data[26..26]);
+	w_data684w[] = ( data[117..117], data[87..87], data[57..57], data[27..27]);
+	w_data709w[] = ( data[118..118], data[88..88], data[58..58], data[28..28]);
+	w_data734w[] = ( data[119..119], data[89..89], data[59..59], data[29..29]);
+	w_data84w[] = ( data[93..93], data[63..63], data[33..33], data[3..3]);
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg
new file mode 100644
index 0000000..4526151
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/prev_cmp_DE0_D5M.qmsg
@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456854095145 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II 64-Bit " "Running Quartus II 64-Bit Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456854095145 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 17:41:35 2016 " "Processing started: Tue Mar 01 17:41:35 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456854095145 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456854095145 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M --generate_symbol=\"C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M --generate_symbol=\"C:/Catapult C/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456854095146 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "417 " "Peak virtual memory: 417 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456854095635 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 17:41:35 2016 " "Processing ended: Tue Mar 01 17:41:35 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456854095635 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456854095635 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456854095635 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456854095635 ""}
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf
new file mode 100644
index 0000000..39eb4d9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf
@@ -0,0 +1,50 @@
+--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" NUMBER_OF_TAPS=5 TAP_DISTANCE=800 WIDTH=30 clken clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altshift_taps 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION altsyncram_vp81 (address_a[9..0], address_b[9..0], clock0, clocken0, data_a[149..0], wren_a)
+RETURNS ( q_b[149..0]);
+FUNCTION cntr_1tf (clk_en, clock)
+RETURNS ( q[9..0]);
+
+--synthesis_resources = lut 10 M9K 17 reg 10 
+SUBDESIGN shift_taps_lpm
+( 
+	clken	:	input;
+	clock	:	input;
+	shiftin[29..0]	:	input;
+	shiftout[29..0]	:	output;
+	taps[149..0]	:	output;
+) 
+VARIABLE 
+	altsyncram2 : altsyncram_vp81;
+	cntr1 : cntr_1tf;
+
+BEGIN 
+	altsyncram2.address_a[] = cntr1.q[];
+	altsyncram2.address_b[] = cntr1.q[];
+	altsyncram2.clock0 = clock;
+	altsyncram2.clocken0 = clken;
+	altsyncram2.data_a[] = ( altsyncram2.q_b[119..0], shiftin[]);
+	altsyncram2.wren_a = B"1";
+	cntr1.clk_en = clken;
+	cntr1.clock = clock;
+	shiftout[29..0] = altsyncram2.q_b[149..120];
+	taps[] = altsyncram2.q_b[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf
new file mode 100644
index 0000000..6dece17
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf
@@ -0,0 +1,50 @@
+--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" NUMBER_OF_TAPS=2 TAP_DISTANCE=1280 WIDTH=12 clken clock shiftin shiftout taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
+--VERSION_BEGIN 13.0 cbx_altdpram 2013:06:12:18:03:43:SJ cbx_altshift_taps 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION altsyncram_lp81 (address_a[10..0], address_b[10..0], clock0, clocken0, data_a[23..0], wren_a)
+RETURNS ( q_b[23..0]);
+FUNCTION cntr_cuf (clk_en, clock)
+RETURNS ( q[10..0]);
+
+--synthesis_resources = lut 11 M9K 6 reg 11 
+SUBDESIGN shift_taps_rnn
+( 
+	clken	:	input;
+	clock	:	input;
+	shiftin[11..0]	:	input;
+	shiftout[11..0]	:	output;
+	taps[23..0]	:	output;
+) 
+VARIABLE 
+	altsyncram2 : altsyncram_lp81;
+	cntr1 : cntr_cuf;
+
+BEGIN 
+	altsyncram2.address_a[] = cntr1.q[];
+	altsyncram2.address_b[] = cntr1.q[];
+	altsyncram2.clock0 = clock;
+	altsyncram2.clocken0 = clken;
+	altsyncram2.data_a[] = ( altsyncram2.q_b[11..0], shiftin[]);
+	altsyncram2.wren_a = B"1";
+	cntr1.clk_en = clken;
+	cntr1.clock = clock;
+	shiftout[11..0] = altsyncram2.q_b[23..12];
+	taps[] = altsyncram2.q_b[];
+END;
+--VALID FILE
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..a13a74e
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt
@@ -0,0 +1,11 @@
+LPM_SIZE=4
+LPM_TYPE=LPM_MUX
+LPM_WIDTH=30
+LPM_WIDTHS=2
+DEVICE_FAMILY="Cyclone III"
+data
+data
+data
+data
+sel
+result
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/README b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.db_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.db_info
new file mode 100644
index 0000000..eb0996d
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 01 17:41:00 2016
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.ammdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.ammdb
new file mode 100644
index 0000000..fe1d058
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.ammdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.cdb
new file mode 100644
index 0000000..e768019
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.dfp b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.dfp
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.hdb
new file mode 100644
index 0000000..52522a2
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.logdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.rcfdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..bc8115c
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.cmp.rcfdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.cdb
new file mode 100644
index 0000000..5cf3d16
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.dpi b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.dpi
new file mode 100644
index 0000000..e7915d9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.dpi
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.cdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..d3ec979
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.cdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hb_info b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..f5c15cc
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hb_info
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..6e2f0ca
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.sig b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..682f0a1
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+7b81eaf314cd59741fced60c2f8bb713
\ No newline at end of file
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hdb b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hdb
new file mode 100644
index 0000000..a18f2f4
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.hdb
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.kpt b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.kpt
new file mode 100644
index 0000000..e1cc348
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/incremental_db/compiled_partitions/DE0_D5M.root_partition.map.kpt
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf
new file mode 100644
index 0000000..ad72508
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 256 128)
+	(text "mean_vga" (rect 5 0 48 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vin_rsc_z[89..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "vin_rsc_z[89..0]" (rect 21 27 85 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 43 31 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 59 30 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 75 46 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 240 32)
+		(output)
+		(text "vout_rsc_z[29..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "vout_rsc_z[29..0]" (rect 149 27 219 39)(font "Arial" ))
+		(line (pt 240 32)(pt 224 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 224 96)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf
new file mode 100644
index 0000000..782bad9
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 384 128)
+	(text "mean_vga_core" (rect 5 0 72 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 0 0 122 12)(font "Arial" ))
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 21 75 143 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 368 32)
+		(output)
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 204 27 347 39)(font "Arial" ))
+		(line (pt 368 32)(pt 352 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 352 96)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf
new file mode 100644
index 0000000..bf9fac3
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf
@@ -0,0 +1,153 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 224 256)
+	(text "ps2" (rect 5 0 19 12)(font "Arial" ))
+	(text "inst" (rect 8 224 20 236)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "iSTART" (rect 0 0 35 12)(font "Arial" ))
+		(text "iSTART" (rect 21 27 56 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "iRST_n" (rect 0 0 31 12)(font "Arial" ))
+		(text "iRST_n" (rect 21 43 52 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "iCLK_50" (rect 0 0 36 12)(font "Arial" ))
+		(text "iCLK_50" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "oLEFBUT" (rect 0 0 42 12)(font "Arial" ))
+		(text "oLEFBUT" (rect 145 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64)(line_width 1))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "oRIGBUT" (rect 0 0 41 12)(font "Arial" ))
+		(text "oRIGBUT" (rect 146 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80)(line_width 1))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "oMIDBUT" (rect 0 0 41 12)(font "Arial" ))
+		(text "oMIDBUT" (rect 146 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96)(line_width 1))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "oX[7..0]" (rect 0 0 30 12)(font "Arial" ))
+		(text "oX[7..0]" (rect 157 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112)(line_width 3))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "oY[7..0]" (rect 0 0 31 12)(font "Arial" ))
+		(text "oY[7..0]" (rect 156 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128)(line_width 3))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "oX_MOV1[6..0]" (rect 0 0 63 12)(font "Arial" ))
+		(text "oX_MOV1[6..0]" (rect 124 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144)(line_width 3))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "oX_MOV2[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "oX_MOV2[6..0]" (rect 123 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160)(line_width 3))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "oY_MOV1[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "oY_MOV1[6..0]" (rect 123 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "oY_MOV2[6..0]" (rect 0 0 66 12)(font "Arial" ))
+		(text "oY_MOV2[6..0]" (rect 121 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 32)
+		(bidir)
+		(text "PS2_CLK" (rect 0 0 42 12)(font "Arial" ))
+		(text "PS2_CLK" (rect 145 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 1))
+	)
+	(port
+		(pt 208 48)
+		(bidir)
+		(text "PS2_DAT" (rect 0 0 43 12)(font "Arial" ))
+		(text "PS2_DAT" (rect 144 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48)(line_width 1))
+	)
+	(parameter
+		"enable_byte"
+		"011110100"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"listen"
+		"00"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pullclk"
+		"01"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pulldat"
+		"10"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"trans"
+		"11"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(drawing
+		(rectangle (rect 16 16 192 224)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 224 -64 324 16))
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf
new file mode 100644
index 0000000..ce4ccaf
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 192)
+	(text "vga_mouse_square" (rect 5 0 86 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vga_xy_rsc_z[19..0]" (rect 0 0 83 12)(font "Arial" ))
+		(text "vga_xy_rsc_z[19..0]" (rect 21 27 104 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "mouse_xy_rsc_z[19..0]" (rect 0 0 95 12)(font "Arial" ))
+		(text "mouse_xy_rsc_z[19..0]" (rect 21 43 116 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "cursor_size_rsc_z[7..0]" (rect 0 0 94 12)(font "Arial" ))
+		(text "cursor_size_rsc_z[7..0]" (rect 21 59 115 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "video_in_rsc_z[29..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "video_in_rsc_z[29..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 91 31 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 107 30 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 123 46 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "video_out_rsc_z[29..0]" (rect 0 0 92 12)(font "Arial" ))
+		(text "video_out_rsc_z[29..0]" (rect 175 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 160)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf
new file mode 100644
index 0000000..f468b93
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 440 192)
+	(text "vga_mouse_square_core" (rect 5 0 110 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vga_xy_rsc_mgc_in_wire_d[19..0]" (rect 0 0 141 12)(font "Arial" ))
+		(text "vga_xy_rsc_mgc_in_wire_d[19..0]" (rect 21 75 162 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "mouse_xy_rsc_mgc_in_wire_d[19..0]" (rect 0 0 153 12)(font "Arial" ))
+		(text "mouse_xy_rsc_mgc_in_wire_d[19..0]" (rect 21 91 174 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "cursor_size_rsc_mgc_in_wire_d[7..0]" (rect 0 0 152 12)(font "Arial" ))
+		(text "cursor_size_rsc_mgc_in_wire_d[7..0]" (rect 21 107 173 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "video_in_rsc_mgc_in_wire_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "video_in_rsc_mgc_in_wire_d[29..0]" (rect 21 123 164 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 424 32)
+		(output)
+		(text "video_out_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 165 12)(font "Arial" ))
+		(text "video_out_rsc_mgc_out_stdreg_d[29..0]" (rect 238 27 403 39)(font "Arial" ))
+		(line (pt 424 32)(pt 408 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 408 160)(line_width 1))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf
new file mode 100644
index 0000000..5130f75
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 112)
+	(text "vga_mux" (rect 48 0 108 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[29..0]" (rect 4 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[29..0]" (rect 4 42 65 55)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[29..0]" (rect 4 58 65 71)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[29..0]" (rect 4 74 65 87)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 72 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 65 59 78 95)(font "Arial" (font_size 8))(vertical))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
+	)
+	(port
+		(pt 144 64)
+		(output)
+		(text "result[29..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[29..0]" (rect 84 50 139 63)(font "Arial" (font_size 8)))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 104))
+		(line (pt 64 24)(pt 80 32))
+		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 32)(pt 80 96))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp
new file mode 100644
index 0000000..38915ab
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component vga_mux
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
+	);
+end component;
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip
new file mode 100644
index 0000000..363283f
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "vga_mux.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vga_mux.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vga_mux.cmp"]
diff --git a/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd
new file mode 100644
index 0000000..1df4d5a
--- /dev/null
+++ b/student_files_2015/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd
@@ -0,0 +1,238 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_MUX 
+
+-- ============================================================
+-- File Name: vga_mux.vhd
+-- Megafunction Name(s):
+-- 			LPM_MUX
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY vga_mux IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
+	);
+END vga_mux;
+
+
+ARCHITECTURE SYN OF vga_mux IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 29 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(29 DOWNTO 0);
+	sub_wire4    <= data1x(29 DOWNTO 0);
+	sub_wire3    <= data2x(29 DOWNTO 0);
+	result    <= sub_wire0(29 DOWNTO 0);
+	sub_wire1    <= data3x(29 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+
+	LPM_MUX_component : LPM_MUX
+	GENERIC MAP (
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 30,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		data => sub_wire2,
+		sel => sel,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: data0x 0 0 30 0 INPUT NODEFVAL "data0x[29..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 30 0 INPUT NODEFVAL "data1x[29..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 30 0 INPUT NODEFVAL "data2x[29..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 30 0 INPUT NODEFVAL "data3x[29..0]"
+-- Retrieval info: USED_PORT: result 0 0 30 0 OUTPUT NODEFVAL "result[29..0]"
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
+-- Retrieval info: CONNECT: @data 1 0 30 0 data0x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 1 30 0 data1x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 2 30 0 data2x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 3 30 0 data3x 0 0 30 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: CONNECT: result 0 0 30 0 @result 0 0 30 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/._.DS_Store b/student_files_2015[2]/__MACOSX/student_files_2015/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/._.DS_Store
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/._launch_catapult.bat b/student_files_2015[2]/__MACOSX/student_files_2015/._launch_catapult.bat
new file mode 100644
index 0000000..14f037e
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/._launch_catapult.bat
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/._prj1 b/student_files_2015[2]/__MACOSX/student_files_2015/._prj1
new file mode 100644
index 0000000..9e21eaa
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/._prj1
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/._prj2 b/student_files_2015[2]/__MACOSX/student_files_2015/._prj2
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/._prj2
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/DE0_user_manual/._.DS_Store b/student_files_2015[2]/__MACOSX/student_files_2015/DE0_user_manual/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/DE0_user_manual/._.DS_Store
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/DE0_user_manual/._DE0_User_manual_2012.pdf b/student_files_2015[2]/__MACOSX/student_files_2015/DE0_user_manual/._DE0_User_manual_2012.pdf
new file mode 100644
index 0000000..f706d5e
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/DE0_user_manual/._DE0_User_manual_2012.pdf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._.DS_Store b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._.DS_Store
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._dot_product_source b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._dot_product_source
new file mode 100644
index 0000000..9e21eaa
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._dot_product_source
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._quartus_proj_DE0 b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._quartus_proj_DE0
new file mode 100644
index 0000000..c6b7c72
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/._quartus_proj_DE0
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.cpp b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.cpp
new file mode 100644
index 0000000..5ddb363
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.cpp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.h
new file mode 100644
index 0000000..5ddb363
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._dot_product.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._tb_dot_product.cpp b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._tb_dot_product.cpp
new file mode 100644
index 0000000..5ddb363
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/dot_product_source/._tb_dot_product.cpp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._.DS_Store b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._.DS_Store
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.bdf b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.bdf
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.bdf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.pin b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.pin
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.pin
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qpf b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qpf
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qpf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qsf
new file mode 100644
index 0000000..1bd5320
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj1/quartus_proj_DE0/._ise_proj.qsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._.DS_Store b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._.DS_Store
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._catapult_proj b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._catapult_proj
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._catapult_proj
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._instructions.doc b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._instructions.doc
new file mode 100644
index 0000000..43630d1
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._instructions.doc
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._quartus_proj b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._quartus_proj
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/._quartus_proj
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._.DS_Store b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._.DS_Store
new file mode 100644
index 0000000..09fa6bd
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._.DS_Store
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_blur b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_blur
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_blur
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_mouse b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_mouse
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/._vga_mouse
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.c b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.c
new file mode 100644
index 0000000..1ba2247
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.c
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._blur.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.cpp b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.cpp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.cpp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._bmp_io.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._shift_class.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._shift_class.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._shift_class.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._tb_blur.cpp b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._tb_blur.cpp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_blur/._tb_blur.cpp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_mouse/._vga_mouse_square.c b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_mouse/._vga_mouse_square.c
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/catapult_proj/vga_mouse/._vga_mouse_square.c
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA_MOUSE b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA_MOUSE
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/._DE0_CAMERA_MOUSE
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Copy of DE1_D5M.qsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Copy of DE1_D5M.qsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Copy of DE1_D5M.qsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.asm.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.asm.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.asm.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.done b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.done
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.done
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.smsg b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.smsg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.smsg
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.summary b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.fit.summary
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.flow.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.flow.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.flow.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.jdi b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.jdi
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.jdi
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.summary b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.map.summary
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pin b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pin
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pin
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pof b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.pof
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qpf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qpf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qpf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qsf.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qws b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qws
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.qws
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sdc b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sdc
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sdc
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sof b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sof
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.summary b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.sta.summary
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.tis_db_list.ddb b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE0_D5M.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE1_D5M_assignment_defaults.qdf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE1_D5M_assignment_defaults.qdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._DE1_D5M_assignment_defaults.qdf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Line_Buffer.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Line_Buffer.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Line_Buffer.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_Control_4Port b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_Control_4Port
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_Control_4Port
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_FIFO.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._Sdram_FIFO.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._TOP_CAMERA.bdf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._TOP_CAMERA.bdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._TOP_CAMERA.bdf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._V b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._V
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._V
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._demo batch b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._demo batch
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._demo batch
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._greybox_tmp b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._greybox_tmp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._greybox_tmp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._qmegawiz_errors_log.txt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._qmegawiz_errors_log.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._qmegawiz_errors_log.txt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._sdram_pll.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/._sdram_pll.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Control_4Port.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Control_4Port.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Control_4Port.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_FIFO.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Params.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Params.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._Sdram_Params.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._command.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._command.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._command.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._control_interface.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._control_interface.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._control_interface.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._sdr_data_path.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._sdr_data_path.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/._sdr_data_path.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._CCD_Capture.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._CCD_Capture.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._CCD_Capture.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_CCD_Config.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_Controller.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._I2C_Controller.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Line_Buffer.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._RAW2RGB.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._RAW2RGB.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._RAW2RGB.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Reset_Delay.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Reset_Delay.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._Reset_Delay.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT_8.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT_8.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._SEG7_LUT_8.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Controller.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Controller.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Param.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Param.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._VGA_Param.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.ppf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.ppf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.ppf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_wave0.jpg b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_wave0.jpg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_wave0.jpg
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_waveforms.html b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_waveforms.html
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/._sdram_pll_waveforms.html
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.bat b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.bat
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.bat
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.sof b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.sof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/._DE1_D5M.sof
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/._cbx_args.txt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/._cbx_args.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/._cbx_args.txt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.asm.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.asm.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.asm.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.cdf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.cdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.cdf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.done b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.done
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.done
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.smsg b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.smsg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.smsg
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.summary b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.fit.summary
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.flow.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.flow.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.flow.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.jdi b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.jdi
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.jdi
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.summary b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.map.summary
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pin b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pin
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pin
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pof b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.pof
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qpf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qpf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qpf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qsf.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qws b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qws
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.qws
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sdc b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sdc
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sdc
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sof b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sof
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sof
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.rpt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.rpt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.rpt
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.summary b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.summary
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.sta.summary
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.tis_db_list.ddb b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._DE0_D5M.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Line_Buffer.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Line_Buffer.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Line_Buffer.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_Control_4Port b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_Control_4Port
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_Control_4Port
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_FIFO.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._Sdram_FIFO.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._V b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._V
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._V
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._catapult_ip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._catapult_ip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._catapult_ip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._greybox_tmp b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._greybox_tmp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._greybox_tmp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga_core.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga_core.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._mean_vga_core.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._ps2.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._ps2.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._ps2.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._sdram_pll.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._sdram_pll.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square_core.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square_core.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mouse_square_core.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.cmp b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.cmp
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.cmp
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.vhd b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.vhd
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/._vga_mux.vhd
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Control_4Port.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Control_4Port.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Control_4Port.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_FIFO.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Params.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Params.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._Sdram_Params.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._command.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._command.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._command.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._control_interface.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._control_interface.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._control_interface.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._sdr_data_path.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._sdr_data_path.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/._sdr_data_path.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._CCD_Capture.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._CCD_Capture.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._CCD_Capture.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_CCD_Config.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_Controller.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._I2C_Controller.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Line_Buffer.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._RAW2RGB.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._RAW2RGB.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._RAW2RGB.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Reset_Delay.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Reset_Delay.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._Reset_Delay.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT_8.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT_8.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._SEG7_LUT_8.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._TOP_DE0_CAMERA_MOUSE.bdf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._TOP_DE0_CAMERA_MOUSE.bdf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._TOP_DE0_CAMERA_MOUSE.bdf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Controller.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Param.h b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Param.h
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._VGA_Param.h
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._ps2.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._ps2.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._ps2.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.bsf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.bsf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.bsf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.ppf b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.ppf
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.ppf
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.qip b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.qip
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.qip
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v.bak b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v.bak
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll.v.bak
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_wave0.jpg
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/._sdram_pll_waveforms.html
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3 b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._blur3x3
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/._mouse
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/._rtl_mgc_ioport_v2001.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/._rtl_mgc_ioport_v2001.v
diff --git a/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt
new file mode 100644
index 0000000..dfaecb5
--- /dev/null
+++ b/student_files_2015[2]/__MACOSX/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/._cbx_args.txt
diff --git a/student_files_2015[2]/student_files_2015/.DS_Store b/student_files_2015[2]/student_files_2015/.DS_Store
new file mode 100644
index 0000000..2095bfd
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/.DS_Store
diff --git a/student_files_2015[2]/student_files_2015/DE0_user_manual/.DS_Store b/student_files_2015[2]/student_files_2015/DE0_user_manual/.DS_Store
new file mode 100644
index 0000000..5008ddf
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/DE0_user_manual/.DS_Store
diff --git a/student_files_2015[2]/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf b/student_files_2015[2]/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf
new file mode 100644
index 0000000..c4831e1
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/DE0_user_manual/DE0_User_manual_2012.pdf
diff --git a/student_files_2015[2]/student_files_2015/launch_catapult.bat b/student_files_2015[2]/student_files_2015/launch_catapult.bat
new file mode 100644
index 0000000..f6e649e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/launch_catapult.bat
@@ -0,0 +1,3 @@
+@echo off
+set Path=
+"C:\Program Files\Calypto Design Systems\Catapult Synthesis 2011a.126 Production Release\Mgc_home\bin\catapult.exe"
diff --git a/student_files_2015[2]/student_files_2015/prj1/.DS_Store b/student_files_2015[2]/student_files_2015/prj1/.DS_Store
new file mode 100644
index 0000000..fd7d3a6
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/.DS_Store
diff --git a/student_files_2015[2]/student_files_2015/prj1/dot_product_source/dot_product.cpp b/student_files_2015[2]/student_files_2015/prj1/dot_product_source/dot_product.cpp
new file mode 100644
index 0000000..8fc78d5
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/dot_product_source/dot_product.cpp
@@ -0,0 +1,39 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           dot_product.cpp
+//  Description:    dot product calculator
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+#include "dot_product.h"
+#include "stdio.h"
+
+#pragma design top
+void dot_product(ac_int<8> *input_a, ac_int<8> *input_b, ac_int<8> *output) {
+  ac_int<8> acc = 0;
+  int i; 
+
+  MAC: for(i = 0; i < VECTOR_LEN; i++) {
+    acc += input_a[i] * *(input_b + i); 
+    /* you can access the values in the vector in either way: var[i] = *(var + i) */
+  }
+  *output = acc;
+}
+
+
+// end of file
diff --git a/student_files_2015[2]/student_files_2015/prj1/dot_product_source/dot_product.h b/student_files_2015[2]/student_files_2015/prj1/dot_product_source/dot_product.h
new file mode 100644
index 0000000..e67cc7f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/dot_product_source/dot_product.h
@@ -0,0 +1,35 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           dot_product.h
+//  Description:    dot product calculator
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _DOT_PROD_H
+#define _DOT_PROD_H
+
+#include "ac_int.h"
+
+#define VECTOR_LEN 5
+
+void dot_product(ac_int<8> *input_a, ac_int<8> *input_b, ac_int<8> *output);
+
+#endif
+
+// end of file
diff --git a/student_files_2015[2]/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp b/student_files_2015[2]/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
new file mode 100644
index 0000000..7f382cd
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp
@@ -0,0 +1,51 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_dot_product.cpp
+//  Description:    dot product calculator testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+
+#include "dot_product.h"
+#include <mc_scverify.h>
+
+CCS_MAIN(int argc, char *argv[])
+{
+  ac_int<8> inA[VECTOR_LEN] = {1,2,3,4,5};
+  ac_int<8> inB[VECTOR_LEN] = {5,4,3,2,1};
+  ac_int<8> output;
+  int i, exp_out;
+
+  // Test design
+  CCS_DESIGN(dot_product)(inA,inB,&output);
+
+  // Expected result  
+  exp_out = 0;
+  for(i = 0; i < VECTOR_LEN; i++) {
+    exp_out += inA[i] * inB[i];
+  }
+
+  // Display results
+  for(i = 0; i < VECTOR_LEN; i++) {
+    printf ("Inputs: A = %d, B = %d \n", (int)inA[i], (int)inB[i]);
+  }
+  printf ("Design output  : %d \n", (int)output);
+  printf ("Expected output: %d \n", exp_out);
+   
+  CCS_RETURN(0);
+}
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/.DS_Store b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/.DS_Store
new file mode 100644
index 0000000..5008ddf
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/.DS_Store
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.cdb
new file mode 100644
index 0000000..02c7749
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.hdb
new file mode 100644
index 0000000..07fa365
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(0).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.cdb
new file mode 100644
index 0000000..5f275ae
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.hdb
new file mode 100644
index 0000000..44624d1
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(1).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.cdb
new file mode 100644
index 0000000..170554e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.hdb
new file mode 100644
index 0000000..fb7ed28
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(2).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.cdb
new file mode 100644
index 0000000..b8eaa8c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.hdb
new file mode 100644
index 0000000..fb7ed28
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(3).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.cdb
new file mode 100644
index 0000000..16b4ad9
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.hdb
new file mode 100644
index 0000000..2899bcd
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(4).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.cdb
new file mode 100644
index 0000000..bb32ce7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.hdb
new file mode 100644
index 0000000..cfc9d46
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(5).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.cdb
new file mode 100644
index 0000000..7d0450d
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.hdb
new file mode 100644
index 0000000..2967f6f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(6).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.cdb
new file mode 100644
index 0000000..056cfad
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.hdb
new file mode 100644
index 0000000..3b43956
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.(7).cnf.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.bpm b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.bpm
new file mode 100644
index 0000000..d576aaf
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.bpm
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.cdb
new file mode 100644
index 0000000..71a85c9
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.hdb
new file mode 100644
index 0000000..2b1a406
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ace_cmp.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.qmsg b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.qmsg
new file mode 100644
index 0000000..9407db7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848314932 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848314933 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:05:14 2016 " "Processing started: Tue Mar 01 16:05:14 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848314933 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1456848314933 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj " "Command: quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1456848314933 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1456848315621 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1456848315638 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "424 " "Peak virtual memory: 424 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848315866 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:15 2016 " "Processing ended: Tue Mar 01 16:05:15 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848315866 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848315866 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848315866 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1456848315866 ""}
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.rdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.rdb
new file mode 100644
index 0000000..c18f915
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm.rdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm_labs.ddb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm_labs.ddb
new file mode 100644
index 0000000..9d1c0e7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.asm_labs.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cbx.xml b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cbx.xml
new file mode 100644
index 0000000..a82e4db
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cbx.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" ?>
+<LOG_ROOT>
+	<PROJECT NAME="ise_proj">
+		<CBX_INST_ENTRY INSTANCE_NAME="|ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0" CBX_FILE_NAME="mult_a7t.tdf"/>
+	</PROJECT>
+</LOG_ROOT>
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.bpm b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.bpm
new file mode 100644
index 0000000..d576aaf
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.bpm
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.cdb
new file mode 100644
index 0000000..71a85c9
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.hdb
new file mode 100644
index 0000000..2b1a406
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.idb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.idb
new file mode 100644
index 0000000..75d0479
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.idb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.kpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.kpt
new file mode 100644
index 0000000..a6e2c9a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.kpt
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.logdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.logdb
new file mode 100644
index 0000000..0ae295b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.logdb
@@ -0,0 +1,93 @@
+v1
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,48;0;48;0;0;51;48;0;51;51;0;3;0;0;17;0;3;17;0;0;0;3;0;0;0;0;0;51;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,3;51;3;51;51;0;3;51;0;0;51;48;51;51;34;51;48;34;51;51;51;48;51;51;51;51;51;0;51;51,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,VGA_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_SYNC,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_BLANK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_VS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_HS,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,HEX0_D[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDG[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BUTTON[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BUTTON[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_B[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_G[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,VGA_R[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_MSDAT,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,PS2_MSCLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,CLOCK_50_2,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,BUTTON[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.rdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.rdb
new file mode 100644
index 0000000..03c180a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp.rdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp_merge.kpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp_merge.kpt
new file mode 100644
index 0000000..3f1d0e8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cmp_merge.kpt
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..da9e360
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
new file mode 100644
index 0000000..c2d6061
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.db_info b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.db_info
new file mode 100644
index 0000000..7693551
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 01 16:04:21 2016
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.eco.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.eco.cdb
new file mode 100644
index 0000000..74d5728
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.eco.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.fit.qmsg b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.fit.qmsg
new file mode 100644
index 0000000..9e7e1f8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.fit.qmsg
@@ -0,0 +1,49 @@
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1456848309046 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "ise_proj EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"ise_proj\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1456848309276 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456848309318 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456848309319 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1456848309319 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1456848309384 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456848309563 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456848309563 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1456848309563 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1456848309563 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 573 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848309564 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 575 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848309564 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 577 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848309564 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 579 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1456848309564 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1456848309564 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1456848309565 ""}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 51 " "No exact pin location assignment(s) for 3 pins of 51 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_CLK " "Pin VGA_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_CLK } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 680 32 208 696 "VGA_CLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 58 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456848310256 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_SYNC " "Pin VGA_SYNC not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_SYNC } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 656 32 208 672 "VGA_SYNC" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_SYNC } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 59 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456848310256 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "VGA_BLANK " "Pin VGA_BLANK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { VGA_BLANK } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 632 32 208 648 "VGA_BLANK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { VGA_BLANK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 60 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1456848310256 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1456848310256 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ise_proj.sdc " "Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1456848310386 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1456848310386 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1456848310387 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1456848310388 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." {  } {  } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1456848310388 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1456848310533 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456848310533 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1456848310533 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456848310534 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1456848310534 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1456848310534 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1456848310534 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1456848310535 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1456848310544 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1456848310544 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1456848310544 ""}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 2.5V 0 3 0 " "Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 0 input, 3 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1456848310552 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1456848310552 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1456848310552 ""}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 27 6 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 2 44 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  44 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 15 28 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 8 39 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  39 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1456848310553 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1456848310553 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1456848310553 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[0\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[10\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[11\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[12\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[1\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[2\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[3\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[4\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[5\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[6\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[7\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[8\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_ADDR\[9\] " "Ignored I/O standard assignment to node \"DRAM_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA_0 " "Ignored I/O standard assignment to node \"DRAM_BA_0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_BA_1 " "Ignored I/O standard assignment to node \"DRAM_BA_1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CAS_N " "Ignored I/O standard assignment to node \"DRAM_CAS_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CKE " "Ignored I/O standard assignment to node \"DRAM_CKE\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CLK " "Ignored I/O standard assignment to node \"DRAM_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_CS_N " "Ignored I/O standard assignment to node \"DRAM_CS_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[0\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[10\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[11\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[12\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[13\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[14\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[15\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[1\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[2\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[3\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[4\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[5\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[6\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[7\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[8\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_DQ\[9\] " "Ignored I/O standard assignment to node \"DRAM_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_LDQM " "Ignored I/O standard assignment to node \"DRAM_LDQM\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_RAS_N " "Ignored I/O standard assignment to node \"DRAM_RAS_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_UDQM " "Ignored I/O standard assignment to node \"DRAM_UDQM\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "DRAM_WE_N " "Ignored I/O standard assignment to node \"DRAM_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[0\] " "Ignored I/O standard assignment to node \"FL_ADDR\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[10\] " "Ignored I/O standard assignment to node \"FL_ADDR\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[11\] " "Ignored I/O standard assignment to node \"FL_ADDR\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[12\] " "Ignored I/O standard assignment to node \"FL_ADDR\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[13\] " "Ignored I/O standard assignment to node \"FL_ADDR\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[14\] " "Ignored I/O standard assignment to node \"FL_ADDR\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[15\] " "Ignored I/O standard assignment to node \"FL_ADDR\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[16\] " "Ignored I/O standard assignment to node \"FL_ADDR\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[17\] " "Ignored I/O standard assignment to node \"FL_ADDR\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[18\] " "Ignored I/O standard assignment to node \"FL_ADDR\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[19\] " "Ignored I/O standard assignment to node \"FL_ADDR\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[1\] " "Ignored I/O standard assignment to node \"FL_ADDR\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[20\] " "Ignored I/O standard assignment to node \"FL_ADDR\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[21\] " "Ignored I/O standard assignment to node \"FL_ADDR\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[2\] " "Ignored I/O standard assignment to node \"FL_ADDR\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[3\] " "Ignored I/O standard assignment to node \"FL_ADDR\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[4\] " "Ignored I/O standard assignment to node \"FL_ADDR\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[5\] " "Ignored I/O standard assignment to node \"FL_ADDR\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[6\] " "Ignored I/O standard assignment to node \"FL_ADDR\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[7\] " "Ignored I/O standard assignment to node \"FL_ADDR\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[8\] " "Ignored I/O standard assignment to node \"FL_ADDR\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_ADDR\[9\] " "Ignored I/O standard assignment to node \"FL_ADDR\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_BYTE_N " "Ignored I/O standard assignment to node \"FL_BYTE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_CE_N " "Ignored I/O standard assignment to node \"FL_CE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ15_AM1 " "Ignored I/O standard assignment to node \"FL_DQ15_AM1\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[0\] " "Ignored I/O standard assignment to node \"FL_DQ\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[10\] " "Ignored I/O standard assignment to node \"FL_DQ\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[11\] " "Ignored I/O standard assignment to node \"FL_DQ\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[12\] " "Ignored I/O standard assignment to node \"FL_DQ\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[13\] " "Ignored I/O standard assignment to node \"FL_DQ\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[14\] " "Ignored I/O standard assignment to node \"FL_DQ\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[1\] " "Ignored I/O standard assignment to node \"FL_DQ\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[2\] " "Ignored I/O standard assignment to node \"FL_DQ\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[3\] " "Ignored I/O standard assignment to node \"FL_DQ\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[4\] " "Ignored I/O standard assignment to node \"FL_DQ\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[5\] " "Ignored I/O standard assignment to node \"FL_DQ\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[6\] " "Ignored I/O standard assignment to node \"FL_DQ\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[7\] " "Ignored I/O standard assignment to node \"FL_DQ\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[8\] " "Ignored I/O standard assignment to node \"FL_DQ\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_DQ\[9\] " "Ignored I/O standard assignment to node \"FL_DQ\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_OE_N " "Ignored I/O standard assignment to node \"FL_OE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RST_N " "Ignored I/O standard assignment to node \"FL_RST_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_RY " "Ignored I/O standard assignment to node \"FL_RY\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WE_N " "Ignored I/O standard assignment to node \"FL_WE_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "FL_WP_N " "Ignored I/O standard assignment to node \"FL_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO0_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[0\] " "Ignored I/O standard assignment to node \"GPIO0_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[10\] " "Ignored I/O standard assignment to node \"GPIO0_D\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[11\] " "Ignored I/O standard assignment to node \"GPIO0_D\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[12\] " "Ignored I/O standard assignment to node \"GPIO0_D\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[13\] " "Ignored I/O standard assignment to node \"GPIO0_D\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[14\] " "Ignored I/O standard assignment to node \"GPIO0_D\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[15\] " "Ignored I/O standard assignment to node \"GPIO0_D\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[16\] " "Ignored I/O standard assignment to node \"GPIO0_D\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[17\] " "Ignored I/O standard assignment to node \"GPIO0_D\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[18\] " "Ignored I/O standard assignment to node \"GPIO0_D\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[19\] " "Ignored I/O standard assignment to node \"GPIO0_D\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[1\] " "Ignored I/O standard assignment to node \"GPIO0_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[20\] " "Ignored I/O standard assignment to node \"GPIO0_D\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[21\] " "Ignored I/O standard assignment to node \"GPIO0_D\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[22\] " "Ignored I/O standard assignment to node \"GPIO0_D\[22\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[22\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[23\] " "Ignored I/O standard assignment to node \"GPIO0_D\[23\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[23\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[24\] " "Ignored I/O standard assignment to node \"GPIO0_D\[24\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[24\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[25\] " "Ignored I/O standard assignment to node \"GPIO0_D\[25\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[25\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[26\] " "Ignored I/O standard assignment to node \"GPIO0_D\[26\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[26\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[27\] " "Ignored I/O standard assignment to node \"GPIO0_D\[27\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[27\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[28\] " "Ignored I/O standard assignment to node \"GPIO0_D\[28\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[28\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[29\] " "Ignored I/O standard assignment to node \"GPIO0_D\[29\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[29\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[2\] " "Ignored I/O standard assignment to node \"GPIO0_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[30\] " "Ignored I/O standard assignment to node \"GPIO0_D\[30\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[30\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[31\] " "Ignored I/O standard assignment to node \"GPIO0_D\[31\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[31\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[3\] " "Ignored I/O standard assignment to node \"GPIO0_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[4\] " "Ignored I/O standard assignment to node \"GPIO0_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[5\] " "Ignored I/O standard assignment to node \"GPIO0_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[6\] " "Ignored I/O standard assignment to node \"GPIO0_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[7\] " "Ignored I/O standard assignment to node \"GPIO0_D\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[8\] " "Ignored I/O standard assignment to node \"GPIO0_D\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO0_D\[9\] " "Ignored I/O standard assignment to node \"GPIO0_D\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKIN\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Ignored I/O standard assignment to node \"GPIO1_CLKOUT\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[0\] " "Ignored I/O standard assignment to node \"GPIO1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[10\] " "Ignored I/O standard assignment to node \"GPIO1_D\[10\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[10\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[11\] " "Ignored I/O standard assignment to node \"GPIO1_D\[11\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[11\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[12\] " "Ignored I/O standard assignment to node \"GPIO1_D\[12\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[12\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[13\] " "Ignored I/O standard assignment to node \"GPIO1_D\[13\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[13\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[14\] " "Ignored I/O standard assignment to node \"GPIO1_D\[14\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[14\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[15\] " "Ignored I/O standard assignment to node \"GPIO1_D\[15\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[15\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[16\] " "Ignored I/O standard assignment to node \"GPIO1_D\[16\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[16\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[17\] " "Ignored I/O standard assignment to node \"GPIO1_D\[17\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[17\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[18\] " "Ignored I/O standard assignment to node \"GPIO1_D\[18\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[18\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[19\] " "Ignored I/O standard assignment to node \"GPIO1_D\[19\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[19\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[1\] " "Ignored I/O standard assignment to node \"GPIO1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[20\] " "Ignored I/O standard assignment to node \"GPIO1_D\[20\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[20\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[21\] " "Ignored I/O standard assignment to node \"GPIO1_D\[21\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[21\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[22\] " "Ignored I/O standard assignment to node \"GPIO1_D\[22\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[22\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[23\] " "Ignored I/O standard assignment to node \"GPIO1_D\[23\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[23\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[24\] " "Ignored I/O standard assignment to node \"GPIO1_D\[24\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[24\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[25\] " "Ignored I/O standard assignment to node \"GPIO1_D\[25\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[25\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[26\] " "Ignored I/O standard assignment to node \"GPIO1_D\[26\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[26\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[27\] " "Ignored I/O standard assignment to node \"GPIO1_D\[27\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[27\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[28\] " "Ignored I/O standard assignment to node \"GPIO1_D\[28\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[28\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[29\] " "Ignored I/O standard assignment to node \"GPIO1_D\[29\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[29\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[2\] " "Ignored I/O standard assignment to node \"GPIO1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[30\] " "Ignored I/O standard assignment to node \"GPIO1_D\[30\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[30\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[31\] " "Ignored I/O standard assignment to node \"GPIO1_D\[31\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[31\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[3\] " "Ignored I/O standard assignment to node \"GPIO1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[4\] " "Ignored I/O standard assignment to node \"GPIO1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[5\] " "Ignored I/O standard assignment to node \"GPIO1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[6\] " "Ignored I/O standard assignment to node \"GPIO1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[7\] " "Ignored I/O standard assignment to node \"GPIO1_D\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[8\] " "Ignored I/O standard assignment to node \"GPIO1_D\[8\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[8\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO1_D\[9\] " "Ignored I/O standard assignment to node \"GPIO1_D\[9\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[9\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX0_DP " "Ignored I/O standard assignment to node \"HEX0_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_DP " "Ignored I/O standard assignment to node \"HEX1_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[0\] " "Ignored I/O standard assignment to node \"HEX1_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[1\] " "Ignored I/O standard assignment to node \"HEX1_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[2\] " "Ignored I/O standard assignment to node \"HEX1_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[3\] " "Ignored I/O standard assignment to node \"HEX1_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[4\] " "Ignored I/O standard assignment to node \"HEX1_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[5\] " "Ignored I/O standard assignment to node \"HEX1_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX1_D\[6\] " "Ignored I/O standard assignment to node \"HEX1_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_DP " "Ignored I/O standard assignment to node \"HEX2_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[0\] " "Ignored I/O standard assignment to node \"HEX2_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[1\] " "Ignored I/O standard assignment to node \"HEX2_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[2\] " "Ignored I/O standard assignment to node \"HEX2_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[3\] " "Ignored I/O standard assignment to node \"HEX2_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[4\] " "Ignored I/O standard assignment to node \"HEX2_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[5\] " "Ignored I/O standard assignment to node \"HEX2_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX2_D\[6\] " "Ignored I/O standard assignment to node \"HEX2_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_DP " "Ignored I/O standard assignment to node \"HEX3_DP\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[0\] " "Ignored I/O standard assignment to node \"HEX3_D\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[1\] " "Ignored I/O standard assignment to node \"HEX3_D\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[2\] " "Ignored I/O standard assignment to node \"HEX3_D\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[3\] " "Ignored I/O standard assignment to node \"HEX3_D\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[4\] " "Ignored I/O standard assignment to node \"HEX3_D\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[5\] " "Ignored I/O standard assignment to node \"HEX3_D\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "HEX3_D\[6\] " "Ignored I/O standard assignment to node \"HEX3_D\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_BLON " "Ignored I/O standard assignment to node \"LCD_BLON\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[0\] " "Ignored I/O standard assignment to node \"LCD_DATA\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[1\] " "Ignored I/O standard assignment to node \"LCD_DATA\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[2\] " "Ignored I/O standard assignment to node \"LCD_DATA\[2\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[3\] " "Ignored I/O standard assignment to node \"LCD_DATA\[3\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[4\] " "Ignored I/O standard assignment to node \"LCD_DATA\[4\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[5\] " "Ignored I/O standard assignment to node \"LCD_DATA\[5\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[6\] " "Ignored I/O standard assignment to node \"LCD_DATA\[6\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_DATA\[7\] " "Ignored I/O standard assignment to node \"LCD_DATA\[7\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_EN " "Ignored I/O standard assignment to node \"LCD_EN\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RS " "Ignored I/O standard assignment to node \"LCD_RS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "LCD_RW " "Ignored I/O standard assignment to node \"LCD_RW\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBCLK " "Ignored I/O standard assignment to node \"PS2_KBCLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "PS2_KBDAT " "Ignored I/O standard assignment to node \"PS2_KBDAT\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CLK " "Ignored I/O standard assignment to node \"SD_CLK\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_CMD " "Ignored I/O standard assignment to node \"SD_CMD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT0 " "Ignored I/O standard assignment to node \"SD_DAT0\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_DAT3 " "Ignored I/O standard assignment to node \"SD_DAT3\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "SD_WP_N " "Ignored I/O standard assignment to node \"SD_WP_N\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_CTS " "Ignored I/O standard assignment to node \"UART_CTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RTS " "Ignored I/O standard assignment to node \"UART_RTS\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_RXD " "Ignored I/O standard assignment to node \"UART_RXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "UART_TXD " "Ignored I/O standard assignment to node \"UART_TXD\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848310578 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1456848310578 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_0 " "Node \"DRAM_BA_0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA_1 " "Node \"DRAM_BA_1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_BA_1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_LDQM " "Node \"DRAM_LDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_LDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_UDQM " "Node \"DRAM_UDQM\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_UDQM" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_BYTE_N " "Node \"FL_BYTE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_BYTE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ15_AM1 " "Node \"FL_DQ15_AM1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ15_AM1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[10\] " "Node \"FL_DQ\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[11\] " "Node \"FL_DQ\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[12\] " "Node \"FL_DQ\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[13\] " "Node \"FL_DQ\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[14\] " "Node \"FL_DQ\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[8\] " "Node \"FL_DQ\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[9\] " "Node \"FL_DQ\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKIN\[0\] " "Node \"GPIO0_CLKIN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKIN\[1\] " "Node \"GPIO0_CLKIN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKIN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKOUT\[0\] " "Node \"GPIO0_CLKOUT\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_CLKOUT\[1\] " "Node \"GPIO0_CLKOUT\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_CLKOUT\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[0\] " "Node \"GPIO0_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[10\] " "Node \"GPIO0_D\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[11\] " "Node \"GPIO0_D\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[12\] " "Node \"GPIO0_D\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[13\] " "Node \"GPIO0_D\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[14\] " "Node \"GPIO0_D\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[15\] " "Node \"GPIO0_D\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[16\] " "Node \"GPIO0_D\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[17\] " "Node \"GPIO0_D\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[18\] " "Node \"GPIO0_D\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[19\] " "Node \"GPIO0_D\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[1\] " "Node \"GPIO0_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[20\] " "Node \"GPIO0_D\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[21\] " "Node \"GPIO0_D\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[22\] " "Node \"GPIO0_D\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[23\] " "Node \"GPIO0_D\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[24\] " "Node \"GPIO0_D\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[25\] " "Node \"GPIO0_D\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[26\] " "Node \"GPIO0_D\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[27\] " "Node \"GPIO0_D\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[28\] " "Node \"GPIO0_D\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[29\] " "Node \"GPIO0_D\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[2\] " "Node \"GPIO0_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[30\] " "Node \"GPIO0_D\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[31\] " "Node \"GPIO0_D\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[3\] " "Node \"GPIO0_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[4\] " "Node \"GPIO0_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[5\] " "Node \"GPIO0_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[6\] " "Node \"GPIO0_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[7\] " "Node \"GPIO0_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[8\] " "Node \"GPIO0_D\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO0_D\[9\] " "Node \"GPIO0_D\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO0_D\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKIN\[0\] " "Node \"GPIO1_CLKIN\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKIN\[1\] " "Node \"GPIO1_CLKIN\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKIN\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKOUT\[0\] " "Node \"GPIO1_CLKOUT\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_CLKOUT\[1\] " "Node \"GPIO1_CLKOUT\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_CLKOUT\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[0\] " "Node \"GPIO1_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[10\] " "Node \"GPIO1_D\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[11\] " "Node \"GPIO1_D\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[12\] " "Node \"GPIO1_D\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[13\] " "Node \"GPIO1_D\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[14\] " "Node \"GPIO1_D\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[15\] " "Node \"GPIO1_D\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[16\] " "Node \"GPIO1_D\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[17\] " "Node \"GPIO1_D\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[18\] " "Node \"GPIO1_D\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[19\] " "Node \"GPIO1_D\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[1\] " "Node \"GPIO1_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[20\] " "Node \"GPIO1_D\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[21\] " "Node \"GPIO1_D\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[22\] " "Node \"GPIO1_D\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[23\] " "Node \"GPIO1_D\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[24\] " "Node \"GPIO1_D\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[25\] " "Node \"GPIO1_D\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[26\] " "Node \"GPIO1_D\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[27\] " "Node \"GPIO1_D\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[28\] " "Node \"GPIO1_D\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[29\] " "Node \"GPIO1_D\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[2\] " "Node \"GPIO1_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[30\] " "Node \"GPIO1_D\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[31\] " "Node \"GPIO1_D\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[3\] " "Node \"GPIO1_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[4\] " "Node \"GPIO1_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[5\] " "Node \"GPIO1_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[6\] " "Node \"GPIO1_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[7\] " "Node \"GPIO1_D\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[8\] " "Node \"GPIO1_D\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO1_D\[9\] " "Node \"GPIO1_D\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO1_D\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[0\] " "Node \"GPIO_0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[10\] " "Node \"GPIO_0\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[11\] " "Node \"GPIO_0\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[12\] " "Node \"GPIO_0\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[13\] " "Node \"GPIO_0\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[14\] " "Node \"GPIO_0\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[15\] " "Node \"GPIO_0\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[16\] " "Node \"GPIO_0\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[17\] " "Node \"GPIO_0\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[18\] " "Node \"GPIO_0\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[19\] " "Node \"GPIO_0\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[1\] " "Node \"GPIO_0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[20\] " "Node \"GPIO_0\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[21\] " "Node \"GPIO_0\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[22\] " "Node \"GPIO_0\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[23\] " "Node \"GPIO_0\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[24\] " "Node \"GPIO_0\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[25\] " "Node \"GPIO_0\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[26\] " "Node \"GPIO_0\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[27\] " "Node \"GPIO_0\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[28\] " "Node \"GPIO_0\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[29\] " "Node \"GPIO_0\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[2\] " "Node \"GPIO_0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[30\] " "Node \"GPIO_0\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[31\] " "Node \"GPIO_0\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[3\] " "Node \"GPIO_0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[4\] " "Node \"GPIO_0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[5\] " "Node \"GPIO_0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[6\] " "Node \"GPIO_0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[7\] " "Node \"GPIO_0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[8\] " "Node \"GPIO_0\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0\[9\] " "Node \"GPIO_0\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[0\] " "Node \"GPIO_1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[10\] " "Node \"GPIO_1\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[11\] " "Node \"GPIO_1\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[12\] " "Node \"GPIO_1\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[13\] " "Node \"GPIO_1\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[14\] " "Node \"GPIO_1\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[15\] " "Node \"GPIO_1\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[16\] " "Node \"GPIO_1\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[17\] " "Node \"GPIO_1\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[18\] " "Node \"GPIO_1\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[19\] " "Node \"GPIO_1\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[1\] " "Node \"GPIO_1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[20\] " "Node \"GPIO_1\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[21\] " "Node \"GPIO_1\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[22\] " "Node \"GPIO_1\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[23\] " "Node \"GPIO_1\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[24\] " "Node \"GPIO_1\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[25\] " "Node \"GPIO_1\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[26\] " "Node \"GPIO_1\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[27\] " "Node \"GPIO_1\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[28\] " "Node \"GPIO_1\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[29\] " "Node \"GPIO_1\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[2\] " "Node \"GPIO_1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[30\] " "Node \"GPIO_1\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[31\] " "Node \"GPIO_1\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[3\] " "Node \"GPIO_1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[4\] " "Node \"GPIO_1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[5\] " "Node \"GPIO_1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[6\] " "Node \"GPIO_1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[7\] " "Node \"GPIO_1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[8\] " "Node \"GPIO_1\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1\[9\] " "Node \"GPIO_1\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_N0 " "Node \"GPIO_CLKIN_N0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_N0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_N1 " "Node \"GPIO_CLKIN_N1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_N1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_P0 " "Node \"GPIO_CLKIN_P0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_P0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKIN_P1 " "Node \"GPIO_CLKIN_P1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKIN_P1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_N0 " "Node \"GPIO_CLKOUT_N0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_N0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_N1 " "Node \"GPIO_CLKOUT_N1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_N1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_P0 " "Node \"GPIO_CLKOUT_P0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_P0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_CLKOUT_P1 " "Node \"GPIO_CLKOUT_P1\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_CLKOUT_P1" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[7\] " "Node \"HEX0\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0_DP " "Node \"HEX0_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX0_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[7\] " "Node \"HEX1\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_DP " "Node \"HEX1_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[0\] " "Node \"HEX1_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[1\] " "Node \"HEX1_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[2\] " "Node \"HEX1_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[3\] " "Node \"HEX1_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[4\] " "Node \"HEX1_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[5\] " "Node \"HEX1_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1_D\[6\] " "Node \"HEX1_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX1_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[7\] " "Node \"HEX2\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_DP " "Node \"HEX2_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[0\] " "Node \"HEX2_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[1\] " "Node \"HEX2_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[2\] " "Node \"HEX2_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[3\] " "Node \"HEX2_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[4\] " "Node \"HEX2_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[5\] " "Node \"HEX2_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2_D\[6\] " "Node \"HEX2_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX2_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[7\] " "Node \"HEX3\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_DP " "Node \"HEX3_DP\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_DP" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[0\] " "Node \"HEX3_D\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[1\] " "Node \"HEX3_D\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[2\] " "Node \"HEX3_D\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[3\] " "Node \"HEX3_D\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[4\] " "Node \"HEX3_D\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[5\] " "Node \"HEX3_D\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3_D\[6\] " "Node \"HEX3_D\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "HEX3_D\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_KBCLK " "Node \"PS2_KBCLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBCLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_KBDAT " "Node \"PS2_KBDAT\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_KBDAT" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT0 " "Node \"SD_DAT0\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT0" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT3 " "Node \"SD_DAT3\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1456848310587 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1456848310587 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848310602 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1456848311067 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848311117 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1456848311124 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1456848311440 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848311440 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1456848311609 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y20 X9_Y29 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29" {  } { { "loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29"} 0 20 10 10 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1456848311995 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1456848311995 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848312146 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1456848312148 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1456848312148 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1456848312153 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456848312178 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456848312416 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1456848312440 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1456848312702 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1456848313014 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1456848313634 ""}
+{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "17 Cyclone III " "17 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BUTTON\[1\] 3.3-V LVTTL G3 " "Pin BUTTON\[1\] uses I/O standard 3.3-V LVTTL at G3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BUTTON[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[1\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BUTTON[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 34 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BUTTON\[0\] 3.3-V LVTTL H2 " "Pin BUTTON\[0\] uses I/O standard 3.3-V LVTTL at H2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BUTTON[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[0\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BUTTON[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 35 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_MSDAT 3.3-V LVTTL R22 " "Pin PS2_MSDAT uses I/O standard 3.3-V LVTTL at R22" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_MSDAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_MSDAT" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 416 40 208 432 "PS2_MSDAT" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_MSDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 63 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PS2_MSCLK 3.3-V LVTTL R21 " "Pin PS2_MSCLK uses I/O standard 3.3-V LVTTL at R21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_MSCLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_MSCLK" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 440 40 208 456 "PS2_MSCLK" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_MSCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 64 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50 3.3-V LVTTL G21 " "Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 88 40 208 104 "CLOCK_50" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 65 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK_50_2 3.3-V LVTTL B12 " "Pin CLOCK_50_2 uses I/O standard 3.3-V LVTTL at B12" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50_2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50_2" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 56 40 208 72 "CLOCK_50_2" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 66 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[3\] 3.3-V LVTTL G4 " "Pin SW\[3\] uses I/O standard 3.3-V LVTTL at G4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 42 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[2\] 3.3-V LVTTL H6 " "Pin SW\[2\] uses I/O standard 3.3-V LVTTL at H6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 43 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[1\] 3.3-V LVTTL H5 " "Pin SW\[1\] uses I/O standard 3.3-V LVTTL at H5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 44 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BUTTON\[2\] 3.3-V LVTTL F1 " "Pin BUTTON\[2\] uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { BUTTON[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "BUTTON\[2\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BUTTON[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 33 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[9\] 3.3-V LVTTL D2 " "Pin SW\[9\] uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 36 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[8\] 3.3-V LVTTL E4 " "Pin SW\[8\] uses I/O standard 3.3-V LVTTL at E4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[8\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 37 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[7\] 3.3-V LVTTL E3 " "Pin SW\[7\] uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 38 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[6\] 3.3-V LVTTL H7 " "Pin SW\[6\] uses I/O standard 3.3-V LVTTL at H7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 39 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[5\] 3.3-V LVTTL J7 " "Pin SW\[5\] uses I/O standard 3.3-V LVTTL at J7" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 40 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[0\] 3.3-V LVTTL J6 " "Pin SW\[0\] uses I/O standard 3.3-V LVTTL at J6" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 45 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SW\[4\] 3.3-V LVTTL G5 " "Pin SW\[4\] uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 240 40 208 256 "SW" "" } } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/" { { 0 { 0 ""} 0 41 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1456848313640 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1456848313640 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg " "Generated suppressed messages file C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1456848313718 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 524 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 524 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1070 " "Peak virtual memory: 1070 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848313892 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:13 2016 " "Processing ended: Tue Mar 01 16:05:13 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848313892 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848313892 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848313892 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1456848313892 ""}
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hier_info b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hier_info
new file mode 100644
index 0000000..eb5a7db
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hier_info
@@ -0,0 +1,228 @@
+|ise_proj
+VGA_CLK <= <GND>
+VGA_SYNC <= <GND>
+VGA_BLANK <= <GND>
+VGA_VS <= <GND>
+VGA_HS <= <GND>
+HEX0_D[0] <= <GND>
+HEX0_D[1] <= <GND>
+HEX0_D[2] <= <GND>
+HEX0_D[3] <= <GND>
+HEX0_D[4] <= <GND>
+HEX0_D[5] <= <GND>
+HEX0_D[6] <= <GND>
+LEDG[0] <= dot_product:inst.output_rsc_z[0]
+LEDG[1] <= dot_product:inst.output_rsc_z[1]
+LEDG[2] <= dot_product:inst.output_rsc_z[2]
+LEDG[3] <= dot_product:inst.output_rsc_z[3]
+LEDG[4] <= dot_product:inst.output_rsc_z[4]
+LEDG[5] <= dot_product:inst.output_rsc_z[5]
+LEDG[6] <= dot_product:inst.output_rsc_z[6]
+LEDG[7] <= dot_product:inst.output_rsc_z[7]
+LEDG[8] <= <GND>
+LEDG[9] <= <GND>
+BUTTON[0] => ~NO_FANOUT~
+BUTTON[1] => ~NO_FANOUT~
+BUTTON[2] => dot_product:inst.clk
+SW[0] => dot_product:inst.input_b_rsc_z[0]
+SW[1] => dot_product:inst.input_b_rsc_z[1]
+SW[2] => dot_product:inst.input_b_rsc_z[2]
+SW[3] => dot_product:inst.input_b_rsc_z[3]
+SW[4] => dot_product:inst.input_a_rsc_z[0]
+SW[5] => dot_product:inst.input_a_rsc_z[1]
+SW[6] => dot_product:inst.input_a_rsc_z[2]
+SW[7] => dot_product:inst.input_a_rsc_z[3]
+SW[8] => dot_product:inst.en
+SW[9] => dot_product:inst.arst_n
+VGA_B[0] <= <GND>
+VGA_B[1] <= <GND>
+VGA_B[2] <= <GND>
+VGA_B[3] <= <GND>
+VGA_G[0] <= <GND>
+VGA_G[1] <= <GND>
+VGA_G[2] <= <GND>
+VGA_G[3] <= <GND>
+VGA_R[0] <= <GND>
+VGA_R[1] <= <GND>
+VGA_R[2] <= <GND>
+VGA_R[3] <= <GND>
+PS2_MSDAT => ~NO_FANOUT~
+PS2_MSCLK => ~NO_FANOUT~
+CLOCK_50 => ~NO_FANOUT~
+CLOCK_50_2 => ~NO_FANOUT~
+
+
+|ise_proj|dot_product:inst
+input_a_rsc_z[0] => input_a_rsc_z[0].IN1
+input_a_rsc_z[1] => input_a_rsc_z[1].IN1
+input_a_rsc_z[2] => input_a_rsc_z[2].IN1
+input_a_rsc_z[3] => input_a_rsc_z[3].IN1
+input_a_rsc_z[4] => input_a_rsc_z[4].IN1
+input_a_rsc_z[5] => input_a_rsc_z[5].IN1
+input_a_rsc_z[6] => input_a_rsc_z[6].IN1
+input_a_rsc_z[7] => input_a_rsc_z[7].IN1
+input_b_rsc_z[0] => input_b_rsc_z[0].IN1
+input_b_rsc_z[1] => input_b_rsc_z[1].IN1
+input_b_rsc_z[2] => input_b_rsc_z[2].IN1
+input_b_rsc_z[3] => input_b_rsc_z[3].IN1
+input_b_rsc_z[4] => input_b_rsc_z[4].IN1
+input_b_rsc_z[5] => input_b_rsc_z[5].IN1
+input_b_rsc_z[6] => input_b_rsc_z[6].IN1
+input_b_rsc_z[7] => input_b_rsc_z[7].IN1
+output_rsc_z[0] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[1] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[2] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[3] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[4] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[5] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[6] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+output_rsc_z[7] <= mgc_out_stdreg:output_rsc_mgc_out_stdreg.z
+clk => clk.IN1
+en => en.IN1
+arst_n => arst_n.IN1
+
+
+|ise_proj|dot_product:inst|mgc_in_wire:input_a_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+
+
+|ise_proj|dot_product:inst|mgc_in_wire:input_b_rsc_mgc_in_wire
+d[0] <= z[0].DB_MAX_OUTPUT_PORT_TYPE
+d[1] <= z[1].DB_MAX_OUTPUT_PORT_TYPE
+d[2] <= z[2].DB_MAX_OUTPUT_PORT_TYPE
+d[3] <= z[3].DB_MAX_OUTPUT_PORT_TYPE
+d[4] <= z[4].DB_MAX_OUTPUT_PORT_TYPE
+d[5] <= z[5].DB_MAX_OUTPUT_PORT_TYPE
+d[6] <= z[6].DB_MAX_OUTPUT_PORT_TYPE
+d[7] <= z[7].DB_MAX_OUTPUT_PORT_TYPE
+z[0] => d[0].DATAIN
+z[1] => d[1].DATAIN
+z[2] => d[2].DATAIN
+z[3] => d[3].DATAIN
+z[4] => d[4].DATAIN
+z[5] => d[5].DATAIN
+z[6] => d[6].DATAIN
+z[7] => d[7].DATAIN
+
+
+|ise_proj|dot_product:inst|mgc_out_stdreg:output_rsc_mgc_out_stdreg
+d[0] => z[0].DATAIN
+d[1] => z[1].DATAIN
+d[2] => z[2].DATAIN
+d[3] => z[3].DATAIN
+d[4] => z[4].DATAIN
+d[5] => z[5].DATAIN
+d[6] => z[6].DATAIN
+d[7] => z[7].DATAIN
+z[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
+z[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
+z[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
+z[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
+z[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
+z[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
+z[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE
+z[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst
+clk => exit_MAC_lpi.CLK
+clk => i_1_sva_1[0].CLK
+clk => i_1_sva_1[1].CLK
+clk => i_1_sva_1[2].CLK
+clk => acc_sva_1[0].CLK
+clk => acc_sva_1[1].CLK
+clk => acc_sva_1[2].CLK
+clk => acc_sva_1[3].CLK
+clk => acc_sva_1[4].CLK
+clk => acc_sva_1[5].CLK
+clk => acc_sva_1[6].CLK
+clk => acc_sva_1[7].CLK
+clk => output_rsc_mgc_out_stdreg_d[0]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[1]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[2]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[3]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[4]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[5]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[6]~reg0.CLK
+clk => output_rsc_mgc_out_stdreg_d[7]~reg0.CLK
+en => exit_MAC_lpi.ENA
+en => output_rsc_mgc_out_stdreg_d[7]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[6]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[5]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[4]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[3]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[2]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[1]~reg0.ENA
+en => output_rsc_mgc_out_stdreg_d[0]~reg0.ENA
+en => acc_sva_1[7].ENA
+en => acc_sva_1[6].ENA
+en => acc_sva_1[5].ENA
+en => acc_sva_1[4].ENA
+en => acc_sva_1[3].ENA
+en => acc_sva_1[2].ENA
+en => acc_sva_1[1].ENA
+en => acc_sva_1[0].ENA
+en => i_1_sva_1[2].ENA
+en => i_1_sva_1[1].ENA
+en => i_1_sva_1[0].ENA
+arst_n => exit_MAC_lpi.PRESET
+arst_n => i_1_sva_1[0].ACLR
+arst_n => i_1_sva_1[1].ACLR
+arst_n => i_1_sva_1[2].ACLR
+arst_n => acc_sva_1[0].ACLR
+arst_n => acc_sva_1[1].ACLR
+arst_n => acc_sva_1[2].ACLR
+arst_n => acc_sva_1[3].ACLR
+arst_n => acc_sva_1[4].ACLR
+arst_n => acc_sva_1[5].ACLR
+arst_n => acc_sva_1[6].ACLR
+arst_n => acc_sva_1[7].ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[0]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[1]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[2]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[3]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[4]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[5]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[6]~reg0.ACLR
+arst_n => output_rsc_mgc_out_stdreg_d[7]~reg0.ACLR
+input_a_rsc_mgc_in_wire_d[0] => Mult0.IN7
+input_a_rsc_mgc_in_wire_d[1] => Mult0.IN6
+input_a_rsc_mgc_in_wire_d[2] => Mult0.IN5
+input_a_rsc_mgc_in_wire_d[3] => Mult0.IN4
+input_a_rsc_mgc_in_wire_d[4] => Mult0.IN3
+input_a_rsc_mgc_in_wire_d[5] => Mult0.IN2
+input_a_rsc_mgc_in_wire_d[6] => Mult0.IN1
+input_a_rsc_mgc_in_wire_d[7] => Mult0.IN0
+input_b_rsc_mgc_in_wire_d[0] => Mult0.IN15
+input_b_rsc_mgc_in_wire_d[1] => Mult0.IN14
+input_b_rsc_mgc_in_wire_d[2] => Mult0.IN13
+input_b_rsc_mgc_in_wire_d[3] => Mult0.IN12
+input_b_rsc_mgc_in_wire_d[4] => Mult0.IN11
+input_b_rsc_mgc_in_wire_d[5] => Mult0.IN10
+input_b_rsc_mgc_in_wire_d[6] => Mult0.IN9
+input_b_rsc_mgc_in_wire_d[7] => Mult0.IN8
+output_rsc_mgc_out_stdreg_d[0] <= output_rsc_mgc_out_stdreg_d[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[1] <= output_rsc_mgc_out_stdreg_d[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[2] <= output_rsc_mgc_out_stdreg_d[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[3] <= output_rsc_mgc_out_stdreg_d[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[4] <= output_rsc_mgc_out_stdreg_d[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[5] <= output_rsc_mgc_out_stdreg_d[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[6] <= output_rsc_mgc_out_stdreg_d[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+output_rsc_mgc_out_stdreg_d[7] <= output_rsc_mgc_out_stdreg_d[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hif b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hif
new file mode 100644
index 0000000..1485e77
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.hif
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ipinfo b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ipinfo
new file mode 100644
index 0000000..3560eab
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.ipinfo
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.html b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.html
new file mode 100644
index 0000000..c807037
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.html
@@ -0,0 +1,98 @@
+<TABLE>
+<TR  bgcolor="#C0C0C0">
+<TH>Hierarchy</TH>
+<TH>Input</TH>
+<TH>Constant Input</TH>
+<TH>Unused Input</TH>
+<TH>Floating Input</TH>
+<TH>Output</TH>
+<TH>Constant Output</TH>
+<TH>Unused Output</TH>
+<TH>Floating Output</TH>
+<TH>Bidir</TH>
+<TH>Constant Bidir</TH>
+<TH>Unused Bidir</TH>
+<TH>Input only Bidir</TH>
+<TH>Output only Bidir</TH>
+</TR>
+<TR >
+<TD >inst|dot_product_core_inst</TD>
+<TD >19</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|output_rsc_mgc_out_stdreg</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|input_b_rsc_mgc_in_wire</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst|input_a_rsc_mgc_in_wire</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+<TR >
+<TD >inst</TD>
+<TD >19</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >8</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+<TD >0</TD>
+</TR>
+</TABLE>
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.rdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.rdb
new file mode 100644
index 0000000..d6b8d43
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.rdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.txt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.txt
new file mode 100644
index 0000000..d8de620
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.lpc.txt
@@ -0,0 +1,11 @@
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates                                                                                                                                                                                                          ;
++--------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy                      ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++--------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst|dot_product_core_inst     ; 19    ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|output_rsc_mgc_out_stdreg ; 8     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|input_b_rsc_mgc_in_wire   ; 8     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst|input_a_rsc_mgc_in_wire   ; 8     ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
+; inst                           ; 19    ; 0              ; 0            ; 0              ; 8      ; 0               ; 0             ; 0               ; 0     ; 0              ; 0            ; 0                ; 0                 ;
++--------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.ammdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.ammdb
new file mode 100644
index 0000000..8b8ff04
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.ammdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.bpm b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.bpm
new file mode 100644
index 0000000..fd41559
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.bpm
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.cdb
new file mode 100644
index 0000000..5c56410
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.hdb
new file mode 100644
index 0000000..d7ed64b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.kpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.kpt
new file mode 100644
index 0000000..ae6a269
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.kpt
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.logdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.qmsg b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.qmsg
new file mode 100644
index 0000000..d51af7e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.qmsg
@@ -0,0 +1,44 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848306525 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848306526 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:05:06 2016 " "Processing started: Tue Mar 01 16:05:06 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848306526 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456848306526 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj " "Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456848306526 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456848306795 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v 7 7 " "Found 7 design units, including 7 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_out_reg_pos " "Found entity 1: mgc_out_reg_pos" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_out_reg_neg " "Found entity 2: mgc_out_reg_neg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 68 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_out_reg " "Found entity 3: mgc_out_reg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 133 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_out_buf_wait " "Found entity 4: mgc_out_buf_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 210 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_fifo_wait " "Found entity 5: mgc_out_fifo_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 296 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_fifo_wait_core " "Found entity 6: mgc_out_fifo_wait_core" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 353 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_pipe " "Found entity 7: mgc_pipe" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v" 644 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848306834 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl_mgc_ioport (2).v 20 20 " "Found 20 design units, including 20 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport (2).v" { { "Info" "ISGN_ENTITY_NAME" "1 mgc_in_wire " "Found entity 1: mgc_in_wire" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 13 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "2 mgc_in_wire_en " "Found entity 2: mgc_in_wire_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "3 mgc_in_wire_wait " "Found entity 3: mgc_in_wire_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 49 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "4 mgc_chan_in " "Found entity 4: mgc_chan_in" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 72 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "5 mgc_out_stdreg " "Found entity 5: mgc_out_stdreg" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 109 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "6 mgc_out_stdreg_en " "Found entity 6: mgc_out_stdreg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 125 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "7 mgc_out_stdreg_wait " "Found entity 7: mgc_out_stdreg_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 145 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "8 mgc_out_prereg_en " "Found entity 8: mgc_out_prereg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 169 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "9 mgc_inout_stdreg_en " "Found entity 9: mgc_inout_stdreg_en" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 191 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "10 hid_tribuf " "Found entity 10: hid_tribuf" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 217 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "11 mgc_inout_stdreg_wait " "Found entity 11: mgc_inout_stdreg_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "12 mgc_inout_buf_wait " "Found entity 12: mgc_inout_buf_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 269 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "13 mgc_inout_fifo_wait " "Found entity 13: mgc_inout_fifo_wait" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 339 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "14 mgc_io_sync " "Found entity 14: mgc_io_sync" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 419 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "15 mgc_bsync_rdy " "Found entity 15: mgc_bsync_rdy" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 428 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "16 mgc_bsync_vld " "Found entity 16: mgc_bsync_vld" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 443 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "17 mgc_bsync_rv " "Found entity 17: mgc_bsync_rv" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 458 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "18 mgc_sync " "Found entity 18: mgc_sync" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 479 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "19 funccall_inout " "Found entity 19: funccall_inout" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""} { "Info" "ISGN_ENTITY_NAME" "20 modulario_en_in " "Found entity 20: modulario_en_in" {  } { { "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v" 526 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848306838 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/catapult c/dot_product/dot_product/rtl (2).v 2 2 " "Found 2 design units, including 2 entities, in source file /catapult c/dot_product/dot_product/rtl (2).v" { { "Info" "ISGN_ENTITY_NAME" "1 dot_product_core " "Found entity 1: dot_product_core" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306840 ""} { "Info" "ISGN_ENTITY_NAME" "2 dot_product " "Found entity 2: dot_product" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 119 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306840 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848306840 ""}
+{ "Warning" "WSGN_SEARCH_FILE" "ise_proj.bdf 1 1 " "Using design file ise_proj.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 ise_proj " "Found entity 1: ise_proj" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848306872 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1456848306872 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ise_proj " "Elaborating entity \"ise_proj\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1456848306873 ""}
+{ "Warning" "WGDFX_NO_SUPERSET_FOUND" "" "No superset bus at connection" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 96 744 811 112 "A\[7..4\]" "" } { 112 744 817 128 "B\[7..4\]" "" } { 128 744 837 144 "LEDG\[9..8\]" "" } { 112 744 744 128 "" "" } { 128 744 744 144 "" "" } { 144 744 744 168 "" "" } } } }  } 0 275002 "No superset bus at connection" 0 0 "Quartus II" 0 -1 1456848306874 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_CLK " "Pin \"VGA_CLK\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 680 32 208 696 "VGA_CLK" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306874 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_SYNC " "Pin \"VGA_SYNC\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 656 32 208 672 "VGA_SYNC" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306874 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_BLANK " "Pin \"VGA_BLANK\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 632 32 208 648 "VGA_BLANK" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306874 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_VS " "Pin \"VGA_VS\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 608 32 208 624 "VGA_VS" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_HS " "Pin \"VGA_HS\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 584 32 208 600 "VGA_HS" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "HEX0_D\[6..0\] " "Pin \"HEX0_D\[6..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_B\[3..0\] " "Pin \"VGA_B\[3..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_G\[3..0\] " "Pin \"VGA_G\[3..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_NO_SOURCE_FOR_PIN" "VGA_R\[3..0\] " "Pin \"VGA_R\[3..0\]\" is missing source" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 275043 "Pin \"%1!s!\" is missing source" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "PS2_MSDAT " "Pin \"PS2_MSDAT\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 416 40 208 432 "PS2_MSDAT" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "PS2_MSCLK " "Pin \"PS2_MSCLK\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 440 40 208 456 "PS2_MSCLK" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "CLOCK_50 " "Pin \"CLOCK_50\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 88 40 208 104 "CLOCK_50" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Warning" "WGDFX_PIN_IGNORED" "CLOCK_50_2 " "Pin \"CLOCK_50_2\" not connected" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 56 40 208 72 "CLOCK_50_2" "" } } } }  } 0 275009 "Pin \"%1!s!\" not connected" 0 0 "Quartus II" 0 -1 1456848306875 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dot_product dot_product:inst " "Elaborating entity \"dot_product\" for hierarchy \"dot_product:inst\"" {  } { { "ise_proj.bdf" "inst" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 152 304 552 296 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848306876 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire dot_product:inst\|mgc_in_wire:input_a_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"dot_product:inst\|mgc_in_wire:input_a_rsc_mgc_in_wire\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "input_a_rsc_mgc_in_wire" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 141 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848306879 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_in_wire dot_product:inst\|mgc_in_wire:input_b_rsc_mgc_in_wire " "Elaborating entity \"mgc_in_wire\" for hierarchy \"dot_product:inst\|mgc_in_wire:input_b_rsc_mgc_in_wire\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "input_b_rsc_mgc_in_wire" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 146 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848306881 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mgc_out_stdreg dot_product:inst\|mgc_out_stdreg:output_rsc_mgc_out_stdreg " "Elaborating entity \"mgc_out_stdreg\" for hierarchy \"dot_product:inst\|mgc_out_stdreg:output_rsc_mgc_out_stdreg\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "output_rsc_mgc_out_stdreg" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 151 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848306882 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dot_product_core dot_product:inst\|dot_product_core:dot_product_core_inst " "Elaborating entity \"dot_product_core\" for hierarchy \"dot_product:inst\|dot_product_core:dot_product_core_inst\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "dot_product_core_inst" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 159 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848306884 ""}
+{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "dot_product:inst\|dot_product_core:dot_product_core_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"dot_product:inst\|dot_product_core:dot_product_core_inst\|Mult0\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "Mult0" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 42 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307081 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1456848307081 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "dot_product:inst\|dot_product_core:dot_product_core_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"dot_product:inst\|dot_product_core:dot_product_core_inst\|lpm_mult:Mult0\"" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 42 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "dot_product:inst\|dot_product_core:dot_product_core_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"dot_product:inst\|dot_product_core:dot_product_core_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 4 " "Parameter \"LPM_WIDTHB\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 8 " "Parameter \"LPM_WIDTHP\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 8 " "Parameter \"LPM_WIDTHR\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1456848307122 ""}  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 42 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1456848307122 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_a7t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_a7t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_a7t " "Found entity 1: mult_a7t" {  } { { "db/mult_a7t.tdf" "" { Text "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1456848307172 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1456848307172 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "dot_product:inst\|dot_product_core:dot_product_core_inst\|lpm_mult:Mult0\|mult_a7t:auto_generated\|le5a\[4\] " "Synthesized away node \"dot_product:inst\|dot_product_core:dot_product_core_inst\|lpm_mult:Mult0\|mult_a7t:auto_generated\|le5a\[4\]\"" {  } { { "db/mult_a7t.tdf" "" { Text "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf" 42 6 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 42 -1 0 } } { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 159 0 0 } } { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 152 304 552 296 "inst" "" } } } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307191 "|ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[4]"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Quartus II" 0 -1 1456848307191 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Quartus II" 0 -1 1456848307191 ""}
+{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "48 " "Ignored 48 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "4 " "Ignored 4 CARRY_SUM buffer(s)" {  } {  } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Quartus II" 0 -1 1456848307320 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "44 " "Ignored 44 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1456848307320 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1456848307320 ""}
+{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "../../../../dot_product/dot_product/rtl (2).v" "" { Text "C:/Catapult C/dot_product/dot_product/rtl (2).v" 29 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1456848307324 ""}
+{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1456848307324 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_CLK GND " "Pin \"VGA_CLK\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 680 32 208 696 "VGA_CLK" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_CLK"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_SYNC GND " "Pin \"VGA_SYNC\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 656 32 208 672 "VGA_SYNC" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_SYNC"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_BLANK GND " "Pin \"VGA_BLANK\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 632 32 208 648 "VGA_BLANK" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_BLANK"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_VS GND " "Pin \"VGA_VS\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 608 32 208 624 "VGA_VS" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_VS"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_HS GND " "Pin \"VGA_HS\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 584 32 208 600 "VGA_HS" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_HS"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[6\] GND " "Pin \"HEX0_D\[6\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[5\] GND " "Pin \"HEX0_D\[5\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[4\] GND " "Pin \"HEX0_D\[4\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[3\] GND " "Pin \"HEX0_D\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[2\] GND " "Pin \"HEX0_D\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[1\] GND " "Pin \"HEX0_D\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0_D\[0\] GND " "Pin \"HEX0_D\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 360 32 208 376 "HEX0_D\[6..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|HEX0_D[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[9\] GND " "Pin \"LEDG\[9\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 128 744 837 144 "LEDG\[9..8\]" "" } { 304 216 289 320 "LEDG\[9..0\]" "" } { 168 552 615 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|LEDG[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDG\[8\] GND " "Pin \"LEDG\[8\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 312 32 208 328 "LEDG\[9..0\]" "" } { 128 744 837 144 "LEDG\[9..8\]" "" } { 304 216 289 320 "LEDG\[9..0\]" "" } { 168 552 615 184 "LEDG\[7..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|LEDG[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[3\] GND " "Pin \"VGA_B\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_B[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[2\] GND " "Pin \"VGA_B\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_B[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Pin \"VGA_B\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_B[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Pin \"VGA_B\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 560 32 208 576 "VGA_B\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_B[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[3\] GND " "Pin \"VGA_G\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_G[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[2\] GND " "Pin \"VGA_G\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_G[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Pin \"VGA_G\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_G[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Pin \"VGA_G\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 536 32 208 552 "VGA_G\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_G[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[3\] GND " "Pin \"VGA_R\[3\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_R[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[2\] GND " "Pin \"VGA_R\[2\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_R[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[1\] GND " "Pin \"VGA_R\[1\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_R[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_R\[0\] GND " "Pin \"VGA_R\[0\]\" is stuck at GND" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 504 32 208 520 "VGA_R\[3..0\]" "" } } } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1456848307343 "|ise_proj|VGA_R[0]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1456848307343 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1456848307438 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_TOP " "Ignored assignments for entity \"DE0_TOP\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307545 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848307545 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_VGA " "Ignored assignments for entity \"DE0_VGA\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848307546 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848307546 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1456848307681 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307681 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "6 " "Design contains 6 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "BUTTON\[1\] " "No output dependent on input pin \"BUTTON\[1\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307712 "|ise_proj|BUTTON[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "BUTTON\[0\] " "No output dependent on input pin \"BUTTON\[0\]\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 120 40 208 136 "BUTTON" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307712 "|ise_proj|BUTTON[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PS2_MSDAT " "No output dependent on input pin \"PS2_MSDAT\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 416 40 208 432 "PS2_MSDAT" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307712 "|ise_proj|PS2_MSDAT"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PS2_MSCLK " "No output dependent on input pin \"PS2_MSCLK\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 440 40 208 456 "PS2_MSCLK" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307712 "|ise_proj|PS2_MSCLK"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_50 " "No output dependent on input pin \"CLOCK_50\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 88 40 208 104 "CLOCK_50" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307712 "|ise_proj|CLOCK_50"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLOCK_50_2 " "No output dependent on input pin \"CLOCK_50_2\"" {  } { { "ise_proj.bdf" "" { Schematic "C:/Catapult C/student_files_2015\[2\]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf" { { 56 40 208 72 "CLOCK_50_2" "" } } } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1456848307712 "|ise_proj|CLOCK_50_2"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1456848307712 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "118 " "Implemented 118 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Implemented 17 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1456848307713 ""} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Implemented 34 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1456848307713 ""} { "Info" "ICUT_CUT_TM_LCELLS" "67 " "Implemented 67 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1456848307713 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1456848307713 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 102 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 102 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848307729 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:07 2016 " "Processing ended: Tue Mar 01 16:05:07 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848307729 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848307729 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848307729 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456848307729 ""}
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.rdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.rdb
new file mode 100644
index 0000000..123cfe1
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map.rdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.cdb
new file mode 100644
index 0000000..ae2238f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.hdb
new file mode 100644
index 0000000..183bb14
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.logdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pre_map.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pre_map.hdb
new file mode 100644
index 0000000..bfcf218
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pre_map.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pti_db_list.ddb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pti_db_list.ddb
new file mode 100644
index 0000000..4c5fa0d
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.pti_db_list.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.root_partition.map.reg_db.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..0089964
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.root_partition.map.reg_db.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.routing.rdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.routing.rdb
new file mode 100644
index 0000000..461f40a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.routing.rdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv.hdb
new file mode 100644
index 0000000..dd25cc7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg.cdb
new file mode 100644
index 0000000..b4c906c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg_swap.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg_swap.cdb
new file mode 100644
index 0000000..9745439
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.rtlv_sg_swap.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.cdb
new file mode 100644
index 0000000..5ffa022
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.hdb
new file mode 100644
index 0000000..6c8ed68
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sgdiff.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry.sci b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry.sci
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry_dsc.sci b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry_dsc.sci
new file mode 100644
index 0000000..91c4798
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sld_design_entry_dsc.sci
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smart_action.txt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.qmsg b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.qmsg
new file mode 100644
index 0000000..a0305ff
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.qmsg
@@ -0,0 +1,44 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456848317026 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317027 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 16:05:16 2016 " "Processing started: Tue Mar 01 16:05:16 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456848317027 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456848317027 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta ise_proj -c ise_proj " "Command: quartus_sta ise_proj -c ise_proj" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456848317027 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1456848317084 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_TOP " "Ignored assignments for entity \"DE0_TOP\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317134 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848317134 ""}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "DE0_VGA " "Ignored assignments for entity \"DE0_VGA\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" " "Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id \"Root Region\" was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top " "Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to \| -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top " "Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored" {  } {  } 0 20014 "Assignment for entity %1!s! was ignored" 0 0 "Quartus II" 0 -1 1456848317136 ""}  } {  } 0 20013 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "Quartus II" 0 -1 1456848317136 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1456848317204 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456848317205 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456848317248 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1456848317248 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "ise_proj.sdc " "Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1456848317382 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1456848317383 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name BUTTON\[2\] BUTTON\[2\] " "create_clock -period 1.000 -name BUTTON\[2\] BUTTON\[2\]" {  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317383 ""}  } {  } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317383 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1456848317481 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456848317481 ""}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1456848317481 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1456848317490 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456848317498 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456848317498 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.141 " "Worst-case setup slack is -2.141" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317499 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -2.141       -24.967 BUTTON\[2\]  " "   -2.141       -24.967 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317499 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317499 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.382 " "Worst-case hold slack is 0.382" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.382         0.000 BUTTON\[2\]  " "    0.382         0.000 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317501 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317501 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848317503 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848317505 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317506 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317506 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -23.000 BUTTON\[2\]  " "   -3.000       -23.000 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317506 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317506 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456848317533 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1456848317551 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1456848317856 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456848317878 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456848317883 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456848317883 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.805 " "Worst-case setup slack is -1.805" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -1.805       -20.320 BUTTON\[2\]  " "   -1.805       -20.320 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317885 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317885 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.333 " "Worst-case hold slack is 0.333" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317887 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317887 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.333         0.000 BUTTON\[2\]  " "    0.333         0.000 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317887 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317887 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848317890 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848317892 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317894 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -23.000 BUTTON\[2\]  " "   -3.000       -23.000 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317894 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317894 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1456848317925 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1456848317992 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." {  } {  } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Quartus II" 0 -1 1456848317994 ""}  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1456848317994 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup -0.738 " "Worst-case setup slack is -0.738" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.738        -5.942 BUTTON\[2\]  " "   -0.738        -5.942 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848317997 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848317997 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.201 " "Worst-case hold slack is 0.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848318000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848318000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.201         0.000 BUTTON\[2\]  " "    0.201         0.000 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848318000 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848318000 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848318003 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1456848318006 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848318009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848318009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -3.000       -30.776 BUTTON\[2\]  " "   -3.000       -30.776 BUTTON\[2\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1456848318009 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1456848318009 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456848318161 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1456848318161 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 54 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "480 " "Peak virtual memory: 480 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456848318211 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 16:05:18 2016 " "Processing ended: Tue Mar 01 16:05:18 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456848318211 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456848318211 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456848318211 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456848318211 ""}
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.rdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.rdb
new file mode 100644
index 0000000..f7d7441
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta.rdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta_cmp.6_slow_1200mv_85c.tdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta_cmp.6_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..fa2aa21
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.sta_cmp.6_slow_1200mv_85c.tdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.syn_hier_info b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.syn_hier_info
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.syn_hier_info
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tis_db_list.ddb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tis_db_list.ddb
new file mode 100644
index 0000000..ba46866
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tis_db_list.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.fast_1200mv_0c.ddb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..6a2bcc4
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.fast_1200mv_0c.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_0c.ddb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..588808c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_0c.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_85c.ddb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..f3b56aa
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tiscmp.slow_1200mv_85c.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tmw_info b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tmw_info
new file mode 100644
index 0000000..56df19c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.tmw_info
@@ -0,0 +1,6 @@
+start_full_compilation:s:00:00:13
+start_analysis_synthesis:s:00:00:03-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:06-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.vpr.ammdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.vpr.ammdb
new file mode 100644
index 0000000..89a44ee
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/ise_proj.vpr.ammdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/logic_util_heursitic.dat b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/logic_util_heursitic.dat
new file mode 100644
index 0000000..b96a33a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/logic_util_heursitic.dat
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf
new file mode 100644
index 0000000..96eb86d
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf
@@ -0,0 +1,93 @@
+--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=4 LPM_WIDTHB=4 LPM_WIDTHP=8 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_mult 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_padd 2013:06:12:18:03:43:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+FUNCTION carry_sum (cin, sin)
+RETURNS ( cout, sout);
+FUNCTION lcell (in)
+RETURNS ( out);
+FUNCTION soft (in)
+RETURNS ( out);
+
+--synthesis_resources = lut 45 
+SUBDESIGN mult_a7t
+( 
+	dataa[3..0]	:	input;
+	datab[3..0]	:	input;
+	result[7..0]	:	output;
+) 
+VARIABLE
+	add10_result[7..0]	:	WIRE;
+	add14_result[2..0]	:	WIRE;
+	add6_result[10..0]	:	WIRE;
+	cs1a[2..0] : carry_sum;
+	cs2a[2..0] : carry_sum;
+	le3a[5..0] : lcell;
+	le4a[5..0] : lcell;
+	le5a[4..0] : lcell;
+	sft11a[7..0] : soft;
+	sft12a[7..0] : soft;
+	sft13a[7..0] : soft;
+	sft15a[2..0] : soft;
+	sft16a[2..0] : soft;
+	sft17a[2..0] : soft;
+	sft7a[10..0] : soft;
+	sft8a[10..0] : soft;
+	sft9a[10..0] : soft;
+	dataa_node[3..0]	: WIRE;
+	datab_node[3..0]	: WIRE;
+	final_result_node[7..0]	: WIRE;
+	w117w[5..0]	: WIRE;
+	w183w	: WIRE;
+	w196w	: WIRE;
+	w257w[10..0]	: WIRE;
+	w70w[5..0]	: WIRE;
+	w7w[5..0]	: WIRE;
+
+BEGIN 
+	add10_result[] = sft11a[].out + sft12a[].out;
+	add14_result[] = sft15a[].out + sft16a[].out;
+	add6_result[] = sft7a[].out + sft8a[].out;
+	cs1a[].cin = ( ((w7w[4..4] & cs1a[1].cout) # w7w[5..5]), ((w7w[2..2] & cs1a[0].cout) # w7w[3..3]), w7w[1..1]);
+	cs1a[].sin = ( ((((((! w7w[5..5]) & w7w[4..4]) & cs1a[1].cout) # ((w7w[5..5] & w7w[4..4]) & (! cs1a[1].cout))) # ((w7w[5..5] & (! w7w[4..4])) & cs1a[1].cout)) # ((w7w[5..5] & (! w7w[4..4])) & (! cs1a[1].cout))), ((((((! w7w[3..3]) & w7w[2..2]) & cs1a[0].cout) # ((w7w[3..3] & w7w[2..2]) & (! cs1a[0].cout))) # ((w7w[3..3] & (! w7w[2..2])) & cs1a[0].cout)) # ((w7w[3..3] & (! w7w[2..2])) & (! cs1a[0].cout))), w7w[1..1]);
+	cs2a[].cin = ( ((w7w[4..4] & cs2a[1].cout) # w7w[5..5]), ((w7w[2..2] & cs2a[0].cout) # w7w[3..3]), w7w[1..1]);
+	cs2a[].sin = ( ((((((! w7w[5..5]) & (! w7w[4..4])) & cs2a[1].cout) # (((! w7w[5..5]) & w7w[4..4]) & (! cs2a[1].cout))) # ((w7w[5..5] & w7w[4..4]) & (! cs2a[1].cout))) # ((w7w[5..5] & (! w7w[4..4])) & cs2a[1].cout)), ((((((! w7w[3..3]) & (! w7w[2..2])) & cs2a[0].cout) # (((! w7w[3..3]) & w7w[2..2]) & (! cs2a[0].cout))) # ((w7w[3..3] & w7w[2..2]) & (! cs2a[0].cout))) # ((w7w[3..3] & (! w7w[2..2])) & cs2a[0].cout)), w7w[0..0]);
+	le3a[].in = (! ((! (((! ( B"0", dataa_node[], B"0")) & cs1a[0].sout) & (! cs2a[0].sout))) & (! ((((! ( B"0", B"0", dataa_node[])) & cs1a[0].sout) & cs2a[0].sout) # ((( B"0", B"0", dataa_node[]) & (! cs1a[0].sout)) & cs2a[0].sout)))));
+	le4a[].in = (! ((! (((! ( B"0", dataa_node[], B"0")) & cs1a[1].sout) & (! cs2a[1].sout))) & (! ((((! ( B"0", B"0", dataa_node[])) & cs1a[1].sout) & cs2a[1].sout) # ((( B"0", B"0", dataa_node[]) & (! cs1a[1].sout)) & cs2a[1].sout)))));
+	le5a[].in = ((cs1a[2].sout & ( dataa_node[], B"0")) # (cs2a[2].sout & ( B"0", dataa_node[])));
+	sft11a[].in = ( w196w, ( w183w, ( le5a[3..3].out, ( le5a[2..2].out, ( le5a[1..1].out, ( le4a[2..2].out, ( le3a[3..2].out)))))));
+	sft12a[].in = ( w196w, ( w196w, ( (! w117w[5..5]), ( le4a[4..4].out, ( le4a[3..3].out, ( le3a[4..4].out, ( w196w, cs1a[1].sout)))))));
+	sft13a[].in = add10_result[];
+	sft15a[].in = ( w196w, ( w183w, w183w));
+	sft16a[].in = ( w196w, ( w196w, (! w70w[5..5])));
+	sft17a[].in = add14_result[];
+	sft7a[].in = ( w183w, ( w183w, ( le5a[4..4].out, ( sft13a[5..5].out, ( sft13a[4..4].out, ( sft13a[3..3].out, ( le5a[0..0].out, ( le4a[1..1].out, ( le4a[0..0].out, ( le3a[1..0].out))))))))));
+	sft8a[].in = ( w196w, ( sft13a[7..7].out, ( sft13a[6..6].out, ( sft17a[2..2].out, ( sft17a[1..1].out, ( sft17a[0..0].out, ( sft13a[2..2].out, ( sft13a[1..1].out, ( sft13a[0..0].out, ( w196w, cs1a[0].sout))))))))));
+	sft9a[].in = add6_result[];
+	dataa_node[] = ( dataa[3..0]);
+	datab_node[] = ( datab[3..0]);
+	final_result_node[] = ( w257w[7..0]);
+	result[] = ( final_result_node[7..0]);
+	w117w[] = le4a[].out;
+	w183w = B"1";
+	w196w = B"0";
+	w257w[] = ( sft9a[10..9].out, sft9a[8..7].out, sft9a[6..5].out, sft9a[4..3].out, sft9a[2..1].out, sft9a[0..0].out);
+	w70w[] = le3a[].out;
+	w7w[] = ( B"00", datab_node[]);
+END;
+--VALID FILE
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/prev_cmp_ise_proj.qmsg b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/prev_cmp_ise_proj.qmsg
new file mode 100644
index 0000000..f6c2c32
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/prev_cmp_ise_proj.qmsg
@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1456847729878 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II 64-Bit " "Running Quartus II 64-Bit Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1456847729879 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 01 15:55:29 2016 " "Processing started: Tue Mar 01 15:55:29 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1456847729879 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1456847729879 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj --generate_symbol=\"C:/Catapult C/dot_product/dot_product/rtl (2).v\" " "Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj --generate_symbol=\"C:/Catapult C/dot_product/dot_product/rtl (2).v\"" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1456847729879 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "417 " "Peak virtual memory: 417 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1456847730363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 01 15:55:30 2016 " "Processing ended: Tue Mar 01 15:55:30 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1456847730363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1456847730363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1456847730363 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1456847730363 ""}
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/dot_product.bsf b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/dot_product.bsf
new file mode 100644
index 0000000..8dbba23
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/dot_product.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 264 160)
+	(text "dot_product" (rect 5 0 52 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "input_a_rsc_z[7..0]" (rect 0 0 76 12)(font "Arial" ))
+		(text "input_a_rsc_z[7..0]" (rect 21 27 97 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input_b_rsc_z[7..0]" (rect 0 0 76 12)(font "Arial" ))
+		(text "input_b_rsc_z[7..0]" (rect 21 43 97 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 59 31 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 75 30 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 91 46 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 248 32)
+		(output)
+		(text "output_rsc_z[7..0]" (rect 0 0 71 12)(font "Arial" ))
+		(text "output_rsc_z[7..0]" (rect 156 27 227 39)(font "Arial" ))
+		(line (pt 248 32)(pt 232 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 232 128)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/dot_product_core.bsf b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/dot_product_core.bsf
new file mode 100644
index 0000000..4691fe9
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/dot_product_core.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 400 160)
+	(text "dot_product_core" (rect 5 0 75 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "input_a_rsc_mgc_in_wire_d[7..0]" (rect 0 0 134 12)(font "Arial" ))
+		(text "input_a_rsc_mgc_in_wire_d[7..0]" (rect 21 75 155 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "input_b_rsc_mgc_in_wire_d[7..0]" (rect 0 0 134 12)(font "Arial" ))
+		(text "input_b_rsc_mgc_in_wire_d[7..0]" (rect 21 91 155 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 384 32)
+		(output)
+		(text "output_rsc_mgc_out_stdreg_d[7..0]" (rect 0 0 145 12)(font "Arial" ))
+		(text "output_rsc_mgc_out_stdreg_d[7..0]" (rect 218 27 363 39)(font "Arial" ))
+		(line (pt 384 32)(pt 368 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 368 128)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/README b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used.  To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.db_info b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.db_info
new file mode 100644
index 0000000..82512e6
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+Version_Index = 302049280
+Creation_Time = Tue Mar 01 15:55:13 2016
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.ammdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.ammdb
new file mode 100644
index 0000000..4b279cd
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.ammdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.cdb
new file mode 100644
index 0000000..9c648c0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.dfp b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.dfp
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.hdb
new file mode 100644
index 0000000..6a5b604
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.kpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.kpt
new file mode 100644
index 0000000..b1479c0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.kpt
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.logdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.rcfdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..34c0f60
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.cmp.rcfdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.cdb
new file mode 100644
index 0000000..6a708ac
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.dpi b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.dpi
new file mode 100644
index 0000000..7535ec7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.dpi
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.cdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..690a2ba
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.cdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hb_info b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hb_info
new file mode 100644
index 0000000..8210c55
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hb_info
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hdb
new file mode 100644
index 0000000..e0a935d
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.sig b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..ef58eaa
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+d1187c24d5e18b5b14f48701f0f8928b
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hdb b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hdb
new file mode 100644
index 0000000..b056a45
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.hdb
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.kpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.kpt
new file mode 100644
index 0000000..89004d9
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/incremental_db/compiled_partitions/ise_proj.root_partition.map.kpt
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.asm.rpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.asm.rpt
new file mode 100644
index 0000000..7965d51
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.asm.rpt
@@ -0,0 +1,116 @@
+Assembler report for ise_proj
+Tue Mar 01 16:05:15 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof
+  6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Tue Mar 01 16:05:15 2016 ;
+; Revision Name         ; ise_proj                              ;
+; Top-level Entity Name ; ise_proj                              ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; Off      ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Use configuration device                                                    ; Off      ; Off           ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Assembler Generated Files                                                                 ;
++-------------------------------------------------------------------------------------------+
+; File Name                                                                                 ;
++-------------------------------------------------------------------------------------------+
+; C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof ;
++-------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof ;
++----------------+----------------------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                                            ;
++----------------+----------------------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                                       ;
+; JTAG usercode  ; 0x000D0667                                                                                         ;
+; Checksum       ; 0x000D0667                                                                                         ;
++----------------+----------------------------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 16:05:14 2016
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 424 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:15 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf
new file mode 100644
index 0000000..cd0cbef
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf
@@ -0,0 +1,512 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 40 120 208 136)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "BUTTON[2..0]" (rect 5 0 74 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 112 32 120))
+)
+(pin
+	(input)
+	(rect 40 416 208 432)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "PS2_MSDAT" (rect 5 0 67 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 224 416 280 424))
+)
+(pin
+	(input)
+	(rect 40 440 208 456)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "PS2_MSCLK" (rect 5 0 67 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 232 440 288 456))
+)
+(pin
+	(input)
+	(rect 40 240 208 256)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9]" (rect 5 0 35 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 240 32 256))
+)
+(pin
+	(input)
+	(rect 40 224 208 240)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[8]" (rect 5 0 35 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -32 208 24 224))
+)
+(pin
+	(input)
+	(rect 40 176 208 192)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[7..4]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 176 32 192))
+)
+(pin
+	(input)
+	(rect 40 152 208 168)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[3..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 136 32 152))
+)
+(pin
+	(input)
+	(rect 40 88 208 104)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 72 32 88))
+)
+(pin
+	(input)
+	(rect 40 56 208 72)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50_2" (rect 5 0 72 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -24 40 32 56))
+)
+(pin
+	(output)
+	(rect 32 536 208 552)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 536 272 544))
+)
+(pin
+	(output)
+	(rect 32 680 208 696)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 5 0 54 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 352 704 408 720))
+)
+(pin
+	(output)
+	(rect 32 656 208 672)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_SYNC" (rect 5 0 65 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 560 752 616 768))
+)
+(pin
+	(output)
+	(rect 32 632 208 648)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_BLANK" (rect 5 0 68 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 616 688 672 704))
+)
+(pin
+	(output)
+	(rect 32 608 208 624)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_VS" (rect 5 0 47 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 240 608 296 624))
+)
+(pin
+	(output)
+	(rect 32 584 208 600)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_HS" (rect 5 0 48 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 240 584 296 600))
+)
+(pin
+	(output)
+	(rect 32 504 208 520)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_R[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 504 264 520))
+)
+(pin
+	(output)
+	(rect 32 560 208 576)
+	(text "OUTPUT" (rect 140 0 178 10)(font "Arial" (font_size 6)))
+	(text "VGA_B[3..0]" (rect 5 0 66 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 179 8)(pt 127 8))
+		(line (pt 127 4)(pt 101 4))
+		(line (pt 127 12)(pt 101 12))
+		(line (pt 127 12)(pt 127 4))
+		(line (pt 101 4)(pt 97 8))
+		(line (pt 97 8)(pt 101 12))
+		(line (pt 101 12)(pt 97 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 248 560 280 568))
+)
+(pin
+	(output)
+	(rect 32 360 208 376)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX0_D[6..0]" (rect 5 0 72 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 208 376 264 392))
+)
+(pin
+	(output)
+	(rect 32 312 208 328)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "LEDG[9..0]" (rect 5 0 60 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 176 336 232 352))
+)
+(symbol
+	(rect 304 152 552 296)
+	(text "dot_product" (rect 5 0 62 12)(font "Arial" ))
+	(text "inst" (rect 8 128 25 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "input_a_rsc_z[7..0]" (rect 0 0 93 12)(font "Arial" ))
+		(text "input_a_rsc_z[7..0]" (rect 21 27 114 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input_b_rsc_z[7..0]" (rect 0 0 93 12)(font "Arial" ))
+		(text "input_b_rsc_z[7..0]" (rect 21 43 114 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 59 35 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "en" (rect 0 0 11 12)(font "Arial" ))
+		(text "en" (rect 21 75 32 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "arst_n" (rect 0 0 30 12)(font "Arial" ))
+		(text "arst_n" (rect 21 91 51 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 248 32)
+		(output)
+		(text "output_rsc_z[7..0]" (rect 0 0 88 12)(font "Arial" ))
+		(text "output_rsc_z[7..0]" (rect 153 27 241 39)(font "Arial" ))
+		(line (pt 248 32)(pt 232 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 232 128))
+	)
+)
+(symbol
+	(rect 728 168 760 200)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst1" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(connector
+	(text "A[7..4]" (rect 778 96 811 108)(font "Arial" ))
+	(pt 744 112)
+	(pt 792 112)
+	(bus)
+)
+(connector
+	(text "B[7..4]" (rect 784 112 817 124)(font "Arial" ))
+	(pt 744 128)
+	(pt 792 128)
+	(bus)
+)
+(connector
+	(text "LEDG[9..8]" (rect 782 128 837 140)(font "Arial" ))
+	(pt 744 144)
+	(pt 792 144)
+	(bus)
+)
+(connector
+	(pt 744 112)
+	(pt 744 128)
+	(bus)
+)
+(connector
+	(pt 744 128)
+	(pt 744 144)
+	(bus)
+)
+(connector
+	(pt 744 144)
+	(pt 744 168)
+	(bus)
+)
+(connector
+	(text "BUTTON[2]" (rect 220 208 276 220)(font "Arial" ))
+	(pt 304 216)
+	(pt 280 216)
+)
+(connector
+	(text "B[7..0]" (rect 251 184 284 196)(font "Arial" ))
+	(pt 304 200)
+	(pt 280 200)
+	(bus)
+)
+(connector
+	(text "A[7..0]" (rect 274 168 307 180)(font "Arial" ))
+	(pt 304 184)
+	(pt 280 184)
+	(bus)
+)
+(connector
+	(text "LEDG[9..0]" (rect 234 304 289 316)(font "Arial" ))
+	(pt 216 320)
+	(pt 240 320)
+	(bus)
+)
+(connector
+	(pt 208 232)
+	(pt 304 232)
+)
+(connector
+	(pt 208 248)
+	(pt 304 248)
+)
+(connector
+	(text "B[3..0]" (rect 220 144 253 156)(font "Arial" ))
+	(pt 208 160)
+	(pt 224 160)
+	(bus)
+)
+(connector
+	(text "A[3..0]" (rect 220 168 253 180)(font "Arial" ))
+	(pt 208 184)
+	(pt 224 184)
+	(bus)
+)
+(connector
+	(text "BUTTON[2..0]" (rect 219 112 288 124)(font "Arial" ))
+	(pt 208 128)
+	(pt 224 128)
+	(bus)
+)
+(connector
+	(text "LEDG[7..0]" (rect 560 168 615 180)(font "Arial" ))
+	(pt 584 184)
+	(pt 552 184)
+	(bus)
+)
+(junction (pt 744 128))
+(junction (pt 744 144))
+(text "FPGA PINS" (rect 72 16 202 38)(font "Arial" (font_size 14)))
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.done b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.done
new file mode 100644
index 0000000..bc5f511
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.done
@@ -0,0 +1 @@
+Tue Mar 01 16:05:18 2016
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt
new file mode 100644
index 0000000..c3e1165
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.rpt
@@ -0,0 +1,2749 @@
+Fitter report for ise_proj
+Tue Mar 01 16:05:13 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Dual Purpose and Dedicated Pins
+ 16. I/O Bank Usage
+ 17. All Package Pins
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Non-Global High Fan-Out Signals
+ 23. Other Routing Usage Summary
+ 24. LAB Logic Elements
+ 25. LAB-wide Signals
+ 26. LAB Signals Sourced
+ 27. LAB Signals Sourced Out
+ 28. LAB Distinct Inputs
+ 29. I/O Rules Summary
+ 30. I/O Rules Details
+ 31. I/O Rules Matrix
+ 32. Fitter Device Options
+ 33. Operating Settings and Conditions
+ 34. Estimated Delay Added for Hold Timing Summary
+ 35. Estimated Delay Added for Hold Timing Details
+ 36. Fitter Messages
+ 37. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Fitter Summary                                                                        ;
++------------------------------------+--------------------------------------------------+
+; Fitter Status                      ; Successful - Tue Mar 01 16:05:13 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ise_proj                                         ;
+; Top-level Entity Name              ; ise_proj                                         ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 53 / 15,408 ( < 1 % )                            ;
+;     Total combinational functions  ; 51 / 15,408 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 20 / 15,408 ( < 1 % )                            ;
+; Total registers                    ; 20                                               ;
+; Total pins                         ; 51 / 347 ( 15 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Nominal Core Supply Voltage                                                ; 1.2V                                  ;                                       ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 2.5 V                                 ;                                       ;
+; Use smart compilation                                                      ; Off                                   ; Off                                   ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.75        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  25.0%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------+
+; I/O Assignment Warnings                          ;
++-----------+--------------------------------------+
+; Pin Name  ; Reason                               ;
++-----------+--------------------------------------+
+; VGA_CLK   ; Missing drive strength and slew rate ;
+; VGA_SYNC  ; Missing drive strength and slew rate ;
+; VGA_BLANK ; Missing drive strength and slew rate ;
+; VGA_VS    ; Missing drive strength               ;
+; VGA_HS    ; Missing drive strength               ;
+; HEX0_D[6] ; Missing drive strength               ;
+; HEX0_D[5] ; Missing drive strength               ;
+; HEX0_D[4] ; Missing drive strength               ;
+; HEX0_D[3] ; Missing drive strength               ;
+; HEX0_D[2] ; Missing drive strength               ;
+; HEX0_D[1] ; Missing drive strength               ;
+; HEX0_D[0] ; Missing drive strength               ;
+; LEDG[9]   ; Missing drive strength               ;
+; LEDG[8]   ; Missing drive strength               ;
+; LEDG[7]   ; Missing drive strength               ;
+; LEDG[6]   ; Missing drive strength               ;
+; LEDG[5]   ; Missing drive strength               ;
+; LEDG[4]   ; Missing drive strength               ;
+; LEDG[3]   ; Missing drive strength               ;
+; LEDG[2]   ; Missing drive strength               ;
+; LEDG[1]   ; Missing drive strength               ;
+; LEDG[0]   ; Missing drive strength               ;
+; VGA_B[3]  ; Missing drive strength               ;
+; VGA_B[2]  ; Missing drive strength               ;
+; VGA_B[1]  ; Missing drive strength               ;
+; VGA_B[0]  ; Missing drive strength               ;
+; VGA_G[3]  ; Missing drive strength               ;
+; VGA_G[2]  ; Missing drive strength               ;
+; VGA_G[1]  ; Missing drive strength               ;
+; VGA_G[0]  ; Missing drive strength               ;
+; VGA_R[3]  ; Missing drive strength               ;
+; VGA_R[2]  ; Missing drive strength               ;
+; VGA_R[1]  ; Missing drive strength               ;
+; VGA_R[0]  ; Missing drive strength               ;
++-----------+--------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                             ;
++--------------+----------------+--------------+-----------------+---------------+----------------+
+; Name         ; Ignored Entity ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++--------------+----------------+--------------+-----------------+---------------+----------------+
+; Location     ;                ;              ; DRAM_ADDR[0]    ; PIN_C4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[10]   ; PIN_B4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[11]   ; PIN_A7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[1]    ; PIN_A3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[2]    ; PIN_B3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[3]    ; PIN_C3        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[4]    ; PIN_A5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[5]    ; PIN_C6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[6]    ; PIN_B6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[7]    ; PIN_A6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[8]    ; PIN_C7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_ADDR[9]    ; PIN_B7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA[0]      ; PIN_B5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA[1]      ; PIN_A4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA_0       ; PIN_B5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_BA_1       ; PIN_A4        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CAS_N      ; PIN_G8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CKE        ; PIN_E6        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CLK        ; PIN_E5        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_CS_N       ; PIN_G7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[0]      ; PIN_D10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[10]     ; PIN_A9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[11]     ; PIN_C10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[12]     ; PIN_B10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[13]     ; PIN_A10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[14]     ; PIN_E10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[15]     ; PIN_F10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[1]      ; PIN_G10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[2]      ; PIN_H10       ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[3]      ; PIN_E9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[4]      ; PIN_F9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[5]      ; PIN_G9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[6]      ; PIN_H9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[7]      ; PIN_F8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[8]      ; PIN_A8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_DQ[9]      ; PIN_B9        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_LDQM       ; PIN_E7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_RAS_N      ; PIN_F7        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_UDQM       ; PIN_B8        ; QSF Assignment ;
+; Location     ;                ;              ; DRAM_WE_N       ; PIN_D6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[0]      ; PIN_P7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[10]     ; PIN_N1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[11]     ; PIN_M3        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[12]     ; PIN_M2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[13]     ; PIN_M1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[14]     ; PIN_L7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[15]     ; PIN_L6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[16]     ; PIN_AA2       ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[17]     ; PIN_M5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[18]     ; PIN_M6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[19]     ; PIN_P1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[1]      ; PIN_P5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[20]     ; PIN_P3        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[21]     ; PIN_R2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[2]      ; PIN_P6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[3]      ; PIN_N7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[4]      ; PIN_N5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[5]      ; PIN_N6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[6]      ; PIN_M8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[7]      ; PIN_M4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[8]      ; PIN_P2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_ADDR[9]      ; PIN_N2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_BYTE_N       ; PIN_AA1       ; QSF Assignment ;
+; Location     ;                ;              ; FL_CE_N         ; PIN_N8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ15_AM1     ; PIN_Y2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[0]        ; PIN_R7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[10]       ; PIN_T4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[11]       ; PIN_U2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[12]       ; PIN_V1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[13]       ; PIN_V4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[14]       ; PIN_W2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[1]        ; PIN_P8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[2]        ; PIN_R8        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[3]        ; PIN_U1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[4]        ; PIN_V2        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[5]        ; PIN_V3        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[6]        ; PIN_W1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[7]        ; PIN_Y1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[8]        ; PIN_T5        ; QSF Assignment ;
+; Location     ;                ;              ; FL_DQ[9]        ; PIN_T7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_OE_N         ; PIN_R6        ; QSF Assignment ;
+; Location     ;                ;              ; FL_RST_N        ; PIN_R1        ; QSF Assignment ;
+; Location     ;                ;              ; FL_RY           ; PIN_M7        ; QSF Assignment ;
+; Location     ;                ;              ; FL_WE_N         ; PIN_P4        ; QSF Assignment ;
+; Location     ;                ;              ; FL_WP_N         ; PIN_T3        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKIN[0]  ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKIN[1]  ; PIN_AA12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKOUT[0] ; PIN_AB3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_CLKOUT[1] ; PIN_AA3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[0]      ; PIN_AB16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[10]     ; PIN_AB8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[11]     ; PIN_AA8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[12]     ; PIN_AB5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[13]     ; PIN_AA5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[14]     ; PIN_AB4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[15]     ; PIN_AA4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[16]     ; PIN_V14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[17]     ; PIN_U14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[18]     ; PIN_Y13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[19]     ; PIN_W13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[1]      ; PIN_AA16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[20]     ; PIN_U13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[21]     ; PIN_V12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[22]     ; PIN_R10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[23]     ; PIN_V11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[24]     ; PIN_Y10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[25]     ; PIN_W10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[26]     ; PIN_T8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[27]     ; PIN_V8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[28]     ; PIN_W7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[29]     ; PIN_W6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[2]      ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[30]     ; PIN_V5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[31]     ; PIN_U7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[3]      ; PIN_AB15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[4]      ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[5]      ; PIN_AB14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[6]      ; PIN_AB13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[7]      ; PIN_AA13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[8]      ; PIN_AB10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO0_D[9]      ; PIN_AA10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKIN[0]  ; PIN_AB11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKIN[1]  ; PIN_AA11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKOUT[0] ; PIN_R16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_CLKOUT[1] ; PIN_T16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[0]      ; PIN_AA20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[10]     ; PIN_U15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[11]     ; PIN_T15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[12]     ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[13]     ; PIN_V15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[14]     ; PIN_AB9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[15]     ; PIN_AA9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[16]     ; PIN_AA7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[17]     ; PIN_AB7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[18]     ; PIN_T14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[19]     ; PIN_R14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[1]      ; PIN_AB20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[20]     ; PIN_U12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[21]     ; PIN_T12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[22]     ; PIN_R11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[23]     ; PIN_R12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[24]     ; PIN_U10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[25]     ; PIN_T10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[26]     ; PIN_U9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[27]     ; PIN_T9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[28]     ; PIN_Y7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[29]     ; PIN_U8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[2]      ; PIN_AA19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[30]     ; PIN_V6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[31]     ; PIN_V7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[3]      ; PIN_AB19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[4]      ; PIN_AB18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[5]      ; PIN_AA18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[6]      ; PIN_AA17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[7]      ; PIN_AB17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[8]      ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO1_D[9]      ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[0]       ; PIN_AB16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[10]      ; PIN_AB8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[11]      ; PIN_AA8       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[12]      ; PIN_AB5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[13]      ; PIN_AA5       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[14]      ; PIN_AB4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[15]      ; PIN_AA4       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[16]      ; PIN_V14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[17]      ; PIN_U14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[18]      ; PIN_Y13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[19]      ; PIN_W13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[1]       ; PIN_AA16      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[20]      ; PIN_U13       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[21]      ; PIN_V12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[22]      ; PIN_R10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[23]      ; PIN_V11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[24]      ; PIN_Y10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[25]      ; PIN_W10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[26]      ; PIN_T8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[27]      ; PIN_V8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[28]      ; PIN_W7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[29]      ; PIN_W6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[2]       ; PIN_AA15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[30]      ; PIN_V5        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[31]      ; PIN_U7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[3]       ; PIN_AB15      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[4]       ; PIN_AA14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[5]       ; PIN_AB14      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[6]       ; PIN_AB13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[7]       ; PIN_AA13      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[8]       ; PIN_AB10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_0[9]       ; PIN_AA10      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[0]       ; PIN_AA20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[10]      ; PIN_U15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[11]      ; PIN_T15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[12]      ; PIN_W15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[13]      ; PIN_V15       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[14]      ; PIN_AB9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[15]      ; PIN_AA9       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[16]      ; PIN_AA7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[17]      ; PIN_AB7       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[18]      ; PIN_T14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[19]      ; PIN_R14       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[1]       ; PIN_AB20      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[20]      ; PIN_U12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[21]      ; PIN_T12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[22]      ; PIN_R11       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[23]      ; PIN_R12       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[24]      ; PIN_U10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[25]      ; PIN_T10       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[26]      ; PIN_U9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[27]      ; PIN_T9        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[28]      ; PIN_Y7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[29]      ; PIN_U8        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[2]       ; PIN_AA19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[30]      ; PIN_V6        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[31]      ; PIN_V7        ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[3]       ; PIN_AB19      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[4]       ; PIN_AB18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[5]       ; PIN_AA18      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[6]       ; PIN_AA17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[7]       ; PIN_AB17      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[8]       ; PIN_Y17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_1[9]       ; PIN_W17       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_N0   ; PIN_AB12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_N1   ; PIN_AB11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_P0   ; PIN_AA12      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKIN_P1   ; PIN_AA11      ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_N0  ; PIN_AB3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_N1  ; PIN_R16       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_P0  ; PIN_AA3       ; QSF Assignment ;
+; Location     ;                ;              ; GPIO_CLKOUT_P1  ; PIN_T16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[0]         ; PIN_E11       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[1]         ; PIN_F11       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[2]         ; PIN_H12       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[3]         ; PIN_H13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[4]         ; PIN_G12       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[5]         ; PIN_F12       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[6]         ; PIN_F13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0[7]         ; PIN_D13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[0]         ; PIN_A13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[1]         ; PIN_B13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[2]         ; PIN_C13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[3]         ; PIN_A14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[4]         ; PIN_B14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[5]         ; PIN_E14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[6]         ; PIN_A15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1[7]         ; PIN_B15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[0]       ; PIN_A13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[1]       ; PIN_B13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[2]       ; PIN_C13       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[3]       ; PIN_A14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[4]       ; PIN_B14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[5]       ; PIN_E14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX1_D[6]       ; PIN_A15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[0]         ; PIN_D15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[1]         ; PIN_A16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[2]         ; PIN_B16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[3]         ; PIN_E15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[4]         ; PIN_A17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[5]         ; PIN_B17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[6]         ; PIN_F14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2[7]         ; PIN_A18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[0]       ; PIN_D15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[1]       ; PIN_A16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[2]       ; PIN_B16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[3]       ; PIN_E15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[4]       ; PIN_A17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[5]       ; PIN_B17       ; QSF Assignment ;
+; Location     ;                ;              ; HEX2_D[6]       ; PIN_F14       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[0]         ; PIN_B18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[1]         ; PIN_F15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[2]         ; PIN_A19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[3]         ; PIN_B19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[4]         ; PIN_C19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[5]         ; PIN_D19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[6]         ; PIN_G15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3[7]         ; PIN_G16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[0]       ; PIN_B18       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[1]       ; PIN_F15       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[2]       ; PIN_A19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[3]       ; PIN_B19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[4]       ; PIN_C19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[5]       ; PIN_D19       ; QSF Assignment ;
+; Location     ;                ;              ; HEX3_D[6]       ; PIN_G15       ; QSF Assignment ;
+; Location     ;                ;              ; KEY[0]          ; PIN_H2        ; QSF Assignment ;
+; Location     ;                ;              ; KEY[1]          ; PIN_G3        ; QSF Assignment ;
+; Location     ;                ;              ; KEY[2]          ; PIN_F1        ; QSF Assignment ;
+; Location     ;                ;              ; LCD_BLON        ; PIN_F21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[0]     ; PIN_D22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[1]     ; PIN_D21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[2]     ; PIN_C22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[3]     ; PIN_C21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[4]     ; PIN_B22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[5]     ; PIN_B21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[6]     ; PIN_D20       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_DATA[7]     ; PIN_C20       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_EN          ; PIN_E21       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_RS          ; PIN_F22       ; QSF Assignment ;
+; Location     ;                ;              ; LCD_RW          ; PIN_E22       ; QSF Assignment ;
+; Location     ;                ;              ; PS2_KBCLK       ; PIN_P22       ; QSF Assignment ;
+; Location     ;                ;              ; PS2_KBDAT       ; PIN_P21       ; QSF Assignment ;
+; Location     ;                ;              ; SD_CLK          ; PIN_Y21       ; QSF Assignment ;
+; Location     ;                ;              ; SD_CMD          ; PIN_Y22       ; QSF Assignment ;
+; Location     ;                ;              ; SD_DAT0         ; PIN_AA22      ; QSF Assignment ;
+; Location     ;                ;              ; SD_DAT3         ; PIN_W21       ; QSF Assignment ;
+; Location     ;                ;              ; SD_WP_N         ; PIN_W20       ; QSF Assignment ;
+; Location     ;                ;              ; UART_CTS        ; PIN_V21       ; QSF Assignment ;
+; Location     ;                ;              ; UART_RTS        ; PIN_V22       ; QSF Assignment ;
+; Location     ;                ;              ; UART_RXD        ; PIN_U22       ; QSF Assignment ;
+; Location     ;                ;              ; UART_TXD        ; PIN_U21       ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[0]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[10]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[11]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[1]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[2]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[3]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[4]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[5]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[6]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[7]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[8]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_ADDR[9]    ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_BA_0       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_BA_1       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CAS_N      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CKE        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CLK        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_CS_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_DQ[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_LDQM       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_RAS_N      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_UDQM       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; DRAM_WE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[22]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[23]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[24]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[25]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[26]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[27]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[28]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[29]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[30]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[31]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO0_D[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[22]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[23]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[24]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[25]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[26]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[27]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[28]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[29]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[30]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[31]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; GPIO1_D[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard ;                ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
++--------------+----------------+--------------+-----------------+---------------+----------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+------------------------+
+; Type                ; Value                  ;
++---------------------+------------------------+
+; Placement (by node) ;                        ;
+;     -- Requested    ; 0 / 182 ( 0.00 % )     ;
+;     -- Achieved     ; 0 / 182 ( 0.00 % )     ;
+;                     ;                        ;
+; Routing (by net)    ;                        ;
+;     -- Requested    ; 0 / 0 ( 0.00 % )       ;
+;     -- Achieved     ; 0 / 0 ( 0.00 % )       ;
++---------------------+------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                             ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name                 ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+; Top                            ; 174     ; 0                 ; N/A                     ; Source File       ;
+; hard_block:auto_generated_inst ; 8       ; 0                 ; N/A                     ; Source File       ;
++--------------------------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                       ;
++---------------------------------------------+-----------------------+
+; Resource                                    ; Usage                 ;
++---------------------------------------------+-----------------------+
+; Total logic elements                        ; 53 / 15,408 ( < 1 % ) ;
+;     -- Combinational with no register       ; 33                    ;
+;     -- Register only                        ; 2                     ;
+;     -- Combinational with a register        ; 18                    ;
+;                                             ;                       ;
+; Logic element usage by number of LUT inputs ;                       ;
+;     -- 4 input functions                    ; 13                    ;
+;     -- 3 input functions                    ; 22                    ;
+;     -- <=2 input functions                  ; 16                    ;
+;     -- Register only                        ; 2                     ;
+;                                             ;                       ;
+; Logic elements by mode                      ;                       ;
+;     -- normal mode                          ; 32                    ;
+;     -- arithmetic mode                      ; 19                    ;
+;                                             ;                       ;
+; Total registers*                            ; 20 / 17,068 ( < 1 % ) ;
+;     -- Dedicated logic registers            ; 20 / 15,408 ( < 1 % ) ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )     ;
+;                                             ;                       ;
+; Total LABs:  partially or completely used   ; 5 / 963 ( < 1 % )     ;
+; Virtual pins                                ; 0                     ;
+; I/O pins                                    ; 51 / 347 ( 15 % )     ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )        ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )         ;
+;                                             ;                       ;
+; Global signals                              ; 0                     ;
+; M9Ks                                        ; 0 / 56 ( 0 % )        ;
+; Total block memory bits                     ; 0 / 516,096 ( 0 % )   ;
+; Total block memory implementation bits      ; 0 / 516,096 ( 0 % )   ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ;
+; PLLs                                        ; 0 / 4 ( 0 % )         ;
+; Global clocks                               ; 0 / 20 ( 0 % )        ;
+; JTAGs                                       ; 0 / 1 ( 0 % )         ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )         ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )         ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )         ;
+; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%          ;
+; Peak interconnect usage (total/H/V)         ; 0% / 0% / 1%          ;
+; Maximum fan-out                             ; 20                    ;
+; Highest non-global fan-out                  ; 20                    ;
+; Total fan-out                               ; 295                   ;
+; Average fan-out                             ; 1.61                  ;
++---------------------------------------------+-----------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                         ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic                                   ; Top                  ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                  ; Low                            ;
+;                                             ;                      ;                                ;
+; Total logic elements                        ; 53 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 33                   ; 0                              ;
+;     -- Register only                        ; 2                    ; 0                              ;
+;     -- Combinational with a register        ; 18                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic element usage by number of LUT inputs ;                      ;                                ;
+;     -- 4 input functions                    ; 13                   ; 0                              ;
+;     -- 3 input functions                    ; 22                   ; 0                              ;
+;     -- <=2 input functions                  ; 16                   ; 0                              ;
+;     -- Register only                        ; 2                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Logic elements by mode                      ;                      ;                                ;
+;     -- normal mode                          ; 32                   ; 0                              ;
+;     -- arithmetic mode                      ; 19                   ; 0                              ;
+;                                             ;                      ;                                ;
+; Total registers                             ; 20                   ; 0                              ;
+;     -- Dedicated logic registers            ; 20 / 15408 ( < 1 % ) ; 0 / 15408 ( 0 % )              ;
+;                                             ;                      ;                                ;
+; Total LABs:  partially or completely used   ; 5 / 963 ( < 1 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                      ;                                ;
+; Virtual pins                                ; 0                    ; 0                              ;
+; I/O pins                                    ; 51                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )      ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 0                    ; 0                              ;
+; Total RAM block bits                        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Connections                                 ;                      ;                                ;
+;     -- Input Connections                    ; 0                    ; 0                              ;
+;     -- Registered Input Connections         ; 0                    ; 0                              ;
+;     -- Output Connections                   ; 0                    ; 0                              ;
+;     -- Registered Output Connections        ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Internal Connections                        ;                      ;                                ;
+;     -- Total Connections                    ; 291                  ; 4                              ;
+;     -- Registered Connections               ; 37                   ; 0                              ;
+;                                             ;                      ;                                ;
+; External Connections                        ;                      ;                                ;
+;     -- Top                                  ; 0                    ; 0                              ;
+;     -- hard_block:auto_generated_inst       ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Partition Interface                         ;                      ;                                ;
+;     -- Input Ports                          ; 17                   ; 0                              ;
+;     -- Output Ports                         ; 34                   ; 0                              ;
+;     -- Bidir Ports                          ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Registered Ports                            ;                      ;                                ;
+;     -- Registered Input Ports               ; 0                    ; 0                              ;
+;     -- Registered Output Ports              ; 0                    ; 0                              ;
+;                                             ;                      ;                                ;
+; Port Connectivity                           ;                      ;                                ;
+;     -- Input Ports driven by GND            ; 0                    ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                    ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                    ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                    ; 0                              ;
+;     -- Input Ports with no Source           ; 0                    ; 0                              ;
+;     -- Output Ports with no Source          ; 0                    ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                    ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                    ; 0                              ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                      ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; BUTTON[0]  ; H2    ; 1        ; 0            ; 21           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; BUTTON[1]  ; G3    ; 1        ; 0            ; 23           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; BUTTON[2]  ; F1    ; 1        ; 0            ; 23           ; 0            ; 20                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; CLOCK_50   ; G21   ; 6        ; 41           ; 15           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; CLOCK_50_2 ; B12   ; 7        ; 19           ; 29           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; PS2_MSCLK  ; R21   ; 5        ; 41           ; 10           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; PS2_MSDAT  ; R22   ; 5        ; 41           ; 10           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]      ; J6    ; 1        ; 0            ; 24           ; 0            ; 5                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]      ; H5    ; 1        ; 0            ; 27           ; 0            ; 17                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]      ; H6    ; 1        ; 0            ; 25           ; 21           ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]      ; G4    ; 1        ; 0            ; 23           ; 7            ; 7                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]      ; G5    ; 1        ; 0            ; 27           ; 21           ; 5                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]      ; J7    ; 1        ; 0            ; 22           ; 14           ; 5                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]      ; H7    ; 1        ; 0            ; 25           ; 14           ; 5                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]      ; E3    ; 1        ; 0            ; 26           ; 7            ; 5                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]      ; E4    ; 1        ; 0            ; 26           ; 0            ; 13                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]      ; D2    ; 1        ; 0            ; 25           ; 0            ; 20                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination                       ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; HEX0_D[0] ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[1] ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[2] ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[3] ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[4] ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[5] ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0_D[6] ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]   ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]   ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]   ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]   ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]   ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]   ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]   ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]   ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]   ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]   ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_BLANK ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_B[0]  ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]  ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]  ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]  ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK   ; R12   ; 3        ; 5            ; 0            ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]  ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]  ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]  ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]  ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS    ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]  ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]  ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]  ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]  ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_SYNC  ; E9    ; 8        ; 11           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 2.5 V        ; Default          ; Series 50 Ohm without Calibration ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_VS    ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                               ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                   ;
++----------+---------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                              ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+---------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                    ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO               ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO           ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                               ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                  ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                 ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                               ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                   ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                             ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                 ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                     ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                   ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO        ; HEX0_D[6]               ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                   ; Use as regular IO        ; HEX0_D[0]               ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                   ; Use as regular IO        ; HEX0_D[1]               ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                    ; Use as regular IO        ; VGA_BLANK               ; Dual Purpose Pin          ;
++----------+---------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 2.5V          ; --           ;
+; 3        ; 1 / 46 ( 2 % )   ; 2.5V          ; --           ;
+; 4        ; 0 / 41 ( 0 % )   ; 2.5V          ; --           ;
+; 5        ; 2 / 46 ( 4 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 8 / 47 ( 17 % )  ; 3.3V          ; --           ;
+; 8        ; 2 / 43 ( 5 % )   ; 2.5V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A4       ; 350        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A5       ; 345        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A6       ; 336        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A7       ; 334        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A8       ; 332        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A9       ; 328        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A10      ; 326        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A14      ; 312        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A15      ; 307        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A16      ; 298        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A17      ; 296        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA18     ; 163        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA19     ; 164        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA20     ; 169        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB18     ; 162        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB19     ; 165        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB20     ; 170        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B4       ; 351        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B5       ; 346        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B6       ; 337        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B7       ; 335        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B8       ; 333        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B9       ; 329        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B10      ; 327        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; CLOCK_50_2                                                ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B13      ; 315        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B14      ; 313        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B17      ; 297        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B18      ; 292        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B19      ; 289        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C4       ; 359        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C7       ; 340        ; 8        ; VGA_BLANK                                                 ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E6       ; 362        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E7       ; 357        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; VGA_SYNC                                                  ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E11      ; 317        ; 7        ; HEX0_D[0]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E15      ; 294        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; BUTTON[2]                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F8       ; 352        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F9       ; 347        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F10      ; 348        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F11      ; 318        ; 7        ; HEX0_D[1]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0_D[5]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0_D[6]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F15      ; 276        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; BUTTON[1]                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G8       ; 353        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G9       ; 342        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G10      ; 341        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0_D[4]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; BUTTON[0]                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H10      ; 343        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0_D[2]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0_D[3]                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R12      ; 98         ; 3        ; VGA_CLK                                                   ; output ; 2.5 V        ;         ; Column I/O ; N               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; PS2_MSCLK                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R22      ; 206        ; 5        ; PS2_MSDAT                                                 ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T10      ; 121        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T15      ; 161        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T16      ; 171        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U9       ; 112        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U10      ; 122        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V7       ; 105        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                    ;
++------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                     ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                      ; Library Name ;
++------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+
+; |ise_proj                                      ; 53 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 51   ; 0            ; 33 (0)       ; 2 (0)             ; 18 (0)           ; |ise_proj                                                                                                ; work         ;
+;    |dot_product:inst|                          ; 53 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (0)       ; 2 (0)             ; 18 (0)           ; |ise_proj|dot_product:inst                                                                               ; work         ;
+;       |dot_product_core:dot_product_core_inst| ; 53 (23)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 33 (3)       ; 2 (2)             ; 18 (18)          ; |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst                                        ; work         ;
+;          |lpm_mult:Mult0|                      ; 30 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (0)       ; 0 (0)             ; 0 (0)            ; |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0                         ; work         ;
+;             |mult_a7t:auto_generated|          ; 30 (30)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 0 (0)            ; |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated ; work         ;
++------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                        ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name       ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+; VGA_CLK    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_SYNC   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_BLANK  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[6]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[5]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[4]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[3]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[2]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[1]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0_D[0]  ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; BUTTON[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; BUTTON[0]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]   ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; PS2_MSDAT  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; PS2_MSCLK  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; CLOCK_50   ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; CLOCK_50_2 ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[3]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[2]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[1]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; BUTTON[2]  ; Input    ; --            ; (0) 0 ps      ; --                    ; --  ; --   ;
+; SW[9]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[8]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[7]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[6]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[5]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[0]      ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[4]      ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                ;
++-----------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                             ; Pad To Core Index ; Setting ;
++-----------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; BUTTON[1]                                                                                                       ;                   ;         ;
+; BUTTON[0]                                                                                                       ;                   ;         ;
+; PS2_MSDAT                                                                                                       ;                   ;         ;
+; PS2_MSCLK                                                                                                       ;                   ;         ;
+; CLOCK_50                                                                                                        ;                   ;         ;
+; CLOCK_50_2                                                                                                      ;                   ;         ;
+; SW[3]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[5]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[4]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[1]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[0]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[0]   ; 1                 ; 6       ;
+; SW[2]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[5]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[3]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[4]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[2]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|cs2a[1]~0 ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[1]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[0]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[0]   ; 0                 ; 6       ;
+; SW[1]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~0    ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[5]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[4]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|cs2a[1]~0 ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[1]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[4]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[0]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[0]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[1]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[0]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~14   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~12   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~10   ; 1                 ; 6       ;
+; BUTTON[2]                                                                                                       ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]                   ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                                     ; 1                 ; 0       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                                     ; 1                 ; 0       ;
+; SW[9]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]                   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                                     ; 1                 ; 6       ;
+; SW[8]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]~0                 ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                                     ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                                     ; 1                 ; 6       ;
+; SW[7]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[4]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[4]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[3]   ; 1                 ; 6       ;
+; SW[6]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[2]   ; 1                 ; 6       ;
+; SW[5]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[1]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[1]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[1]   ; 1                 ; 6       ;
+; SW[0]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[4]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[3]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[2]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[1]   ; 1                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[0]   ; 1                 ; 6       ;
+; SW[4]                                                                                                           ;                   ;         ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[0]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[1]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[0]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[1]   ; 0                 ; 6       ;
+;      - dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[0]   ; 0                 ; 6       ;
++-----------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                      ;
++------------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                     ; Location          ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++------------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; BUTTON[2]                                                                                ; PIN_F1            ; 20      ; Clock        ; no     ; --                   ; --               ; --                        ;
+; SW[8]                                                                                    ; PIN_E4            ; 13      ; Clock enable ; no     ; --                   ; --               ; --                        ;
+; SW[9]                                                                                    ; PIN_D2            ; 20      ; Async. clear ; no     ; --                   ; --               ; --                        ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]~0 ; LCCOMB_X1_Y24_N28 ; 8       ; Clock enable ; no     ; --                   ; --               ; --                        ;
++------------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                    ;
++----------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                     ; Fan-Out ;
++----------------------------------------------------------------------------------------------------------+---------+
+; SW[9]~input                                                                                              ; 20      ;
+; BUTTON[2]~input                                                                                          ; 20      ;
+; SW[1]~input                                                                                              ; 17      ;
+; SW[8]~input                                                                                              ; 13      ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                                     ; 13      ;
+; SW[2]~input                                                                                              ; 8       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]~0                 ; 8       ;
+; SW[3]~input                                                                                              ; 7       ;
+; SW[4]~input                                                                                              ; 5       ;
+; SW[0]~input                                                                                              ; 5       ;
+; SW[5]~input                                                                                              ; 5       ;
+; SW[6]~input                                                                                              ; 5       ;
+; SW[7]~input                                                                                              ; 5       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[5]   ; 5       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                                     ; 3       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|cs2a[1]~0 ; 3       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                                     ; 3       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                                     ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[7]~22                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[6]~20                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[5]~18                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[4]~16                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[3]~14                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[2]~12                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[1]~10                               ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[0]~8                                ; 2       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|Add1~1                                           ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_i_1_sva_2~1                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|Add1~0                                           ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_i_1_sva_2~0                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[0]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[1]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[0]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[1]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[0]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[2]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[3]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[2]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le3a[4]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[1]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[3]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[2]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le4a[4]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[3]   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~7                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~6                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~5                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~4                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~3                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~2                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~1                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2~0                                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                                     ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]                   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[6]~21                               ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[5]~19                               ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[4]~17                               ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[3]~15                               ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[2]~13                               ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[1]~11                               ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|nl_acc_sva_2[0]~9                                ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~14   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~13   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~12   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~11   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~10   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~9    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~8    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~7    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~6    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~5    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~4    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~3    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~2    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~1    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_3~0    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~10   ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~9    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~8    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~7    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~6    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~5    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~4    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~3    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~2    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~1    ; 1       ;
+; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|op_1~0    ; 1       ;
++----------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------+
+; Other Routing Usage Summary                         ;
++-----------------------------+-----------------------+
+; Other Routing Resource Type ; Usage                 ;
++-----------------------------+-----------------------+
+; Block interconnects         ; 67 / 47,787 ( < 1 % ) ;
+; C16 interconnects           ; 0 / 1,804 ( 0 % )     ;
+; C4 interconnects            ; 28 / 31,272 ( < 1 % ) ;
+; Direct links                ; 19 / 47,787 ( < 1 % ) ;
+; Global clocks               ; 0 / 20 ( 0 % )        ;
+; Local interconnects         ; 22 / 15,408 ( < 1 % ) ;
+; R24 interconnects           ; 0 / 1,775 ( 0 % )     ;
+; R4 interconnects            ; 27 / 41,310 ( < 1 % ) ;
++-----------------------------+-----------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Logic Elements                                                        ;
++---------------------------------------------+-----------------------------+
+; Number of Logic Elements  (Average = 10.60) ; Number of LABs  (Total = 5) ;
++---------------------------------------------+-----------------------------+
+; 1                                           ; 0                           ;
+; 2                                           ; 0                           ;
+; 3                                           ; 1                           ;
+; 4                                           ; 0                           ;
+; 5                                           ; 0                           ;
+; 6                                           ; 0                           ;
+; 7                                           ; 0                           ;
+; 8                                           ; 0                           ;
+; 9                                           ; 1                           ;
+; 10                                          ; 0                           ;
+; 11                                          ; 1                           ;
+; 12                                          ; 0                           ;
+; 13                                          ; 0                           ;
+; 14                                          ; 1                           ;
+; 15                                          ; 0                           ;
+; 16                                          ; 1                           ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals                                                 ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals  (Average = 1.60) ; Number of LABs  (Total = 5) ;
++------------------------------------+-----------------------------+
+; 1 Async. clear                     ; 3                           ;
+; 1 Clock                            ; 3                           ;
+; 1 Clock enable                     ; 2                           ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced  (Average = 14.60) ; Number of LABs  (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 0                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 1                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 0                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 0                           ;
+; 13                                           ; 0                           ;
+; 14                                           ; 1                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 1                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 1                           ;
+; 19                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                       ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out  (Average = 8.40) ; Number of LABs  (Total = 5) ;
++-------------------------------------------------+-----------------------------+
+; 0                                               ; 0                           ;
+; 1                                               ; 1                           ;
+; 2                                               ; 0                           ;
+; 3                                               ; 0                           ;
+; 4                                               ; 0                           ;
+; 5                                               ; 0                           ;
+; 6                                               ; 0                           ;
+; 7                                               ; 1                           ;
+; 8                                               ; 0                           ;
+; 9                                               ; 2                           ;
+; 10                                              ; 0                           ;
+; 11                                              ; 0                           ;
+; 12                                              ; 0                           ;
+; 13                                              ; 0                           ;
+; 14                                              ; 0                           ;
+; 15                                              ; 0                           ;
+; 16                                              ; 1                           ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                        ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs  (Average = 11.60) ; Number of LABs  (Total = 5) ;
++----------------------------------------------+-----------------------------+
+; 0                                            ; 0                           ;
+; 1                                            ; 0                           ;
+; 2                                            ; 0                           ;
+; 3                                            ; 0                           ;
+; 4                                            ; 1                           ;
+; 5                                            ; 0                           ;
+; 6                                            ; 0                           ;
+; 7                                            ; 0                           ;
+; 8                                            ; 1                           ;
+; 9                                            ; 0                           ;
+; 10                                           ; 0                           ;
+; 11                                           ; 0                           ;
+; 12                                           ; 1                           ;
+; 13                                           ; 1                           ;
+; 14                                           ; 0                           ;
+; 15                                           ; 0                           ;
+; 16                                           ; 0                           ;
+; 17                                           ; 0                           ;
+; 18                                           ; 0                           ;
+; 19                                           ; 0                           ;
+; 20                                           ; 0                           ;
+; 21                                           ; 1                           ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 12    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 18    ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area                ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O                 ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O                 ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Pass         ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O                 ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; No open drain assignments found.                                         ; I/O                 ;                   ;
+; Pass         ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength assignments found.                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O                 ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O                 ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O                 ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O                 ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O                 ;                   ;
+; ----         ; ----      ; Disclaimer                        ; OCT rules are checked but not reported.                                                              ; None     ; ----                                                                     ; On Chip Termination ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 48           ; 0            ; 48           ; 0            ; 0            ; 51        ; 48           ; 0            ; 51        ; 51        ; 0            ; 3            ; 0            ; 0            ; 17           ; 0            ; 3            ; 17           ; 0            ; 0            ; 0            ; 3            ; 0            ; 0            ; 0            ; 0            ; 0            ; 51        ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 3            ; 51           ; 3            ; 51           ; 51           ; 0         ; 3            ; 51           ; 0         ; 0         ; 51           ; 48           ; 51           ; 51           ; 34           ; 51           ; 48           ; 34           ; 51           ; 51           ; 51           ; 48           ; 51           ; 51           ; 51           ; 51           ; 51           ; 0         ; 51           ; 51           ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_SYNC           ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_BLANK          ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0_D[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BUTTON[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BUTTON[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_MSDAT          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_MSCLK          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50_2         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; BUTTON[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; On                       ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary              ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer.
+
+
++------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                              ;
++-----------------+----------------------------------------------------------------------+-------------------+
+; Source Register ; Destination Register                                                 ; Delay Added in ns ;
++-----------------+----------------------------------------------------------------------+-------------------+
+; BUTTON[2]       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; 0.522             ;
++-----------------+----------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 1 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "ise_proj"
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 3 pins of 51 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+    Info (169086): Pin VGA_SYNC not assigned to an exact location on the device
+    Info (169086): Pin VGA_BLANK not assigned to an exact location on the device
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 3 (unused VREF, 2.5V VCCIO, 0 input, 3 output, 0 bidirectional)
+        Info (176212): I/O standards used: 2.5 V.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  41 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used --  44 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used --  39 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  43 pins available
+Warning (15709): Ignored I/O standard assignments to the following nodes
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[0]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[10]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[11]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[1]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[2]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[3]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[4]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[5]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[6]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[7]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[8]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_ADDR[9]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_BA_0"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_BA_1"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CAS_N"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CKE"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CLK"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_CS_N"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[0]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[10]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[11]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[12]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[13]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[14]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[15]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[1]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[2]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[3]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[4]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[5]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[6]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[7]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[8]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_DQ[9]"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_LDQM"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_RAS_N"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_UDQM"
+    Warning (15710): Ignored I/O standard assignment to node "DRAM_WE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[15]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[16]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[17]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[18]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[19]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[20]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[21]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_ADDR[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_BYTE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_CE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ15_AM1"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[0]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[10]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[11]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[12]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[13]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[14]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[1]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[2]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[3]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[4]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[5]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[6]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[7]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[8]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_DQ[9]"
+    Warning (15710): Ignored I/O standard assignment to node "FL_OE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RST_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_RY"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WE_N"
+    Warning (15710): Ignored I/O standard assignment to node "FL_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[10]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[11]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[12]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[13]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[14]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[15]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[16]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[17]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[18]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[19]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[20]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[21]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[22]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[23]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[24]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[25]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[26]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[27]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[28]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[29]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[30]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[31]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[7]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[8]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO0_D[9]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKIN[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_CLKOUT[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[10]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[11]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[12]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[13]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[14]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[15]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[16]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[17]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[18]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[19]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[20]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[21]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[22]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[23]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[24]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[25]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[26]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[27]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[28]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[29]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[30]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[31]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[7]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[8]"
+    Warning (15710): Ignored I/O standard assignment to node "GPIO1_D[9]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX0_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX1_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX2_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_DP"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[0]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[1]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[2]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[3]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[4]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[5]"
+    Warning (15710): Ignored I/O standard assignment to node "HEX3_D[6]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_BLON"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[0]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[1]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[2]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[3]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[4]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[5]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[6]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_DATA[7]"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_EN"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RS"
+    Warning (15710): Ignored I/O standard assignment to node "LCD_RW"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBCLK"
+    Warning (15710): Ignored I/O standard assignment to node "PS2_KBDAT"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CLK"
+    Warning (15710): Ignored I/O standard assignment to node "SD_CMD"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT0"
+    Warning (15710): Ignored I/O standard assignment to node "SD_DAT3"
+    Warning (15710): Ignored I/O standard assignment to node "SD_WP_N"
+    Warning (15710): Ignored I/O standard assignment to node "UART_CTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RTS"
+    Warning (15710): Ignored I/O standard assignment to node "UART_RXD"
+    Warning (15710): Ignored I/O standard assignment to node "UART_TXD"
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA_0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_BA_1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_LDQM" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_UDQM" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_BYTE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ15_AM1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_DQ[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKIN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKIN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKOUT[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_CLKOUT[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_D[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKIN[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKIN[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKOUT[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_CLKOUT[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_D[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_0[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[10]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[11]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[13]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[14]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[15]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[16]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[17]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[18]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[19]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[20]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[21]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[22]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[23]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[24]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[25]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[26]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[27]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[28]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[29]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[30]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[31]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[8]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_1[9]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_N0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_N1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_P0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKIN_P1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_N0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_N1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_P0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO_CLKOUT_P1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_D[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_KBCLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_KBDAT" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_DAT0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_DAT3" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y20 to location X9_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 0.14 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 17 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin BUTTON[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin BUTTON[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin PS2_MSDAT uses I/O standard 3.3-V LVTTL at R22
+    Info (169178): Pin PS2_MSCLK uses I/O standard 3.3-V LVTTL at R21
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin CLOCK_50_2 uses I/O standard 3.3-V LVTTL at B12
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin BUTTON[2] uses I/O standard 3.3-V LVTTL at F1
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+Info (144001): Generated suppressed messages file C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 524 warnings
+    Info: Peak virtual memory: 1070 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:13 2016
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:06
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg.
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.summary b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.summary
new file mode 100644
index 0000000..492bb14
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Tue Mar 01 16:05:13 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : ise_proj
+Top-level Entity Name : ise_proj
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 53 / 15,408 ( < 1 % )
+    Total combinational functions : 51 / 15,408 ( < 1 % )
+    Dedicated logic registers : 20 / 15,408 ( < 1 % )
+Total registers : 20
+Total pins : 51 / 347 ( 15 % )
+Total virtual pins : 0
+Total memory bits : 0 / 516,096 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.flow.rpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.flow.rpt
new file mode 100644
index 0000000..bc2e320
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.flow.rpt
@@ -0,0 +1,132 @@
+Flow report for ise_proj
+Tue Mar 01 16:05:18 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Flow Summary                                                                          ;
++------------------------------------+--------------------------------------------------+
+; Flow Status                        ; Successful - Tue Mar 01 16:05:15 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ise_proj                                         ;
+; Top-level Entity Name              ; ise_proj                                         ;
+; Family                             ; Cyclone III                                      ;
+; Device                             ; EP3C16F484C6                                     ;
+; Timing Models                      ; Final                                            ;
+; Total logic elements               ; 53 / 15,408 ( < 1 % )                            ;
+;     Total combinational functions  ; 51 / 15,408 ( < 1 % )                            ;
+;     Dedicated logic registers      ; 20 / 15,408 ( < 1 % )                            ;
+; Total registers                    ; 20                                               ;
+; Total pins                         ; 51 / 347 ( 15 % )                                ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0 / 516,096 ( 0 % )                              ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                                  ;
+; Total PLLs                         ; 0 / 4 ( 0 % )                                    ;
++------------------------------------+--------------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/01/2016 16:05:06 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; ise_proj            ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                       ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+; ALLOW_POWER_UP_DONT_CARE            ; Off                                   ; On            ; --          ; --         ;
+; COMPILER_SIGNATURE_ID               ; 260248564268246.145684830604272       ; --            ; --          ; --         ;
+; CYCLONEII_OPTIMIZATION_TECHNIQUE    ; Speed                                 ; Balanced      ; --          ; --         ;
+; ENABLE_ADVANCED_IO_TIMING           ; On                                    ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --          ; --         ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE         ; 1.2V                                  ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; DE0_TOP     ; Top        ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; DE0_VGA     ; Top        ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; --          ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; --          ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; DE0_TOP     ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; DE0_VGA     ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; --          ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                                   ; --            ; --          ; eda_palace ;
++-------------------------------------+---------------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:01     ; 1.0                     ; 465 MB              ; 00:00:01                           ;
+; Fitter                    ; 00:00:05     ; 1.8                     ; 1070 MB             ; 00:00:06                           ;
+; Assembler                 ; 00:00:01     ; 1.0                     ; 424 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:02     ; 1.0                     ; 480 MB              ; 00:00:01                           ;
+; Total                     ; 00:00:09     ; --                      ; --                  ; 00:00:09                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; eews104a-015     ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj
+quartus_fit --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj
+quartus_asm --read_settings_files=off --write_settings_files=off ise_proj -c ise_proj
+quartus_sta ise_proj -c ise_proj
+
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.jdi b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.jdi
new file mode 100644
index 0000000..ef75c5a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="c232bba5bf2fa8b9c342"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="ise_proj.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.rpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.rpt
new file mode 100644
index 0000000..1231e9f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.rpt
@@ -0,0 +1,538 @@
+Analysis & Synthesis report for ise_proj
+Tue Mar 01 16:05:07 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. General Register Statistics
+  9. Inverted Register Statistics
+ 10. Parameter Settings for User Entity Instance: dot_product:inst|mgc_in_wire:input_a_rsc_mgc_in_wire
+ 11. Parameter Settings for User Entity Instance: dot_product:inst|mgc_in_wire:input_b_rsc_mgc_in_wire
+ 12. Parameter Settings for User Entity Instance: dot_product:inst|mgc_out_stdreg:output_rsc_mgc_out_stdreg
+ 13. Parameter Settings for Inferred Entity Instance: dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0
+ 14. lpm_mult Parameter Settings by Entity Instance
+ 15. Elapsed Time Per Partition
+ 16. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                          ;
++------------------------------------+--------------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Tue Mar 01 16:05:07 2016            ;
+; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version ;
+; Revision Name                      ; ise_proj                                         ;
+; Top-level Entity Name              ; ise_proj                                         ;
+; Family                             ; Cyclone III                                      ;
+; Total logic elements               ; 59                                               ;
+;     Total combinational functions  ; 51                                               ;
+;     Dedicated logic registers      ; 20                                               ;
+; Total registers                    ; 20                                               ;
+; Total pins                         ; 51                                               ;
+; Total virtual pins                 ; 0                                                ;
+; Total memory bits                  ; 0                                                ;
+; Embedded Multiplier 9-bit elements ; 0                                                ;
+; Total PLLs                         ; 0                                                ;
++------------------------------------+--------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; ise_proj           ; ise_proj           ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Power-Up Don't Care                                                        ; Off                ; On                 ;
+; Optimization Technique                                                     ; Speed              ; Balanced           ;
+; Use smart compilation                                                      ; Off                ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 1           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                                         ;
++----------------------------------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path                         ; Used in Netlist ; File Type                                ; File Name with Absolute Path                                                                 ; Library ;
++----------------------------------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------------+---------+
+; ../../../../dot_product/dot_product/rtl_mgc_ioport (2).v ; yes             ; User Verilog HDL File                    ; C:/Catapult C/dot_product/dot_product/rtl_mgc_ioport (2).v                                   ;         ;
+; ../../../../dot_product/dot_product/rtl (2).v            ; yes             ; User Verilog HDL File                    ; C:/Catapult C/dot_product/dot_product/rtl (2).v                                              ;         ;
+; ise_proj.bdf                                             ; yes             ; Auto-Found Block Diagram/Schematic File  ; C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.bdf    ;         ;
+; lpm_mult.tdf                                             ; yes             ; Megafunction                             ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf                               ;         ;
+; aglobal130.inc                                           ; yes             ; Megafunction                             ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc                             ;         ;
+; lpm_add_sub.inc                                          ; yes             ; Megafunction                             ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc                            ;         ;
+; multcore.inc                                             ; yes             ; Megafunction                             ; c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.inc                               ;         ;
+; bypassff.inc                                             ; yes             ; Megafunction                             ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc                               ;         ;
+; altshift.inc                                             ; yes             ; Megafunction                             ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc                               ;         ;
+; db/mult_a7t.tdf                                          ; yes             ; Auto-Generated Megafunction              ; C:/Catapult C/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/db/mult_a7t.tdf ;         ;
++----------------------------------------------------------+-----------------+------------------------------------------+----------------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                   ;
++---------------------------------------------+-----------------+
+; Resource                                    ; Usage           ;
++---------------------------------------------+-----------------+
+; Estimated Total logic elements              ; 59              ;
+;                                             ;                 ;
+; Total combinational functions               ; 51              ;
+; Logic element usage by number of LUT inputs ;                 ;
+;     -- 4 input functions                    ; 13              ;
+;     -- 3 input functions                    ; 22              ;
+;     -- <=2 input functions                  ; 16              ;
+;                                             ;                 ;
+; Logic elements by mode                      ;                 ;
+;     -- normal mode                          ; 32              ;
+;     -- arithmetic mode                      ; 19              ;
+;                                             ;                 ;
+; Total registers                             ; 20              ;
+;     -- Dedicated logic registers            ; 20              ;
+;     -- I/O registers                        ; 0               ;
+;                                             ;                 ;
+; I/O pins                                    ; 51              ;
+; Embedded Multiplier 9-bit elements          ; 0               ;
+; Maximum fan-out node                        ; BUTTON[2]~input ;
+; Maximum fan-out                             ; 20              ;
+; Total fan-out                               ; 289             ;
+; Average fan-out                             ; 1.67            ;
++---------------------------------------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                  ;
++------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                     ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                      ; Library Name ;
++------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
+; |ise_proj                                      ; 51 (0)            ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 51   ; 0            ; |ise_proj                                                                                                ; work         ;
+;    |dot_product:inst|                          ; 51 (0)            ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ise_proj|dot_product:inst                                                                               ; work         ;
+;       |dot_product_core:dot_product_core_inst| ; 51 (21)           ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst                                        ; work         ;
+;          |lpm_mult:Mult0|                      ; 30 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0                         ; work         ;
+;             |mult_a7t:auto_generated|          ; 30 (30)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ise_proj|dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated ; work         ;
++------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 20    ;
+; Number of registers using Synchronous Clear  ; 0     ;
+; Number of registers using Synchronous Load   ; 0     ;
+; Number of registers using Asynchronous Clear ; 20    ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 20    ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++--------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                   ;
++----------------------------------------------------------------------+---------+
+; Inverted Register                                                    ; Fan out ;
++----------------------------------------------------------------------+---------+
+; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; 13      ;
+; Total number of inverted registers = 1                               ;         ;
++----------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: dot_product:inst|mgc_in_wire:input_a_rsc_mgc_in_wire ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                           ;
+; width          ; 8     ; Signed Integer                                                           ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: dot_product:inst|mgc_in_wire:input_b_rsc_mgc_in_wire ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                           ;
+; width          ; 8     ; Signed Integer                                                           ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: dot_product:inst|mgc_out_stdreg:output_rsc_mgc_out_stdreg ;
++----------------+-------+-------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                          ;
++----------------+-------+-------------------------------------------------------------------------------+
+; rscid          ; 3     ; Signed Integer                                                                ;
+; width          ; 8     ; Signed Integer                                                                ;
++----------------+-------+-------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0 ;
++------------------------------------------------+-------------+----------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                     ;
++------------------------------------------------+-------------+----------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                               ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                             ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                             ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                           ;
+; LPM_WIDTHA                                     ; 4           ; Untyped                                                  ;
+; LPM_WIDTHB                                     ; 4           ; Untyped                                                  ;
+; LPM_WIDTHP                                     ; 8           ; Untyped                                                  ;
+; LPM_WIDTHR                                     ; 8           ; Untyped                                                  ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                  ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                  ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                  ;
+; LATENCY                                        ; 0           ; Untyped                                                  ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                  ;
+; INPUT_B_IS_CONSTANT                            ; NO          ; Untyped                                                  ;
+; USE_EAB                                        ; OFF         ; Untyped                                                  ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                  ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                  ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                  ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                      ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                  ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                  ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                  ;
+; CBXI_PARAMETER                                 ; mult_a7t    ; Untyped                                                  ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                  ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                  ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                  ;
++------------------------------------------------+-------------+----------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                                 ;
++---------------------------------------+------------------------------------------------------------------------+
+; Name                                  ; Value                                                                  ;
++---------------------------------------+------------------------------------------------------------------------+
+; Number of entity instances            ; 1                                                                      ;
+; Entity Instance                       ; dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0 ;
+;     -- LPM_WIDTHA                     ; 4                                                                      ;
+;     -- LPM_WIDTHB                     ; 4                                                                      ;
+;     -- LPM_WIDTHP                     ; 8                                                                      ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                               ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                     ;
+;     -- INPUT_B_IS_CONSTANT            ; NO                                                                     ;
+;     -- USE_EAB                        ; OFF                                                                    ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                   ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                     ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                     ;
++---------------------------------------+------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:00     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 16:05:06 2016
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ise_proj -c ise_proj
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 7 design units, including 7 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v
+    Info (12023): Found entity 1: mgc_out_reg_pos
+    Info (12023): Found entity 2: mgc_out_reg_neg
+    Info (12023): Found entity 3: mgc_out_reg
+    Info (12023): Found entity 4: mgc_out_buf_wait
+    Info (12023): Found entity 5: mgc_out_fifo_wait
+    Info (12023): Found entity 6: mgc_out_fifo_wait_core
+    Info (12023): Found entity 7: mgc_pipe
+Info (12021): Found 20 design units, including 20 entities, in source file /catapult c/dot_product/dot_product/rtl_mgc_ioport (2).v
+    Info (12023): Found entity 1: mgc_in_wire
+    Info (12023): Found entity 2: mgc_in_wire_en
+    Info (12023): Found entity 3: mgc_in_wire_wait
+    Info (12023): Found entity 4: mgc_chan_in
+    Info (12023): Found entity 5: mgc_out_stdreg
+    Info (12023): Found entity 6: mgc_out_stdreg_en
+    Info (12023): Found entity 7: mgc_out_stdreg_wait
+    Info (12023): Found entity 8: mgc_out_prereg_en
+    Info (12023): Found entity 9: mgc_inout_stdreg_en
+    Info (12023): Found entity 10: hid_tribuf
+    Info (12023): Found entity 11: mgc_inout_stdreg_wait
+    Info (12023): Found entity 12: mgc_inout_buf_wait
+    Info (12023): Found entity 13: mgc_inout_fifo_wait
+    Info (12023): Found entity 14: mgc_io_sync
+    Info (12023): Found entity 15: mgc_bsync_rdy
+    Info (12023): Found entity 16: mgc_bsync_vld
+    Info (12023): Found entity 17: mgc_bsync_rv
+    Info (12023): Found entity 18: mgc_sync
+    Info (12023): Found entity 19: funccall_inout
+    Info (12023): Found entity 20: modulario_en_in
+Info (12021): Found 2 design units, including 2 entities, in source file /catapult c/dot_product/dot_product/rtl (2).v
+    Info (12023): Found entity 1: dot_product_core
+    Info (12023): Found entity 2: dot_product
+Warning (12125): Using design file ise_proj.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
+    Info (12023): Found entity 1: ise_proj
+Info (12127): Elaborating entity "ise_proj" for the top level hierarchy
+Warning (275002): No superset bus at connection
+Warning (275043): Pin "VGA_CLK" is missing source
+Warning (275043): Pin "VGA_SYNC" is missing source
+Warning (275043): Pin "VGA_BLANK" is missing source
+Warning (275043): Pin "VGA_VS" is missing source
+Warning (275043): Pin "VGA_HS" is missing source
+Warning (275043): Pin "HEX0_D[6..0]" is missing source
+Warning (275043): Pin "VGA_B[3..0]" is missing source
+Warning (275043): Pin "VGA_G[3..0]" is missing source
+Warning (275043): Pin "VGA_R[3..0]" is missing source
+Warning (275009): Pin "PS2_MSDAT" not connected
+Warning (275009): Pin "PS2_MSCLK" not connected
+Warning (275009): Pin "CLOCK_50" not connected
+Warning (275009): Pin "CLOCK_50_2" not connected
+Info (12128): Elaborating entity "dot_product" for hierarchy "dot_product:inst"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "dot_product:inst|mgc_in_wire:input_a_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "dot_product:inst|mgc_in_wire:input_b_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "dot_product:inst|mgc_out_stdreg:output_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "dot_product_core" for hierarchy "dot_product:inst|dot_product_core:dot_product_core_inst"
+Info (278001): Inferred 1 megafunctions from design logic
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "dot_product:inst|dot_product_core:dot_product_core_inst|Mult0"
+Info (12130): Elaborated megafunction instantiation "dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0"
+Info (12133): Instantiated megafunction "dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "4"
+    Info (12134): Parameter "LPM_WIDTHB" = "4"
+    Info (12134): Parameter "LPM_WIDTHP" = "8"
+    Info (12134): Parameter "LPM_WIDTHR" = "8"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/mult_a7t.tdf
+    Info (12023): Found entity 1: mult_a7t
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following LCELL buffer node(s):
+        Warning (14320): Synthesized away node "dot_product:inst|dot_product_core:dot_product_core_inst|lpm_mult:Mult0|mult_a7t:auto_generated|le5a[4]"
+Info (13014): Ignored 48 buffer(s)
+    Info (13016): Ignored 4 CARRY_SUM buffer(s)
+    Info (13019): Ignored 44 SOFT buffer(s)
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "VGA_CLK" is stuck at GND
+    Warning (13410): Pin "VGA_SYNC" is stuck at GND
+    Warning (13410): Pin "VGA_BLANK" is stuck at GND
+    Warning (13410): Pin "VGA_VS" is stuck at GND
+    Warning (13410): Pin "VGA_HS" is stuck at GND
+    Warning (13410): Pin "HEX0_D[6]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[5]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[4]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[3]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[2]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[1]" is stuck at GND
+    Warning (13410): Pin "HEX0_D[0]" is stuck at GND
+    Warning (13410): Pin "LEDG[9]" is stuck at GND
+    Warning (13410): Pin "LEDG[8]" is stuck at GND
+    Warning (13410): Pin "VGA_B[3]" is stuck at GND
+    Warning (13410): Pin "VGA_B[2]" is stuck at GND
+    Warning (13410): Pin "VGA_B[1]" is stuck at GND
+    Warning (13410): Pin "VGA_B[0]" is stuck at GND
+    Warning (13410): Pin "VGA_G[3]" is stuck at GND
+    Warning (13410): Pin "VGA_G[2]" is stuck at GND
+    Warning (13410): Pin "VGA_G[1]" is stuck at GND
+    Warning (13410): Pin "VGA_G[0]" is stuck at GND
+    Warning (13410): Pin "VGA_R[3]" is stuck at GND
+    Warning (13410): Pin "VGA_R[2]" is stuck at GND
+    Warning (13410): Pin "VGA_R[1]" is stuck at GND
+    Warning (13410): Pin "VGA_R[0]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Warning (20013): Ignored assignments for entity "DE0_TOP" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored
+Warning (20013): Ignored assignments for entity "DE0_VGA" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 6 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "BUTTON[1]"
+    Warning (15610): No output dependent on input pin "BUTTON[0]"
+    Warning (15610): No output dependent on input pin "PS2_MSDAT"
+    Warning (15610): No output dependent on input pin "PS2_MSCLK"
+    Warning (15610): No output dependent on input pin "CLOCK_50"
+    Warning (15610): No output dependent on input pin "CLOCK_50_2"
+Info (21057): Implemented 118 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 17 input pins
+    Info (21059): Implemented 34 output pins
+    Info (21061): Implemented 67 logic cells
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 102 warnings
+    Info: Peak virtual memory: 465 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:07 2016
+    Info: Elapsed time: 00:00:01
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.summary b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.summary
new file mode 100644
index 0000000..a8287c0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Tue Mar 01 16:05:07 2016
+Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+Revision Name : ise_proj
+Top-level Entity Name : ise_proj
+Family : Cyclone III
+Total logic elements : 59
+    Total combinational functions : 51
+    Dedicated logic registers : 20
+Total registers : 20
+Total pins : 51
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin
new file mode 100644
index 0000000..32e420b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		2.5V
+ --					Bank 3:		2.5V
+ --					Bank 4:		2.5V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		2.5V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+CHIP  "ise_proj"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10       :        :                   :         : 8         :                
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GND+                         : AA11      :        :                   :         : 3         :                
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA20      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GND+                         : AB11      :        :                   :         : 3         :                
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20      :        :                   :         : 4         :                
+VCCIO4                       : AB21      : power  :                   : 2.5V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10       :        :                   :         : 8         :                
+GND+                         : B11       :        :                   :         : 8         :                
+CLOCK_50_2                   : B12       : input  : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4        :        :                   :         : 8         :                
+GND                          : C5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6        :        :                   :         : 8         :                
+VGA_BLANK                    : C7        : output : 2.5 V             :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10       :        :                   :         : 8         :                
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13       :        :                   :         : 7         :                
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6        :        :                   :         : 8         :                
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 2.5V    : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10       :        :                   :         : 8         :                
+VCCIO8                       : D11       : power  :                   : 2.5V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15       :        :                   :         : 7         :                
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E6        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7        :        :                   :         : 8         :                
+VCCIO8                       : E8        : power  :                   : 2.5V    : 8         :                
+VGA_SYNC                     : E9        : output : 2.5 V             :         : 8         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10       :        :                   :         : 8         :                
+HEX0_D[0]                    : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+BUTTON[2]                    : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10       :        :                   :         : 8         :                
+HEX0_D[1]                    : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0_D[5]                    : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0_D[6]                    : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+BUTTON[1]                    : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0_D[4]                    : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+BUTTON[0]                    : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H9        :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10       :        :                   :         : 8         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0_D[2]                    : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0_D[3]                    : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 2.5V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R11       :        :                   :         : 3         :                
+VGA_CLK                      : R12       : output : 2.5 V             :         : 3         : N              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+PS2_MSCLK                    : R21       : input  : 3.3-V LVTTL       :         : 5         : Y              
+PS2_MSDAT                    : R22       : input  : 3.3-V LVTTL       :         : 5         : Y              
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T12       :        :                   :         : 4         :                
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T16       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 2.5V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U15       :        :                   :         : 4         :                
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V15       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 2.5V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 2.5V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 2.5V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W15       :        :                   :         : 4         :                
+VCCIO4                       : W16       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W17       :        :                   :         : 4         :                
+VCCIO4                       : W18       : power  :                   : 2.5V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 2.5V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17       :        :                   :         : 4         :                
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf
new file mode 100644
index 0000000..57c6904
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Full Version
+# Date created = 04:19:33  August 08, 2012
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.0"
+DATE = "04:19:33  August 08, 2012"
+
+# Revisions
+
+PROJECT_REVISION = "ise_proj"
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf
new file mode 100644
index 0000000..5c56cd8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qsf
@@ -0,0 +1,688 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.0 Build 178 05/31/2012 SJ Full Version
+# Date created = 04:19:33  August 08, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ise_proj_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY ise_proj
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "04:19:33  AUGUST 08, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_location_assignment PIN_F1 -to BUTTON[2]
+set_location_assignment PIN_G3 -to BUTTON[1]
+set_location_assignment PIN_H2 -to BUTTON[0]
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+set_location_assignment PIN_U7 -to GPIO0_D[31]
+set_location_assignment PIN_V5 -to GPIO0_D[30]
+set_location_assignment PIN_W6 -to GPIO0_D[29]
+set_location_assignment PIN_W7 -to GPIO0_D[28]
+set_location_assignment PIN_V8 -to GPIO0_D[27]
+set_location_assignment PIN_T8 -to GPIO0_D[26]
+set_location_assignment PIN_W10 -to GPIO0_D[25]
+set_location_assignment PIN_Y10 -to GPIO0_D[24]
+set_location_assignment PIN_V11 -to GPIO0_D[23]
+set_location_assignment PIN_R10 -to GPIO0_D[22]
+set_location_assignment PIN_V12 -to GPIO0_D[21]
+set_location_assignment PIN_U13 -to GPIO0_D[20]
+set_location_assignment PIN_W13 -to GPIO0_D[19]
+set_location_assignment PIN_Y13 -to GPIO0_D[18]
+set_location_assignment PIN_U14 -to GPIO0_D[17]
+set_location_assignment PIN_V14 -to GPIO0_D[16]
+set_location_assignment PIN_AA4 -to GPIO0_D[15]
+set_location_assignment PIN_AB4 -to GPIO0_D[14]
+set_location_assignment PIN_AA5 -to GPIO0_D[13]
+set_location_assignment PIN_AB5 -to GPIO0_D[12]
+set_location_assignment PIN_AA8 -to GPIO0_D[11]
+set_location_assignment PIN_AB8 -to GPIO0_D[10]
+set_location_assignment PIN_AA10 -to GPIO0_D[9]
+set_location_assignment PIN_AB10 -to GPIO0_D[8]
+set_location_assignment PIN_AA13 -to GPIO0_D[7]
+set_location_assignment PIN_AB13 -to GPIO0_D[6]
+set_location_assignment PIN_AB14 -to GPIO0_D[5]
+set_location_assignment PIN_AA14 -to GPIO0_D[4]
+set_location_assignment PIN_AB15 -to GPIO0_D[3]
+set_location_assignment PIN_AA15 -to GPIO0_D[2]
+set_location_assignment PIN_AA16 -to GPIO0_D[1]
+set_location_assignment PIN_AB16 -to GPIO0_D[0]
+set_location_assignment PIN_AB12 -to GPIO0_CLKIN[0]
+set_location_assignment PIN_AA12 -to GPIO0_CLKIN[1]
+set_location_assignment PIN_AB3 -to GPIO0_CLKOUT[0]
+set_location_assignment PIN_AA3 -to GPIO0_CLKOUT[1]
+set_location_assignment PIN_AA11 -to GPIO1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO1_CLKIN[0]
+set_location_assignment PIN_T16 -to GPIO1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO1_CLKOUT[0]
+set_location_assignment PIN_V7 -to GPIO1_D[31]
+set_location_assignment PIN_V6 -to GPIO1_D[30]
+set_location_assignment PIN_U8 -to GPIO1_D[29]
+set_location_assignment PIN_Y7 -to GPIO1_D[28]
+set_location_assignment PIN_T9 -to GPIO1_D[27]
+set_location_assignment PIN_U9 -to GPIO1_D[26]
+set_location_assignment PIN_T10 -to GPIO1_D[25]
+set_location_assignment PIN_U10 -to GPIO1_D[24]
+set_location_assignment PIN_R12 -to GPIO1_D[23]
+set_location_assignment PIN_R11 -to GPIO1_D[22]
+set_location_assignment PIN_T12 -to GPIO1_D[21]
+set_location_assignment PIN_U12 -to GPIO1_D[20]
+set_location_assignment PIN_R14 -to GPIO1_D[19]
+set_location_assignment PIN_T14 -to GPIO1_D[18]
+set_location_assignment PIN_AB7 -to GPIO1_D[17]
+set_location_assignment PIN_AA7 -to GPIO1_D[16]
+set_location_assignment PIN_AA9 -to GPIO1_D[15]
+set_location_assignment PIN_AB9 -to GPIO1_D[14]
+set_location_assignment PIN_V15 -to GPIO1_D[13]
+set_location_assignment PIN_W15 -to GPIO1_D[12]
+set_location_assignment PIN_T15 -to GPIO1_D[11]
+set_location_assignment PIN_U15 -to GPIO1_D[10]
+set_location_assignment PIN_W17 -to GPIO1_D[9]
+set_location_assignment PIN_Y17 -to GPIO1_D[8]
+set_location_assignment PIN_AB17 -to GPIO1_D[7]
+set_location_assignment PIN_AA17 -to GPIO1_D[6]
+set_location_assignment PIN_AA18 -to GPIO1_D[5]
+set_location_assignment PIN_AB18 -to GPIO1_D[4]
+set_location_assignment PIN_AB19 -to GPIO1_D[3]
+set_location_assignment PIN_AA19 -to GPIO1_D[2]
+set_location_assignment PIN_AB20 -to GPIO1_D[1]
+set_location_assignment PIN_AA20 -to GPIO1_D[0]
+set_location_assignment PIN_P22 -to PS2_KBCLK
+set_location_assignment PIN_P21 -to PS2_KBDAT
+set_location_assignment PIN_R21 -to PS2_MSCLK
+set_location_assignment PIN_R22 -to PS2_MSDAT
+set_location_assignment PIN_U22 -to UART_RXD
+set_location_assignment PIN_U21 -to UART_TXD
+set_location_assignment PIN_V22 -to UART_RTS
+set_location_assignment PIN_V21 -to UART_CTS
+set_location_assignment PIN_Y21 -to SD_CLK
+set_location_assignment PIN_Y22 -to SD_CMD
+set_location_assignment PIN_AA22 -to SD_DAT0
+set_location_assignment PIN_W21 -to SD_DAT3
+set_location_assignment PIN_W20 -to SD_WP_N
+set_location_assignment PIN_C20 -to LCD_DATA[7]
+set_location_assignment PIN_D20 -to LCD_DATA[6]
+set_location_assignment PIN_B21 -to LCD_DATA[5]
+set_location_assignment PIN_B22 -to LCD_DATA[4]
+set_location_assignment PIN_C21 -to LCD_DATA[3]
+set_location_assignment PIN_C22 -to LCD_DATA[2]
+set_location_assignment PIN_D21 -to LCD_DATA[1]
+set_location_assignment PIN_D22 -to LCD_DATA[0]
+set_location_assignment PIN_E22 -to LCD_RW
+set_location_assignment PIN_F22 -to LCD_RS
+set_location_assignment PIN_E21 -to LCD_EN
+set_location_assignment PIN_F21 -to LCD_BLON
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_D[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_D[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_MSCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region"
+set_location_assignment PIN_F1 -to KEY[2]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_U7 -to GPIO_0[31]
+set_location_assignment PIN_V5 -to GPIO_0[30]
+set_location_assignment PIN_W6 -to GPIO_0[29]
+set_location_assignment PIN_W7 -to GPIO_0[28]
+set_location_assignment PIN_V8 -to GPIO_0[27]
+set_location_assignment PIN_T8 -to GPIO_0[26]
+set_location_assignment PIN_W10 -to GPIO_0[25]
+set_location_assignment PIN_Y10 -to GPIO_0[24]
+set_location_assignment PIN_V11 -to GPIO_0[23]
+set_location_assignment PIN_R10 -to GPIO_0[22]
+set_location_assignment PIN_V12 -to GPIO_0[21]
+set_location_assignment PIN_U13 -to GPIO_0[20]
+set_location_assignment PIN_W13 -to GPIO_0[19]
+set_location_assignment PIN_Y13 -to GPIO_0[18]
+set_location_assignment PIN_U14 -to GPIO_0[17]
+set_location_assignment PIN_V14 -to GPIO_0[16]
+set_location_assignment PIN_AA4 -to GPIO_0[15]
+set_location_assignment PIN_AB4 -to GPIO_0[14]
+set_location_assignment PIN_AA5 -to GPIO_0[13]
+set_location_assignment PIN_AB5 -to GPIO_0[12]
+set_location_assignment PIN_AA8 -to GPIO_0[11]
+set_location_assignment PIN_AB8 -to GPIO_0[10]
+set_location_assignment PIN_AA10 -to GPIO_0[9]
+set_location_assignment PIN_AB10 -to GPIO_0[8]
+set_location_assignment PIN_AA13 -to GPIO_0[7]
+set_location_assignment PIN_AB13 -to GPIO_0[6]
+set_location_assignment PIN_AB14 -to GPIO_0[5]
+set_location_assignment PIN_AA14 -to GPIO_0[4]
+set_location_assignment PIN_AB15 -to GPIO_0[3]
+set_location_assignment PIN_AA15 -to GPIO_0[2]
+set_location_assignment PIN_AA16 -to GPIO_0[1]
+set_location_assignment PIN_AB16 -to GPIO_0[0]
+set_location_assignment PIN_AB12 -to GPIO_CLKIN_N0
+set_location_assignment PIN_AA12 -to GPIO_CLKIN_P0
+set_location_assignment PIN_AB3 -to GPIO_CLKOUT_N0
+set_location_assignment PIN_AA3 -to GPIO_CLKOUT_P0
+set_location_assignment PIN_AA11 -to GPIO_CLKIN_P1
+set_location_assignment PIN_AB11 -to GPIO_CLKIN_N1
+set_location_assignment PIN_T16 -to GPIO_CLKOUT_P1
+set_location_assignment PIN_R16 -to GPIO_CLKOUT_N1
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0[7]
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1[7]
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2[7]
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3[7]
+set_location_assignment PIN_B5 -to DRAM_BA[0]
+set_location_assignment PIN_A4 -to DRAM_BA[1]
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name VERILOG_FILE "../../../../dot_product/dot_product/rtl_mgc_ioport_v2001 (2).v"
+set_global_assignment -name VERILOG_FILE "../../../../dot_product/dot_product/rtl_mgc_ioport (2).v"
+set_global_assignment -name VERILOG_FILE "../../../../dot_product/dot_product/rtl (2).v"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qws b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qws
new file mode 100644
index 0000000..db5a1d6
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.qws
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof
new file mode 100644
index 0000000..ece1e6c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sof
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt
new file mode 100644
index 0000000..4726b7a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.rpt
@@ -0,0 +1,1893 @@
+TimeQuest Timing Analyzer report for ise_proj
+Tue Mar 01 16:05:18 2016
+Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. Clocks
+  5. Slow 1200mV 85C Model Fmax Summary
+  6. Timing Closure Recommendations
+  7. Slow 1200mV 85C Model Setup Summary
+  8. Slow 1200mV 85C Model Hold Summary
+  9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Setup: 'BUTTON[2]'
+ 13. Slow 1200mV 85C Model Hold: 'BUTTON[2]'
+ 14. Slow 1200mV 85C Model Minimum Pulse Width: 'BUTTON[2]'
+ 15. Setup Times
+ 16. Hold Times
+ 17. Clock to Output Times
+ 18. Minimum Clock to Output Times
+ 19. Slow 1200mV 85C Model Metastability Report
+ 20. Slow 1200mV 0C Model Fmax Summary
+ 21. Slow 1200mV 0C Model Setup Summary
+ 22. Slow 1200mV 0C Model Hold Summary
+ 23. Slow 1200mV 0C Model Recovery Summary
+ 24. Slow 1200mV 0C Model Removal Summary
+ 25. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 26. Slow 1200mV 0C Model Setup: 'BUTTON[2]'
+ 27. Slow 1200mV 0C Model Hold: 'BUTTON[2]'
+ 28. Slow 1200mV 0C Model Minimum Pulse Width: 'BUTTON[2]'
+ 29. Setup Times
+ 30. Hold Times
+ 31. Clock to Output Times
+ 32. Minimum Clock to Output Times
+ 33. Slow 1200mV 0C Model Metastability Report
+ 34. Fast 1200mV 0C Model Setup Summary
+ 35. Fast 1200mV 0C Model Hold Summary
+ 36. Fast 1200mV 0C Model Recovery Summary
+ 37. Fast 1200mV 0C Model Removal Summary
+ 38. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 39. Fast 1200mV 0C Model Setup: 'BUTTON[2]'
+ 40. Fast 1200mV 0C Model Hold: 'BUTTON[2]'
+ 41. Fast 1200mV 0C Model Minimum Pulse Width: 'BUTTON[2]'
+ 42. Setup Times
+ 43. Hold Times
+ 44. Clock to Output Times
+ 45. Minimum Clock to Output Times
+ 46. Fast 1200mV 0C Model Metastability Report
+ 47. Multicorner Timing Analysis Summary
+ 48. Setup Times
+ 49. Hold Times
+ 50. Clock to Output Times
+ 51. Minimum Clock to Output Times
+ 52. Board Trace Model Assignments
+ 53. Input Transition Times
+ 54. Slow Corner Signal Integrity Metrics
+ 55. Fast Corner Signal Integrity Metrics
+ 56. Setup Transfers
+ 57. Hold Transfers
+ 58. Report TCCS
+ 59. Report RSKM
+ 60. Unconstrained Paths
+ 61. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++-----------------------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                                       ;
++--------------------+--------------------------------------------------------------------+
+; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version ;
+; Revision Name      ; ise_proj                                                           ;
+; Device Family      ; Cyclone III                                                        ;
+; Device Name        ; EP3C16F484C6                                                       ;
+; Timing Models      ; Final                                                              ;
+; Delay Model        ; Combined                                                           ;
+; Rise/Fall Delays   ; Enabled                                                            ;
++--------------------+--------------------------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+; Clock Name ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets       ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+; BUTTON[2]  ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { BUTTON[2] } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                                        ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; 318.37 MHz ; 250.0 MHz       ; BUTTON[2]  ; limit due to minimum period restriction (max I/O toggle rate) ;
++------------+-----------------+------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++-------------------------------------+
+; Slow 1200mV 85C Model Setup Summary ;
++-----------+--------+----------------+
+; Clock     ; Slack  ; End Point TNS  ;
++-----------+--------+----------------+
+; BUTTON[2] ; -2.141 ; -24.967        ;
++-----------+--------+----------------+
+
+
++------------------------------------+
+; Slow 1200mV 85C Model Hold Summary ;
++-----------+-------+----------------+
+; Clock     ; Slack ; End Point TNS  ;
++-----------+-------+----------------+
+; BUTTON[2] ; 0.382 ; 0.000          ;
++-----------+-------+----------------+
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++-----------+--------+------------------------------+
+; Clock     ; Slack  ; End Point TNS                ;
++-----------+--------+------------------------------+
+; BUTTON[2] ; -3.000 ; -23.000                      ;
++-----------+--------+------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'BUTTON[2]'                                                                                                                                                                                                     ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                                            ; To Node                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -2.141 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 3.114      ;
+; -2.082 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 3.055      ;
+; -2.058 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 3.031      ;
+; -2.045 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 3.018      ;
+; -2.030 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 3.003      ;
+; -2.030 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 3.003      ;
+; -1.999 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.972      ;
+; -1.986 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.959      ;
+; -1.967 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.940      ;
+; -1.953 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.926      ;
+; -1.949 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.922      ;
+; -1.890 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.863      ;
+; -1.882 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.855      ;
+; -1.872 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.845      ;
+; -1.817 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.790      ;
+; -1.805 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.778      ;
+; -1.776 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.749      ;
+; -1.758 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.731      ;
+; -1.738 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.711      ;
+; -1.718 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.691      ;
+; -1.706 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.679      ;
+; -1.702 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.675      ;
+; -1.701 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.674      ;
+; -1.695 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.668      ;
+; -1.679 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.652      ;
+; -1.655 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.628      ;
+; -1.643 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.616      ;
+; -1.635 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.608      ;
+; -1.628 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.601      ;
+; -1.622 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.595      ;
+; -1.620 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.593      ;
+; -1.528 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.501      ;
+; -1.504 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.477      ;
+; -1.431 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.404      ;
+; -1.361 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.337      ;
+; -1.355 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.331      ;
+; -1.354 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.327      ;
+; -1.338 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.314      ;
+; -1.278 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.254      ;
+; -1.265 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.241      ;
+; -1.261 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.237      ;
+; -1.247 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.220      ;
+; -1.245 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.221      ;
+; -1.239 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.215      ;
+; -1.222 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.198      ;
+; -1.210 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.183      ;
+; -1.186 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.159      ;
+; -1.177 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.150      ;
+; -1.162 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.138      ;
+; -1.149 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.125      ;
+; -1.145 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.121      ;
+; -1.129 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.105      ;
+; -1.123 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.099      ;
+; -1.106 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.082      ;
+; -1.084 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.060      ;
+; -1.071 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.044      ;
+; -1.050 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 2.023      ;
+; -1.046 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.022      ;
+; -1.037 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.013      ;
+; -1.033 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.009      ;
+; -1.031 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.007      ;
+; -1.029 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 2.005      ;
+; -1.009 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.985      ;
+; -0.990 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.966      ;
+; -0.984 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 1.957      ;
+; -0.974 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 1.947      ;
+; -0.968 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.944      ;
+; -0.962 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.938      ;
+; -0.922 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.898      ;
+; -0.921 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.897      ;
+; -0.916 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.892      ;
+; -0.915 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.891      ;
+; -0.913 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.889      ;
+; -0.893 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.869      ;
+; -0.893 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.869      ;
+; -0.887 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.863      ;
+; -0.852 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.828      ;
+; -0.846 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.822      ;
+; -0.830 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.806      ;
+; -0.741 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.042     ; 1.714      ;
+; -0.614 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.590      ;
+; -0.609 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.585      ;
+; -0.457 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.159     ; 1.313      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.159     ; 1.311      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.047      ; 1.517      ;
+; -0.453 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.159     ; 1.309      ;
+; -0.424 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.400      ;
+; -0.418 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.394      ;
+; -0.402 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.378      ;
+; -0.401 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.377      ;
+; -0.394 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.370      ;
+; -0.131 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.039     ; 1.107      ;
+; 0.016  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.026      ; 1.025      ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'BUTTON[2]'                                                                                                                                                                                                     ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                                            ; To Node                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.382 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.038      ; 0.577      ;
+; 0.382 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.038      ; 0.577      ;
+; 0.385 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.038      ; 0.580      ;
+; 0.385 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.038      ; 0.580      ;
+; 0.578 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.040      ; 0.775      ;
+; 0.581 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.040      ; 0.778      ;
+; 0.581 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.040      ; 0.778      ;
+; 0.612 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.159      ; 0.928      ;
+; 0.786 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.024      ;
+; 0.947 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.185      ;
+; 0.949 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.187      ;
+; 0.952 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.190      ;
+; 0.986 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.224      ;
+; 0.986 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.224      ;
+; 1.023 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.261      ;
+; 1.025 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.263      ;
+; 1.031 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.269      ;
+; 1.032 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.270      ;
+; 1.034 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.272      ;
+; 1.067 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.305      ;
+; 1.070 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.308      ;
+; 1.085 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.026     ; 1.216      ;
+; 1.087 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.026     ; 1.218      ;
+; 1.091 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.026     ; 1.222      ;
+; 1.097 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.335      ;
+; 1.106 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.344      ;
+; 1.136 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.374      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.207 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.180      ; 1.544      ;
+; 1.223 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.461      ;
+; 1.224 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.462      ;
+; 1.231 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.469      ;
+; 1.238 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.476      ;
+; 1.251 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.489      ;
+; 1.260 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.498      ;
+; 1.277 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.515      ;
+; 1.304 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.542      ;
+; 1.308 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.546      ;
+; 1.335 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.573      ;
+; 1.343 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.581      ;
+; 1.350 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.588      ;
+; 1.369 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.607      ;
+; 1.372 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.610      ;
+; 1.384 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.622      ;
+; 1.386 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.624      ;
+; 1.416 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.654      ;
+; 1.422 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.621      ;
+; 1.455 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.693      ;
+; 1.479 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.717      ;
+; 1.481 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.719      ;
+; 1.483 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.682      ;
+; 1.496 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.734      ;
+; 1.498 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.736      ;
+; 1.511 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.710      ;
+; 1.557 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.756      ;
+; 1.560 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.759      ;
+; 1.585 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.784      ;
+; 1.591 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.829      ;
+; 1.593 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.831      ;
+; 1.608 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.846      ;
+; 1.610 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.848      ;
+; 1.638 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.837      ;
+; 1.703 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.941      ;
+; 1.720 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.081      ; 1.958      ;
+; 1.741 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.940      ;
+; 1.772 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.971      ;
+; 1.775 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.974      ;
+; 1.783 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 1.982      ;
+; 1.823 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.022      ;
+; 1.837 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.036      ;
+; 1.840 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.039      ;
+; 1.857 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.056      ;
+; 1.867 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.066      ;
+; 1.884 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.083      ;
+; 1.918 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.117      ;
+; 1.941 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.140      ;
+; 1.982 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.181      ;
+; 1.999 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.198      ;
+; 2.005 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.204      ;
+; 2.021 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.220      ;
+; 2.023 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.222      ;
+; 2.049 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.248      ;
+; 2.074 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.273      ;
+; 2.074 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.273      ;
+; 2.083 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.282      ;
+; 2.088 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.287      ;
+; 2.089 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.288      ;
+; 2.127 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.326      ;
+; 2.132 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.331      ;
+; 2.147 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.346      ;
+; 2.164 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.363      ;
+; 2.272 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.471      ;
+; 2.289 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.488      ;
+; 2.332 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.042      ; 2.531      ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'BUTTON[2]'                                                                                                                      ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                                                                 ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; BUTTON[2] ; Rise       ; BUTTON[2]                                                                              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; 0.097  ; 0.281        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; 0.102  ; 0.286        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; 0.106  ; 0.290        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; 0.106  ; 0.290        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; 0.106  ; 0.290        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; 0.245  ; 0.245        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; BUTTON[2]~input|o                                                                      ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6]|clk                          ;
+; 0.257  ; 0.257        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]|clk                          ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[0]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[1]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[2]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[3]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[4]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[5]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[6]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[7]|clk                                            ;
+; 0.262  ; 0.262        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|exit_MAC_lpi|clk                                            ;
+; 0.266  ; 0.266        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[0]|clk                                            ;
+; 0.266  ; 0.266        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[1]|clk                                            ;
+; 0.266  ; 0.266        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[2]|clk                                            ;
+; 0.494  ; 0.710        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; 0.494  ; 0.710        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; 0.494  ; 0.710        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; 0.496  ; 0.712        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; BUTTON[2]~input|i                                                                      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; BUTTON[2]~input|i                                                                      ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; 0.503  ; 0.719        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 0.732  ; 0.732        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[0]|clk                                            ;
+; 0.732  ; 0.732        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[1]|clk                                            ;
+; 0.732  ; 0.732        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[2]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[0]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[1]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[2]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[3]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[4]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[5]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[6]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[7]|clk                                            ;
+; 0.734  ; 0.734        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|exit_MAC_lpi|clk                                            ;
+; 0.741  ; 0.741        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]|clk                          ;
+; 0.741  ; 0.741        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]|clk                          ;
+; 0.741  ; 0.741        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]|clk                          ;
+; 0.741  ; 0.741        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]|clk                          ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; 7.383 ; 7.891 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; 6.704 ; 7.200 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; 7.383 ; 7.891 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; 6.674 ; 7.197 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; 6.824 ; 7.333 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; 5.408 ; 5.661 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; 6.484 ; 7.044 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; 6.452 ; 6.945 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; 6.754 ; 7.259 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; 2.293 ; 2.791 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; -1.757 ; -2.238 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; -2.691 ; -3.206 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; -2.439 ; -2.947 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; -2.301 ; -2.782 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; -2.659 ; -3.161 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; -2.479 ; -2.979 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; -2.662 ; -3.203 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; -3.144 ; -3.587 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; -3.480 ; -3.969 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; -1.757 ; -2.238 ; Rise       ; BUTTON[2]       ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 7.240 ; 7.014 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 5.373 ; 5.305 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 5.355 ; 5.282 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 7.240 ; 7.014 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 5.384 ; 5.320 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 5.247 ; 5.143 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 5.240 ; 5.135 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 5.552 ; 5.449 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 5.406 ; 5.338 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 5.135 ; 5.030 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 5.262 ; 5.192 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 5.245 ; 5.170 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 7.130 ; 6.901 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 5.274 ; 5.207 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 5.142 ; 5.037 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 5.135 ; 5.030 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 5.436 ; 5.332 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 5.296 ; 5.226 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+----------------------------------------------
+; Slow 1200mV 85C Model Metastability Report ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                                         ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; Fmax       ; Restricted Fmax ; Clock Name ; Note                                                          ;
++------------+-----------------+------------+---------------------------------------------------------------+
+; 356.51 MHz ; 250.0 MHz       ; BUTTON[2]  ; limit due to minimum period restriction (max I/O toggle rate) ;
++------------+-----------------+------------+---------------------------------------------------------------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------+
+; Slow 1200mV 0C Model Setup Summary ;
++-----------+--------+---------------+
+; Clock     ; Slack  ; End Point TNS ;
++-----------+--------+---------------+
+; BUTTON[2] ; -1.805 ; -20.320       ;
++-----------+--------+---------------+
+
+
++-----------------------------------+
+; Slow 1200mV 0C Model Hold Summary ;
++-----------+-------+---------------+
+; Clock     ; Slack ; End Point TNS ;
++-----------+-------+---------------+
+; BUTTON[2] ; 0.333 ; 0.000         ;
++-----------+-------+---------------+
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++-----------+--------+-----------------------------+
+; Clock     ; Slack  ; End Point TNS               ;
++-----------+--------+-----------------------------+
+; BUTTON[2] ; -3.000 ; -23.000                     ;
++-----------+--------+-----------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'BUTTON[2]'                                                                                                                                                                                                      ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                                            ; To Node                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -1.805 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.783      ;
+; -1.755 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.733      ;
+; -1.735 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.713      ;
+; -1.730 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.708      ;
+; -1.718 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.696      ;
+; -1.685 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.663      ;
+; -1.678 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.656      ;
+; -1.668 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.646      ;
+; -1.660 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.638      ;
+; -1.652 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.630      ;
+; -1.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.602      ;
+; -1.608 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.586      ;
+; -1.582 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.560      ;
+; -1.560 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.538      ;
+; -1.538 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.516      ;
+; -1.514 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.492      ;
+; -1.497 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.475      ;
+; -1.464 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.442      ;
+; -1.449 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.427      ;
+; -1.437 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.415      ;
+; -1.431 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.409      ;
+; -1.419 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.397      ;
+; -1.416 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.394      ;
+; -1.399 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.377      ;
+; -1.387 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.365      ;
+; -1.377 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.355      ;
+; -1.375 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.353      ;
+; -1.361 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.339      ;
+; -1.359 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.337      ;
+; -1.344 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.322      ;
+; -1.333 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.311      ;
+; -1.259 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.237      ;
+; -1.235 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.213      ;
+; -1.201 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.179      ;
+; -1.131 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.109      ;
+; -1.091 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 2.072      ;
+; -1.087 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 2.068      ;
+; -1.069 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 2.050      ;
+; -1.027 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 2.005      ;
+; -1.021 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 2.002      ;
+; -1.017 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.998      ;
+; -1.000 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.981      ;
+; -0.991 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.972      ;
+; -0.987 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.968      ;
+; -0.980 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.958      ;
+; -0.973 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.951      ;
+; -0.969 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.950      ;
+; -0.958 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.936      ;
+; -0.921 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.902      ;
+; -0.917 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.898      ;
+; -0.900 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.881      ;
+; -0.891 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.872      ;
+; -0.887 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.868      ;
+; -0.869 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.850      ;
+; -0.858 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.839      ;
+; -0.840 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.818      ;
+; -0.837 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.815      ;
+; -0.821 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.802      ;
+; -0.817 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.798      ;
+; -0.800 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.781      ;
+; -0.798 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.779      ;
+; -0.796 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.777      ;
+; -0.791 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.772      ;
+; -0.778 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.759      ;
+; -0.763 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.741      ;
+; -0.758 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.739      ;
+; -0.749 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.727      ;
+; -0.740 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.721      ;
+; -0.721 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.702      ;
+; -0.698 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.679      ;
+; -0.698 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.679      ;
+; -0.698 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.679      ;
+; -0.696 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.677      ;
+; -0.680 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.661      ;
+; -0.680 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.661      ;
+; -0.678 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.659      ;
+; -0.658 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.639      ;
+; -0.640 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.621      ;
+; -0.639 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.620      ;
+; -0.573 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.037     ; 1.551      ;
+; -0.430 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.411      ;
+; -0.429 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.410      ;
+; -0.315 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.145     ; 1.185      ;
+; -0.311 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.145     ; 1.181      ;
+; -0.311 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.145     ; 1.181      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.307 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.043      ; 1.365      ;
+; -0.259 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.240      ;
+; -0.255 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.236      ;
+; -0.248 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.229      ;
+; -0.244 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.225      ;
+; -0.227 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 1.208      ;
+; -0.012 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.034     ; 0.993      ;
+; 0.126  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.023      ; 0.912      ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'BUTTON[2]'                                                                                                                                                                                                      ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                                            ; To Node                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.333 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.034      ; 0.511      ;
+; 0.333 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.034      ; 0.511      ;
+; 0.341 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.034      ; 0.519      ;
+; 0.341 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.034      ; 0.519      ;
+; 0.518 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 0.699      ;
+; 0.520 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 0.701      ;
+; 0.520 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 0.701      ;
+; 0.554 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.145      ; 0.843      ;
+; 0.687 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 0.906      ;
+; 0.853 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.072      ;
+; 0.853 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.072      ;
+; 0.857 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.076      ;
+; 0.874 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.093      ;
+; 0.879 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.098      ;
+; 0.932 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.151      ;
+; 0.933 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.152      ;
+; 0.937 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.156      ;
+; 0.941 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.160      ;
+; 0.942 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.161      ;
+; 0.974 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.193      ;
+; 0.976 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.195      ;
+; 0.984 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.023     ; 1.105      ;
+; 0.989 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.023     ; 1.110      ;
+; 0.999 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.218      ;
+; 1.001 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.023     ; 1.122      ;
+; 1.008 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.227      ;
+; 1.029 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.248      ;
+; 1.084 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.303      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.090 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.166      ; 1.400      ;
+; 1.100 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.319      ;
+; 1.100 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.319      ;
+; 1.104 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.323      ;
+; 1.110 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.329      ;
+; 1.113 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.332      ;
+; 1.148 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.367      ;
+; 1.151 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.370      ;
+; 1.151 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.370      ;
+; 1.180 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.399      ;
+; 1.196 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.415      ;
+; 1.206 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.425      ;
+; 1.209 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.428      ;
+; 1.242 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.461      ;
+; 1.244 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.463      ;
+; 1.247 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.466      ;
+; 1.254 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.473      ;
+; 1.272 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.453      ;
+; 1.276 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.495      ;
+; 1.331 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.550      ;
+; 1.338 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.557      ;
+; 1.343 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.562      ;
+; 1.350 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.569      ;
+; 1.357 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.538      ;
+; 1.384 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.565      ;
+; 1.419 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.600      ;
+; 1.424 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.605      ;
+; 1.427 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.646      ;
+; 1.434 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.653      ;
+; 1.439 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.658      ;
+; 1.446 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.665      ;
+; 1.451 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.632      ;
+; 1.501 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.682      ;
+; 1.523 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.742      ;
+; 1.535 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.075      ; 1.754      ;
+; 1.575 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.756      ;
+; 1.586 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.767      ;
+; 1.586 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.767      ;
+; 1.614 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.795      ;
+; 1.638 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.819      ;
+; 1.656 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.837      ;
+; 1.667 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.848      ;
+; 1.684 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.865      ;
+; 1.691 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.872      ;
+; 1.706 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.887      ;
+; 1.735 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.916      ;
+; 1.753 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.934      ;
+; 1.790 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.971      ;
+; 1.810 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.991      ;
+; 1.817 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 1.998      ;
+; 1.822 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.003      ;
+; 1.828 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.009      ;
+; 1.834 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.015      ;
+; 1.860 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.041      ;
+; 1.861 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.042      ;
+; 1.877 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.058      ;
+; 1.881 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.062      ;
+; 1.890 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.071      ;
+; 1.899 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.080      ;
+; 1.926 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.107      ;
+; 1.931 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.112      ;
+; 1.939 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.120      ;
+; 2.046 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.227      ;
+; 2.058 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.239      ;
+; 2.108 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.037      ; 2.289      ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'BUTTON[2]'                                                                                                                       ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                                                                 ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; BUTTON[2] ; Rise       ; BUTTON[2]                                                                              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; 0.135  ; 0.319        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; 0.138  ; 0.322        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; 0.140  ; 0.324        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; 0.140  ; 0.324        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; 0.140  ; 0.324        ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; 0.245  ; 0.245        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; BUTTON[2]~input|o                                                                      ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6]|clk                          ;
+; 0.295  ; 0.295        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]|clk                          ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[0]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[1]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[2]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[3]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[4]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[5]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[6]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[7]|clk                                            ;
+; 0.298  ; 0.298        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|exit_MAC_lpi|clk                                            ;
+; 0.300  ; 0.300        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[0]|clk                                            ;
+; 0.300  ; 0.300        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[1]|clk                                            ;
+; 0.300  ; 0.300        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[2]|clk                                            ;
+; 0.457  ; 0.673        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; 0.457  ; 0.673        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; 0.457  ; 0.673        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; 0.459  ; 0.675        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; 0.462  ; 0.678        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; BUTTON[2]~input|i                                                                      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; BUTTON[2]~input|i                                                                      ;
+; 0.697  ; 0.697        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[0]|clk                                            ;
+; 0.697  ; 0.697        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[1]|clk                                            ;
+; 0.697  ; 0.697        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[2]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[0]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[1]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[2]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[3]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[4]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[5]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[6]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[7]|clk                                            ;
+; 0.699  ; 0.699        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|exit_MAC_lpi|clk                                            ;
+; 0.702  ; 0.702        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]|clk                          ;
+; 0.702  ; 0.702        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]|clk                          ;
+; 0.702  ; 0.702        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]|clk                          ;
+; 0.702  ; 0.702        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]|clk                          ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; 6.470 ; 6.920 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; 5.870 ; 6.283 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; 6.470 ; 6.920 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; 5.845 ; 6.294 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; 5.977 ; 6.420 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; 4.729 ; 4.945 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; 5.676 ; 6.149 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; 5.637 ; 6.064 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; 5.908 ; 6.343 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; 1.928 ; 2.378 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; -1.446 ; -1.868 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; -2.289 ; -2.712 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; -2.063 ; -2.482 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; -1.939 ; -2.374 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; -2.270 ; -2.717 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; -2.114 ; -2.553 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; -2.269 ; -2.738 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; -2.696 ; -3.104 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; -2.985 ; -3.400 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; -1.446 ; -1.868 ; Rise       ; BUTTON[2]       ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 7.041 ; 6.783 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 5.174 ; 5.078 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 5.158 ; 5.052 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 7.041 ; 6.783 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 5.184 ; 5.091 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 5.073 ; 4.938 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 5.066 ; 4.931 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 5.354 ; 5.205 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 5.204 ; 5.110 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 4.972 ; 4.837 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 5.075 ; 4.977 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 5.059 ; 4.952 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 6.942 ; 6.683 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 5.085 ; 4.991 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 4.978 ; 4.844 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 4.972 ; 4.837 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 5.249 ; 5.100 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 5.105 ; 5.010 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Slow 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++------------------------------------+
+; Fast 1200mV 0C Model Setup Summary ;
++-----------+--------+---------------+
+; Clock     ; Slack  ; End Point TNS ;
++-----------+--------+---------------+
+; BUTTON[2] ; -0.738 ; -5.942        ;
++-----------+--------+---------------+
+
+
++-----------------------------------+
+; Fast 1200mV 0C Model Hold Summary ;
++-----------+-------+---------------+
+; Clock     ; Slack ; End Point TNS ;
++-----------+-------+---------------+
+; BUTTON[2] ; 0.201 ; 0.000         ;
++-----------+-------+---------------+
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++-----------+--------+-----------------------------+
+; Clock     ; Slack  ; End Point TNS               ;
++-----------+--------+-----------------------------+
+; BUTTON[2] ; -3.000 ; -30.776                     ;
++-----------+--------+-----------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'BUTTON[2]'                                                                                                                                                                                                      ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                                            ; To Node                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; -0.738 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.721      ;
+; -0.701 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.684      ;
+; -0.689 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.672      ;
+; -0.689 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.672      ;
+; -0.686 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.669      ;
+; -0.652 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.635      ;
+; -0.652 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.635      ;
+; -0.651 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.634      ;
+; -0.637 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.620      ;
+; -0.637 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.620      ;
+; -0.603 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.586      ;
+; -0.602 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.585      ;
+; -0.602 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.585      ;
+; -0.558 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.541      ;
+; -0.554 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.537      ;
+; -0.554 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.537      ;
+; -0.521 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.504      ;
+; -0.512 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.495      ;
+; -0.506 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.489      ;
+; -0.498 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.481      ;
+; -0.497 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.480      ;
+; -0.493 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.476      ;
+; -0.475 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.458      ;
+; -0.471 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.454      ;
+; -0.463 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.446      ;
+; -0.461 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.444      ;
+; -0.449 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.432      ;
+; -0.448 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.431      ;
+; -0.448 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.431      ;
+; -0.415 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.398      ;
+; -0.414 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.397      ;
+; -0.406 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.389      ;
+; -0.345 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.328      ;
+; -0.322 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.305      ;
+; -0.318 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.301      ;
+; -0.314 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.297      ;
+; -0.274 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.257      ;
+; -0.273 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.256      ;
+; -0.273 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.256      ;
+; -0.269 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.252      ;
+; -0.269 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.252      ;
+; -0.254 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.237      ;
+; -0.250 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.233      ;
+; -0.246 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.229      ;
+; -0.213 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.196      ;
+; -0.205 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.188      ;
+; -0.205 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.188      ;
+; -0.203 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.186      ;
+; -0.201 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.184      ;
+; -0.201 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.184      ;
+; -0.188 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.171      ;
+; -0.186 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.169      ;
+; -0.182 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.165      ;
+; -0.153 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.136      ;
+; -0.142 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.125      ;
+; -0.138 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.121      ;
+; -0.137 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.120      ;
+; -0.137 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.120      ;
+; -0.134 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.117      ;
+; -0.133 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.116      ;
+; -0.133 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.116      ;
+; -0.123 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.106      ;
+; -0.104 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.087      ;
+; -0.093 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.076      ;
+; -0.092 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.075      ;
+; -0.085 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.068      ;
+; -0.077 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.060      ;
+; -0.074 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.057      ;
+; -0.073 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.056      ;
+; -0.070 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.053      ;
+; -0.069 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.052      ;
+; -0.066 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.049      ;
+; -0.041 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.024      ;
+; -0.029 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.012      ;
+; -0.024 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.007      ;
+; -0.018 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.001      ;
+; -0.017 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 1.000      ;
+; -0.016 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.999      ;
+; 0.002  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.981      ;
+; 0.040  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.943      ;
+; 0.103  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.880      ;
+; 0.103  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.880      ;
+; 0.146  ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.104     ; 0.757      ;
+; 0.151  ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.104     ; 0.752      ;
+; 0.154  ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.104     ; 0.749      ;
+; 0.205  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.778      ;
+; 0.207  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.776      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.771      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.212  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; 0.040      ; 0.835      ;
+; 0.214  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.769      ;
+; 0.222  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.761      ;
+; 0.369  ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.024     ; 0.614      ;
+; 0.466  ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 1.000        ; -0.023     ; 0.518      ;
++--------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'BUTTON[2]'                                                                                                                                                                                                      ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                                            ; To Node                                                                                ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.201 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.022      ; 0.307      ;
+; 0.201 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.022      ; 0.307      ;
+; 0.208 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.022      ; 0.314      ;
+; 0.208 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.022      ; 0.314      ;
+; 0.303 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.104      ; 0.491      ;
+; 0.311 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.023      ; 0.418      ;
+; 0.312 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.023      ; 0.419      ;
+; 0.312 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.023      ; 0.419      ;
+; 0.409 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.537      ;
+; 0.500 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.628      ;
+; 0.502 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.630      ;
+; 0.503 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.631      ;
+; 0.518 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.646      ;
+; 0.519 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.647      ;
+; 0.544 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.672      ;
+; 0.545 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.673      ;
+; 0.548 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.676      ;
+; 0.550 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.678      ;
+; 0.551 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.679      ;
+; 0.567 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.695      ;
+; 0.569 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.697      ;
+; 0.579 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.707      ;
+; 0.583 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.711      ;
+; 0.587 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.715      ;
+; 0.592 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.030     ; 0.646      ;
+; 0.596 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.030     ; 0.650      ;
+; 0.597 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; -0.030     ; 0.651      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.624 ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.114      ; 0.822      ;
+; 0.650 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.778      ;
+; 0.651 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.779      ;
+; 0.659 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.787      ;
+; 0.662 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.790      ;
+; 0.677 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.805      ;
+; 0.678 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.806      ;
+; 0.680 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.808      ;
+; 0.713 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.841      ;
+; 0.714 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.842      ;
+; 0.716 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.844      ;
+; 0.725 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.853      ;
+; 0.727 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.855      ;
+; 0.728 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.856      ;
+; 0.732 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.840      ;
+; 0.736 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.864      ;
+; 0.739 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.867      ;
+; 0.743 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.871      ;
+; 0.779 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.907      ;
+; 0.781 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.889      ;
+; 0.790 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.918      ;
+; 0.791 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.919      ;
+; 0.793 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.901      ;
+; 0.793 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.921      ;
+; 0.802 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.930      ;
+; 0.805 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.933      ;
+; 0.814 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.922      ;
+; 0.815 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.923      ;
+; 0.828 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.936      ;
+; 0.856 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.984      ;
+; 0.858 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 0.966      ;
+; 0.859 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.987      ;
+; 0.868 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.996      ;
+; 0.871 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 0.999      ;
+; 0.910 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.018      ;
+; 0.912 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.020      ;
+; 0.922 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 1.050      ;
+; 0.926 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.034      ;
+; 0.933 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.041      ;
+; 0.934 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.044      ; 1.062      ;
+; 0.951 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.059      ;
+; 0.960 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.068      ;
+; 0.972 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.080      ;
+; 0.974 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.082      ;
+; 0.983 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.091      ;
+; 1.000 ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.108      ;
+; 1.001 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.109      ;
+; 1.037 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.145      ;
+; 1.041 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.149      ;
+; 1.053 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.161      ;
+; 1.065 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.173      ;
+; 1.066 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.174      ;
+; 1.069 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.177      ;
+; 1.083 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.191      ;
+; 1.094 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.202      ;
+; 1.095 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.203      ;
+; 1.100 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.208      ;
+; 1.102 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.210      ;
+; 1.114 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.222      ;
+; 1.130 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.238      ;
+; 1.136 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.244      ;
+; 1.142 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.250      ;
+; 1.148 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.256      ;
+; 1.200 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.308      ;
+; 1.212 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.320      ;
+; 1.226 ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1] ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ; BUTTON[2]    ; BUTTON[2]   ; 0.000        ; 0.024      ; 1.334      ;
++-------+----------------------------------------------------------------------+----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'BUTTON[2]'                                                                                                                       ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+; Slack  ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                                                                 ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+; -3.000 ; 1.000        ; 4.000          ; Port Rate        ; BUTTON[2] ; Rise       ; BUTTON[2]                                                                              ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; -1.000 ; 1.000        ; 2.000          ; Min Period       ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; -0.289 ; -0.105       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; -0.279 ; -0.095       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; -0.277 ; -0.093       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; -0.277 ; -0.093       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; -0.277 ; -0.093       ; 0.184          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6]|clk                          ;
+; -0.109 ; -0.109       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7]|clk                          ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[0]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[1]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[2]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[3]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[4]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[5]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[6]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[7]|clk                                            ;
+; -0.100 ; -0.100       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|exit_MAC_lpi|clk                                            ;
+; -0.097 ; -0.097       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[0]|clk                                            ;
+; -0.097 ; -0.097       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[1]|clk                                            ;
+; -0.097 ; -0.097       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[2]|clk                                            ;
+; -0.059 ; -0.059       ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; BUTTON[2]~input|o                                                                      ;
+; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; BUTTON[2]~input|i                                                                      ;
+; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; BUTTON[2] ; Rise       ; BUTTON[2]~input|i                                                                      ;
+; 0.874  ; 1.090        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[0]                   ;
+; 0.874  ; 1.090        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[1]                   ;
+; 0.874  ; 1.090        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|i_1_sva_1[2]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[0]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[1]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[2]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[3]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[4]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[5]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[6]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|acc_sva_1[7]                   ;
+; 0.878  ; 1.094        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|exit_MAC_lpi                   ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[3] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[4] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[5] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[6] ;
+; 0.887  ; 1.103        ; 0.216          ; High Pulse Width ; BUTTON[2] ; Rise       ; dot_product:inst|dot_product_core:dot_product_core_inst|output_rsc_mgc_out_stdreg_d[7] ;
+; 1.059  ; 1.059        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; BUTTON[2]~input|o                                                                      ;
+; 1.096  ; 1.096        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[0]|clk                                            ;
+; 1.096  ; 1.096        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[1]|clk                                            ;
+; 1.096  ; 1.096        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|i_1_sva_1[2]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[0]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[1]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[2]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[3]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[4]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[5]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[6]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|acc_sva_1[7]|clk                                            ;
+; 1.099  ; 1.099        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|exit_MAC_lpi|clk                                            ;
+; 1.109  ; 1.109        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[0]|clk                          ;
+; 1.109  ; 1.109        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[1]|clk                          ;
+; 1.109  ; 1.109        ; 0.000          ; High Pulse Width ; BUTTON[2] ; Rise       ; inst|dot_product_core_inst|output_rsc_mgc_out_stdreg_d[2]|clk                          ;
++--------+--------------+----------------+------------------+-----------+------------+----------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; 4.122 ; 4.893 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; 3.743 ; 4.504 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; 4.122 ; 4.893 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; 3.725 ; 4.461 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; 3.792 ; 4.558 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; 3.048 ; 3.688 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; 3.644 ; 4.398 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; 3.620 ; 4.339 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; 3.789 ; 4.549 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; 1.343 ; 2.081 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; -1.061 ; -1.781 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; -1.523 ; -2.286 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; -1.397 ; -2.165 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; -1.312 ; -2.023 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; -1.522 ; -2.270 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; -1.419 ; -2.164 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; -1.533 ; -2.286 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; -1.773 ; -2.460 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; -1.939 ; -2.702 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; -1.061 ; -1.781 ; Rise       ; BUTTON[2]       ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 4.612 ; 4.409 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 3.158 ; 3.141 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 3.145 ; 3.122 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 4.612 ; 4.409 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 3.170 ; 3.153 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 3.070 ; 3.040 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 3.065 ; 3.034 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 3.243 ; 3.239 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 3.186 ; 3.172 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 3.006 ; 2.974 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 3.095 ; 3.075 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 3.083 ; 3.058 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 4.550 ; 4.344 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 3.107 ; 3.088 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 3.011 ; 2.979 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 3.006 ; 2.974 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 3.178 ; 3.171 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 3.124 ; 3.107 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
+---------------------------------------------
+; Fast 1200mV 0C Model Metastability Report ;
+---------------------------------------------
+No synchronizer chains to report.
+
+
++-------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                           ;
++------------------+---------+-------+----------+---------+---------------------+
+; Clock            ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack ; -2.141  ; 0.201 ; N/A      ; N/A     ; -3.000              ;
+;  BUTTON[2]       ; -2.141  ; 0.201 ; N/A      ; N/A     ; -3.000              ;
+; Design-wide TNS  ; -24.967 ; 0.0   ; 0.0      ; 0.0     ; -30.776             ;
+;  BUTTON[2]       ; -24.967 ; 0.000 ; N/A      ; N/A     ; -30.776             ;
++------------------+---------+-------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------+
+; Setup Times                                                           ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; 7.383 ; 7.891 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; 6.704 ; 7.200 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; 7.383 ; 7.891 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; 6.674 ; 7.197 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; 6.824 ; 7.333 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; 5.408 ; 5.661 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; 6.484 ; 7.044 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; 6.452 ; 6.945 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; 6.754 ; 7.259 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; 2.293 ; 2.791 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-------------------------------------------------------------------------+
+; Hold Times                                                              ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; SW[*]     ; BUTTON[2]  ; -1.061 ; -1.781 ; Rise       ; BUTTON[2]       ;
+;  SW[0]    ; BUTTON[2]  ; -1.523 ; -2.286 ; Rise       ; BUTTON[2]       ;
+;  SW[1]    ; BUTTON[2]  ; -1.397 ; -2.165 ; Rise       ; BUTTON[2]       ;
+;  SW[2]    ; BUTTON[2]  ; -1.312 ; -2.023 ; Rise       ; BUTTON[2]       ;
+;  SW[3]    ; BUTTON[2]  ; -1.522 ; -2.270 ; Rise       ; BUTTON[2]       ;
+;  SW[4]    ; BUTTON[2]  ; -1.419 ; -2.164 ; Rise       ; BUTTON[2]       ;
+;  SW[5]    ; BUTTON[2]  ; -1.533 ; -2.286 ; Rise       ; BUTTON[2]       ;
+;  SW[6]    ; BUTTON[2]  ; -1.773 ; -2.460 ; Rise       ; BUTTON[2]       ;
+;  SW[7]    ; BUTTON[2]  ; -1.939 ; -2.702 ; Rise       ; BUTTON[2]       ;
+;  SW[8]    ; BUTTON[2]  ; -1.061 ; -1.781 ; Rise       ; BUTTON[2]       ;
++-----------+------------+--------+--------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Clock to Output Times                                                 ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 7.240 ; 7.014 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 5.373 ; 5.305 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 5.355 ; 5.282 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 7.240 ; 7.014 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 5.384 ; 5.320 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 5.247 ; 5.143 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 5.240 ; 5.135 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 5.552 ; 5.449 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 5.406 ; 5.338 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++-----------------------------------------------------------------------+
+; Minimum Clock to Output Times                                         ;
++-----------+------------+-------+-------+------------+-----------------+
+; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference ;
++-----------+------------+-------+-------+------------+-----------------+
+; LEDG[*]   ; BUTTON[2]  ; 3.006 ; 2.974 ; Rise       ; BUTTON[2]       ;
+;  LEDG[0]  ; BUTTON[2]  ; 3.095 ; 3.075 ; Rise       ; BUTTON[2]       ;
+;  LEDG[1]  ; BUTTON[2]  ; 3.083 ; 3.058 ; Rise       ; BUTTON[2]       ;
+;  LEDG[2]  ; BUTTON[2]  ; 4.550 ; 4.344 ; Rise       ; BUTTON[2]       ;
+;  LEDG[3]  ; BUTTON[2]  ; 3.107 ; 3.088 ; Rise       ; BUTTON[2]       ;
+;  LEDG[4]  ; BUTTON[2]  ; 3.011 ; 2.979 ; Rise       ; BUTTON[2]       ;
+;  LEDG[5]  ; BUTTON[2]  ; 3.006 ; 2.974 ; Rise       ; BUTTON[2]       ;
+;  LEDG[6]  ; BUTTON[2]  ; 3.178 ; 3.171 ; Rise       ; BUTTON[2]       ;
+;  LEDG[7]  ; BUTTON[2]  ; 3.124 ; 3.107 ; Rise       ; BUTTON[2]       ;
++-----------+------------+-------+-------+------------+-----------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; VGA_CLK       ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_SYNC      ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_BLANK     ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0_D[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; BUTTON[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; BUTTON[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_MSDAT               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_MSCLK               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50_2              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; BUTTON[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; VGA_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_SYNC      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.33 V              ; -0.00341 V          ; 0.17 V                               ; 0.084 V                              ; 3.33e-09 s                  ; 3.24e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.33 V             ; -0.00341 V         ; 0.17 V                              ; 0.084 V                             ; 3.33e-09 s                 ; 3.24e-09 s                 ; Yes                       ; Yes                       ;
+; VGA_BLANK     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.08e-06 V                   ; 2.36 V              ; -0.0113 V           ; 0.122 V                              ; 0.022 V                              ; 4.5e-10 s                   ; 4.45e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.08e-06 V                  ; 2.36 V             ; -0.0113 V          ; 0.122 V                             ; 0.022 V                             ; 4.5e-10 s                  ; 4.45e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_VS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_HS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; HEX0_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; VGA_CLK       ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_SYNC      ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.64 V              ; -0.011 V            ; 0.212 V                              ; 0.198 V                              ; 2.38e-09 s                  ; 2.29e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.64 V             ; -0.011 V           ; 0.212 V                             ; 0.198 V                             ; 2.38e-09 s                 ; 2.29e-09 s                 ; No                        ; Yes                       ;
+; VGA_BLANK     ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.11e-08 V                   ; 2.73 V              ; -0.0566 V           ; 0.191 V                              ; 0.12 V                               ; 2.69e-10 s                  ; 2.76e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.11e-08 V                  ; 2.73 V             ; -0.0566 V          ; 0.191 V                             ; 0.12 V                              ; 2.69e-10 s                 ; 2.76e-10 s                 ; Yes                       ; Yes                       ;
+; VGA_VS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_HS        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; HEX0_D[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0_D[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------+
+; Setup Transfers                                                    ;
++------------+-----------+----------+----------+----------+----------+
+; From Clock ; To Clock  ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------+----------+----------+----------+----------+
+; BUTTON[2]  ; BUTTON[2] ; 171      ; 0        ; 0        ; 0        ;
++------------+-----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------+
+; Hold Transfers                                                     ;
++------------+-----------+----------+----------+----------+----------+
+; From Clock ; To Clock  ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------+----------+----------+----------+----------+
+; BUTTON[2]  ; BUTTON[2] ; 171      ; 0        ; 0        ; 0        ;
++------------+-----------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 0     ; 0    ;
+; Unconstrained Input Ports       ; 10    ; 10   ;
+; Unconstrained Input Port Paths  ; 148   ; 148  ;
+; Unconstrained Output Ports      ; 8     ; 8    ;
+; Unconstrained Output Port Paths ; 8     ; 8    ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+    Info: Processing started: Tue Mar 01 16:05:16 2016
+Info: Command: quartus_sta ise_proj -c ise_proj
+Info: qsta_default_script.tcl version: #1
+Warning (20013): Ignored assignments for entity "DE0_TOP" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_TOP -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_TOP -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_TOP -section_id Top was ignored
+Warning (20013): Ignored assignments for entity "DE0_VGA" -- entity does not exist in design
+    Warning (20014): Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity DE0_VGA -section_id "Root Region" was ignored
+    Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 14622752 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity DE0_VGA -section_id Top was ignored
+    Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity DE0_VGA -section_id Top was ignored
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Core supply voltage is 1.2V
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'ise_proj.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+    Info (332105): create_clock -period 1.000 -name BUTTON[2] BUTTON[2]
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -2.141
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -2.141       -24.967 BUTTON[2] 
+Info (332146): Worst-case hold slack is 0.382
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.382         0.000 BUTTON[2] 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -23.000 BUTTON[2] 
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -1.805
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -1.805       -20.320 BUTTON[2] 
+Info (332146): Worst-case hold slack is 0.333
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.333         0.000 BUTTON[2] 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -23.000 BUTTON[2] 
+Info: Analyzing Fast 1200mV 0C Model
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.738
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -0.738        -5.942 BUTTON[2] 
+Info (332146): Worst-case hold slack is 0.201
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):     0.201         0.000 BUTTON[2] 
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Info (332146): Worst-case minimum pulse width slack is -3.000
+    Info (332119):     Slack End Point TNS Clock 
+    Info (332119): ========= ============= =====================
+    Info (332119):    -3.000       -30.776 BUTTON[2] 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 54 warnings
+    Info: Peak virtual memory: 480 megabytes
+    Info: Processing ended: Tue Mar 01 16:05:18 2016
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.summary b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.summary
new file mode 100644
index 0000000..1404020
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj1/quartus_proj_DE0/ise_proj.sta.summary
@@ -0,0 +1,41 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'BUTTON[2]'
+Slack : -2.141
+TNS   : -24.967
+
+Type  : Slow 1200mV 85C Model Hold 'BUTTON[2]'
+Slack : 0.382
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'BUTTON[2]'
+Slack : -3.000
+TNS   : -23.000
+
+Type  : Slow 1200mV 0C Model Setup 'BUTTON[2]'
+Slack : -1.805
+TNS   : -20.320
+
+Type  : Slow 1200mV 0C Model Hold 'BUTTON[2]'
+Slack : 0.333
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'BUTTON[2]'
+Slack : -3.000
+TNS   : -23.000
+
+Type  : Fast 1200mV 0C Model Setup 'BUTTON[2]'
+Slack : -0.738
+TNS   : -5.942
+
+Type  : Fast 1200mV 0C Model Hold 'BUTTON[2]'
+Slack : 0.201
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'BUTTON[2]'
+Slack : -3.000
+TNS   : -30.776
+
+------------------------------------------------------------
diff --git a/student_files_2015[2]/student_files_2015/prj2/.DS_Store b/student_files_2015[2]/student_files_2015/prj2/.DS_Store
new file mode 100644
index 0000000..d3509f7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/.DS_Store
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/.DS_Store b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/.DS_Store
new file mode 100644
index 0000000..7eb20ea
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/.DS_Store
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/blur.c b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/blur.c
new file mode 100644
index 0000000..37811dc
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/blur.c
@@ -0,0 +1,136 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           blur.cpp
+//  Description:    video to vga blur filter - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+// based on the FIR design - page 230 of HLS Blue Book
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 27 MHz
+//  Top design: vga_blur
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraints:
+//  interface>vin: wordlength = 150, streaming = 150
+//  interface>vout: wordlength = 30, streaming = 30
+//  core>main: pipeline + distributed + merged
+//  core>main>frame: merged
+//  core>main>frame>shift, mac1, mac2: unroll + merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+#include <ac_fixed.h>
+#include "blur.h"
+#include <iostream>
+
+// shift_class: page 119 HLS Blue Book
+#include "shift_class.h" 
+
+
+
+
+#pragma hls_design top
+void mean_vga(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS])
+{
+    ac_int<16, false> red, green, blue, r[KERNEL_WIDTH], g[KERNEL_WIDTH], b[KERNEL_WIDTH];
+    
+
+// #if 1: use filter
+// #if 0: copy input to output bypassing filter
+#if 1
+
+    // shifts pixels from KERNEL_WIDTH rows and keeps KERNEL_WIDTH columns (KERNEL_WIDTHxKERNEL_WIDTH pixels stored)
+    static shift_class<ac_int<PIXEL_WL*KERNEL_WIDTH,false>, KERNEL_WIDTH> regs;
+    int i;
+
+    FRAME: for(int p = 0; p < NUM_PIXELS; p++) {
+		// init
+		red = 0; 
+		green = 0; 
+		blue = 0;
+		RESET: for(i = 0; i < KERNEL_WIDTH; i++) {
+			r[i] = 0;
+			g[i] = 0;
+			b[i] = 0;
+		}
+	    
+		// shift input data in the filter fifo
+		regs << vin[p]; // advance the pointer address by the pixel number (testbench/simulation only)
+		// accumulate
+		ACC1: for(i = 0; i < KERNEL_WIDTH; i++) {
+			// current line
+			r[0] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL));
+			g[0] += (regs[i].slc<COLOUR_WL>(COLOUR_WL));
+			b[0] += (regs[i].slc<COLOUR_WL>(0));
+			// the line before ...
+			r[1] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + PIXEL_WL));
+			g[1] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + PIXEL_WL));
+			b[1] += (regs[i].slc<COLOUR_WL>(0 + PIXEL_WL));
+			// the line before ...
+			r[2] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 2*PIXEL_WL));
+			g[2] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 2*PIXEL_WL)) ;
+			b[2] += (regs[i].slc<COLOUR_WL>(0 + 2*PIXEL_WL)) ;
+			// the line before ... 
+			r[3] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 3*PIXEL_WL));
+			g[3] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 3*PIXEL_WL)) ;
+			b[3] += (regs[i].slc<COLOUR_WL>(0 + 3*PIXEL_WL)) ;
+			// the line before ...
+			r[4] += (regs[i].slc<COLOUR_WL>(2*COLOUR_WL + 4*PIXEL_WL));
+			g[4] += (regs[i].slc<COLOUR_WL>(COLOUR_WL + 4*PIXEL_WL)) ;
+			b[4] += (regs[i].slc<COLOUR_WL>(0 + 4*PIXEL_WL)) ;
+		}
+		// add the accumualted value for all processed lines
+		ACC2: for(i = 0; i < KERNEL_WIDTH; i++) {    
+			red += r[i];
+			green += g[i];
+			blue += b[i];
+		}
+		// normalize result
+		red /= KERNEL_NUMEL;
+		green /= KERNEL_NUMEL;
+		blue /= KERNEL_NUMEL;
+	    
+		// group the RGB components into a single signal
+		vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);
+	    
+    }
+}
+     
+     
+     
+     
+     
+     
+#else    
+// display input  (test only)
+    FRAME: for(p = 0; p < NUM_PIXELS; p++) {
+        // copy the value of each colour component from the input stream
+        red = vin[p].slc<COLOUR_WL>(2*COLOUR_WL);
+        green = vin[p].slc<COLOUR_WL>(COLOUR_WL);
+        blue = vin[p].slc<COLOUR_WL>(0);
+
+		// combine the 3 color components into 1 signal only
+        vout[p] = ((((ac_int<PIXEL_WL, false>)red) << (2*COLOUR_WL)) | (((ac_int<PIXEL_WL, false>)green) << COLOUR_WL) | (ac_int<PIXEL_WL, false>)blue);   
+    }
+}
+#endif
+
+
+// end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/blur.h b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/blur.h
new file mode 100644
index 0000000..565b7c3
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/blur.h
@@ -0,0 +1,45 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           blur.h
+//  Description:    vga blur - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA stream and then produces a blured output
+////////////////////////////////////////////////////////////////////////////////
+
+
+#ifndef _BLUR
+#define _BLUR
+
+#include <ac_int.h>
+#include <iostream>
+
+// total number of pixels from screen frame/image read in testbench
+#define NUM_PIXELS (640*480)
+
+#define KERNEL_WIDTH      5
+#define KERNEL_NUMEL      (KERNEL_WIDTH * KERNEL_WIDTH)
+#define COLOUR_WL         10
+#define PIXEL_WL          (3 * COLOUR_WL)
+
+#define  COORD_WL          10
+
+
+void mean_vga(ac_int<PIXEL_WL*KERNEL_WIDTH,false> vin[NUM_PIXELS], ac_int<PIXEL_WL,false> vout[NUM_PIXELS]);
+
+#endif
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp
new file mode 100644
index 0000000..a3d7bff
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.cpp
@@ -0,0 +1,2967 @@
+#include <cstdlib>
+#include <iostream>
+#include <iomanip>
+#include <fstream>
+
+using namespace std;
+
+#include "bmp_io.h"
+
+//
+//  BMP_BYTE_SWAP controls how the program assumes that the bytes in 
+//  multi-byte data are ordered.
+//
+//  "true" is the correct value to use when running on a little-endian machine,
+//  and "false" is for big-endian.
+//
+
+static bool bmp_byte_swap = true;
+
+//****************************************************************************80
+
+bool bmp_byte_swap_get ( void )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_GET returns the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, bool BMP_BYTE_SWAP_GET, the internal value of BMP_BYTE_SWAP.
+//
+{
+  return bmp_byte_swap;
+}
+//****************************************************************************80
+
+void bmp_byte_swap_set ( bool value )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_BYTE_SWAP_SET sets the internal value of BMP_BYTE_SWAP.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    26 February 2003
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, bool VALUE, the new value of BMP_BYTE_SWAP.
+//
+{
+  bmp_byte_swap = value;
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_READ reads 8 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//    Thanks to Kelly Anderson for pointing out how to modify the program
+//    to handle monochrome images.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    01 April 2005
+//
+//  Author:
+//
+//    Kelly Anderson
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, a pointer to the red color arrays.
+//
+//    Output, bool BMP_08_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_08_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_08_DATA_WRITE writes 8 bit image data to a BMP file.
+//
+//  Discussion:
+//
+//    This routine does not seem to be performing properly.  The monochrome
+//    images it creates cannot be read by the XV program, which says that 
+//    they seem to have been prematurely truncated.
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexr;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_READ reads 24 bit image data of the BMP file.
+// 
+//  Discussion:
+//
+//    On output, the RGB information in the file has been copied into the
+//    R, G and B arrays.
+//
+//    Thanks to Peter Kionga-Kamau for pointing out an error in the
+//    previous implementation.
+//
+//    The standard ">>" operator cannot be used to transfer data, because
+//    it will be deceived by characters that "look like" new lines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the 
+//    red, green and blue color arrays.
+//
+//    Output, bool BMP_24_DATA_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int numbyte;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+  numbyte = 0;
+
+  for ( j = 0; j < abs ( height ); j++ ) 
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading B for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexb = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexb = indexb + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading G for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexg = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexg = indexg + 1;
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error ) 
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ: Fatal error!\n";
+        cout << "  Failed reading R for pixel (" << i << "," << j << ").\n";
+        return error;
+      }
+
+      *indexr = ( unsigned char ) c;
+      numbyte = numbyte + 1;
+      indexr = indexr + 1;
+    }
+//
+//  If necessary, read a few padding characters.
+//
+    for ( i = 0; i < padding; i++ )
+    {
+
+      file_in.read ( &c, 1 );
+
+      error = file_in.eof();
+
+      if ( error )
+      {
+        cout << "\n";
+        cout << "BMP_24_DATA_READ - Warning!\n";
+        cout << "  Failed while reading padding character " << i << "\n";
+        cout << "  of total " << padding << " characters\n";
+        cout << "  at the end of line " << j << "\n";
+        cout << "\n";
+        cout << "  This is a minor error.\n";
+        return false;
+      }
+    }
+  }
+
+  return false;
+}
+//****************************************************************************80
+
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_24_DATA_WRITE writes 24 bit image data to the BMP file.
+//
+//  Discussion:
+//
+//    The BMP format requires that each horizontal line be a multiple of 4 bytes.
+//    If the data itself does not have a WIDTH that is a multiple of 4, then
+//    the file must be padded with a few extra bytes so that each line has the
+//    appropriate length.  This information, and the corresponding corrective
+//    code, was supplied by Lee Mulcahy.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    11 December 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image in bytes.
+//
+//    Input, long int HEIGHT, the Y dimension of the image in bytes.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+{
+  int i;
+  unsigned int i2;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int padding;
+//
+//  Set the padding.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j = 0; j < abs ( height ); j++ )
+  {
+    for ( i2 = 0; i2 < width; i2++ )
+    {
+      file_out << *indexb;
+      file_out << *indexg;
+      file_out << *indexr;
+
+      indexb = indexb + 1;
+      indexg = indexg + 1;
+      indexr = indexr + 1;
+    }
+
+    for ( i = 0; i < padding; i++ )
+    {
+      file_out << 0;
+    }
+  }
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_PRINT prints the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file header:\n";
+  cout << "\n";
+  cout << "    FILETYPE =     " << filetype     << "\n";
+  cout << "    FILESIZE =     " << filesize     << "\n";
+  cout << "    RESERVED1 =    " << reserved1    << "\n";
+  cout << "    RESERVED2 =    " << reserved2    << "\n";
+  cout << "    BITMAPOFFSET = " << bitmapoffset << "\n";
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned short int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_READ reads the header information of a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    15 December 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned short int *FILETYPE, the file type.
+//
+//    Output, unsigned long int *FILESIZE, the file size.
+//
+//    Output, unsigned short int *RESERVED1, a reserved value.
+//
+//    Output, unsigned short int *RESERVED2, a reserved value.
+//
+//    Output, unsigned long int *BITMAPOFFSET, the bitmap offset.
+//
+{
+  bool error;
+  char i1;
+  char i2;  
+//
+//  Read FILETYPE.
+//
+  error = u_short_int_read ( filetype, file_in );
+
+  if ( error )
+  {
+    return error;
+  }
+//
+//  If you are doing swapping, you have to reunswap the filetype, I think, JVB 15 December 2004.
+//
+  if ( bmp_byte_swap )
+  {
+    i1 = ( char ) ( *filetype / 256 );
+    i2 = ( char ) ( *filetype % 256 );
+    *filetype = i2 * 256 + i1;
+  }
+//
+//  Read FILESIZE.
+//
+  error = u_long_int_read ( filesize, file_in );
+  if ( error ) 
+  {
+    return error;
+  }
+//
+//  Read RESERVED1.
+//
+  error = u_short_int_read ( reserved1, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read RESERVED2.
+//
+  error = u_short_int_read ( reserved2, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITMAPOFFSET.
+//
+  error = u_long_int_read ( bitmapoffset, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER1_WRITE writes the header information to a BMP file.
+//
+//  Discussion:
+//
+//    The header comprises 14 bytes:
+//
+//    2 bytes FILETYPE;        Magic number: "BM",
+//    4 bytes FILESIZE;        Size of file in 32 byte integers,
+//    2 bytes RESERVED1;       Always 0,
+//    2 bytes RESERVED2;       Always 0,
+//    4 bytes BITMAPOFFSET.    Starting position of image data, in bytes.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned short int FILETYPE, the file type.
+//
+//    Input, unsigned long int FILESIZE, the file size.
+//
+//    Input, unsigned short int RESERVED1, a reserved value.
+//
+//    Input, unsigned short int RESERVED2, a reserved value.
+//
+//    Input, unsigned long int BITMAPOFFSET, the bitmap offset.
+//
+{
+  u_short_int_write ( filetype, file_out );
+  u_long_int_write ( filesize, file_out );
+  u_short_int_write ( reserved1, file_out );
+  u_short_int_write ( reserved2, file_out );
+  u_long_int_write ( bitmapoffset, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_PRINT prints the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header ( = 40 bytes).
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    06 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned short int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  cout << "\n";
+  cout << "  Contents of BMP file bitmap header:\n";
+  cout << "\n";
+  cout << "    SIZE =            " << size            << "\n";
+  cout << "    WIDTH =           " << width           << "\n";
+  cout << "    HEIGHT =          " << height          << "\n";
+  cout << "    PLANES =          " << planes          << "\n";
+  cout << "    BITSPERPIXEL =    " << bitsperpixel    << "\n";
+  cout << "    COMPRESSION =     " << compression     << "\n";
+  cout << "    SIZEOFBITMAP =    " << sizeofbitmap    << "\n";
+  cout << "    HORZRESOLUTION =  " << horzresolution  << "\n";
+  cout << "    VERTRESOLUTION =  " << vertresolution  << "\n";
+  cout << "    COLORSUSED =      " << colorsused      << "\n";
+  cout << "    COLORSIMPORTANT = " << colorsimportant << "\n";
+
+  return;
+} 
+//****************************************************************************80
+
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_READ reads the bitmap header information of a BMP file.
+//
+//  Discussion:
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, unsigned long int *SIZE, the size of this header in bytes.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned short int *PLANES, the number of color planes.
+//
+//    Output, unsigned short int *BITSPERPIXEL, color bits per pixel.
+//
+//    Output, unsigned long int *COMPRESSION, the compression option.
+//
+//    Output, unsigned long int *SIZEOFBITMAP, the size of the bitmap.
+//
+//    Output, unsigned long int *HORZRESOLUTION, the horizontal resolution.
+//
+//    Output, unsigned long int *VERTRESOLUTION, the vertical resolution.
+//
+//    Output, unsigned long int *COLORSUSED, the number of colors in the palette.
+//
+//    Output, unsigned long int *COLORSIMPORTANT, the minimum number of colors.
+//
+//    Output, bool BMP_HEADER2_READ, is true if an error occurred.
+//
+{
+  bool error;
+//
+//  Read SIZE, the size of the header in bytes.
+//
+  error = u_long_int_read ( size, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read WIDTH, the image width in pixels.
+//
+  error = u_long_int_read ( width, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HEIGHT, the image height in pixels.
+//
+  error = long_int_read ( height, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read PLANES, the number of color planes.
+//
+  error = u_short_int_read ( planes, file_in ); 
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read BITSPERPIXEL.
+//
+  error = u_short_int_read ( bitsperpixel, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COMPRESSION.
+//
+  error = u_long_int_read ( compression, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read SIZEOFBITMAP.
+//
+  error = u_long_int_read ( sizeofbitmap, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read HORZRESOLUTION.
+//
+  error = u_long_int_read ( horzresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read VERTRESOLUTION.
+//
+  error = u_long_int_read ( vertresolution, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSUSED.
+//
+  error = u_long_int_read ( colorsused, file_in );
+  if ( error )
+  {
+    return error;
+  }
+//
+//  Read COLORSIMPORTANT.
+//
+  error = u_long_int_read ( colorsimportant, file_in );
+  if ( error )
+  {
+    return error;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_HEADER2_WRITE writes the bitmap header information to a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Mark Cave-Ayland, mca198@ecs.soton.ac.uk, for pointing out an 
+//    error which caused the code to write one too many long ints, 19 May 2001.
+//
+//    The bitmap header is 40 bytes long:
+//
+//    4 bytes SIZE;                Size of this header, in bytes.
+//    4 bytes WIDTH;               Image width, in pixels.   
+//    4 bytes HEIGHT;              Image height, in pixels.  
+//                                 (Pos/Neg, origin at bottom, top)
+//    2 bytes PLANES;              Number of color planes (always 1).
+//    2 bytes BITSPERPIXEL;        1 to 24.  1, 4, 8, 16, 24 or 32.
+//    4 bytes COMPRESSION;         0, uncompressed; 1, 8 bit RLE; 
+//                                 2, 4 bit RLE; 3, bitfields.
+//    4 bytes SIZEOFBITMAP;        Size of bitmap in bytes. (0 if uncompressed).
+//    4 bytes HORZRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes VERTRESOLUTION;      Pixels per meter. (Can be zero)
+//    4 bytes COLORSUSED;          Number of colors in palette.  (Can be zero).
+//    4 bytes COLORSIMPORTANT.     Minimum number of important colors. (Can be zero).
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    03 March 2004
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int SIZE, the size of this header in bytes.
+//
+//    Input, unsigned long int WIDTH, the X dimensions of the image.
+//
+//    Input, long int HEIGHT, the Y dimensions of the image.
+//
+//    Input, unsigned short int PLANES, the number of color planes.
+//
+//    Input, unsigned short int BITSPERPIXEL, color bits per pixel.
+//
+//    Input, unsigned long int COMPRESSION, the compression option.
+//
+//    Input, unsigned long int SIZEOFBITMAP, the size of the bitmap.
+//
+//    Input, unsigned long int HORZRESOLUTION, the horizontal resolution.
+//
+//    Input, unsigned long int VERTRESOLUTION, the vertical resolution.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned long int COLORSIMPORTANT, the minimum number of colors.
+//
+{
+  u_long_int_write ( size, file_out );
+  u_long_int_write ( width, file_out );
+  long_int_write ( height, file_out );
+  u_short_int_write ( planes, file_out ); 
+  u_short_int_write ( bitsperpixel, file_out );
+  u_long_int_write ( compression, file_out );
+  u_long_int_write ( sizeofbitmap, file_out );
+  u_long_int_write ( horzresolution, file_out );
+  u_long_int_write ( vertresolution, file_out );
+  u_long_int_write ( colorsused, file_out );
+  u_long_int_write ( colorsimportant, file_out );
+
+  return;
+}
+//****************************************************************************80
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_PRINT prints the palette data in a BMP file.
+// 
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  cout << "\n";
+  cout << "  Palette information from BMP file:\n";
+  cout << "\n";
+
+  if ( colorsused < 1 )
+  {
+    cout << "    There are NO colors defined for the palette.\n";
+    return;
+  }
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  cout << "\n";
+  cout << " Color    Blue   Green     Red   Trans\n";
+  cout << "\n";
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    cout << setw(6) << i       << "  "
+         << setw(6) << *indexb << "  "
+         << setw(6) << *indexg << "  "
+         << setw(6) << *indexr << "  "
+         << setw(6) << *indexa << "\n";
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_PALETTE_READ reads the palette information of a BMP file.
+//
+//  Discussion:
+// 
+//    There are COLORSUSED colors listed.  For each color, the values of
+//    (B,G,R,A) are listed, where A is a quantity reserved for future use.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    05 March 2003
+// 
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+//    Output, bool BMP_PALETTE_READ, is true if an error occurred.
+//
+{
+  char c;
+  bool error;
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading B for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexb = ( unsigned char ) c;
+    indexb = indexb + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading G for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexg = ( unsigned char ) c;
+    indexg = indexg + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading R for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexr = ( unsigned char ) c;
+    indexr = indexr + 1;
+
+    file_in.read ( &c, 1 );
+
+    error = file_in.eof();
+
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_PALETTE_READ: Fatal error!\n";
+      cout << "  Failed reading A for palette color " << i << ".\n";
+      return error;
+    }
+
+    *indexa = ( unsigned char ) c;
+    indexa = indexa + 1;
+  }
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray )
+
+//****************************************************************************80
+//
+//  Purpose:
+//  
+//    BMP_PALETTE_WRITE writes the palette data to the BMP file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    04 March 2004
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+//    Input, unsigned long int COLORSUSED, the number of colors in the palette.
+//
+//    Input, unsigned char *RPARRAY, *GPARRAY, *BPARRAY, *APARRAY, pointers to the 
+//    red, green, blue and transparency palette arrays.
+//
+{
+  unsigned int i;
+  unsigned char *indexa;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+
+  indexr = rparray;
+  indexg = gparray;
+  indexb = bparray;
+  indexa = aparray;
+
+  for ( i = 0; i < colorsused; i++ )
+  {
+    file_out << *indexb;
+    file_out << *indexg;
+    file_out << *indexr;
+    file_out << *indexa;
+
+    indexb = indexb + 1;
+    indexg = indexg + 1;
+    indexr = indexr + 1;
+    indexa = indexa + 1;
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool bmp_print_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_PRINT_TEST tests the BMP print routines.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    13 August 2007
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_PRINT_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *aparray;
+  unsigned char *barray;
+  unsigned char *bparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *garray;
+  unsigned char *gparray;
+  long int height;
+  unsigned long int horzresolution;
+  int numbytes;
+  unsigned short int planes;
+  unsigned char *rarray;
+  unsigned char *rparray;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+  unsigned long int width;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_PRINT_TEST - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+  cout << "\n";
+  cout << "BMP_PRINT_TEST:\n";
+  cout << "  Contents of BMP file \"" << file_in_name << "\"\n";
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+
+  bmp_header1_print ( filetype, filesize, reserved1, reserved2, bitmapoffset );
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, &width, &height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+
+  bmp_header2_print ( size, width, height, planes, bitsperpixel,
+    compression, sizeofbitmap, horzresolution, vertresolution, 
+    colorsused, colorsimportant );
+//
+//  Read the palette.
+//
+//if ( 0 < colorsused )
+//{
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+
+    bmp_palette_print ( colorsused, rparray, gparray, bparray, aparray );
+
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+//}
+//
+//  Allocate storage.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, width, height, rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    rarray = new unsigned char[numbytes];
+    garray = new unsigned char[numbytes];
+    barray = new unsigned char[numbytes];
+    
+    error = bmp_24_data_read ( file_in, width, height, rarray, garray, 
+      barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_PRINT_TEST: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_PRINT_TEST: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_READ reads the header and data of a BMP file.
+//
+//  Discussion:
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//    Thanks to Kelly Anderson for discovering that the routine could not read
+//    monochrome images (bitsperpixel = 8 ) and suggesting how to fix that.
+//
+//    Thanks to Vladimir Levin for correcting a memory leak in the monochrome
+//    image portion of the test, 13 August 2007.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    13 August 2007
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, unsigned long int *WIDTH, the X dimension of the image.
+//
+//    Output, long int *HEIGHT, the Y dimension of the image.
+//
+//    Output, unsigned char **RARRAY, **GARRAY, **BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_READ, is true if an error occurred.
+//
+{
+  unsigned char *aparray;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ifstream file_in;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray;
+  unsigned long int horzresolution;
+  unsigned short int magic;
+  int numbytes;
+  unsigned short int planes;
+  unsigned short int reserved1;
+  unsigned short int reserved2;
+  unsigned char *rparray;
+  unsigned long int size;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the input file.
+//
+  file_in.open ( file_in_name, ios::in | ios::binary );
+
+  if ( !file_in ) 
+  {
+    error = true;
+    cout << "\n";
+    cout << "BMP_READ - Fatal error!\n";
+    cout << "  Could not open the input file.\n";
+    return error;
+  }
+//
+//  Read header 1.
+//
+  error = bmp_header1_read ( file_in, &filetype, &filesize, &reserved1, 
+    &reserved2, &bitmapoffset );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER1_READ failed.\n";
+    return error;
+  }
+//
+//  Make sure the filetype is 'BM'.
+//
+  magic = 'B' * 256 + 'M';
+
+  if ( filetype != magic )
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  The file's internal magic number is not \"BM\".\n";
+    cout << "  with the numeric value " << magic << "\n";
+    cout << "\n";
+    cout << "  Instead, it is \"" 
+         << ( char ) ( filetype / 256 ) 
+         << ( char ) ( filetype % 256 )
+         << "\".\n";
+    cout << "  with the numeric value " << filetype << "\n";
+    cout << "\n";
+    cout << "  (Perhaps you need to reverse the byte swapping option!)\n";
+    return 1;
+  }
+//
+//  Read header 2.
+//
+  error = bmp_header2_read ( file_in, &size, width, height, &planes,
+    &bitsperpixel, &compression, &sizeofbitmap, &horzresolution,
+    &vertresolution, &colorsused, &colorsimportant );
+
+  if ( error ) 
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  BMP_HEADER2_READ failed.\n";
+    return error;
+  }
+//
+//  Read the palette.
+//
+  if ( 0 < colorsused )
+  {
+    rparray = new unsigned char[colorsused];
+    gparray = new unsigned char[colorsused];
+    bparray = new unsigned char[colorsused];
+    aparray = new unsigned char[colorsused];
+
+    error = bmp_palette_read ( file_in, colorsused, rparray, gparray,
+      bparray, aparray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_PALETTE_READ failed.\n";
+      return error;
+    }
+    delete [] rparray;
+    delete [] gparray;
+    delete [] bparray;
+    delete [] aparray;
+  }
+//
+//  Allocate storage.
+//
+  numbytes = ( *width ) * ( abs ( *height ) ) * sizeof ( unsigned char );
+//
+//  Read the data.
+//
+  if ( bitsperpixel == 8 )
+  {
+    *rarray = new unsigned char[numbytes];
+
+    error = bmp_08_data_read ( file_in, *width, *height, *rarray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_08_DATA_READ failed.\n";
+      return error;
+    }
+
+    *garray = *rarray;
+    *barray = *rarray;
+  }
+  else if ( bitsperpixel == 24 )
+  {
+    *rarray = new unsigned char[numbytes];
+    *garray = new unsigned char[numbytes];
+    *barray = new unsigned char[numbytes];
+
+    error = bmp_24_data_read ( file_in, *width, *height, *rarray, *garray, 
+      *barray );
+
+    if ( error ) 
+    {
+      cout << "\n";
+      cout << "BMP_READ: Fatal error!\n";
+      cout << "  BMP_24_DATA_READ failed.\n";
+      return error;
+    }
+  }
+  else
+  {
+    cout << "\n";
+    cout << "BMP_READ: Fatal error!\n";
+    cout << "  Unrecognized value of BITSPERPIXEL = " << bitsperpixel << "\n";
+    return 1;
+  }
+//
+//  Close the file.
+//
+  file_in.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_read_test ( char *file_in_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_READ_TEST tests the BMP read routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_IN_NAME, the name of the input file.
+//
+//    Output, bool BMP_READ_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  rarray = NULL;
+  garray = NULL;
+  barray = NULL;
+//
+//  Read the data from file.
+//
+  error = bmp_read ( file_in_name, &width, &height, &rarray, &garray, 
+    &barray );
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    if ( error )
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST - Fatal error!\n";
+      cout << "  The test failed.\n";
+    }
+    else
+    {
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  WIDTH =  " << width  << ".\n";
+      cout << "  HEIGHT = " << height << ".\n";
+      cout << "\n";
+      cout << "BMP_READ_TEST:\n";
+      cout << "  The test was successful.\n";
+    }
+  }
+
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width,
+  long int height, unsigned char *rarray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_08_WRITE writes the header and data for a monochrome BMP file.
+//
+//  Discussion:
+//
+//    XV seems to think the resulting BMP file is "unexpectedly truncated".
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, pointer to the red color array.
+//
+//    Output, bool BMP_08_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 1 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( width + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 8;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_08_data_write ( file_out, width, height, rarray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_08_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_08_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    02 April 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_08_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  bool error;
+  long int height;
+  int i;
+  unsigned char *indexr;
+  int j;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 255;
+  height = 255;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+//
+//  Set the data.
+//
+  indexr = rarray;
+
+  for ( j = 0; j < height; j++ )
+  {
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      *indexr = i % ( j + 1 );
+      indexr = indexr + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_08_write ( file_out_name, width, height, rarray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_08_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, 
+  unsigned char *barray )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    BMP_24_WRITE writes the header and data for a BMP file using three colors.
+//
+//  Discussion
+//
+//    Thanks to Keefe Roedersheimer for pointing out that I was creating
+//    a filetype of 'MB' instead of 'BM'.
+//
+//    Lee Mulcahy pointed out that the BMP format requires that horizonal lines
+//    must have a length that is a multiple of 4, or be padded so that this is the case.
+//
+//    Thanks to Tak Fung for suggesting that BMP files should be opened with
+//    the binary option.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+// 
+//    02 April 2005
+//
+//  Author:
+// 
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Input, unsigned long int WIDTH, the X dimension of the image.
+//
+//    Input, long int HEIGHT, the Y dimension of the image.
+//
+//    Input, unsigned char *RARRAY, *GARRAY, *BARRAY, pointers to the red, green
+//    and blue color arrays.
+//
+//    Output, bool BMP_24_WRITE, is true if an error occurred.
+//
+{
+  unsigned char *aparray = NULL;
+  unsigned long int bitmapoffset;
+  unsigned short int bitsperpixel;
+  unsigned char *bparray = NULL;
+  unsigned long int colorsimportant;
+  unsigned long int colorsused;
+  unsigned long int compression;
+  bool error;
+  ofstream file_out;
+  unsigned long int filesize;
+  unsigned short int filetype;
+  unsigned char *gparray = NULL;
+  unsigned long int horzresolution;
+  int padding;
+  unsigned short int planes;
+  unsigned short int reserved1 = 0;
+  unsigned short int reserved2 = 0;
+  unsigned char *rparray = NULL;
+  unsigned long int size = 40;
+  unsigned long int sizeofbitmap;
+  unsigned long int vertresolution;
+//
+//  Open the output file.
+//
+  file_out.open ( file_out_name, ios::out | ios::binary );
+
+  error = !file_out;
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE - Fatal error!\n";
+    cout << "  Could not open the output file.\n";
+    return error;
+  }
+//
+//  Write header 1.
+//
+  if ( bmp_byte_swap )
+  {
+    filetype = 'M' * 256 + 'B';
+  }
+  else
+  {
+    filetype = 'B' * 256 + 'M';
+  }
+//
+//  Determine the padding needed when WIDTH is not a multiple of 4.
+//
+  padding = ( 4 - ( ( 3 * width ) % 4 ) ) % 4;
+
+  filesize = 54 + ( ( 3 * width ) + padding ) * abs ( height );
+  bitmapoffset = 54;
+
+  bmp_header1_write ( file_out, filetype, filesize, reserved1, 
+    reserved2, bitmapoffset );
+//
+//  Write header 2.
+//
+  planes = 1;
+  bitsperpixel = 24;
+  compression = 0;
+  sizeofbitmap = 0;
+  horzresolution = 0;
+  vertresolution = 0;
+  colorsused = 0;
+  colorsimportant = 0;
+
+  bmp_header2_write ( file_out, size, width, height, planes, bitsperpixel, 
+    compression, sizeofbitmap, horzresolution, vertresolution,
+    colorsused, colorsimportant );
+//
+//  Write the palette.
+//
+  bmp_palette_write ( file_out, colorsused, rparray, gparray, bparray, 
+    aparray );
+//
+//  Write the data.
+//
+  bmp_24_data_write ( file_out, width, height, rarray, garray, barray );
+//
+//  Close the file.
+//
+  file_out.close ( );
+
+  error = false;
+  return error;
+}
+//****************************************************************************80
+
+bool bmp_24_write_test ( char *file_out_name )
+
+//****************************************************************************80
+//
+//  Purpose:
+//
+//    BMP_24_WRITE_TEST tests the BMP write routines.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  References:
+//
+//    David Kay and John Levine,
+//    Graphics File Formats,
+//    Second Edition,
+//    McGraw Hill, 1995.
+//
+//    Microsoft Corporation,
+//    Microsoft Windows Programmer's Reference,
+//    Volume 5; Messages, Structures, and Macros,
+//    Microsoft Press, 1993.
+//
+//    John Miano,
+//    Compressed Image File Formats,
+//    Addison Wesley, 1999.
+//
+//  Parameters:
+//
+//    Input, char *FILE_OUT_NAME, the name of the output file.
+//
+//    Output, bool BMP_24_WRITE_TEST, is true if an error occurred.
+//
+{
+# define VERBOSE false
+
+  unsigned char *barray;
+  bool error;
+  unsigned char *garray;
+  long int height;
+  int i;
+  unsigned char *indexb;
+  unsigned char *indexg;
+  unsigned char *indexr;
+  int j;
+  int j2;
+  int numbytes;
+  unsigned char *rarray;
+  unsigned long int width;
+
+  width = 200;
+  height = 200;
+//
+//  Allocate the memory.
+//
+  numbytes = width * abs ( height ) * sizeof ( unsigned char );  
+
+  rarray = new unsigned char[numbytes];
+  garray = new unsigned char[numbytes];
+  barray = new unsigned char[numbytes];
+//
+//  Set the data.
+//  Note that BMP files go from "bottom" up, so we'll reverse the
+//  sense of "J" here to get what we want.
+//
+  indexr = rarray;
+  indexg = garray;
+  indexb = barray;
+
+  for ( j2 = 0; j2 < abs ( height ); j2++ )
+  {
+    j = abs ( height ) - j2;
+    for ( i = 0; i < ( int ) width; i++ )
+    {
+      if ( i <= j )
+      {
+        *indexr = 255;
+        *indexg = 0;
+        *indexb = 0;
+      }
+      else if ( ( width - 1 ) * j + ( abs ( height ) - 1 ) * i <= 
+        ( width - 1 ) * ( abs ( height ) - 1 ) )
+      {
+        *indexr = 0;
+        *indexg = 255;
+        *indexb = 0;
+      }
+      else
+      {
+        *indexr = 0;
+        *indexg = 0;
+        *indexb = 255;
+      }
+      indexr = indexr + 1;
+      indexg = indexg + 1;
+      indexb = indexb + 1;
+    }
+  }
+//
+//  Write the data to a file.
+//
+  error = bmp_24_write ( file_out_name, width, height, rarray, garray, barray );
+
+  if ( error )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST - Fatal error!\n";
+    cout << "  The test failed.\n";
+    return error;
+  }
+//
+//  Free the memory.
+//
+  delete [] rarray;
+  delete [] garray;
+  delete [] barray;
+
+  if ( VERBOSE )
+  {
+    cout << "\n";
+    cout << "BMP_24_WRITE_TEST:\n";
+    cout << "  The test was successful.\n";
+  }
+
+  error = false;
+  return error;
+# undef VERBOSE
+}
+//****************************************************************************80
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_READ reads a long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, long int *LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+
+  *long_int_val = ( long int ) 
+    ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void long_int_write ( long int long_int_val, ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    LONG_INT_WRITE writes a long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    06 March 2004
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, long int *LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  long int temp;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  temp = long_int_val / 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_hi = ( unsigned short ) temp;
+
+  temp = long_int_val % 65536;
+  if ( temp < 0 )
+  {
+    temp = temp + 65536;
+  }
+  u_short_int_val_lo = ( unsigned short ) temp;
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_READ reads an unsigned long int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned long int *U_LONG_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_LONG_INT_READ, is true if an error occurred.
+//
+{
+  bool error;
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  if ( bmp_byte_swap )
+  {
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+  else
+  {
+    error = u_short_int_read ( &u_short_int_val_hi, file_in );
+    if ( error )
+    {
+      return error;
+    }
+    error = u_short_int_read ( &u_short_int_val_lo, file_in );
+    if ( error )
+    {
+      return error;
+    }
+  }
+//
+//  Acknowledgement:
+//
+//    A correction to the following line was supplied by
+//    Peter Kionga-Kamau, 20 May 2000.
+//
+
+  *u_long_int_val = ( u_short_int_val_hi << 16 ) | u_short_int_val_lo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_long_int_write ( unsigned long int u_long_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_LONG_INT_WRITE writes an unsigned long int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    05 March 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned long int *U_LONG_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned short int u_short_int_val_hi;
+  unsigned short int u_short_int_val_lo;
+
+  u_short_int_val_hi = ( unsigned short ) ( u_long_int_val / 65536 );
+  u_short_int_val_lo = ( unsigned short ) ( u_long_int_val % 65536 );
+
+  if ( bmp_byte_swap )
+  {
+    u_short_int_write ( u_short_int_val_lo, file_out );
+    u_short_int_write ( u_short_int_val_hi, file_out );
+  }
+  else
+  {
+    u_short_int_write ( u_short_int_val_hi, file_out );
+    u_short_int_write ( u_short_int_val_lo, file_out );
+  }
+
+  return;
+}
+//****************************************************************************80
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, 
+  ifstream &file_in )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_READ reads an unsigned short int from a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    30 March 2005
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Output, unsigned short int *U_SHORT_INT_VAL, the value that was read.
+//
+//    Input, ifstream &FILE_IN, a reference to the input file.
+//
+//    Output, bool U_SHORT_INT_READ, is true if an error occurred.
+//
+{
+  char c;
+  unsigned char chi;
+  unsigned char clo;
+
+  if ( bmp_byte_swap )
+    {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+  }
+  else
+  {
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    chi = ( unsigned char ) c;
+
+    file_in.read ( &c, 1 );
+    if ( file_in.eof() )
+    {
+      return true;
+    }
+    clo = ( unsigned char ) c;
+  }
+
+  *u_short_int_val = ( chi << 8 ) | clo;
+
+  return false;
+}
+//****************************************************************************80
+
+void u_short_int_write ( unsigned short int u_short_int_val, 
+  ofstream &file_out )
+
+//****************************************************************************80
+//
+//  Purpose:
+// 
+//    U_SHORT_INT_WRITE writes an unsigned short int to a file.
+//
+//  Licensing:
+//
+//    This code is distributed under the GNU LGPL license. 
+//
+//  Modified:
+//
+//    26 February 2003
+//
+//  Author:
+//
+//    John Burkardt
+//
+//  Parameters:
+//
+//    Input, unsigned short int *U_SHORT_INT_VAL, the value to be written.
+//
+//    Input, ofstream &FILE_OUT, a reference to the output file.
+//
+{
+  unsigned char chi;
+  unsigned char clo;
+
+  chi = ( unsigned char ) ( u_short_int_val / 256 );
+  clo = ( unsigned char ) ( u_short_int_val % 256 );
+
+  if ( bmp_byte_swap )
+  {
+    file_out << clo << chi;
+  }
+  else
+  {
+    file_out << chi << clo;
+  }
+
+  return;
+}
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h
new file mode 100644
index 0000000..2fe3298
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/bmp_io.h
@@ -0,0 +1,80 @@
+#include <fstream>
+#include <iostream>
+
+using namespace std;
+
+
+bool bmp_byte_swap_get ( void );
+void bmp_byte_swap_set ( bool value );
+
+bool bmp_08_data_read ( ifstream &file_in, unsigned long int width, long int height, 
+  unsigned char *rarray );
+void bmp_08_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray );
+
+bool bmp_24_data_read ( ifstream &file_in, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+void bmp_24_data_write ( ofstream &file_out, unsigned long int width, 
+  long int height, unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+
+void bmp_header1_print ( unsigned short int filetype, 
+  unsigned long int filesize, unsigned short int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+bool bmp_header1_read ( ifstream &file_in, unsigned short int *filetype, 
+  unsigned long int *filesize, unsigned long int *reserved1, 
+  unsigned short int *reserved2, unsigned long int *bitmapoffset );
+void bmp_header1_write ( ofstream &file_out, unsigned short int filetype,
+  unsigned long int filesize, unsigned long int reserved1, 
+  unsigned short int reserved2, unsigned long int bitmapoffset );
+
+void bmp_header2_print ( unsigned long int size, unsigned long int width, 
+  long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel, 
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused,  unsigned long int colorsimportant );
+bool bmp_header2_read ( ifstream &file_in, unsigned long int *size,
+  unsigned long int *width, long int *height, 
+  unsigned short int *planes, unsigned short int *bitsperpixel,
+  unsigned long int *compression, unsigned long int *sizeofbitmap,
+  unsigned long int *horzresolution, unsigned long int *vertresolution,
+  unsigned long int *colorsused, unsigned long int *colorsimportant );
+void bmp_header2_write ( ofstream &file_out, unsigned long int size,
+  unsigned long int width, long int height, 
+  unsigned short int planes, unsigned short int bitsperpixel,
+  unsigned long int compression, unsigned long int sizeofbitmap,
+  unsigned long int horzresolution, unsigned long int vertresolution,
+  unsigned long int colorsused, unsigned long int colorsimportant );
+
+void bmp_palette_print ( unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+bool bmp_palette_read ( ifstream &file_in, unsigned long int colorsused,
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray, 
+  unsigned char *aparray );
+void bmp_palette_write ( ofstream &file_out, unsigned long int colorsused, 
+  unsigned char *rparray, unsigned char *gparray, unsigned char *bparray,
+  unsigned char *aparray );
+
+bool bmp_print_test ( char *file_in_name );
+
+bool bmp_read ( char *file_in_name, unsigned long int *width, long int *height, 
+  unsigned char **rarray, unsigned char **garray, unsigned char **barray );
+bool bmp_read_test ( char *file_in_name );
+
+bool bmp_08_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_08_write_test ( char *file_out_name );
+
+bool bmp_24_write ( char *file_out_name, unsigned long int width, long int height, 
+  unsigned char *rarray, unsigned char *garray, unsigned char *barray );
+bool bmp_24_write_test ( char *file_out_name );
+
+bool long_int_read ( long int *long_int_val, ifstream &file_in );
+void long_int_write ( long int long_int_val, ofstream &file_out );
+
+bool u_long_int_read ( unsigned long int *u_long_int_val, ifstream &file_in );
+void u_long_int_write ( unsigned long int u_long_int_val, ofstream &file_out );
+
+bool u_short_int_read ( unsigned short int *u_short_int_val, ifstream &file_in );
+void u_short_int_write ( unsigned short int u_short_int_val, ofstream &file_out );
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h
new file mode 100644
index 0000000..be64c0f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/shift_class.h
@@ -0,0 +1,54 @@
+#ifndef __SHIFT_CLASS__
+#define __SHIFT_CLASS__
+
+template<typename dataType, int NUM_REGS>
+class shift_class{
+private:
+    dataType regs[NUM_REGS];
+    bool en;
+    bool sync_rst;
+    bool ld;
+    dataType *load_data;
+public:
+    shift_class():en(true),sync_rst(false),ld(false){}
+    shift_class(dataType din[NUM_REGS]):
+    en(true),sync_rst(false),ld(false){ load_data = din; }
+
+    void set_sync_rst(bool srst)
+    {
+        sync_rst = srst;
+    }
+
+    void load(bool load_in)
+    {
+        ld = load_in;
+    }
+
+    void set_enable(bool enable)
+    {
+        en = enable;
+    }
+
+    void operator << (dataType din)
+    {
+    SHIFT:for(int i=NUM_REGS-1;i>=0;i--){
+    if(en)
+        if(sync_rst)
+            regs[i] = 0;
+        else if(ld)
+            regs[i] = load_data[i];
+        else
+        if(i==0)
+            regs[i] = din;
+        else
+            regs[i] = regs[i-1];
+        }
+    }
+
+    dataType operator [](int i)
+    {
+        return regs[i];
+    }
+};
+
+#endif
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp
new file mode 100644
index 0000000..b3df259
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_blur/tb_blur.cpp
@@ -0,0 +1,341 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           tb_blur.cpp
+//  Description:    blur filter testbench
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// Testbench to test the blur filter design.
+// It uses an input BMP image with the same resolution as the VGA in the DE2
+// Use images with the same size only and 24 bits (3colours*8bits)
+// Source: icl1.bmp,  width = 640,  height = 480
+// 
+// Settings: 
+// Exclude from compilation (same applies to bmp*.h/cpp files)
+// Enable SCVerify in Flow Manager
+////////////////////////////////////////////////////////////////////////////////
+//
+// WARNING: this testbench is incomplete.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+#include "mc_testbench.h"
+#include <mc_scverify.h>
+
+
+#include <iostream>
+#include "ac_int.h"
+// filter defs and protos
+#include "blur.h"
+// bmp lib
+#include "bmp_io.h"
+
+// file names
+char *source_bmp_file = "icl1.bmp";
+char *hw_bmp_file = "icl2.bmp";
+char *sw_bmp_file = "icl3.bmp";
+
+// pointers to input image contents
+unsigned char *red_in, *green_in, *blue_in;
+// image information
+long int height;
+unsigned long int width;
+int num_pixels;   
+
+   
+// function prototypes:
+void testbench();
+void sw_test();
+
+
+
+
+
+// Main Verification Function
+CCS_MAIN(int argc, char *argv[])
+{
+	// teste your design
+	// blur filter
+    cout << "*** start testbench *** " << endl;
+    testbench();
+    cout << "*** end of testbench *** " << endl;
+
+	// test your algorithm in sw
+	// grayscale convertion
+    cout << "*** start sw test *** " << endl;
+    sw_test();
+    cout << "*** end of sw test *** " << endl;
+
+
+    //  Free the memory
+    delete [] red_in;
+    delete [] green_in;
+    delete [] blue_in;
+       
+    CCS_RETURN(0);
+}
+
+
+
+
+
+
+// this function tests your image processing algorithm implmented 
+// in hardware using the RGB streams from BMP file
+void testbench()
+{
+ 
+    unsigned char *red_out, *green_out, *blue_out;
+    bool error;
+    int i, j;
+
+
+	// these signals have to match the ones in the block diagram 
+	// where they are connected
+    ac_int<PIXEL_WL * KERNEL_WIDTH, false> *input_stream;
+    ac_int<PIXEL_WL, false> *output_stream;
+
+
+
+	/************************************************************************
+    * reads the original/source BMP file, to emulate video frame
+  	* colour arrays are automatically allocated inside the function
+  	* size of the image is extracted from the BMP header
+  	* bmp_read(filename, *width, *height, *red, *green, *blue);
+	************************************************************************/
+	error = bmp_read(source_bmp_file, &width, &height, &red_in, &green_in, &blue_in);
+    if (error)
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << width << "x" << height << endl;
+    }
+
+
+    num_pixels = width * abs (height) * sizeof ( unsigned char );     
+
+    if(num_pixels != NUM_PIXELS) {
+        cout << "ERROR: Expecting a 640x480 BMP image!" << endl;
+        delete [] red_in;
+        delete [] green_in;
+        delete [] blue_in;
+        return;
+    }
+    
+    
+
+    // need to reserve memory to store results from the filter
+    // allocate memory to input & output streams from/to your hardware block
+    input_stream = new ac_int<PIXEL_WL * KERNEL_WIDTH, false>[num_pixels];
+    output_stream = new ac_int<PIXEL_WL, false>[num_pixels];
+
+
+    // RGB colour components to be written in file
+    // the output must have the same number of bytes/pixels as the input
+    red_out = new unsigned char[num_pixels];
+    green_out = new unsigned char[num_pixels];
+    blue_out = new unsigned char[num_pixels];
+
+
+    // filter buffer = shift register from input column (KERNEL_WIDTH columns)
+    ac_int<PIXEL_WL, false>col_pixel_buf[KERNEL_WIDTH];
+
+    // group the 3 colour components into 1 single steam
+    // generate the input stream emulating the camera
+    for(i = 0; i < num_pixels; i++) {
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+			// bits 29..20 = RED,  19..10 = GREEN, 9..0 = BLUE
+            col_pixel_buf[j] = ((((ac_int<PIXEL_WL, false>)red_in[i + j * width]) << (2*COLOUR_WL)) | 
+                                (((ac_int<PIXEL_WL, false>)green_in[i + j * width]) << COLOUR_WL) 
+                                | (ac_int<PIXEL_WL, false>)blue_in[i + j * width]);
+        }
+        input_stream[i] = 0;
+        for(j = 0; j < KERNEL_WIDTH; j++) {
+            input_stream[i] |= ((ac_int<PIXEL_WL * KERNEL_WIDTH, false>)col_pixel_buf[j]) << (j * PIXEL_WL);
+        }
+    }
+    
+    
+    
+    
+    
+    /******************************************************************/
+    /* test your design                                               */
+    /******************************************************************/
+
+    CCS_DESIGN(mean_vga)(input_stream, output_stream); 
+
+/*  by-pass your block - check I/Os  
+	for(int i = 0; i < num_pixels; i++) {
+        output_stream[i] = input_stream[i].slc<PIXEL_WL>(0); // copy current pixel (0,30,60,90,120)
+    }    */
+
+
+    
+    
+    // recover your RGB colour signals from the output stream
+    for(int i = 0; i < num_pixels; i++) {
+        red_out[i] = (output_stream[i].slc<COLOUR_WL>(2*COLOUR_WL));
+        green_out[i] = (output_stream[i].slc<COLOUR_WL>(COLOUR_WL));
+        blue_out[i] = (output_stream[i].slc<COLOUR_WL>(0));
+    }    
+
+ 
+
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(hw_bmp_file, width, height, red_out, green_out, blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+
+
+
+   // release memory
+    delete [] input_stream;
+    delete [] output_stream;
+    
+
+    delete [] red_out;
+    delete [] green_out;
+    delete [] blue_out;
+
+    return;        
+
+}
+
+
+
+
+
+
+// this function tests your algorithm in software 
+// usefull to generate the expected result
+void sw_test()
+{
+   // this test copies the original image with swapped colours
+    //unsigned char *red_in, *green_in, *blue_in;
+    unsigned char *sw_red_out, *sw_green_out, *sw_blue_out;
+    bool error;
+    int i, j;
+
+
+
+    
+    
+    
+    // need to reserve memory to store results from the filter
+    // the output must have the same number of bytes/pixels as the input
+    sw_red_out = new unsigned char[num_pixels];
+    sw_green_out = new unsigned char[num_pixels];
+    sw_blue_out = new unsigned char[num_pixels];
+
+
+
+
+    /************************************************************************/
+	/* test of the algorithm in software  
+	/* - data not being processed by your unit
+    /* you can compare the results of your design block 
+    /* e.g. convert from colour to grayscale 
+    /************************************************************************/
+    for(int i = 0; i < num_pixels; i++) {
+        sw_red_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_green_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+        sw_blue_out[i] = (red_in[i] + green_in[i] + blue_in[i]) / 3;
+    }
+
+
+
+    /************************************************************************/
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write(sw_bmp_file, width, height, sw_red_out, sw_green_out, sw_blue_out);
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    /************************************************************************/
+	//  Free the memory
+    delete [] sw_red_out;
+    delete [] sw_green_out;
+    delete [] sw_blue_out;
+
+    return;        
+}
+
+
+
+
+
+void bmp_io_test()
+{
+    // this test copies the original image with swapped colours
+    unsigned char *barray, *garray, *rarray;
+    bool error;
+    long int height;
+    unsigned long int width;
+
+    //  read the original BMP file
+  	// bmp_read(filename, *width, *height, *red, *green, *blue);
+  	// colour arrays are automatically allocated inside the function
+  	// size of the image is also extracted from the BMP header
+	error = bmp_read("icl1.bmp", &width, &height, &rarray,&garray,&barray);
+    if ( error )
+    {
+        cout << "\n";
+        cout << "bmp_read: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_read: OK" << endl;
+        cout << "bmp_read: " << " width = " <<  width << ", height = " << height << endl;
+    }
+
+    // write the new BMP file:  swap blue and green
+	// bmp_24_write(filename, width, height, red, green, blue);
+	error = bmp_24_write("icl2.bmp", width, height, rarray, barray, garray );
+    if ( error ) {
+        cout << "bmp_24_write: ERROR" << endl;
+        return ;
+    }
+    else {
+        cout << "bmp_24_write: OK" << endl;
+    }
+
+    //  Free the memory
+    delete [] rarray;
+    delete [] garray;
+    delete [] barray;
+
+    return;
+}
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c
new file mode 100644
index 0000000..7e11f9d
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/catapult_proj/vga_mouse/vga_mouse_square.c
@@ -0,0 +1,94 @@
+////////////////////////////////////////////////////////////////////////////////
+//  _____                           _       _    _____      _ _
+// |_   _|                         (_)     | |  / ____|    | | |
+//   | |  _ __ ___  _ __   ___ _ __ _  __ _| | | |     ___ | | | ___  __ _  ___
+//   | | | '_ ` _ \| '_ \ / _ \ '__| |/ _` | | | |    / _ \| | |/ _ \/ _` |/ _ \
+//  _| |_| | | | | | |_) |  __/ |  | | (_| | | | |___| (_) | | |  __/ (_| |  __/
+// |_____|_| |_| |_| .__/ \___|_|  |_|\__,_|_|  \_____\___/|_|_|\___|\__, |\___|
+//                 | |                                                __/ |
+//                 |_|                                               |___/
+//  _                     _
+// | |                   | |
+// | |     ___  _ __   __| | ___  _ __
+// | |    / _ \| '_ \ / _` |/ _ \| '_ \
+// | |___| (_) | | | | (_| | (_) | | | |
+// |______\___/|_| |_|\__,_|\___/|_| |_|
+//
+////////////////////////////////////////////////////////////////////////////////
+//  File:           vga_mouse_square.cpp
+//  Description:    video to vga with mouse pointer - real-time processing
+//  By:             rad09
+////////////////////////////////////////////////////////////////////////////////
+// this hardware block receives the VGA scanning coordinates, 
+// the mouse coordinates and then replaces the mouse pointer 
+// with a different value for the pixel
+////////////////////////////////////////////////////////////////////////////////
+// Catapult Project options
+// Constraint Editor:
+//  Frequency: 27 MHz
+//  Top design: vga_mouse_square
+//  clk>reset sync: disable; reset async: enable; enable: enable
+// Architecture Constraint:
+//  core>main: enable pipeline + loop can be merged
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#include "stdio.h"
+#include "ac_int.h"
+
+#define COLOR_WL          10
+#define PIXEL_WL          (3*COLOR_WL)
+
+#define  COORD_WL          10
+
+#pragma hls_design top
+void vga_mouse_square(ac_int<(COORD_WL+COORD_WL), false> * vga_xy, ac_int<(COORD_WL+COORD_WL), false> * mouse_xy, ac_int<(8), false> cursor_size, 
+    ac_int<PIXEL_WL, false> * video_in, ac_int<PIXEL_WL, false> * video_out)
+{
+    ac_int<10, false> i_red, i_green, i_blue; // current pixel
+    ac_int<10, false> o_red, o_green, o_blue; // output pixel
+    ac_int<10, false> mouse_x, mouse_y, vga_x, vga_y; // mouse and screen coordinates
+
+    
+/*  --extract the 3 color components from the 30 bit signal--
+    the 2 blocks are identical - you can shift and mask the desired bits or "slice" the signal <length>(location)
+    
+    i_red = *video_in >> 20;
+    i_green = (*video_in >> 10) & (ac_int<10>)1023;
+    i_blue = *video_in & ((ac_int<10>)1023); 
+*/    
+    i_red = (*video_in).slc<COLOR_WL>(20);
+    i_green = (*video_in).slc<COLOR_WL>(10);
+    i_blue = (*video_in).slc<COLOR_WL>(0);
+
+    // extract mouse X-Y coordinates
+    mouse_x = (*mouse_xy).slc<COORD_WL>(0);
+    mouse_y = (*mouse_xy).slc<COORD_WL>(10);
+    // extract VGA pixel X-Y coordinates
+    vga_x = (*vga_xy).slc<COORD_WL>(0);
+    vga_y = (*vga_xy).slc<COORD_WL>(10);
+   
+   
+    
+    /// something here...
+     
+    
+    /// show pixel
+    if ((vga_x >= mouse_x - cursor_size) && (vga_x <= mouse_x + cursor_size) && (vga_y >= mouse_y - cursor_size) && (vga_y <= mouse_y + cursor_size)){
+        // if it is inside the mouse square
+        o_red = 0;
+        o_green = i_green;
+        o_blue = 0;
+    }
+    else {
+        // if it is outside the mouse square
+        o_red = i_red;
+        o_green = i_green;
+        o_blue = i_blue;
+    }
+    
+    // combine the 3 color components into 1 signal only
+    *video_out = ((((ac_int<PIXEL_WL, false>)o_red) << 20) | (((ac_int<PIXEL_WL, false>)o_green) << 10) | (ac_int<PIXEL_WL, false>)o_blue);
+}
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/instructions.doc b/student_files_2015[2]/student_files_2015/prj2/instructions.doc
new file mode 100644
index 0000000..dfe3225
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/instructions.doc
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf
new file mode 100644
index 0000000..b02e201
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Copy of DE1_D5M.qsf
@@ -0,0 +1,702 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE1_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE1_D5M
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1[16]
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_location_assignment PIN_U7 -to GPIO_0[31]
+set_location_assignment PIN_V5 -to GPIO_0[30]
+set_location_assignment PIN_W6 -to GPIO_0[29]
+set_location_assignment PIN_W7 -to GPIO_0[28]
+set_location_assignment PIN_V8 -to GPIO_0[27]
+set_location_assignment PIN_T8 -to GPIO_0[26]
+set_location_assignment PIN_W10 -to GPIO_0[25]
+set_location_assignment PIN_Y10 -to GPIO_0[24]
+set_location_assignment PIN_V11 -to GPIO_0[23]
+set_location_assignment PIN_R10 -to GPIO_0[22]
+set_location_assignment PIN_V12 -to GPIO_0[21]
+set_location_assignment PIN_U13 -to GPIO_0[20]
+set_location_assignment PIN_W13 -to GPIO_0[19]
+set_location_assignment PIN_Y13 -to GPIO_0[18]
+set_location_assignment PIN_U14 -to GPIO_0[17]
+set_location_assignment PIN_V14 -to GPIO_0[16]
+set_location_assignment PIN_AA4 -to GPIO_0[15]
+set_location_assignment PIN_AB4 -to GPIO_0[14]
+set_location_assignment PIN_AA5 -to GPIO_0[13]
+set_location_assignment PIN_AB5 -to GPIO_0[12]
+set_location_assignment PIN_AA8 -to GPIO_0[11]
+set_location_assignment PIN_AB8 -to GPIO_0[10]
+set_location_assignment PIN_AA10 -to GPIO_0[9]
+set_location_assignment PIN_AB10 -to GPIO_0[8]
+set_location_assignment PIN_AA13 -to GPIO_0[7]
+set_location_assignment PIN_AB13 -to GPIO_0[6]
+set_location_assignment PIN_AB14 -to GPIO_0[5]
+set_location_assignment PIN_AA14 -to GPIO_0[4]
+set_location_assignment PIN_AB15 -to GPIO_0[3]
+set_location_assignment PIN_AA15 -to GPIO_0[2]
+set_location_assignment PIN_AA16 -to GPIO_0[1]
+set_location_assignment PIN_AB16 -to GPIO_0[0]
+
+set_location_assignment PIN_AB12 -to GPIO_0[32]
+set_location_assignment PIN_AA12 -to GPIO_0[33]
+set_location_assignment PIN_AB3 -to GPIO_0[34]
+set_location_assignment PIN_AA3 -to GPIO_0[35]
+
+
+set_location_assignment PIN_AA11 -to GPIO_1[32]
+set_location_assignment PIN_AB11 -to GPIO_1[33]
+set_location_assignment PIN_T16 -to GPIO_1[34]
+set_location_assignment PIN_R16 -to GPIO_1[35]
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_location_assignment PIN_G21 -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+#set_location_assignment PIN_E8 -to TDI
+#set_location_assignment PIN_D8 -to TCS
+#set_location_assignment PIN_C7 -to TCK
+#set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_R2 -to FL_ADDR[21]
+set_location_assignment PIN_P3 -to FL_ADDR[20]
+set_location_assignment PIN_P1 -to FL_ADDR[19]
+set_location_assignment PIN_M6 -to FL_ADDR[18]
+set_location_assignment PIN_M5 -to FL_ADDR[17]
+set_location_assignment PIN_AA2 -to FL_ADDR[16]
+set_location_assignment PIN_L6 -to FL_ADDR[15]
+set_location_assignment PIN_L7 -to FL_ADDR[14]
+set_location_assignment PIN_M1 -to FL_ADDR[13]
+set_location_assignment PIN_M2 -to FL_ADDR[12]
+set_location_assignment PIN_M3 -to FL_ADDR[11]
+set_location_assignment PIN_N1 -to FL_ADDR[10]
+set_location_assignment PIN_N2 -to FL_ADDR[9]
+set_location_assignment PIN_P2 -to FL_ADDR[8]
+set_location_assignment PIN_M4 -to FL_ADDR[7]
+set_location_assignment PIN_M8 -to FL_ADDR[6]
+set_location_assignment PIN_N6 -to FL_ADDR[5]
+set_location_assignment PIN_N5 -to FL_ADDR[4]
+set_location_assignment PIN_N7 -to FL_ADDR[3]
+set_location_assignment PIN_P6 -to FL_ADDR[2]
+set_location_assignment PIN_P5 -to FL_ADDR[1]
+set_location_assignment PIN_P7 -to FL_ADDR[0]
+set_location_assignment PIN_AA1 -to FL_BYTE_N
+set_location_assignment PIN_N8 -to FL_CE_N
+set_location_assignment PIN_R7 -to FL_DQ[0]
+set_location_assignment PIN_P8 -to FL_DQ[1]
+set_location_assignment PIN_R8 -to FL_DQ[2]
+set_location_assignment PIN_U1 -to FL_DQ[3]
+set_location_assignment PIN_V2 -to FL_DQ[4]
+set_location_assignment PIN_V3 -to FL_DQ[5]
+set_location_assignment PIN_W1 -to FL_DQ[6]
+set_location_assignment PIN_Y1 -to FL_DQ[7]
+set_location_assignment PIN_T5 -to FL_DQ[8]
+set_location_assignment PIN_T7 -to FL_DQ[9]
+set_location_assignment PIN_T4 -to FL_DQ[10]
+set_location_assignment PIN_U2 -to FL_DQ[11]
+set_location_assignment PIN_V1 -to FL_DQ[12]
+set_location_assignment PIN_V4 -to FL_DQ[13]
+set_location_assignment PIN_W2 -to FL_DQ[14]
+set_location_assignment PIN_R6 -to FL_OE_N
+set_location_assignment PIN_R1 -to FL_RST_N
+set_location_assignment PIN_M7 -to FL_RY
+set_location_assignment PIN_P4 -to FL_WE_N
+set_location_assignment PIN_T3 -to FL_WP_N
+set_location_assignment PIN_Y2 -to FL_DQ15_AM1
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE1_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE1_D5M.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt
new file mode 100644
index 0000000..a7b1105
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.asm.rpt
@@ -0,0 +1,130 @@
+Assembler report for DE0_D5M
+Mon Mar 17 10:02:44 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof
+  6. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Mon Mar 17 10:02:44 2014 ;
+; Revision Name         ; DE0_D5M                               ;
+; Top-level Entity Name ; TOP_CAMERA                            ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; On       ; Off           ;
+; Use configuration device                                                    ; On       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++---------------------------------------------------------------------------+
+; Assembler Generated Files                                                 ;
++---------------------------------------------------------------------------+
+; File Name                                                                 ;
++---------------------------------------------------------------------------+
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof ;
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof ;
++---------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.sof ;
++----------------+------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                            ;
++----------------+------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                       ;
+; JTAG usercode  ; 0x0019C8D3                                                                         ;
+; Checksum       ; 0x0019C8D3                                                                         ;
++----------------+------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pof ;
++--------------------+--------------------------------------------------------------------------------+
+; Option             ; Setting                                                                        ;
++--------------------+--------------------------------------------------------------------------------+
+; Device             ; EPCS4                                                                          ;
+; JTAG usercode      ; 0x00000000                                                                     ;
+; Checksum           ; 0x05BFF881                                                                     ;
+; Compression Ratio  ; 3                                                                              ;
++--------------------+--------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:39 2014
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 450 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:44 2014
+    Info: Elapsed time: 00:00:05
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf
new file mode 100644
index 0000000..b4e6ef4
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.bsf
@@ -0,0 +1,232 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 480)
+	(text "DE0_D5M" (rect 5 0 49 12)(font "Arial" ))
+	(text "inst" (rect 8 448 20 460)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 49 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 36 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 47 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 220 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 267 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 224 59 267 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 267 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 267 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 177 123 267 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 66 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 201 139 267 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 200 155 267 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160)(line_width 1))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 199 171 267 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176)(line_width 1))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 71 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 196 187 267 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192)(line_width 1))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 73 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 194 203 267 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208)(line_width 1))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 204 219 267 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224)(line_width 1))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 62 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 205 235 267 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240)(line_width 1))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 61 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 206 251 267 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256)(line_width 1))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 57 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 210 267 267 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272)(line_width 1))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 208 283 267 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288)(line_width 1))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_HS" (rect 225 299 267 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304)(line_width 1))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_VS" (rect 224 315 267 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320)(line_width 1))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[3..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_R[3..0]" (rect 210 331 267 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[3..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "VGA_G[3..0]" (rect 211 347 267 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[3..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "VGA_B[3..0]" (rect 212 363 267 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 218 379 267 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384)(line_width 1))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 395 267 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 267 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 411 267 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 448)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done
new file mode 100644
index 0000000..fc5804a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.done
@@ -0,0 +1 @@
+Mon Mar 17 10:02:50 2014
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt
new file mode 100644
index 0000000..b7a9f1b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.rpt
@@ -0,0 +1,3610 @@
+Fitter report for DE0_D5M
+Mon Mar 17 10:02:37 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Non-Global High Fan-Out Signals
+ 27. Fitter RAM Summary
+ 28. Routing Usage Summary
+ 29. LAB Logic Elements
+ 30. LAB-wide Signals
+ 31. LAB Signals Sourced
+ 32. LAB Signals Sourced Out
+ 33. LAB Distinct Inputs
+ 34. I/O Rules Summary
+ 35. I/O Rules Details
+ 36. I/O Rules Matrix
+ 37. Fitter Device Options
+ 38. Operating Settings and Conditions
+ 39. Estimated Delay Added for Hold Timing Summary
+ 40. Estimated Delay Added for Hold Timing Details
+ 41. Fitter Messages
+ 42. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Mon Mar 17 10:02:37 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 1,467 / 15,408 ( 10 % )                     ;
+;     Total combinational functions  ; 1,198 / 15,408 ( 8 % )                      ;
+;     Dedicated logic registers      ; 1,030 / 15,408 ( 7 % )                      ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200 / 516,096 ( 10 % )                   ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Use smart compilation                                                      ; On                                    ; Off                                   ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.43        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;  14.3%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------+
+; I/O Assignment Warnings                   ;
++------------------+------------------------+
+; Pin Name         ; Reason                 ;
++------------------+------------------------+
+; DRAM_LDQM        ; Missing drive strength ;
+; DRAM_UDQM        ; Missing drive strength ;
+; DRAM_BA_1        ; Missing drive strength ;
+; DRAM_BA_0        ; Missing drive strength ;
+; DRAM_CAS_N       ; Missing drive strength ;
+; DRAM_CKE         ; Missing drive strength ;
+; DRAM_CS_N        ; Missing drive strength ;
+; DRAM_RAS_N       ; Missing drive strength ;
+; DRAM_WE_N        ; Missing drive strength ;
+; DRAM_CLK         ; Missing drive strength ;
+; VGA_CLK          ; Missing drive strength ;
+; VGA_HS           ; Missing drive strength ;
+; VGA_VS           ; Missing drive strength ;
+; DRAM_ADDR[11]    ; Missing drive strength ;
+; DRAM_ADDR[10]    ; Missing drive strength ;
+; DRAM_ADDR[9]     ; Missing drive strength ;
+; DRAM_ADDR[8]     ; Missing drive strength ;
+; DRAM_ADDR[7]     ; Missing drive strength ;
+; DRAM_ADDR[6]     ; Missing drive strength ;
+; DRAM_ADDR[5]     ; Missing drive strength ;
+; DRAM_ADDR[4]     ; Missing drive strength ;
+; DRAM_ADDR[3]     ; Missing drive strength ;
+; DRAM_ADDR[2]     ; Missing drive strength ;
+; DRAM_ADDR[1]     ; Missing drive strength ;
+; DRAM_ADDR[0]     ; Missing drive strength ;
+; GPIO_1_CLKOUT[1] ; Missing drive strength ;
+; GPIO_1_CLKOUT[0] ; Missing drive strength ;
+; HEX0[6]          ; Missing drive strength ;
+; HEX0[5]          ; Missing drive strength ;
+; HEX0[4]          ; Missing drive strength ;
+; HEX0[3]          ; Missing drive strength ;
+; HEX0[2]          ; Missing drive strength ;
+; HEX0[1]          ; Missing drive strength ;
+; HEX0[0]          ; Missing drive strength ;
+; HEX1[6]          ; Missing drive strength ;
+; HEX1[5]          ; Missing drive strength ;
+; HEX1[4]          ; Missing drive strength ;
+; HEX1[3]          ; Missing drive strength ;
+; HEX1[2]          ; Missing drive strength ;
+; HEX1[1]          ; Missing drive strength ;
+; HEX1[0]          ; Missing drive strength ;
+; HEX2[6]          ; Missing drive strength ;
+; HEX2[5]          ; Missing drive strength ;
+; HEX2[4]          ; Missing drive strength ;
+; HEX2[3]          ; Missing drive strength ;
+; HEX2[2]          ; Missing drive strength ;
+; HEX2[1]          ; Missing drive strength ;
+; HEX2[0]          ; Missing drive strength ;
+; HEX3[6]          ; Missing drive strength ;
+; HEX3[5]          ; Missing drive strength ;
+; HEX3[4]          ; Missing drive strength ;
+; HEX3[3]          ; Missing drive strength ;
+; HEX3[2]          ; Missing drive strength ;
+; HEX3[1]          ; Missing drive strength ;
+; HEX3[0]          ; Missing drive strength ;
+; LEDG[9]          ; Missing drive strength ;
+; LEDG[8]          ; Missing drive strength ;
+; LEDG[7]          ; Missing drive strength ;
+; LEDG[6]          ; Missing drive strength ;
+; LEDG[5]          ; Missing drive strength ;
+; LEDG[4]          ; Missing drive strength ;
+; LEDG[3]          ; Missing drive strength ;
+; LEDG[2]          ; Missing drive strength ;
+; LEDG[1]          ; Missing drive strength ;
+; LEDG[0]          ; Missing drive strength ;
+; VGA_B[3]         ; Missing drive strength ;
+; VGA_B[2]         ; Missing drive strength ;
+; VGA_B[1]         ; Missing drive strength ;
+; VGA_B[0]         ; Missing drive strength ;
+; VGA_G[3]         ; Missing drive strength ;
+; VGA_G[2]         ; Missing drive strength ;
+; VGA_G[1]         ; Missing drive strength ;
+; VGA_G[0]         ; Missing drive strength ;
+; VGA_R[3]         ; Missing drive strength ;
+; VGA_R[2]         ; Missing drive strength ;
+; VGA_R[1]         ; Missing drive strength ;
+; VGA_R[0]         ; Missing drive strength ;
+; DRAM_DQ[15]      ; Missing drive strength ;
+; DRAM_DQ[14]      ; Missing drive strength ;
+; DRAM_DQ[13]      ; Missing drive strength ;
+; DRAM_DQ[12]      ; Missing drive strength ;
+; DRAM_DQ[11]      ; Missing drive strength ;
+; DRAM_DQ[10]      ; Missing drive strength ;
+; DRAM_DQ[9]       ; Missing drive strength ;
+; DRAM_DQ[8]       ; Missing drive strength ;
+; DRAM_DQ[7]       ; Missing drive strength ;
+; DRAM_DQ[6]       ; Missing drive strength ;
+; DRAM_DQ[5]       ; Missing drive strength ;
+; DRAM_DQ[4]       ; Missing drive strength ;
+; DRAM_DQ[3]       ; Missing drive strength ;
+; DRAM_DQ[2]       ; Missing drive strength ;
+; DRAM_DQ[1]       ; Missing drive strength ;
+; DRAM_DQ[0]       ; Missing drive strength ;
+; GPIO_1[31]       ; Missing drive strength ;
+; GPIO_1[30]       ; Missing drive strength ;
+; GPIO_1[29]       ; Missing drive strength ;
+; GPIO_1[28]       ; Missing drive strength ;
+; GPIO_1[27]       ; Missing drive strength ;
+; GPIO_1[26]       ; Missing drive strength ;
+; GPIO_1[25]       ; Missing drive strength ;
+; GPIO_1[24]       ; Missing drive strength ;
+; GPIO_1[23]       ; Missing drive strength ;
+; GPIO_1[22]       ; Missing drive strength ;
+; GPIO_1[21]       ; Missing drive strength ;
+; GPIO_1[20]       ; Missing drive strength ;
+; GPIO_1[19]       ; Missing drive strength ;
+; GPIO_1[18]       ; Missing drive strength ;
+; GPIO_1[17]       ; Missing drive strength ;
+; GPIO_1[16]       ; Missing drive strength ;
+; GPIO_1[15]       ; Missing drive strength ;
+; GPIO_1[14]       ; Missing drive strength ;
+; GPIO_1[13]       ; Missing drive strength ;
+; GPIO_1[12]       ; Missing drive strength ;
+; GPIO_1[11]       ; Missing drive strength ;
+; GPIO_1[10]       ; Missing drive strength ;
+; GPIO_1[9]        ; Missing drive strength ;
+; GPIO_1[8]        ; Missing drive strength ;
+; GPIO_1[7]        ; Missing drive strength ;
+; GPIO_1[6]        ; Missing drive strength ;
+; GPIO_1[5]        ; Missing drive strength ;
+; GPIO_1[4]        ; Missing drive strength ;
+; GPIO_1[3]        ; Missing drive strength ;
+; GPIO_1[2]        ; Missing drive strength ;
+; GPIO_1[1]        ; Missing drive strength ;
+; GPIO_1[0]        ; Missing drive strength ;
++------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                    ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+; Name                ; Ignored Entity ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+; Location            ;                ;              ; CLOCK_50_2      ; PIN_B12       ; QSF Assignment ;
+; Location            ;                ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location            ;                ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location            ;                ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location            ;                ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location            ;                ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; Location            ;                ;              ; PS2_CLK         ; PIN_R21       ; QSF Assignment ;
+; Location            ;                ;              ; PS2_DAT         ; PIN_R22       ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_DATA       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_FVAL       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_CAMERA     ;              ; rCCD_LVAL       ; ON            ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_ADCDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_ADCLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_BCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_DACDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_DACLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; AUD_XCK         ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; BUTTON[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; CLOCK_50_2      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[32]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[33]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[34]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; GPIO_1[35]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX0_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; I2C_SCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; I2C_SDAT        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; KEY[3]          ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_CLK         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_DAT         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_CAMERA     ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
++---------------------+----------------+--------------+-----------------+---------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                      ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Placement (by node) ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 2644 ) ; 0.00 % ( 0 / 2644 )        ; 0.00 % ( 0 / 2644 )      ;
+;     -- Achieved     ; 0.00 % ( 0 / 2644 ) ; 0.00 % ( 0 / 2644 )        ; 0.00 % ( 0 / 2644 )      ;
+;                     ;                     ;                            ;                          ;
+; Routing (by net)    ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+---------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 2633 )   ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 11 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.pin.
+
+
++-------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                           ;
++---------------------------------------------+---------------------------+
+; Resource                                    ; Usage                     ;
++---------------------------------------------+---------------------------+
+; Total logic elements                        ; 1,467 / 15,408 ( 10 % )   ;
+;     -- Combinational with no register       ; 437                       ;
+;     -- Register only                        ; 269                       ;
+;     -- Combinational with a register        ; 761                       ;
+;                                             ;                           ;
+; Logic element usage by number of LUT inputs ;                           ;
+;     -- 4 input functions                    ; 544                       ;
+;     -- 3 input functions                    ; 261                       ;
+;     -- <=2 input functions                  ; 393                       ;
+;     -- Register only                        ; 269                       ;
+;                                             ;                           ;
+; Logic elements by mode                      ;                           ;
+;     -- normal mode                          ; 886                       ;
+;     -- arithmetic mode                      ; 312                       ;
+;                                             ;                           ;
+; Total registers*                            ; 1,030 / 17,068 ( 6 % )    ;
+;     -- Dedicated logic registers            ; 1,030 / 15,408 ( 7 % )    ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )         ;
+;                                             ;                           ;
+; Total LABs:  partially or completely used   ; 123 / 963 ( 13 % )        ;
+; Virtual pins                                ; 0                         ;
+; I/O pins                                    ; 141 / 347 ( 41 % )        ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )            ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )             ;
+;                                             ;                           ;
+; Global signals                              ; 9                         ;
+; M9Ks                                        ; 10 / 56 ( 18 % )          ;
+; Total block memory bits                     ; 53,200 / 516,096 ( 10 % ) ;
+; Total block memory implementation bits      ; 92,160 / 516,096 ( 18 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )           ;
+; PLLs                                        ; 1 / 4 ( 25 % )            ;
+; Global clocks                               ; 9 / 20 ( 45 % )           ;
+; JTAGs                                       ; 0 / 1 ( 0 % )             ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )             ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )             ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )             ;
+; Average interconnect usage (total/H/V)      ; 2% / 2% / 2%              ;
+; Peak interconnect usage (total/H/V)         ; 7% / 7% / 7%              ;
+; Maximum fan-out                             ; 505                       ;
+; Highest non-global fan-out                  ; 53                        ;
+; Total fan-out                               ; 7900                      ;
+; Average fan-out                             ; 2.85                      ;
++---------------------------------------------+---------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 1467 / 15408 ( 10 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 437                   ; 0                              ;
+;     -- Register only                        ; 269                   ; 0                              ;
+;     -- Combinational with a register        ; 761                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 544                   ; 0                              ;
+;     -- 3 input functions                    ; 261                   ; 0                              ;
+;     -- <=2 input functions                  ; 393                   ; 0                              ;
+;     -- Register only                        ; 269                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 886                   ; 0                              ;
+;     -- arithmetic mode                      ; 312                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1030                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1030 / 15408 ( 7 % )  ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 123 / 963 ( 13 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 141                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 53200                 ; 0                              ;
+; Total RAM block bits                        ; 92160                 ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 10 / 56 ( 17 % )      ; 0 / 56 ( 0 % )                 ;
+; Clock control block                         ; 7 / 24 ( 29 % )       ; 2 / 24 ( 8 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 554                   ; 1                              ;
+;     -- Registered Input Connections         ; 505                   ; 0                              ;
+;     -- Output Connections                   ; 49                    ; 506                            ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 7976                  ; 514                            ;
+;     -- Registered Connections               ; 3805                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 96                    ; 507                            ;
+;     -- hard_block:auto_generated_inst       ; 507                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 16                    ; 1                              ;
+;     -- Output Ports                         ; 77                    ; 2                              ;
+;     -- Bidir Ports                          ; 48                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                           ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name            ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLOCK_50        ; G21   ; 6        ; 41           ; 15           ; 0            ; 97                    ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[0] ; AB11  ; 3        ; 21           ; 0            ; 14           ; 254                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[1] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[0]          ; H2    ; 1        ; 0            ; 21           ; 7            ; 35                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[1]          ; G3    ; 1        ; 0            ; 23           ; 14           ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[2]          ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]           ; J6    ; 1        ; 0            ; 24           ; 0            ; 21                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]           ; H5    ; 1        ; 0            ; 27           ; 0            ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]           ; H6    ; 1        ; 0            ; 25           ; 21           ; 8                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]           ; G4    ; 1        ; 0            ; 23           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]           ; G5    ; 1        ; 0            ; 27           ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]           ; J7    ; 1        ; 0            ; 22           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]           ; H7    ; 1        ; 0            ; 25           ; 14           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]           ; E3    ; 1        ; 0            ; 26           ; 7            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]           ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]           ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name             ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DRAM_ADDR[0]     ; C4    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[10]    ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[11]    ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[1]     ; A3    ; 8        ; 3            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[2]     ; B3    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[3]     ; C3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[4]     ; A5    ; 8        ; 7            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[5]     ; C6    ; 8        ; 5            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[6]     ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[7]     ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[8]     ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[9]     ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_0        ; B5    ; 8        ; 7            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_1        ; A4    ; 8        ; 5            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CAS_N       ; G8    ; 8        ; 5            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CKE         ; E6    ; 8        ; 1            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CLK         ; E5    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CS_N        ; G7    ; 8        ; 1            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_LDQM        ; E7    ; 8        ; 3            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_RAS_N       ; F7    ; 8        ; 1            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_UDQM        ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_WE_N        ; D6    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[0] ; R16   ; 4        ; 37           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[1] ; T16   ; 4        ; 37           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[0]          ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[1]          ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[2]          ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[3]          ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[4]          ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[5]          ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[6]          ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[0]          ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[1]          ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[2]          ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[3]          ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[4]          ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[5]          ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[6]          ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[0]          ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[1]          ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[2]          ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[3]          ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[4]          ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[5]          ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[6]          ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[0]          ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[1]          ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[2]          ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[3]          ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[4]          ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[5]          ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[6]          ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]          ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]          ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]          ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]          ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]          ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]          ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]          ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]          ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]          ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]          ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[0]         ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]         ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]         ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]         ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK          ; U14   ; 4        ; 39           ; 0            ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]         ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]         ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]         ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]         ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS           ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]         ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]         ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]         ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]         ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_VS           ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                               ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; DRAM_DQ[0]  ; D10   ; 8        ; 16           ; 29           ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[10] ; A9    ; 8        ; 16           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[11] ; C10   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[12] ; B10   ; 8        ; 16           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[13] ; A10   ; 8        ; 16           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[14] ; E10   ; 8        ; 16           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[15] ; F10   ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[1]  ; G10   ; 8        ; 9            ; 29           ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[2]  ; H10   ; 8        ; 9            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[3]  ; E9    ; 8        ; 11           ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[4]  ; F9    ; 8        ; 7            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[5]  ; G9    ; 8        ; 9            ; 29           ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[6]  ; H9    ; 8        ; 7            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[7]  ; F8    ; 8        ; 5            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[8]  ; A8    ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[9]  ; B9    ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; GPIO_1[0]   ; AA20  ; 4        ; 37           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[10]  ; U15   ; 4        ; 39           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[11]  ; T15   ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[12]  ; W15   ; 4        ; 32           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[13]  ; V15   ; 4        ; 32           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[14]  ; AB9   ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[15]  ; AA9   ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[16]  ; AA7   ; 3        ; 11           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[17]  ; AB7   ; 3        ; 11           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[18]  ; T14   ; 4        ; 32           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[19]  ; R14   ; 4        ; 39           ; 0            ; 14           ; 4                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO               ; -                   ;
+; GPIO_1[1]   ; AB20  ; 4        ; 37           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[20]  ; U12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[21]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[22]  ; R11   ; 3        ; 3            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[23]  ; R12   ; 3        ; 5            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[24]  ; U10   ; 3        ; 14           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[25]  ; T10   ; 3        ; 14           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[26]  ; U9    ; 3        ; 9            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[27]  ; T9    ; 3        ; 1            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[28]  ; Y7    ; 3        ; 9            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[29]  ; U8    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[2]   ; AA19  ; 4        ; 35           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[30]  ; V6    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[31]  ; V7    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[3]   ; AB19  ; 4        ; 35           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[4]   ; AB18  ; 4        ; 32           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[5]   ; AA18  ; 4        ; 35           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[6]   ; AA17  ; 4        ; 28           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[7]   ; AB17  ; 4        ; 28           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[8]   ; Y17   ; 4        ; 35           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[9]   ; W17   ; 4        ; 35           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                       ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                       ; Use as regular IO        ; HEX3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                       ; Use as regular IO        ; HEX2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                       ; Use as regular IO        ; HEX2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                       ; Use as regular IO        ; HEX1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; HEX0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; HEX1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; HEX1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; HEX1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; HEX1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; HEX1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; HEX1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; HEX0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; HEX0[1]                 ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; DRAM_DQ[12]             ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; DRAM_DQ[10]             ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; DRAM_DQ[9]              ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; DRAM_DQ[8]              ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; DRAM_UDQM               ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO        ; DRAM_ADDR[11]           ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO        ; DRAM_ADDR[9]            ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T10n, PADD19                      ; Use as regular IO        ; DRAM_ADDR[7]            ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T10p, DATA15                      ; Use as regular IO        ; DRAM_ADDR[6]            ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                       ; Use as regular IO        ; DRAM_ADDR[8]            ; Dual Purpose Pin          ;
+; A5       ; DATA5                                    ; Use as regular IO        ; DRAM_ADDR[4]            ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T6p, DATA6                        ; Use as regular IO        ; DRAM_DQ[15]             ; Dual Purpose Pin          ;
+; C6       ; DATA7                                    ; Use as regular IO        ; DRAM_ADDR[5]            ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; DRAM_ADDR[10]           ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T4n, DATA9                        ; Use as regular IO        ; DRAM_DQ[7]              ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T3n, DATA10                       ; Use as regular IO        ; DRAM_ADDR[1]            ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T3p, DATA11                       ; Use as regular IO        ; DRAM_ADDR[2]            ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO        ; DRAM_ADDR[0]            ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 3.3V          ; --           ;
+; 3        ; 16 / 46 ( 35 % ) ; 3.3V          ; --           ;
+; 4        ; 21 / 41 ( 51 % ) ; 3.3V          ; --           ;
+; 5        ; 0 / 46 ( 0 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 28 / 47 ( 60 % ) ; 3.3V          ; --           ;
+; 8        ; 38 / 43 ( 88 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; DRAM_ADDR[1]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 350        ; 8        ; DRAM_BA_1                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 345        ; 8        ; DRAM_ADDR[4]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 336        ; 8        ; DRAM_ADDR[7]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; DRAM_ADDR[11]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 332        ; 8        ; DRAM_DQ[8]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; DRAM_DQ[10]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; DRAM_DQ[13]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; HEX1[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; HEX1[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; HEX1[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; HEX2[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; HEX2[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; HEX3[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; GPIO_1[16]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; GPIO_1[15]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GPIO_1_CLKIN[1]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; GPIO_1[6]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; GPIO_1[5]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 164        ; 4        ; GPIO_1[2]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 169        ; 4        ; GPIO_1[0]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; GPIO_1[17]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; GPIO_1[14]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GPIO_1_CLKIN[0]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; GPIO_1[7]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; GPIO_1[4]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 165        ; 4        ; GPIO_1[3]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 170        ; 4        ; GPIO_1[1]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; DRAM_ADDR[2]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 351        ; 8        ; DRAM_ADDR[10]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; DRAM_BA_0                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 337        ; 8        ; DRAM_ADDR[6]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; DRAM_ADDR[9]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 333        ; 8        ; DRAM_UDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; DRAM_DQ[9]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; DRAM_DQ[12]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; HEX1[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; HEX1[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; HEX2[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; HEX2[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; HEX3[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; HEX3[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; DRAM_ADDR[3]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 359        ; 8        ; DRAM_ADDR[0]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; DRAM_ADDR[5]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 340        ; 8        ; DRAM_ADDR[8]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; DRAM_DQ[11]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; HEX1[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; HEX3[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; DRAM_WE_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; DRAM_DQ[0]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; HEX2[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; HEX3[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; DRAM_CLK                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 362        ; 8        ; DRAM_CKE                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 357        ; 8        ; DRAM_LDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; DRAM_DQ[3]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; DRAM_DQ[14]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; HEX0[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; HEX1[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; HEX2[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; KEY[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; DRAM_RAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 352        ; 8        ; DRAM_DQ[7]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 347        ; 8        ; DRAM_DQ[4]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 348        ; 8        ; DRAM_DQ[15]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 318        ; 7        ; HEX0[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; HEX2[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; HEX3[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; KEY[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; DRAM_CS_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 353        ; 8        ; DRAM_CAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 342        ; 8        ; DRAM_DQ[5]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 341        ; 8        ; DRAM_DQ[1]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; HEX3[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; KEY[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; DRAM_DQ[6]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H10      ; 343        ; 8        ; DRAM_DQ[2]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P22      ; 210        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; GPIO_1[22]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 98         ; 3        ; GPIO_1[23]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; GPIO_1[19]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; GPIO_1_CLKOUT[0]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; GPIO_1[27]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 121        ; 3        ; GPIO_1[25]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; GPIO_1[21]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; GPIO_1[18]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 161        ; 4        ; GPIO_1[11]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ; 171        ; 4        ; GPIO_1_CLKOUT[1]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; GPIO_1[29]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 112        ; 3        ; GPIO_1[26]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 122        ; 3        ; GPIO_1[24]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; GPIO_1[20]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; VGA_CLK                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
+; U15      ; 173        ; 4        ; GPIO_1[10]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; GPIO_1[30]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 105        ; 3        ; GPIO_1[31]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V15      ; 158        ; 4        ; GPIO_1[13]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; GPIO_1[12]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; GPIO_1[9]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; GPIO_1[28]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; GPIO_1[8]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                       ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; Name                          ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; SDC pin name                  ; inst|u6|altpll_component|auto_generated|pll1                                      ;
+; PLL mode                      ; Normal                                                                            ;
+; Compensate clock              ; clock0                                                                            ;
+; Compensated input/output pins ; --                                                                                ;
+; Switchover type               ; --                                                                                ;
+; Input frequency 0             ; 50.0 MHz                                                                          ;
+; Input frequency 1             ; --                                                                                ;
+; Nominal PFD frequency         ; 25.0 MHz                                                                          ;
+; Nominal VCO frequency         ; 625.0 MHz                                                                         ;
+; VCO post scale K counter      ; 2                                                                                 ;
+; VCO frequency control         ; Auto                                                                              ;
+; VCO phase shift step          ; 200 ps                                                                            ;
+; VCO multiply                  ; --                                                                                ;
+; VCO divide                    ; --                                                                                ;
+; Freq min lock                 ; 24.0 MHz                                                                          ;
+; Freq max lock                 ; 52.02 MHz                                                                         ;
+; M VCO Tap                     ; 5                                                                                 ;
+; M Initial                     ; 2                                                                                 ;
+; M value                       ; 25                                                                                ;
+; N value                       ; 2                                                                                 ;
+; Charge pump current           ; setting 1                                                                         ;
+; Loop filter resistance        ; setting 24                                                                        ;
+; Loop filter capacitance       ; setting 0                                                                         ;
+; Bandwidth                     ; 450 kHz to 980 kHz                                                                ;
+; Bandwidth type                ; Medium                                                                            ;
+; Real time reconfigurable      ; Off                                                                               ;
+; Scan chain MIF file           ; --                                                                                ;
+; Preserve PLL counter order    ; Off                                                                               ;
+; PLL location                  ; PLL_2                                                                             ;
+; Inclk0 signal                 ; CLOCK_50                                                                          ;
+; Inclk1 signal                 ; --                                                                                ;
+; Inclk0 signal type            ; Dedicated Pin                                                                     ;
+; Inclk1 signal type            ; --                                                                                ;
++-------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                             ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                        ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0       ; 5    ; 2   ; 125.0 MHz        ; 0 (0 ps)        ; 9.00 (200 ps)    ; 50/50      ; C0      ; 5             ; 3/2 Odd    ; --            ; 2       ; 5       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1       ; 5    ; 2   ; 125.0 MHz        ; -117 (-2600 ps) ; 9.00 (200 ps)    ; 50/50      ; C1      ; 5             ; 3/2 Odd    ; --            ; 1       ; 0       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                          ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                        ; Library Name ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_CAMERA                                         ; 1467 (2)    ; 1030 (0)                  ; 0 (0)         ; 53200       ; 10   ; 0            ; 0       ; 0         ; 141  ; 0            ; 437 (2)      ; 269 (0)           ; 761 (0)          ; |TOP_CAMERA                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                   ; 1465 (15)   ; 1030 (15)                 ; 0 (0)         ; 53200       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 435 (0)      ; 269 (14)          ; 761 (1)          ; |TOP_CAMERA|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                              ; 68 (68)     ; 58 (58)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 10 (10)      ; 2 (2)             ; 56 (56)          ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                           ; 252 (173)   ; 132 (94)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 120 (79)     ; 15 (5)            ; 117 (89)         ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                        ; 79 (79)     ; 38 (38)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 41 (41)      ; 10 (10)           ; 28 (28)          ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                  ; 93 (77)     ; 66 (55)                   ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 27 (22)      ; 9 (9)             ; 57 (46)          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                           ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component| ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|      ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                  ; 16 (13)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 11 (11)          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|               ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                              ; 50 (50)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 35 (35)          ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |SEG7_LUT_8:u5|                               ; 28 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 28 (0)       ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5                                                                                                                                     ; work         ;
+;          |SEG7_LUT:u0|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                         ; work         ;
+;          |SEG7_LUT:u1|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                         ; work         ;
+;          |SEG7_LUT:u2|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                         ; work         ;
+;          |SEG7_LUT:u3|                              ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                         ; work         ;
+;       |Sdram_Control_4Port:u7|                      ; 897 (228)   ; 697 (130)                 ; 0 (0)         ; 22528       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 200 (92)     ; 229 (16)          ; 468 (120)        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                    ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 47 (0)            ; 69 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 129 (35)    ; 116 (30)                  ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (1)       ; 47 (15)           ; 69 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 4 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 4096        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                    ; 135 (0)     ; 116 (0)                   ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (0)       ; 53 (0)            ; 63 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 135 (0)     ; 116 (0)                   ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (0)       ; 53 (0)            ; 63 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 135 (40)    ; 116 (30)                  ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 19 (7)       ; 53 (19)           ; 63 (8)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (0)            ; 3 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 17 (17)           ; 3 (3)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 2048        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                   ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 39 (0)            ; 77 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 129 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (0)       ; 39 (0)            ; 77 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 129 (40)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 13 (3)       ; 39 (16)           ; 77 (13)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 1 (1)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (0)             ; 12 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 8 (8)             ; 12 (12)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                   ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (0)       ; 57 (0)            ; 59 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 141 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (0)       ; 57 (0)            ; 59 (0)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 141 (42)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 25 (10)      ; 57 (24)           ; 59 (5)           ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 1 (1)             ; 14 (14)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 16 (16)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (0)            ; 4 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 16 (16)           ; 4 (4)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                         ; 63 (63)     ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 3 (3)             ; 46 (46)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|               ; 79 (79)     ; 55 (55)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (24)      ; 14 (14)           ; 41 (41)          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                           ; 62 (62)     ; 27 (27)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 35 (35)      ; 0 (0)             ; 27 (27)          ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                  ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|            ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
++-----------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                              ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name             ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; DRAM_LDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[7]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[6]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[5]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[4]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[3]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_UDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_1        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_0        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CKE         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CS_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_RAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_WE_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CLK         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_CLK          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[15]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[14]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[13]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[12]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[11]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[10]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[9]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[8]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[7]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[6]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[5]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[4]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[3]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[2]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[1]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[0]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[31]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[30]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[29]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[28]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[27]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[26]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[25]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[24]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[23]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[22]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[21]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[20]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[19]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[18]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[17]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[16]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[15]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[14]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[13]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[12]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[11]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[10]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[9]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[8]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[7]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[6]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[5]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[4]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[3]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[2]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[1]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[0]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; CLOCK_50         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[0]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; KEY[2]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; KEY[1]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[2]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[1]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[0]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                    ;
++---------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                 ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------+-------------------+---------+
+; GPIO_1_CLKIN[1]                                                     ;                   ;         ;
+; SW[9]                                                               ;                   ;         ;
+; SW[8]                                                               ;                   ;         ;
+; SW[7]                                                               ;                   ;         ;
+; SW[6]                                                               ;                   ;         ;
+; SW[5]                                                               ;                   ;         ;
+; SW[4]                                                               ;                   ;         ;
+; SW[3]                                                               ;                   ;         ;
+; DRAM_DQ[15]                                                         ;                   ;         ;
+; DRAM_DQ[14]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]~feeder      ; 1                 ; 6       ;
+; DRAM_DQ[13]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder      ; 0                 ; 6       ;
+; DRAM_DQ[12]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]~feeder      ; 1                 ; 6       ;
+; DRAM_DQ[11]                                                         ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder      ; 0                 ; 6       ;
+; DRAM_DQ[10]                                                         ;                   ;         ;
+; DRAM_DQ[9]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]~feeder       ; 1                 ; 6       ;
+; DRAM_DQ[8]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]              ; 0                 ; 6       ;
+; DRAM_DQ[7]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]~feeder       ; 1                 ; 6       ;
+; DRAM_DQ[6]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]              ; 0                 ; 6       ;
+; DRAM_DQ[5]                                                          ;                   ;         ;
+; DRAM_DQ[4]                                                          ;                   ;         ;
+; DRAM_DQ[3]                                                          ;                   ;         ;
+; DRAM_DQ[2]                                                          ;                   ;         ;
+; DRAM_DQ[1]                                                          ;                   ;         ;
+; DRAM_DQ[0]                                                          ;                   ;         ;
+; GPIO_1[31]                                                          ;                   ;         ;
+; GPIO_1[30]                                                          ;                   ;         ;
+; GPIO_1[29]                                                          ;                   ;         ;
+; GPIO_1[28]                                                          ;                   ;         ;
+; GPIO_1[27]                                                          ;                   ;         ;
+; GPIO_1[26]                                                          ;                   ;         ;
+; GPIO_1[25]                                                          ;                   ;         ;
+; GPIO_1[24]                                                          ;                   ;         ;
+; GPIO_1[23]                                                          ;                   ;         ;
+; GPIO_1[22]                                                          ;                   ;         ;
+; GPIO_1[21]                                                          ;                   ;         ;
+; GPIO_1[20]                                                          ;                   ;         ;
+; GPIO_1[19]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9      ; 1                 ; 6       ;
+; GPIO_1[18]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_FVAL                                       ; 1                 ; 6       ;
+; GPIO_1[17]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_LVAL                                       ; 1                 ; 6       ;
+; GPIO_1[16]                                                          ;                   ;         ;
+; GPIO_1[15]                                                          ;                   ;         ;
+; GPIO_1[14]                                                          ;                   ;         ;
+; GPIO_1[13]                                                          ;                   ;         ;
+; GPIO_1[12]                                                          ;                   ;         ;
+; GPIO_1[11]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[0]                                    ; 0                 ; 6       ;
+; GPIO_1[10]                                                          ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[1]~feeder                             ; 1                 ; 6       ;
+; GPIO_1[9]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[2]~feeder                             ; 1                 ; 6       ;
+; GPIO_1[8]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[3]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[7]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[4]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[6]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[5]                                    ; 0                 ; 6       ;
+; GPIO_1[5]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[6]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[4]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[7]                                    ; 1                 ; 6       ;
+; GPIO_1[3]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[8]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[2]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[9]~feeder                             ; 0                 ; 6       ;
+; GPIO_1[1]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[10]                                   ; 1                 ; 6       ;
+; GPIO_1[0]                                                           ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[11]~feeder                            ; 0                 ; 6       ;
+; CLOCK_50                                                            ;                   ;         ;
+; GPIO_1_CLKIN[0]                                                     ;                   ;         ;
+; KEY[0]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_2                           ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_0                           ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[0]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[1]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[2]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[3]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[4]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[5]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[6]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[7]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[8]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[9]                          ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[10]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[11]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[12]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[13]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[14]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[15]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[16]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[17]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[18]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[19]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[20]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[21]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[22]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[23]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[24]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[25]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[26]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[27]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[28]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[29]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[30]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[31]                         ; 0                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_1                           ; 0                 ; 6       ;
+; KEY[2]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                         ; 1                 ; 6       ;
+; KEY[1]                                                              ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                         ; 0                 ; 6       ;
+; SW[2]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~3                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~0                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                       ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~15                      ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                      ; 0                 ; 6       ;
+; SW[1]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]~feeder ; 0                 ; 6       ;
+; SW[0]                                                               ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]           ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17         ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~25        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~28        ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46         ; 1                 ; 6       ;
+;      - SW[0]~_wirecell                                              ; 1                 ; 6       ;
++---------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                  ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 4       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 94      ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~40                                                                                             ; LCCOMB_X1_Y23_N4   ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~41                                                                                             ; LCCOMB_X1_Y23_N2   ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]~30                                                                                              ; LCCOMB_X1_Y23_N26  ; 10      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|always2~0                                                                                                 ; LCCOMB_X21_Y23_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                 ; FF_X21_Y23_N7      ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                     ; LCCOMB_X17_Y12_N0  ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                             ; LCCOMB_X15_Y13_N18 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]~1                                                                      ; LCCOMB_X14_Y13_N20 ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                           ; FF_X11_Y13_N21     ; 36      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                           ; FF_X11_Y13_N25     ; 35      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                         ; LCCOMB_X11_Y13_N14 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                            ; LCCOMB_X16_Y14_N24 ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                            ; LCCOMB_X11_Y13_N2  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; LCCOMB_X15_Y11_N4  ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                              ; LCCOMB_X15_Y11_N8  ; 43      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                 ; FF_X15_Y11_N17     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                          ; FF_X12_Y14_N17     ; 72      ; Clock                      ; yes    ; Global Clock         ; GCLK4            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                        ; LCCOMB_X15_Y13_N24 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~31                                                                                 ; LCCOMB_X11_Y11_N16 ; 14      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X20_Y13_N26 ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]~36                                                                                                  ; LCCOMB_X16_Y15_N4  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                 ; LCCOMB_X14_Y24_N0  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; FF_X19_Y26_N1      ; 468     ; Async. clear               ; yes    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; FF_X14_Y24_N21     ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK17           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; FF_X14_Y24_N9      ; 128     ; Async. clear               ; yes    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]~0                                                                                          ; LCCOMB_X19_Y26_N16 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                     ; LCCOMB_X19_Y26_N6  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                      ; LCCOMB_X19_Y23_N8  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y22_N0  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X26_Y23_N8  ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X26_Y17_N8  ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X22_Y17_N28 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X14_Y20_N16 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X10_Y19_N14 ; 18      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X14_Y17_N30 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X14_Y18_N12 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]~2                                                                                      ; LCCOMB_X19_Y23_N18 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                               ; FF_X15_Y27_N11     ; 16      ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~1                                                                    ; LCCOMB_X17_Y27_N0  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                               ; FF_X17_Y23_N25     ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                            ; LCCOMB_X17_Y23_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                              ; LCCOMB_X19_Y27_N4  ; 16      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~45                                                                                  ; LCCOMB_X20_Y23_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46                                                                                  ; LCCOMB_X19_Y23_N4  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46                                                                                  ; LCCOMB_X17_Y26_N0  ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47                                                                                  ; LCCOMB_X19_Y26_N26 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~45                                                                                  ; LCCOMB_X21_Y26_N0  ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46                                                                                  ; LCCOMB_X19_Y26_N12 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46                                                                                  ; LCCOMB_X24_Y26_N30 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47                                                                                  ; LCCOMB_X19_Y26_N30 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                               ; LCCOMB_X39_Y18_N14 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                            ; LCCOMB_X38_Y18_N2  ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                            ; LCCOMB_X40_Y18_N30 ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                                                                  ; FF_X40_Y15_N23     ; 117     ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0]                                                   ; PLL_2              ; 505     ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                                                                       ; PIN_AB11           ; 254     ; Clock                      ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; KEY[0]                                                                                                                                ; PIN_H2             ; 35      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                 ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                ; Location       ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                            ; PIN_G21        ; 94      ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                        ; FF_X12_Y14_N17 ; 72      ; 0                                    ; Global Clock         ; GCLK4            ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                  ; FF_X19_Y26_N1  ; 468     ; 0                                    ; Global Clock         ; GCLK12           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                  ; FF_X14_Y24_N21 ; 55      ; 0                                    ; Global Clock         ; GCLK17           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                  ; FF_X14_Y24_N9  ; 128     ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                ; FF_X40_Y15_N23 ; 117     ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2          ; 505     ; 283                                  ; Global Clock         ; GCLK8            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2          ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                     ; PIN_AB11       ; 254     ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
++-------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                                                                      ; Fan-Out ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; ~GND                                                                                                                                                                      ; 53      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                                                                  ; 43      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1]                                                                                                                               ; 37      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                                                               ; 36      ;
+; KEY[0]~input                                                                                                                                                              ; 35      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]                                                                                                                               ; 35      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                                                               ; 35      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                                                     ; 32      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3]                                                                                                                               ; 32      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; 31      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                                                     ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                                                                   ; 26      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                                                            ; 24      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                                                                 ; 24      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0                                                                                                                                 ; 23      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]~0                                                                                                                           ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                                            ; 22      ;
+; SW[0]~input                                                                                                                                                               ; 21      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada                                                                                                             ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                                            ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]                                                                                                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0                                                                                                                              ; 18      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; 18      ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                                                         ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                                                                ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                                            ; 17      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                                                                   ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~41                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]~40                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                                                                ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                                                         ; 15      ;
+; DE0_D5M:inst|CCD_Capture:u3|always2~0                                                                                                                                     ; 15      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                                                                  ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~31                                                                                                                     ; 14      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~0                                                                                                                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10]                             ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0]                              ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                                            ; 13      ;
+; DE0_D5M:inst|rCCD_LVAL                                                                                                                                                    ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                                                                   ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|always0~1                                                                                                                                  ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                                                                ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                                            ; 12      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1                                                                                                            ; 12      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                                                                ; 12      ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0                                                                                                                                   ; 12      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual                                     ; 11      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6]                                                                                                            ; 11      ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]~36                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5                                                                                                            ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~2                                                                                                                               ; 10      ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                                                        ; 10      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]~30                                                                                                                                  ; 10      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO                                                                                                                                    ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0                                                                                                                               ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[0]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; 9       ;
+; SW[2]~input                                                                                                                                                               ; 8       ;
+; SW[0]~_wirecell                                                                                                                                                           ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~3                                                                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[15]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[14]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[13]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[12]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[11]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[10]                                                                                                                                ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[9]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[8]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[7]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[6]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[5]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[4]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[3]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[2]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[1]                                                                                                                                 ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9]                                                                                              ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~4                                                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                                                                ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]~1                                                                                                          ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0                                                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2]                                                                                              ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15]                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14]                                                                                             ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]~2                                                                                                                            ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                               ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1                                                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8]                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6]                                                                                              ; 5       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                                                      ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7]                                                                                                                                  ; 5       ;
+; GPIO_1[19]~input                                                                                                                                                          ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~3                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~2                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010                                                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~1                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~9                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mSTART                                                                                                                                        ; 4       ;
+; DE0_D5M:inst|rCCD_FVAL                                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20]                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13]                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5]                                                                                                                                  ; 4       ;
+; CLOCK_50~input                                                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~11                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]~0                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDVAL                                                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]~2                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~7                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ; 3       ;
+; DE0_D5M:inst|CCD_Capture:u3|Pre_FVAL                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2                                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~0                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|rClk[0]                                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                                                                                                                        ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1]                             ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0]                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1]                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2]                                                                                                                                  ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10]                                                                                                                                 ; 3       ;
+; SW[1]~input                                                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~1                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~0                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000                                                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1                                                                                                                 ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~4                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~1                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16                                                                                                                  ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~4                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~3                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal7~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|LessThan2~0                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N~0                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal4~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~14                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal2~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~1                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oRequest                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~1                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM~0                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~1                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_V_SYNC                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[13]                            ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[12]                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[12]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[11]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[10]                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                                                                                                                                       ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[10]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[9]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[14]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[13]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[11]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0]                                                                                                                                  ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4]                                                                                                                                  ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[9]                                                                                                                                     ; 2       ;
+; KEY[1]~input                                                                                                                                                              ; 1       ;
+; KEY[2]~input                                                                                                                                                              ; 1       ;
+; GPIO_1[0]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[1]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[2]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[3]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[4]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[5]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[6]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[7]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[8]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[9]~input                                                                                                                                                           ; 1       ;
+; GPIO_1[10]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[11]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[17]~input                                                                                                                                                          ; 1       ;
+; GPIO_1[18]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[6]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[7]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[8]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[9]~input                                                                                                                                                          ; 1       ;
+; DRAM_DQ[11]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[12]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[13]~input                                                                                                                                                         ; 1       ;
+; DRAM_DQ[14]~input                                                                                                                                                         ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell            ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell            ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0~_wirecell             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]~0                                                 ; 1       ;
+; DE0_D5M:inst|rClk[0]~0                                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux6~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux6~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux5~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux5~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~16                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~15                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~6                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~10                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~4                                                                                                                   ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~9                                                                                                      ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~3                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~4                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~7                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~6                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Selector0~2                                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Selector1~2                                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH~2                                                                                                  ; 1       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0~2                                                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read~3                                                                                                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~8                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~7                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~6                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~6                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~5                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~5                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                     ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~6                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~6                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~4                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~4                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46                                                                                                                      ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~30                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~1                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~29                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~28                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~27                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~0                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~26                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~25                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Selector1~0                                                                                                                                ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector3~0                                                                                                              ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~0                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~2                                                                                                                   ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~11                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[0]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~10                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[1]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~9                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[2]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~8                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[3]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~7                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[4]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~6                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[5]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~5                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[6]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~4                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[7]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~3                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[8]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~2                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[9]                                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~1                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[10]                                                                                                                                                ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~2            ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~1            ; 1       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4|aneb_result_wire[0]~0            ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA~0                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|rCCD_DATA[11]                                                                                                                                                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~9                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~9                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~8                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~5                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift~3                                                                                                           ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay~3                                                                                                      ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux3~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux2~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux2~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux0~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux21~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~14                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux21~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux19~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux20~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~13                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~12                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~11                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux17~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~10                                                                                                                                   ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux17~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~9                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux9~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~8                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux4~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux4~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux11~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux11~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~4                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux14~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~2                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux7~0                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~5                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~1                                                                                                                                     ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~3                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~2                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~1                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux15~0                                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]~8                                                                                                                             ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Selector2~0                                                                                                                                ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~12                                                                                                                               ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END~0                                                                                                                    ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector0~2                                                                                                              ; 1       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Selector0~1                                                                                                              ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[0]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[1]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[2]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[3]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[4]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[5]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[6]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[7]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[8]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[9]                                                                                                                                  ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[10]                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_DATA[11]                                                                                                                                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~4                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1~0                    ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~0                             ; 1       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~7                             ; 1       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; Name                                                                                                                                              ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size  ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278         ; 24           ; 1278         ; 24           ; yes                    ; no                      ; yes                    ; yes                     ; 30672 ; 1278                        ; 24                          ; 1278                        ; 24                          ; 30672               ; 6    ; None ; M9K_X25_Y13_N0, M9K_X25_Y12_N0, M9K_X25_Y11_N0, M9K_X13_Y13_N0, M9K_X13_Y12_N0, M9K_X13_Y11_N0 ; Old data             ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 8                           ; 512                         ; 8                           ; 4096                ; 1    ; None ; M9K_X25_Y23_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 4                           ; 512                         ; 4                           ; 2048                ; 1    ; None ; M9K_X25_Y17_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y20_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192  ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y17_N0                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 1,681 / 47,787 ( 4 % ) ;
+; C16 interconnects     ; 32 / 1,804 ( 2 % )     ;
+; C4 interconnects      ; 699 / 31,272 ( 2 % )   ;
+; Direct links          ; 381 / 47,787 ( < 1 % ) ;
+; Global clocks         ; 9 / 20 ( 45 % )        ;
+; Local interconnects   ; 926 / 15,408 ( 6 % )   ;
+; R24 interconnects     ; 37 / 1,775 ( 2 % )     ;
+; R4 interconnects      ; 1,028 / 41,310 ( 2 % ) ;
++-----------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 11.93) ; Number of LABs  (Total = 123) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 12                            ;
+; 2                                           ; 2                             ;
+; 3                                           ; 1                             ;
+; 4                                           ; 5                             ;
+; 5                                           ; 2                             ;
+; 6                                           ; 5                             ;
+; 7                                           ; 7                             ;
+; 8                                           ; 1                             ;
+; 9                                           ; 1                             ;
+; 10                                          ; 1                             ;
+; 11                                          ; 0                             ;
+; 12                                          ; 4                             ;
+; 13                                          ; 4                             ;
+; 14                                          ; 13                            ;
+; 15                                          ; 10                            ;
+; 16                                          ; 55                            ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.85) ; Number of LABs  (Total = 123) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 72                            ;
+; 1 Clock                            ; 100                           ;
+; 1 Clock enable                     ; 37                            ;
+; 1 Sync. clear                      ; 5                             ;
+; 1 Sync. load                       ; 2                             ;
+; 2 Clock enables                    ; 1                             ;
+; 2 Clocks                           ; 11                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 19.33) ; Number of LABs  (Total = 123) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 7                             ;
+; 2                                            ; 5                             ;
+; 3                                            ; 3                             ;
+; 4                                            ; 1                             ;
+; 5                                            ; 1                             ;
+; 6                                            ; 1                             ;
+; 7                                            ; 7                             ;
+; 8                                            ; 2                             ;
+; 9                                            ; 0                             ;
+; 10                                           ; 3                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 1                             ;
+; 13                                           ; 0                             ;
+; 14                                           ; 1                             ;
+; 15                                           ; 3                             ;
+; 16                                           ; 1                             ;
+; 17                                           ; 8                             ;
+; 18                                           ; 4                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 4                             ;
+; 21                                           ; 8                             ;
+; 22                                           ; 4                             ;
+; 23                                           ; 2                             ;
+; 24                                           ; 5                             ;
+; 25                                           ; 3                             ;
+; 26                                           ; 4                             ;
+; 27                                           ; 7                             ;
+; 28                                           ; 5                             ;
+; 29                                           ; 6                             ;
+; 30                                           ; 8                             ;
+; 31                                           ; 9                             ;
+; 32                                           ; 6                             ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 7.69) ; Number of LABs  (Total = 123) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 0                             ;
+; 1                                               ; 21                            ;
+; 2                                               ; 6                             ;
+; 3                                               ; 5                             ;
+; 4                                               ; 4                             ;
+; 5                                               ; 6                             ;
+; 6                                               ; 8                             ;
+; 7                                               ; 13                            ;
+; 8                                               ; 8                             ;
+; 9                                               ; 9                             ;
+; 10                                              ; 7                             ;
+; 11                                              ; 6                             ;
+; 12                                              ; 3                             ;
+; 13                                              ; 10                            ;
+; 14                                              ; 3                             ;
+; 15                                              ; 6                             ;
+; 16                                              ; 7                             ;
+; 17                                              ; 0                             ;
+; 18                                              ; 0                             ;
+; 19                                              ; 0                             ;
+; 20                                              ; 0                             ;
+; 21                                              ; 0                             ;
+; 22                                              ; 1                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 11.10) ; Number of LABs  (Total = 123) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 1                             ;
+; 2                                            ; 5                             ;
+; 3                                            ; 6                             ;
+; 4                                            ; 20                            ;
+; 5                                            ; 7                             ;
+; 6                                            ; 6                             ;
+; 7                                            ; 4                             ;
+; 8                                            ; 8                             ;
+; 9                                            ; 5                             ;
+; 10                                           ; 7                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 8                             ;
+; 13                                           ; 7                             ;
+; 14                                           ; 5                             ;
+; 15                                           ; 4                             ;
+; 16                                           ; 2                             ;
+; 17                                           ; 2                             ;
+; 18                                           ; 6                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 0                             ;
+; 21                                           ; 1                             ;
+; 22                                           ; 0                             ;
+; 23                                           ; 1                             ;
+; 24                                           ; 2                             ;
+; 25                                           ; 5                             ;
+; 26                                           ; 1                             ;
+; 27                                           ; 1                             ;
+; 28                                           ; 0                             ;
+; 29                                           ; 0                             ;
+; 30                                           ; 0                             ;
+; 31                                           ; 1                             ;
+; 32                                           ; 2                             ;
+; 33                                           ; 1                             ;
+; 34                                           ; 0                             ;
+; 35                                           ; 0                             ;
+; 36                                           ; 0                             ;
+; 37                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 140          ; 0            ; 140          ; 0            ; 0            ; 141       ; 140          ; 0            ; 141       ; 141       ; 0            ; 0            ; 0            ; 0            ; 64           ; 0            ; 0            ; 64           ; 0            ; 0            ; 29           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 141       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 1            ; 141          ; 1            ; 141          ; 141          ; 0         ; 1            ; 141          ; 0         ; 0         ; 141          ; 141          ; 141          ; 141          ; 77           ; 141          ; 141          ; 77           ; 141          ; 141          ; 112          ; 141          ; 141          ; 141          ; 141          ; 141          ; 141          ; 0         ; 141          ; 141          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DRAM_LDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[1]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_UDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_1          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_0          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CKE           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CS_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_RAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_WE_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CLK           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[11]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[10]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[9]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[8]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[7]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[6]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[5]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[4]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[3]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[2]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[1]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[0]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[1]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[0]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[15]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[14]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[13]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[12]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[11]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[10]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[9]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[8]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[7]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[6]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[5]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[4]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[3]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[2]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[1]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[0]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[31]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[30]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[29]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[28]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[27]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[26]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[25]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[24]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[23]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[22]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[21]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[20]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[19]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[18]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[17]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[16]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[15]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[14]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[13]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[12]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[11]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[10]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[9]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[8]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[7]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[0]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                                                 ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; Source Clock(s)                                     ; Destination Clock(s)                                ; Delay Added in ns ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.5               ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                     ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                      ; Destination Register                                                                                                                                                   ; Delay Added in ns ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.207             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a9~porta_address_reg0 ; 0.098             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                   ; 0.016             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]              ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                   ; 0.013             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                    ; 0.012             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]              ; 0.011             ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 12 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 141 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 3 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1]
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]~0
+        Info (176357): Destination node GPIO_1_CLKOUT[0]~output
+        Info (176357): Destination node VGA_CLK~output
+Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]~47
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_2 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_2~0
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node GPIO_1[14]~output
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  46 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available
+Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:03
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 2% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 6% of the available device resources in the region that extends from location X10_Y20 to location X20_Y29
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 1.79 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 64 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10
+    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10
+    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10
+    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10
+    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10
+    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9
+    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9
+    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8
+    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8
+    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9
+    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9
+    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9
+    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9
+    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10
+    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10
+    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10
+    Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7
+    Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6
+    Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8
+    Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7
+    Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9
+    Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9
+    Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10
+    Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10
+    Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12
+    Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11
+    Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12
+    Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12
+    Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14
+    Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14
+    Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7
+    Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7
+    Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9
+    Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9
+    Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15
+    Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15
+    Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15
+    Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15
+    Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17
+    Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17
+    Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17
+    Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17
+    Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18
+    Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18
+    Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19
+    Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19
+    Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20
+    Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11
+    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1
+    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin GPIO_1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[20] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[15] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[14] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 22 warnings
+    Info: Peak virtual memory: 1195 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:38 2014
+    Info: Elapsed time: 00:00:15
+    Info: Total CPU time (on all processors): 00:00:17
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.fit.smsg.
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary
new file mode 100644
index 0000000..c5deba6
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Mon Mar 17 10:02:37 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_CAMERA
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 1,467 / 15,408 ( 10 % )
+    Total combinational functions : 1,198 / 15,408 ( 8 % )
+    Dedicated logic registers : 1,030 / 15,408 ( 7 % )
+Total registers : 1030
+Total pins : 141 / 347 ( 41 % )
+Total virtual pins : 0
+Total memory bits : 53,200 / 516,096 ( 10 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt
new file mode 100644
index 0000000..c6e71e5
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.flow.rpt
@@ -0,0 +1,124 @@
+Flow report for DE0_D5M
+Mon Mar 17 10:02:50 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Mon Mar 17 10:02:44 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 1,467 / 15,408 ( 10 % )                     ;
+;     Total combinational functions  ; 1,198 / 15,408 ( 8 % )                      ;
+;     Dedicated logic registers      ; 1,030 / 15,408 ( 7 % )                      ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200 / 516,096 ( 10 % )                   ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/17/2014 10:02:15 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; DE0_D5M             ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                              ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+; Assignment Name                     ; Value                        ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+; COMPILER_SIGNATURE_ID               ; 135308249136.139505053504416 ; --            ; --          ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                           ; --            ; --          ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                            ; --            ; --          ; --         ;
+; PARTITION_COLOR                     ; 14622752                     ; --            ; TOP_CAMERA  ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING        ; --            ; TOP_CAMERA  ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                       ; --            ; TOP_CAMERA  ; Top        ;
+; SMART_RECOMPILE                     ; On                           ; Off           ; --          ; --         ;
+; TOP_LEVEL_ENTITY                    ; TOP_CAMERA                   ; DE0_D5M       ; --          ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                          ; --            ; --          ; eda_palace ;
++-------------------------------------+------------------------------+---------------+-------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:07     ; 1.0                     ; 534 MB              ; 00:00:05                           ;
+; Fitter                    ; 00:00:14     ; 1.4                     ; 1195 MB             ; 00:00:16                           ;
+; Assembler                 ; 00:00:05     ; 1.0                     ; 450 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:03     ; 1.0                     ; 549 MB              ; 00:00:03                           ;
+; Total                     ; 00:00:29     ; --                      ; --                  ; 00:00:25                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_sta DE0_D5M -c DE0_D5M
+
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi
new file mode 100644
index 0000000..a949362
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="ca1109bd0682f003d2ee"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="DE0_D5M.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt
new file mode 100644
index 0000000..187778f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.rpt
@@ -0,0 +1,2506 @@
+Analysis & Synthesis report for DE0_D5M
+Mon Mar 17 10:02:21 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+ 11. Registers Removed During Synthesis
+ 12. Removed Registers Triggering Further Register Optimizations
+ 13. General Register Statistics
+ 14. Inverted Register Statistics
+ 15. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 16. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+ 17. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 69. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1
+ 70. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3
+ 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+ 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+ 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7
+ 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+ 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+ 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+ 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8
+ 82. altshift_taps Parameter Settings by Entity Instance
+ 83. altpll Parameter Settings by Entity Instance
+ 84. dcfifo Parameter Settings by Entity Instance
+ 85. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"
+ 86. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"
+ 87. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"
+ 88. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"
+ 89. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+ 90. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+ 91. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+ 92. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"
+ 93. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5"
+ 94. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+ 95. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"
+ 96. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"
+ 97. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"
+ 98. Elapsed Time Per Partition
+ 99. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Mon Mar 17 10:02:21 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_CAMERA                                  ;
+; Family                             ; Cyclone III                                 ;
+; Total logic elements               ; 1,569                                       ;
+;     Total combinational functions  ; 1,198                                       ;
+;     Dedicated logic registers      ; 1,030                                       ;
+; Total registers                    ; 1030                                        ;
+; Total pins                         ; 141                                         ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 53,200                                      ;
+; Embedded Multiplier 9-bit elements ; 0                                           ;
+; Total PLLs                         ; 1                                           ;
++------------------------------------+---------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                        ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option                                                                     ; Setting            ; Default Value      ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6       ;                    ;
+; Top-level entity name                                                      ; TOP_CAMERA         ; DE0_D5M            ;
+; Family name                                                                ; Cyclone III        ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; On                 ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
+; Enable compact report table                                                ; Off                ; Off                ;
+; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
+; Preserve fewer node names                                                  ; On                 ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
+; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto               ; Auto               ;
+; Safe State Machine                                                         ; Off                ; Off                ;
+; Extract Verilog State Machines                                             ; On                 ; On                 ;
+; Extract VHDL State Machines                                                ; On                 ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
+; Parallel Synthesis                                                         ; On                 ; On                 ;
+; DSP Block Balancing                                                        ; Auto               ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                 ; On                 ;
+; Power-Up Don't Care                                                        ; On                 ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
+; Remove Duplicate Registers                                                 ; On                 ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
+; Optimization Technique                                                     ; Balanced           ; Balanced           ;
+; Carry Chain Length                                                         ; 70                 ; 70                 ;
+; Auto Carry Chains                                                          ; On                 ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
+; Auto ROM Replacement                                                       ; On                 ; On                 ;
+; Auto RAM Replacement                                                       ; On                 ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
+; Strict RAM Replacement                                                     ; Off                ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
+; Auto Resource Sharing                                                      ; Off                ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
+; Report Parameter Settings                                                  ; On                 ; On                 ;
+; Report Source Assignments                                                  ; On                 ; On                 ;
+; Report Connectivity Checks                                                 ; On                 ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
+; HDL message level                                                          ; Level2             ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
+; Clock MUX Protection                                                       ; On                 ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
+; Block Design Naming                                                        ; Auto               ; Auto               ;
+; SDC constraint protection                                                  ; Off                ; Off                ;
+; Synthesis Effort                                                           ; Auto               ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+; Synthesis Seed                                                             ; 1                  ; 1                  ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                               ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path          ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                            ; Library ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Params.h        ;         ;
+; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/command.v             ;         ;
+; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/control_interface.v   ;         ;
+; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/sdr_data_path.v       ;         ;
+; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_Control_4Port.v ;         ;
+; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v          ;         ;
+; V/VGA_Param.h                             ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Param.h                             ;         ;
+; V/CCD_Capture.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/CCD_Capture.v                           ;         ;
+; V/I2C_CCD_Config.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_CCD_Config.v                        ;         ;
+; V/I2C_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/I2C_Controller.v                        ;         ;
+; V/Line_Buffer.v                           ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v                           ;         ;
+; V/RAW2RGB.v                               ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/RAW2RGB.v                               ;         ;
+; V/Reset_Delay.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Reset_Delay.v                           ;         ;
+; V/sdram_pll.v                             ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v                             ;         ;
+; V/SEG7_LUT.v                              ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT.v                              ;         ;
+; V/SEG7_LUT_8.v                            ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/SEG7_LUT_8.v                            ;         ;
+; V/VGA_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/VGA_Controller.v                        ;         ;
+; DE0_D5M.v                                 ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/DE0_D5M.v                                 ;         ;
+; TOP_CAMERA.bdf                            ; yes             ; User Block Diagram/Schematic File  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/TOP_CAMERA.bdf                            ;         ;
+; altshift_taps.tdf                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf                                        ;         ;
+; altdpram.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc                                             ;         ;
+; lpm_counter.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc                                          ;         ;
+; lpm_compare.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc                                          ;         ;
+; lpm_constant.inc                          ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc                                         ;         ;
+; db/shift_taps_rnn.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/shift_taps_rnn.tdf                     ;         ;
+; db/altsyncram_lp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_lp81.tdf                    ;         ;
+; db/cntr_cuf.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cntr_cuf.tdf                           ;         ;
+; db/cmpr_vgc.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_vgc.tdf                           ;         ;
+; altpll.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altpll.tdf                                               ;         ;
+; aglobal131.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc                                           ;         ;
+; stratix_pll.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc                                          ;         ;
+; stratixii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc                                        ;         ;
+; cycloneii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                        ;         ;
+; db/altpll_9ee2.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altpll_9ee2.tdf                        ;         ;
+; dcfifo.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf                                               ;         ;
+; lpm_add_sub.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                          ;         ;
+; a_graycounter.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc                                        ;         ;
+; a_fefifo.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc                                             ;         ;
+; a_gray2bin.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc                                           ;         ;
+; dffpipe.inc                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc                                              ;         ;
+; alt_sync_fifo.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc                                        ;         ;
+; altsyncram_fifo.inc                       ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc                                      ;         ;
+; db/dcfifo_v5o1.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dcfifo_v5o1.tdf                        ;         ;
+; db/a_gray2bin_tgb.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_gray2bin_tgb.tdf                     ;         ;
+; db/a_graycounter_s57.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_s57.tdf                  ;         ;
+; db/a_graycounter_ojc.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/a_graycounter_ojc.tdf                  ;         ;
+; db/altsyncram_de51.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/altsyncram_de51.tdf                    ;         ;
+; db/dffpipe_oe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_oe9.tdf                        ;         ;
+; db/alt_synch_pipe_qld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_qld.tdf                 ;         ;
+; db/dffpipe_pe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_pe9.tdf                        ;         ;
+; db/alt_synch_pipe_rld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/alt_synch_pipe_rld.tdf                 ;         ;
+; db/dffpipe_qe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/dffpipe_qe9.tdf                        ;         ;
+; db/cmpr_e66.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/db/cmpr_e66.tdf                           ;         ;
++-------------------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                       ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                               ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 1,569                                                                               ;
+;                                             ;                                                                                     ;
+; Total combinational functions               ; 1198                                                                                ;
+; Logic element usage by number of LUT inputs ;                                                                                     ;
+;     -- 4 input functions                    ; 544                                                                                 ;
+;     -- 3 input functions                    ; 261                                                                                 ;
+;     -- <=2 input functions                  ; 393                                                                                 ;
+;                                             ;                                                                                     ;
+; Logic elements by mode                      ;                                                                                     ;
+;     -- normal mode                          ; 886                                                                                 ;
+;     -- arithmetic mode                      ; 312                                                                                 ;
+;                                             ;                                                                                     ;
+; Total registers                             ; 1030                                                                                ;
+;     -- Dedicated logic registers            ; 1030                                                                                ;
+;     -- I/O registers                        ; 0                                                                                   ;
+;                                             ;                                                                                     ;
+; I/O pins                                    ; 141                                                                                 ;
+; Total memory bits                           ; 53200                                                                               ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                   ;
+; Total PLLs                                  ; 1                                                                                   ;
+;     -- PLLs                                 ; 1                                                                                   ;
+;                                             ;                                                                                     ;
+; Maximum fan-out node                        ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ;
+; Maximum fan-out                             ; 547                                                                                 ;
+; Total fan-out                               ; 8862                                                                                ;
+; Average fan-out                             ; 3.37                                                                                ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                         ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                          ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                        ; Library Name ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_CAMERA                                         ; 1198 (2)          ; 1030 (0)     ; 53200       ; 0            ; 0       ; 0         ; 141  ; 0            ; |TOP_CAMERA                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                   ; 1196 (1)          ; 1030 (15)    ; 53200       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                              ; 66 (66)           ; 58 (58)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                           ; 237 (168)         ; 132 (94)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                        ; 69 (69)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                  ; 84 (68)           ; 66 (55)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component| ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|     ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                  ; 16 (13)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|               ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                              ; 50 (50)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |SEG7_LUT_8:u5|                               ; 28 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5                                                                                                                                     ; work         ;
+;          |SEG7_LUT:u0|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0                                                                                                                         ; work         ;
+;          |SEG7_LUT:u1|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u1                                                                                                                         ; work         ;
+;          |SEG7_LUT:u2|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u2                                                                                                                         ; work         ;
+;          |SEG7_LUT:u3|                              ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u3                                                                                                                         ; work         ;
+;       |Sdram_Control_4Port:u7|                      ; 668 (212)         ; 697 (130)    ; 22528       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                    ; 82 (0)            ; 116 (0)      ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 82 (0)            ; 116 (0)      ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 82 (15)           ; 116 (30)     ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 4096        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                    ; 82 (0)            ; 116 (0)      ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|               ; 82 (0)            ; 116 (0)      ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 82 (15)           ; 116 (30)     ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin| ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 2048        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                   ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                   ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|               ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|         ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin| ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|     ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|     ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|      ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|        ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|        ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|        ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|         ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|              ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                         ; 60 (60)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|               ; 64 (64)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                           ; 62 (62)           ; 27 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|            ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
++-----------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; Name                                                                                                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672 ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192  ; None ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                 ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+; Vendor ; IP Core Name               ; Version ; Release Date ; License Type ; Entity Instance                                                        ; IP Include File                                                                                ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+; Altera ; Shift register (RAM-based) ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                     ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/Line_Buffer.v                  ;
+; Altera ; ALTPLL                     ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|sdram_pll:u6                                  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/V/sdram_pll.v                    ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_v2.2/Sdram_Control_4Port/Sdram_FIFO.v ;
++--------+----------------------------+---------+--------------+--------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++----------------------------------------------------------------------+
+; State Machine - |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ;
++----------------+----------------+----------------+-------------------+
+; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001    ;
++----------------+----------------+----------------+-------------------+
+; mSetup_ST.0000 ; 0              ; 0              ; 0                 ;
+; mSetup_ST.0001 ; 1              ; 0              ; 1                 ;
+; mSetup_ST.0010 ; 1              ; 1              ; 0                 ;
++----------------+----------------+----------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; Register name                                                                                                                               ; Reason for Removal                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0..5,10,15]                                                                                    ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE                                                                                    ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                 ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                           ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                          ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6]                                                                                             ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                            ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                  ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2]                                                                                         ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                                                                                              ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|rClk[1]                                                                                                                        ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                                                                                              ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9                                                                                                  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10                                                                                                 ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Frame_Cont[16..31]                                                                                              ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[10..15]                                                                                                  ; Lost fanout                                                                         ;
+; Total Number of Removed Registers = 154                                                                                                     ;                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                     ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register                                   ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7],                          ;
+;                                                          ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7],                            ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                           ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1030  ;
+; Number of registers using Synchronous Clear  ; 129   ;
+; Number of registers using Synchronous Load   ; 81    ;
+; Number of registers using Asynchronous Clear ; 723   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 393   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                   ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                    ; Fan out ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                   ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                       ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                       ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                       ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                       ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                       ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; Total number of inverted registers = 30                                                                                                              ;         ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                          ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[3]                                       ;
+; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[9]                                       ;
+; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]              ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8] ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]   ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                      ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                  ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[5]                                   ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                       ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]        ;
+; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]                           ;
+; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[15]                            ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                              ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                          ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                          ;
+; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                               ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                      ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |TOP_CAMERA|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ;
++----------------+-------+----------------------------------------------------+
+; Parameter Name ; Value ; Type                                               ;
++----------------+-------+----------------------------------------------------+
+; H_SYNC_CYC     ; 96    ; Signed Integer                                     ;
+; H_SYNC_BACK    ; 48    ; Signed Integer                                     ;
+; H_SYNC_ACT     ; 640   ; Signed Integer                                     ;
+; H_SYNC_FRONT   ; 16    ; Signed Integer                                     ;
+; H_SYNC_TOTAL   ; 800   ; Signed Integer                                     ;
+; V_SYNC_CYC     ; 2     ; Signed Integer                                     ;
+; V_SYNC_BACK    ; 33    ; Signed Integer                                     ;
+; V_SYNC_ACT     ; 480   ; Signed Integer                                     ;
+; V_SYNC_FRONT   ; 10    ; Signed Integer                                     ;
+; V_SYNC_TOTAL   ; 525   ; Signed Integer                                     ;
+; X_START        ; 144   ; Signed Integer                                     ;
+; Y_START        ; 35    ; Signed Integer                                     ;
++----------------+-------+----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; COLUMN_WIDTH   ; 1280  ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; Parameter Name ; Value          ; Type                                                                                    ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                 ;
+; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                                          ;
+; TAP_DISTANCE   ; 1280           ; Signed Integer                                                                          ;
+; WIDTH          ; 12             ; Signed Integer                                                                          ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                 ;
+; CBXI_PARAMETER ; shift_taps_rnn ; Untyped                                                                                 ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
++-------------------------------+-------------------+--------------------------------------------+
+; Parameter Name                ; Value             ; Type                                       ;
++-------------------------------+-------------------+--------------------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                                    ;
+; PLL_TYPE                      ; AUTO              ; Untyped                                    ;
+; LPM_HINT                      ; UNUSED            ; Untyped                                    ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                    ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                    ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                                    ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                    ;
+; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                             ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                    ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                    ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                    ;
+; LOCK_HIGH                     ; 1                 ; Untyped                                    ;
+; LOCK_LOW                      ; 1                 ; Untyped                                    ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                    ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                    ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                    ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                    ;
+; SKIP_VCO                      ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                    ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                    ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                    ;
+; BANDWIDTH                     ; 0                 ; Untyped                                    ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                    ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                                    ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                                    ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                    ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                                    ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK1_PHASE_SHIFT              ; -2600             ; Untyped                                    ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                                    ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                                    ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                                    ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                                    ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                    ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; VCO_MIN                       ; 0                 ; Untyped                                    ;
+; VCO_MAX                       ; 0                 ; Untyped                                    ;
+; VCO_CENTER                    ; 0                 ; Untyped                                    ;
+; PFD_MIN                       ; 0                 ; Untyped                                    ;
+; PFD_MAX                       ; 0                 ; Untyped                                    ;
+; M_INITIAL                     ; 0                 ; Untyped                                    ;
+; M                             ; 0                 ; Untyped                                    ;
+; N                             ; 1                 ; Untyped                                    ;
+; M2                            ; 1                 ; Untyped                                    ;
+; N2                            ; 1                 ; Untyped                                    ;
+; SS                            ; 1                 ; Untyped                                    ;
+; C0_HIGH                       ; 0                 ; Untyped                                    ;
+; C1_HIGH                       ; 0                 ; Untyped                                    ;
+; C2_HIGH                       ; 0                 ; Untyped                                    ;
+; C3_HIGH                       ; 0                 ; Untyped                                    ;
+; C4_HIGH                       ; 0                 ; Untyped                                    ;
+; C5_HIGH                       ; 0                 ; Untyped                                    ;
+; C6_HIGH                       ; 0                 ; Untyped                                    ;
+; C7_HIGH                       ; 0                 ; Untyped                                    ;
+; C8_HIGH                       ; 0                 ; Untyped                                    ;
+; C9_HIGH                       ; 0                 ; Untyped                                    ;
+; C0_LOW                        ; 0                 ; Untyped                                    ;
+; C1_LOW                        ; 0                 ; Untyped                                    ;
+; C2_LOW                        ; 0                 ; Untyped                                    ;
+; C3_LOW                        ; 0                 ; Untyped                                    ;
+; C4_LOW                        ; 0                 ; Untyped                                    ;
+; C5_LOW                        ; 0                 ; Untyped                                    ;
+; C6_LOW                        ; 0                 ; Untyped                                    ;
+; C7_LOW                        ; 0                 ; Untyped                                    ;
+; C8_LOW                        ; 0                 ; Untyped                                    ;
+; C9_LOW                        ; 0                 ; Untyped                                    ;
+; C0_INITIAL                    ; 0                 ; Untyped                                    ;
+; C1_INITIAL                    ; 0                 ; Untyped                                    ;
+; C2_INITIAL                    ; 0                 ; Untyped                                    ;
+; C3_INITIAL                    ; 0                 ; Untyped                                    ;
+; C4_INITIAL                    ; 0                 ; Untyped                                    ;
+; C5_INITIAL                    ; 0                 ; Untyped                                    ;
+; C6_INITIAL                    ; 0                 ; Untyped                                    ;
+; C7_INITIAL                    ; 0                 ; Untyped                                    ;
+; C8_INITIAL                    ; 0                 ; Untyped                                    ;
+; C9_INITIAL                    ; 0                 ; Untyped                                    ;
+; C0_MODE                       ; BYPASS            ; Untyped                                    ;
+; C1_MODE                       ; BYPASS            ; Untyped                                    ;
+; C2_MODE                       ; BYPASS            ; Untyped                                    ;
+; C3_MODE                       ; BYPASS            ; Untyped                                    ;
+; C4_MODE                       ; BYPASS            ; Untyped                                    ;
+; C5_MODE                       ; BYPASS            ; Untyped                                    ;
+; C6_MODE                       ; BYPASS            ; Untyped                                    ;
+; C7_MODE                       ; BYPASS            ; Untyped                                    ;
+; C8_MODE                       ; BYPASS            ; Untyped                                    ;
+; C9_MODE                       ; BYPASS            ; Untyped                                    ;
+; C0_PH                         ; 0                 ; Untyped                                    ;
+; C1_PH                         ; 0                 ; Untyped                                    ;
+; C2_PH                         ; 0                 ; Untyped                                    ;
+; C3_PH                         ; 0                 ; Untyped                                    ;
+; C4_PH                         ; 0                 ; Untyped                                    ;
+; C5_PH                         ; 0                 ; Untyped                                    ;
+; C6_PH                         ; 0                 ; Untyped                                    ;
+; C7_PH                         ; 0                 ; Untyped                                    ;
+; C8_PH                         ; 0                 ; Untyped                                    ;
+; C9_PH                         ; 0                 ; Untyped                                    ;
+; L0_HIGH                       ; 1                 ; Untyped                                    ;
+; L1_HIGH                       ; 1                 ; Untyped                                    ;
+; G0_HIGH                       ; 1                 ; Untyped                                    ;
+; G1_HIGH                       ; 1                 ; Untyped                                    ;
+; G2_HIGH                       ; 1                 ; Untyped                                    ;
+; G3_HIGH                       ; 1                 ; Untyped                                    ;
+; E0_HIGH                       ; 1                 ; Untyped                                    ;
+; E1_HIGH                       ; 1                 ; Untyped                                    ;
+; E2_HIGH                       ; 1                 ; Untyped                                    ;
+; E3_HIGH                       ; 1                 ; Untyped                                    ;
+; L0_LOW                        ; 1                 ; Untyped                                    ;
+; L1_LOW                        ; 1                 ; Untyped                                    ;
+; G0_LOW                        ; 1                 ; Untyped                                    ;
+; G1_LOW                        ; 1                 ; Untyped                                    ;
+; G2_LOW                        ; 1                 ; Untyped                                    ;
+; G3_LOW                        ; 1                 ; Untyped                                    ;
+; E0_LOW                        ; 1                 ; Untyped                                    ;
+; E1_LOW                        ; 1                 ; Untyped                                    ;
+; E2_LOW                        ; 1                 ; Untyped                                    ;
+; E3_LOW                        ; 1                 ; Untyped                                    ;
+; L0_INITIAL                    ; 1                 ; Untyped                                    ;
+; L1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G0_INITIAL                    ; 1                 ; Untyped                                    ;
+; G1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G2_INITIAL                    ; 1                 ; Untyped                                    ;
+; G3_INITIAL                    ; 1                 ; Untyped                                    ;
+; E0_INITIAL                    ; 1                 ; Untyped                                    ;
+; E1_INITIAL                    ; 1                 ; Untyped                                    ;
+; E2_INITIAL                    ; 1                 ; Untyped                                    ;
+; E3_INITIAL                    ; 1                 ; Untyped                                    ;
+; L0_MODE                       ; BYPASS            ; Untyped                                    ;
+; L1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G0_MODE                       ; BYPASS            ; Untyped                                    ;
+; G1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G2_MODE                       ; BYPASS            ; Untyped                                    ;
+; G3_MODE                       ; BYPASS            ; Untyped                                    ;
+; E0_MODE                       ; BYPASS            ; Untyped                                    ;
+; E1_MODE                       ; BYPASS            ; Untyped                                    ;
+; E2_MODE                       ; BYPASS            ; Untyped                                    ;
+; E3_MODE                       ; BYPASS            ; Untyped                                    ;
+; L0_PH                         ; 0                 ; Untyped                                    ;
+; L1_PH                         ; 0                 ; Untyped                                    ;
+; G0_PH                         ; 0                 ; Untyped                                    ;
+; G1_PH                         ; 0                 ; Untyped                                    ;
+; G2_PH                         ; 0                 ; Untyped                                    ;
+; G3_PH                         ; 0                 ; Untyped                                    ;
+; E0_PH                         ; 0                 ; Untyped                                    ;
+; E1_PH                         ; 0                 ; Untyped                                    ;
+; E2_PH                         ; 0                 ; Untyped                                    ;
+; E3_PH                         ; 0                 ; Untyped                                    ;
+; M_PH                          ; 0                 ; Untyped                                    ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; CLK0_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK1_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK2_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK3_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK4_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK5_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK6_COUNTER                  ; E0                ; Untyped                                    ;
+; CLK7_COUNTER                  ; E1                ; Untyped                                    ;
+; CLK8_COUNTER                  ; E2                ; Untyped                                    ;
+; CLK9_COUNTER                  ; E3                ; Untyped                                    ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                                    ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                                    ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                                    ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                                    ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                                    ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                    ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                    ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                                    ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                                    ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                                    ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK1                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                                    ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                                    ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                                    ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; CBXI_PARAMETER                ; altpll_9ee2       ; Untyped                                    ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                                    ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                                    ;
+; WIDTH_CLOCK                   ; 5                 ; Signed Integer                             ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                                    ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                                    ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                                    ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                                    ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                                    ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                             ;
++-------------------------------+-------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                          ;
+; REF_PER        ; 1024  ; Signed Integer                                          ;
+; SC_CL          ; 3     ; Signed Integer                                          ;
+; SC_RCD         ; 3     ; Signed Integer                                          ;
+; SC_RRD         ; 7     ; Signed Integer                                          ;
+; SC_PM          ; 1     ; Signed Integer                                          ;
+; SC_BL          ; 1     ; Signed Integer                                          ;
+; SDR_BL         ; 111   ; Unsigned Binary                                         ;
+; SDR_BT         ; 0     ; Unsigned Binary                                         ;
+; SDR_CL         ; 011   ; Unsigned Binary                                         ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ;
++----------------+-------+------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                               ;
++----------------+-------+------------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                     ;
+; REF_PER        ; 1024  ; Signed Integer                                                                     ;
+; SC_CL          ; 3     ; Signed Integer                                                                     ;
+; SC_RCD         ; 3     ; Signed Integer                                                                     ;
+; SC_RRD         ; 7     ; Signed Integer                                                                     ;
+; SC_PM          ; 1     ; Signed Integer                                                                     ;
+; SC_BL          ; 1     ; Signed Integer                                                                     ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                    ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                    ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                    ;
++----------------+-------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                           ;
+; REF_PER        ; 1024  ; Signed Integer                                                           ;
+; SC_CL          ; 3     ; Signed Integer                                                           ;
+; SC_RCD         ; 3     ; Signed Integer                                                           ;
+; SC_RRD         ; 7     ; Signed Integer                                                           ;
+; SC_PM          ; 1     ; Signed Integer                                                           ;
+; SC_BL          ; 1     ; Signed Integer                                                           ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                          ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                          ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                          ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
++----------------+-------+----------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                             ;
++----------------+-------+----------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                   ;
+; REF_PER        ; 1024  ; Signed Integer                                                                   ;
+; SC_CL          ; 3     ; Signed Integer                                                                   ;
+; SC_RCD         ; 3     ; Signed Integer                                                                   ;
+; SC_RRD         ; 7     ; Signed Integer                                                                   ;
+; SC_PM          ; 1     ; Signed Integer                                                                   ;
+; SC_BL          ; 1     ; Signed Integer                                                                   ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                  ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                  ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                  ;
++----------------+-------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ;
++-----------------------+------------------+----------------------------------+
+; Parameter Name        ; Value            ; Type                             ;
++-----------------------+------------------+----------------------------------+
+; default_exposure      ; 0000011111000000 ; Unsigned Binary                  ;
+; exposure_change_value ; 0000000011001000 ; Unsigned Binary                  ;
+; CLK_Freq              ; 50000000         ; Signed Integer                   ;
+; I2C_Freq              ; 20000            ; Signed Integer                   ;
+; LUT_SIZE              ; 25               ; Signed Integer                   ;
++-----------------------+------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; altshift_taps Parameter Settings by Entity Instance                                                       ;
++----------------------------+------------------------------------------------------------------------------+
+; Name                       ; Value                                                                        ;
++----------------------------+------------------------------------------------------------------------------+
+; Number of entity instances ; 1                                                                            ;
+; Entity Instance            ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+;     -- NUMBER_OF_TAPS      ; 2                                                                            ;
+;     -- TAP_DISTANCE        ; 1280                                                                         ;
+;     -- WIDTH               ; 12                                                                           ;
++----------------------------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                      ;
++-------------------------------+---------------------------------------------------+
+; Name                          ; Value                                             ;
++-------------------------------+---------------------------------------------------+
+; Number of entity instances    ; 1                                                 ;
+; Entity Instance               ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                            ;
+;     -- PLL_TYPE               ; AUTO                                              ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                            ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                             ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                                 ;
+;     -- VCO_MULTIPLY_BY        ; 0                                                 ;
+;     -- VCO_DIVIDE_BY          ; 0                                                 ;
++-------------------------------+---------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                                    ;
++----------------------------+------------------------------------------------------------------------------------+
+; Name                       ; Value                                                                              ;
++----------------------------+------------------------------------------------------------------------------------+
+; Number of entity instances ; 4                                                                                  ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
++----------------------------+------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"                                                                                                                   ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port       ; Type  ; Severity ; Details                                                                                                                                      ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; iUART_CTRL ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; DM   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; DQM  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"                                                                                 ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port     ; Type  ; Severity ; Details                                                                                                                                      ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; CMD      ; Input ; Warning  ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives.  Extra input bit(s) "CMD[2..2]" will be connected to GND.  ;
+; INIT_ACK ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"                                                                                                                                                               ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port                 ; Type   ; Severity ; Details                                                                                                                                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; RESET_N              ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND.                               ;
+; WR2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND.                               ;
+; RD2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; CS_N                 ; Output ; Warning  ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ;
++-------+--------+----------+----------------------------+
+; Port  ; Type   ; Severity ; Details                    ;
++-------+--------+----------+----------------------------+
+; oSEG4 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG5 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG6 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG7 ; Output ; Info     ; Explicitly unconnected     ;
++-------+--------+----------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"                                                                      ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                                                  ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; shiftout ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"                                                                                                                                                                   ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                            ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; oRed[1..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oGreen[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oBlue[1..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; iX_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; iY_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"                                                                   ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port            ; Type   ; Severity ; Details                                                                             ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; oX_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; oY_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"                                                                                  ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                  ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; oVGA_R[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_G[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_B[5..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                      ;
+; oVGA_SYNC    ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_BLANK   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_CLOCK   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++--------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:02     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:13 2014
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v
+    Info (12023): Found entity 1: command
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v
+    Info (12023): Found entity 1: control_interface
+Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v
+    Info (12023): Found entity 1: sdr_data_path
+Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v
+    Info (12023): Found entity 1: Sdram_Control_4Port
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v
+    Info (12023): Found entity 1: Sdram_FIFO
+Warning (12019): Can't analyze file -- file V/async_receiver.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v
+    Info (12023): Found entity 1: CCD_Capture
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v
+    Info (12023): Found entity 1: I2C_CCD_Config
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v
+    Info (12023): Found entity 1: I2C_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v
+    Info (12023): Found entity 1: Line_Buffer
+Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v
+    Info (12023): Found entity 1: RAW2RGB
+Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v
+    Info (12023): Found entity 1: Reset_Delay
+Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v
+    Info (12023): Found entity 1: sdram_pll
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v
+    Info (12023): Found entity 1: SEG7_LUT
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v
+    Info (12023): Found entity 1: SEG7_LUT_8
+Warning (12019): Can't analyze file -- file V/uart_crtl.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v
+    Info (12023): Found entity 1: VGA_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v
+    Info (12023): Found entity 1: DE0_D5M
+Info (12021): Found 1 design units, including 1 entities, in source file top_camera.bdf
+    Info (12023): Found entity 1: TOP_CAMERA
+Info (12127): Elaborating entity "TOP_CAMERA" for the top level hierarchy
+Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst"
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(188): truncated value with size 16 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(193): truncated value with size 32 to match size of target (2)
+Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(122) has no driver
+Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1"
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(47): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(50): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(53): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(84): truncated value with size 32 to match size of target (12)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(110): truncated value with size 32 to match size of target (12)
+Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2"
+Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3"
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)
+Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4"
+Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter:
+    Info (12134): Parameter "lpm_type" = "altshift_taps"
+    Info (12134): Parameter "number_of_taps" = "2"
+    Info (12134): Parameter "tap_distance" = "1280"
+    Info (12134): Parameter "width" = "12"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf
+    Info (12023): Found entity 1: shift_taps_rnn
+Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf
+    Info (12023): Found entity 1: altsyncram_lp81
+Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf
+    Info (12023): Found entity 1: cntr_cuf
+Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf
+    Info (12023): Found entity 1: cmpr_vgc
+Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4"
+Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5"
+Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0"
+Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6"
+Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "2"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "5"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "2"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "5"
+    Info (12134): Parameter "clk1_phase_shift" = "-2600"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone III"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf
+    Info (12023): Found entity 1: altpll_9ee2
+Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated"
+Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7"
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
+Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
+Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
+Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (272007): Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter:
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
+    Info (12134): Parameter "intended_device_family" = "Cyclone"
+    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K"
+    Info (12134): Parameter "lpm_numwords" = "512"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "dcfifo"
+    Info (12134): Parameter "lpm_width" = "16"
+    Info (12134): Parameter "lpm_widthu" = "9"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf
+    Info (12023): Found entity 1: dcfifo_v5o1
+Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info (12023): Found entity 1: a_gray2bin_tgb
+Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info (12023): Found entity 1: a_graycounter_s57
+Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info (12023): Found entity 1: a_graycounter_ojc
+Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf
+    Info (12023): Found entity 1: altsyncram_de51
+Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info (12023): Found entity 1: dffpipe_oe9
+Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_qld
+Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info (12023): Found entity 1: dffpipe_pe9
+Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_rld
+Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info (12023): Found entity 1: dffpipe_qe9
+Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
+    Info (12023): Found entity 1: cmpr_e66
+Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp"
+Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8"
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)
+Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver.
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver.
+Warning (13039): The following bidir pins have no drivers
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "GPIO_1[15]" is fed by VCC
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13009): TRI or OPNDRN buffers permanently enabled
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
+    Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 41 registers lost all their fanouts during netlist optimizations.
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 8 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+    Warning (15610): No output dependent on input pin "SW[7]"
+    Warning (15610): No output dependent on input pin "SW[6]"
+    Warning (15610): No output dependent on input pin "SW[5]"
+    Warning (15610): No output dependent on input pin "SW[4]"
+    Warning (15610): No output dependent on input pin "SW[3]"
+Info (21057): Implemented 1806 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 77 output pins
+    Info (21060): Implemented 48 bidirectional pins
+    Info (21061): Implemented 1596 logic cells
+    Info (21064): Implemented 68 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 119 warnings
+    Info: Peak virtual memory: 534 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:21 2014
+    Info: Elapsed time: 00:00:08
+    Info: Total CPU time (on all processors): 00:00:06
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary
new file mode 100644
index 0000000..385ec7e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Mon Mar 17 10:02:21 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_CAMERA
+Family : Cyclone III
+Total logic elements : 1,569
+    Total combinational functions : 1,198
+    Dedicated logic registers : 1,030
+Total registers : 1030
+Total pins : 141
+Total virtual pins : 0
+Total memory bits : 53,200
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 1
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin
new file mode 100644
index 0000000..3d3a943
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+CHIP  "DE0_D5M"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+DRAM_ADDR[1]                 : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_1                    : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[4]                 : A5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[7]                 : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[11]                : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[8]                   : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[10]                  : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[13]                  : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+HEX1[0]                      : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[3]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[6]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[1]                      : A16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[4]                      : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+HEX3[2]                      : A19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+GPIO_1[16]                   : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+GPIO_1[15]                   : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[1]              : AA11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+GPIO_1[6]                    : AA17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[5]                    : AA18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[2]                    : AA19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[0]                    : AA20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+GPIO_1[17]                   : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+GPIO_1[14]                   : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[0]              : AB11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+GPIO_1[7]                    : AB17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[4]                    : AB18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[3]                    : AB19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[1]                    : AB20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 3.3V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[2]                 : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[10]                : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_0                    : B5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[6]                 : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[9]                 : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_UDQM                    : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[9]                   : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[12]                  : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+HEX1[1]                      : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[4]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+HEX2[2]                      : B16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[5]                      : B17       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[0]                      : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[3]                      : B19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[3]                 : C3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[0]                 : C4        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+DRAM_ADDR[5]                 : C6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[8]                 : C7        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+DRAM_DQ[11]                  : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+HEX1[2]                      : C13       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+HEX3[4]                      : C19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+DRAM_WE_N                    : D6        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[0]                   : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+HEX2[0]                      : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+HEX3[5]                      : D19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_CLK                     : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CKE                     : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_LDQM                    : E7        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[3]                   : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[14]                  : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[0]                      : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+HEX1[5]                      : E14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[3]                      : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+KEY[2]                       : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+DRAM_RAS_N                   : F7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[7]                   : F8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[4]                   : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[15]                  : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[1]                      : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[5]                      : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[6]                      : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[6]                      : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[1]                      : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+KEY[1]                       : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+DRAM_CS_N                    : G7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CAS_N                   : G8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[5]                   : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[1]                   : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0[4]                      : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+HEX3[6]                      : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+KEY[0]                       : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+DRAM_DQ[6]                   : H9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[2]                   : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0[2]                      : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[3]                      : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+GPIO_1[22]                   : R11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[23]                   : R12       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+GPIO_1[19]                   : R14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+GPIO_1_CLKOUT[0]             : R16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+GPIO_1[27]                   : T9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[25]                   : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+GPIO_1[21]                   : T12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+GPIO_1[18]                   : T14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[11]                   : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_CLKOUT[1]             : T16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+GPIO_1[29]                   : U8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[26]                   : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[24]                   : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+GPIO_1[20]                   : U12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+VGA_CLK                      : U14       : output : 3.3-V LVTTL       :         : 4         : N              
+GPIO_1[10]                   : U15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+GPIO_1[30]                   : V6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[31]                   : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V14       :        :                   :         : 4         :                
+GPIO_1[13]                   : V15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+GPIO_1[12]                   : W15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 3.3V    : 4         :                
+GPIO_1[9]                    : W17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+GPIO_1[28]                   : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 3.3V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+GPIO_1[8]                    : Y17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof
new file mode 100644
index 0000000..77147af
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.pof
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf
new file mode 100644
index 0000000..6eb86c4
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "14:14:24  April 30, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_D5M"
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf
new file mode 100644
index 0000000..15d8d33
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf
@@ -0,0 +1,557 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_CAMERA
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name BDF_FILE TOP_CAMERA.bdf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak
new file mode 100644
index 0000000..cc80243
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qsf.bak
@@ -0,0 +1,586 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY DE0_D5M
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_0[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_0[16]
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[35]
+set_location_assignment PIN_V6 -to GPIO_1[34]
+set_location_assignment PIN_U8 -to GPIO_1[33]
+set_location_assignment PIN_Y7 -to GPIO_1[32]
+set_location_assignment PIN_T9 -to GPIO_1[31]
+set_location_assignment PIN_U9 -to GPIO_1[30]
+set_location_assignment PIN_T10 -to GPIO_1[29]
+set_location_assignment PIN_U10 -to GPIO_1[28]
+set_location_assignment PIN_R12 -to GPIO_1[27]
+set_location_assignment PIN_R11 -to GPIO_1[26]
+set_location_assignment PIN_T12 -to GPIO_1[25]
+set_location_assignment PIN_U12 -to GPIO_1[24]
+set_location_assignment PIN_R14 -to GPIO_1[23]
+set_location_assignment PIN_T14 -to GPIO_1[22]
+set_location_assignment PIN_AB7 -to GPIO_1[21]
+set_location_assignment PIN_AA7 -to GPIO_1[20]
+set_location_assignment PIN_AA9 -to GPIO_1[19]
+set_location_assignment PIN_T16 -to GPIO_1[18]
+set_location_assignment PIN_AB9 -to GPIO_1[17]
+set_location_assignment PIN_R16 -to GPIO_1[16]
+set_location_assignment PIN_V15 -to GPIO_1[15]
+set_location_assignment PIN_W15 -to GPIO_1[14]
+set_location_assignment PIN_T15 -to GPIO_1[13]
+set_location_assignment PIN_U15 -to GPIO_1[12]
+set_location_assignment PIN_W17 -to GPIO_1[11]
+set_location_assignment PIN_Y17 -to GPIO_1[10]
+set_location_assignment PIN_AB17 -to GPIO_1[9]
+set_location_assignment PIN_AA17 -to GPIO_1[8]
+set_location_assignment PIN_AA18 -to GPIO_1[7]
+set_location_assignment PIN_AB18 -to GPIO_1[6]
+set_location_assignment PIN_AB19 -to GPIO_1[5]
+set_location_assignment PIN_AA19 -to GPIO_1[4]
+set_location_assignment PIN_AB20 -to GPIO_1[3]
+set_location_assignment PIN_AA11 -to GPIO_1[2]
+set_location_assignment PIN_AA20 -to GPIO_1[1]
+set_location_assignment PIN_AB11 -to GPIO_1[0]
+
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0_D[0]
+set_location_assignment PIN_F11 -to HEX0_D[1]
+set_location_assignment PIN_H12 -to HEX0_D[2]
+set_location_assignment PIN_H13 -to HEX0_D[3]
+set_location_assignment PIN_G12 -to HEX0_D[4]
+set_location_assignment PIN_F12 -to HEX0_D[5]
+set_location_assignment PIN_F13 -to HEX0_D[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1_D[6]
+set_location_assignment PIN_E14 -to HEX1_D[5]
+set_location_assignment PIN_B14 -to HEX1_D[4]
+set_location_assignment PIN_A14 -to HEX1_D[3]
+set_location_assignment PIN_C13 -to HEX1_D[2]
+set_location_assignment PIN_B13 -to HEX1_D[1]
+set_location_assignment PIN_A13 -to HEX1_D[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2_D[6]
+set_location_assignment PIN_B17 -to HEX2_D[5]
+set_location_assignment PIN_A17 -to HEX2_D[4]
+set_location_assignment PIN_E15 -to HEX2_D[3]
+set_location_assignment PIN_B16 -to HEX2_D[2]
+set_location_assignment PIN_A16 -to HEX2_D[1]
+set_location_assignment PIN_D15 -to HEX2_D[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3_D[6]
+set_location_assignment PIN_D19 -to HEX3_D[5]
+set_location_assignment PIN_C19 -to HEX3_D[4]
+set_location_assignment PIN_B19 -to HEX3_D[3]
+set_location_assignment PIN_A19 -to HEX3_D[2]
+set_location_assignment PIN_F15 -to HEX3_D[1]
+set_location_assignment PIN_B18 -to HEX3_D[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+set_location_assignment PIN_B12 -to CLOCK_50_2
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+
+
+
+
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+
+
+
+
+
+
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/uart_crtl.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws
new file mode 100644
index 0000000..91d2f2b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.qws
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc
new file mode 100644
index 0000000..6a9d418
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sdc
@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 10.0 Build 218 06/27/2010 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_50" -period 20ns [get_ports {CLOCK_50}] -waveform {0.000ns 10.000ns}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof
new file mode 100644
index 0000000..76fca82
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sof
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt
new file mode 100644
index 0000000..760d753
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.rpt
@@ -0,0 +1,10106 @@
+TimeQuest Timing Analyzer report for DE0_D5M
+Mon Mar 17 10:02:50 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1200mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1200mV 85C Model Setup Summary
+  9. Slow 1200mV 85C Model Hold Summary
+ 10. Slow 1200mV 85C Model Recovery Summary
+ 11. Slow 1200mV 85C Model Removal Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 16. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
+ 19. Slow 1200mV 85C Model Removal: 'CLOCK_50'
+ 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 23. Setup Times
+ 24. Hold Times
+ 25. Clock to Output Times
+ 26. Minimum Clock to Output Times
+ 27. Output Enable Times
+ 28. Minimum Output Enable Times
+ 29. Output Disable Times
+ 30. Minimum Output Disable Times
+ 31. MTBF Summary
+ 32. Synchronizer Summary
+ 33. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+ 34. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+ 35. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+ 36. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+ 37. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+ 38. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+ 39. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+ 40. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+ 41. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+ 42. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+ 43. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+ 44. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+ 45. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+ 46. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+ 47. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+ 48. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+ 49. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+ 50. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+ 51. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+ 52. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+ 53. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+ 54. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+ 55. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+ 56. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+ 57. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+ 58. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+ 59. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+ 60. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+ 61. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+ 62. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+ 63. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+ 64. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+ 65. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+ 66. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+ 67. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+ 68. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+ 69. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+ 70. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+ 71. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+ 72. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+ 73. Slow 1200mV 0C Model Fmax Summary
+ 74. Slow 1200mV 0C Model Setup Summary
+ 75. Slow 1200mV 0C Model Hold Summary
+ 76. Slow 1200mV 0C Model Recovery Summary
+ 77. Slow 1200mV 0C Model Removal Summary
+ 78. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 79. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 80. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 81. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 82. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 83. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 84. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
+ 85. Slow 1200mV 0C Model Removal: 'CLOCK_50'
+ 86. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 87. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 88. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 89. Setup Times
+ 90. Hold Times
+ 91. Clock to Output Times
+ 92. Minimum Clock to Output Times
+ 93. Output Enable Times
+ 94. Minimum Output Enable Times
+ 95. Output Disable Times
+ 96. Minimum Output Disable Times
+ 97. MTBF Summary
+ 98. Synchronizer Summary
+ 99. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+100. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+101. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+102. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+103. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+104. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+105. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+106. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+107. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+108. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+109. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+110. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+111. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+112. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+113. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+114. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+115. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+116. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+117. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+118. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+119. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+120. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+121. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+122. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+123. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+124. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+125. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+126. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+127. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+128. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+129. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+130. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+131. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+132. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+133. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+134. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+135. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+136. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+137. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+138. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+139. Fast 1200mV 0C Model Setup Summary
+140. Fast 1200mV 0C Model Hold Summary
+141. Fast 1200mV 0C Model Recovery Summary
+142. Fast 1200mV 0C Model Removal Summary
+143. Fast 1200mV 0C Model Minimum Pulse Width Summary
+144. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+145. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+146. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+147. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+148. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+149. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
+150. Fast 1200mV 0C Model Removal: 'CLOCK_50'
+151. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+152. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+153. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+154. Setup Times
+155. Hold Times
+156. Clock to Output Times
+157. Minimum Clock to Output Times
+158. Output Enable Times
+159. Minimum Output Enable Times
+160. Output Disable Times
+161. Minimum Output Disable Times
+162. MTBF Summary
+163. Synchronizer Summary
+164. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+165. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+166. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+167. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+168. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+169. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+170. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+171. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+172. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+173. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+174. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+175. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+176. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+177. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+178. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+179. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+180. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+181. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+182. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+183. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+184. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+185. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+186. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+187. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+188. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+189. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+190. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+191. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+192. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+193. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+194. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+195. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+196. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+197. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+198. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+199. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+200. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+201. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+202. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+203. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+204. Multicorner Timing Analysis Summary
+205. Setup Times
+206. Hold Times
+207. Clock to Output Times
+208. Minimum Clock to Output Times
+209. Board Trace Model Assignments
+210. Input Transition Times
+211. Slow Corner Signal Integrity Metrics
+212. Fast Corner Signal Integrity Metrics
+213. Setup Transfers
+214. Hold Transfers
+215. Recovery Transfers
+216. Removal Transfers
+217. Report TCCS
+218. Report RSKM
+219. Unconstrained Paths
+220. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                        ;
++--------------------+-----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name      ; DE0_D5M                                             ;
+; Device Family      ; Cyclone III                                         ;
+; Device Name        ; EP3C16F484C6                                        ;
+; Timing Models      ; Final                                               ;
+; Delay Model        ; Combined                                            ;
+; Rise/Fall Delays   ; Enabled                                             ;
++--------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; DE0_D5M.sdc   ; OK     ; Mon Mar 17 10:02:47 2014 ;
++---------------+--------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; Clock Name                                          ; Type      ; Period ; Frequency ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                 ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; CLOCK_50                                            ; Base      ; 20.000 ; 50.0 MHz  ; 0.000  ; 10.000 ;            ;           ;             ;        ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                            ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000  ; 125.0 MHz ; 0.000  ; 4.000  ; 50.00      ; 2         ; 5           ;        ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000  ; 125.0 MHz ; -2.600 ; 1.400  ; 50.00      ; 2         ; 5           ; -117.0 ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                        ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 174.7 MHz  ; 174.7 MHz       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 207.04 MHz ; 207.04 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                          ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454 ; -22.246       ;
+; CLOCK_50                                            ; 15.170 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                          ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.214 ; 0.000         ;
+; CLOCK_50                                            ; 0.358 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                       ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.497 ; -338.162      ;
+; CLOCK_50                                            ; 14.980 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                       ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.616 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.132 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.736 ; 0.000         ;
+; CLOCK_50                                            ; 9.580 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.454 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.208     ; 2.261      ;
+; -0.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.198     ; 2.250      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.178     ; 2.229      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.375 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.205      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.337 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.167      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.185     ; 2.146      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.308 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.123      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.287 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.189     ; 2.113      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.194     ; 1.968      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; -0.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.221     ; 1.932      ;
+; 2.276  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.653      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.320  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.607      ;
+; 2.340  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.278      ; 5.953      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.346  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.581      ;
+; 2.360  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.569      ;
+; 2.365  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.086     ; 5.564      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.384  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.276      ; 5.907      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
+; 2.404  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 5.523      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                          ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.170 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.782      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.659      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.650      ;
+; 15.384 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.568      ;
+; 15.400 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.567      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.404 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.549      ;
+; 15.409 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.558      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.413 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.554      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.435 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.527      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.484      ;
+; 15.474 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.478      ;
+; 15.477 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.475      ;
+; 15.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.462      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
+; 15.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.048     ; 4.416      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.214 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.799      ;
+; 0.230 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.815      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.910      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.428      ; 0.911      ;
+; 0.334 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.381      ; 0.902      ;
+; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.380      ; 0.910      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.380      ; 0.912      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.591      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.592      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.592      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.592      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.594      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.943      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.943      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.580      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.591      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.590      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.591      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.608      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.381 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.600      ;
+; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.385 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.609      ;
+; 0.391 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.609      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.736      ;
+; 0.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.743      ;
+; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.769      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.778      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.777      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.778      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.781      ;
+; 0.568 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.789      ;
+; 0.569 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.790      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.791      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 0.793      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.792      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.794      ;
+; 0.580 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.799      ;
+; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.800      ;
+; 0.585 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.804      ;
+; 0.586 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.805      ;
+; 0.606 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.825      ;
+; 0.700 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.919      ;
+; 0.702 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.921      ;
+; 0.710 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.929      ;
+; 0.825 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.043      ;
+; 0.831 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.050      ;
+; 0.832 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 1.051      ;
+; 0.832 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 1.050      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.497 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.158      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.493 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.280     ; 3.162      ;
+; -1.437 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.285     ; 3.200      ;
+; -1.433 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.277     ; 3.204      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.330 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.802      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.327 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.805      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.535     ; 2.806      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.326 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.804      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.325 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.803      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.324 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.542     ; 2.797      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.546     ; 2.792      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.546     ; 2.792      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
+; -1.323 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 2.793      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                    ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.980 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 5.101      ;
+; 14.989 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 5.092      ;
+; 15.085 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 4.996      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.119 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.838      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.128 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.829      ;
+; 15.144 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.926      ;
+; 15.223 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.066      ; 4.858      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.224 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.733      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.283 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.663      ;
+; 15.287 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.783      ;
+; 15.290 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.780      ;
+; 15.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.773      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.362 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.058     ; 4.595      ;
+; 15.384 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.686      ;
+; 15.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.055      ; 4.678      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
+; 15.426 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.069     ; 4.520      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                   ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.827      ;
+; 1.696 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.228      ; 2.081      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.759 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.970      ;
+; 1.838 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.228      ; 2.223      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.655      ;
+; 2.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.238      ; 2.909      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.778 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.999      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 3.028      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.805 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.069      ; 3.031      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
+; 2.807 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 3.019      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.132 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.681     ; 2.608      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.684     ; 2.606      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.133 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.676     ; 2.614      ;
+; 4.135 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.679     ; 2.613      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.614      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.142 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.605      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.608      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.611      ;
+; 4.144 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.687     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.613      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.614      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.615      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.688     ; 2.615      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.146 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.613      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.148 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.615      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                      ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                  ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0  ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0   ;
+; 3.736 ; 3.966        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg        ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0  ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0   ;
+; 3.737 ; 3.967        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg        ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                           ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                          ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                           ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                           ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0 ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CAS_N                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CS_N[0]                                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[11]                                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[8]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                               ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CAS_N                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CS_N[0]                                                                                                            ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                             ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                              ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[4]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[5]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                   ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                         ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                            ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[12]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[14]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[20]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[22]                                                                                                ;
+; 3.754 ; 3.970        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM[0]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                              ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                     ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                     ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                     ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                           ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.591 ; 9.775        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.632 ; 9.816        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.740 ; 9.740        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.742 ; 9.742        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|rClk[0]|clk                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.252 ; 3.792 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.228 ; 4.804 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.088 ; 4.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.985 ; 4.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.971 ; 4.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.720 ; 4.223 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.722 ; 4.235 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.708 ; 4.219 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.516 ; -2.017 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.569 ; -2.104 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.516 ; -2.017 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -3.030 ; -3.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.758 ; -4.336 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.529 ; -4.083 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -3.407 ; -3.896 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -3.296 ; -3.778 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -3.282 ; -3.768 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -3.041 ; -3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -3.044 ; -3.537 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.030 ; -3.522 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.882  ; 6.755  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.291  ; 5.346  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.733  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.700  ; 3.596  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.732  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.589  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.733  ; 3.638  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.576  ; 3.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.527  ; 3.439  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.575  ; 3.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.357  ; 3.274  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.532  ; 3.433  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.594  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.515  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.381  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.540  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.624  ; 3.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.569  ; 3.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.853  ; 5.686  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.923  ; 5.772  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.841  ; 5.703  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.747  ; 5.603  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.667  ; 5.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 6.210  ; 6.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.690  ; 5.589  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.631  ; 5.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.178  ; 5.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.631  ; 5.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.436  ; 5.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.663  ; 5.519  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.466  ; 5.409  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 6.063  ; 5.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.624  ; 5.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.597  ; 3.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.733  ; 3.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.431  ; 3.340  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.576  ; 5.291  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.575 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.703 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.707  ; 6.581  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.825  ; 6.882  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.707  ; 6.581  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.856  ; 4.807  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.856  ; 4.807  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.175  ; 5.233  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.922  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.251  ; 3.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.283  ; 3.195  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.146  ; 3.077  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.283  ; 3.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.133  ; 3.064  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.085  ; 2.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.132  ; 3.029  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.922  ; 2.838  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.090  ; 2.989  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.150  ; 3.048  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.074  ; 2.982  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.945  ; 2.861  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.098  ; 3.006  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.179  ; 3.087  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.125  ; 3.044  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.236  ; 3.132  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.781  ; 3.692  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.426  ; 4.325  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.302  ; 4.232  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.235  ; 4.172  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.143  ; 5.835  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.933  ; 4.852  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.418  ; 4.365  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.586  ; 4.522  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.454  ; 4.407  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.187  ; 4.101  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.369  ; 4.307  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.773  ; 4.673  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.165  ; 4.074  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.781  ; 3.692  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.341  ; 4.260  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.381  ; 4.264  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.156  ; 4.070  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.153  ; 3.092  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.282  ; 3.197  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.994  ; 2.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.132  ; 4.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.948 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.075 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.674 ; 3.674 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.461 ; 3.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.863 ; 3.863 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.664 ; 3.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.883 ; 3.883 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.847 ; 3.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.170 ; 3.170 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.170 ; 3.170 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.178 ; 3.178 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.160 ; 3.160 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.168 ; 3.168 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.178 ; 3.178 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.158 ; 3.158 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.863 ; 3.863 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.935 ; 2.935 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.945 ; 2.945 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.739 ; 2.739 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.935 ; 2.935 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.146 ; 3.146 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.111 ; 3.111 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.461 ; 2.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.461 ; 2.461 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.469 ; 2.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.451 ; 2.451 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.459 ; 2.459 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.469 ; 2.469 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.449 ; 2.449 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.126 ; 3.126 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.605     ; 3.707     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.615     ; 3.717     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.406     ; 3.508     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.802     ; 3.904     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.605     ; 3.707     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.822     ; 3.924     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.796     ; 3.898     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.104     ; 3.206     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.104     ; 3.206     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.105     ; 3.207     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.094     ; 3.196     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.095     ; 3.197     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.105     ; 3.207     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.085     ; 3.187     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.802     ; 3.904     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.976     ; 3.072     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.986     ; 3.082     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.785     ; 2.881     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.165     ; 3.261     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.976     ; 3.072     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.185     ; 3.281     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.159     ; 3.255     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.496     ; 2.592     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.496     ; 2.592     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.497     ; 2.593     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.486     ; 2.582     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.487     ; 2.583     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.497     ; 2.593     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.477     ; 2.573     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.165     ; 3.261     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.051 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.051                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 3.802        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.254                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 6.970        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.284        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.326                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.074        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.397                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.292        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.434                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.899        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.535        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.441                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.336        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.471                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.219        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.502                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.253        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.552                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 6.898        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.654        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.107        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.470        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.605                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.500        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.628                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.103        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.525        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.632                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.382        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.636                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.531        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.670                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.417        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.684                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.578        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.709                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 6.901        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.808        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.717                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 6.902        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.815        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.748                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.109        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.639        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.765                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.513        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.790                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.773        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.017        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.795                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.104        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.691        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.838                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.985        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.853        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.840                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 6.984        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.856        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.862                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 6.905        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.957        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.886                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.108        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.778        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.896                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.645        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.906                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.662        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.244        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.918                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.667        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.991                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 6.902        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.089        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.005                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.265        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.740        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.055                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.805        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.215                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.964        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.246                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 4.993        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.358                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.254        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.104        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.397                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.292        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.525                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.274        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.641                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.388        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.733                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.267        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.466        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.873                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.126        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.747        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                         ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 193.87 MHz ; 193.87 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 231.32 MHz ; 231.32 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.053  ; 0.000         ;
+; CLOCK_50                                            ; 15.677 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.190 ; 0.000         ;
+; CLOCK_50                                            ; 0.312 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.843 ; -150.984      ;
+; CLOCK_50                                            ; 15.539 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.477 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.638 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.741 ; 0.000         ;
+; CLOCK_50                                            ; 9.561 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.053 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 2.054      ;
+; 0.080 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.893     ; 2.042      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.110 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 2.026      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 2.004      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.168 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.960      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.193 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.887     ; 1.935      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.216 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.904      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.219 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.890     ; 1.906      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.348 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.889     ; 1.778      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.914     ; 1.743      ;
+; 2.842 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.097      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.055      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.898 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 5.034      ;
+; 2.914 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.025      ;
+; 2.919 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.076     ; 5.020      ;
+; 2.931 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.256      ; 5.340      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.949 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.983      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
+; 2.954 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.083     ; 4.978      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.677 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.285      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.806 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.169      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.160      ;
+; 15.875 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.087      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.892 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.069      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.080      ;
+; 15.910 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.065      ;
+; 15.919 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 4.056      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.921 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 4.048      ;
+; 15.951 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.011      ;
+; 15.952 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.053     ; 4.010      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.956 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.052     ; 4.007      ;
+; 15.999 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.976      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
+; 16.022 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 3.953      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.717      ;
+; 0.205 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.732      ;
+; 0.295 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.822      ;
+; 0.296 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.383      ; 0.823      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.301 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.530      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
+; 0.321 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.519      ;
+; 0.324 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.535      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.537      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.387      ; 0.857      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.387      ; 0.857      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.537      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.538      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.341      ; 0.841      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.529      ;
+; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.543      ;
+; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|WRITEA                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.535      ;
+; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.536      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.340      ; 0.847      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 0.548      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.537      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[1]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
+; 0.333 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.341 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.346 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.545      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.466 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.665      ;
+; 0.472 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.671      ;
+; 0.496 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.694      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.698      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.699      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.700      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.700      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.701      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.702      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.703      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.705      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.704      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.714      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.716      ;
+; 0.518 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.716      ;
+; 0.521 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.719      ;
+; 0.525 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.724      ;
+; 0.525 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.723      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.725      ;
+; 0.540 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.739      ;
+; 0.638 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.837      ;
+; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.838      ;
+; 0.640 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.839      ;
+; 0.741 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.939      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.943      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.942      ;
+; 0.744 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.942      ;
+; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
+; 0.745 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.944      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.843 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.817      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.840 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.978     ; 2.820      ;
+; -0.799 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.982     ; 2.857      ;
+; -0.796 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.976     ; 2.860      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.689 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.497      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.687 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.202     ; 2.500      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.498      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.686 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.204     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.685 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.497      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 2.496      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.488      ;
+; -0.680 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 2.485      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.539 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.558      ;
+; 15.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.549      ;
+; 15.628 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.469      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.649 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.315      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.658 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.306      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.396      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.738 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.226      ;
+; 15.755 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.082      ; 4.342      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.153      ;
+; 15.815 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.270      ;
+; 15.818 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.267      ;
+; 15.824 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.261      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.865 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.051     ; 4.099      ;
+; 15.895 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.190      ;
+; 15.902 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.070      ; 4.183      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
+; 15.925 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.027      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.477 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.666      ;
+; 1.534 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.222      ; 1.900      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.576 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.045      ; 1.765      ;
+; 1.632 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.222      ; 1.998      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.407      ;
+; 2.262 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.235      ; 2.641      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.513 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.050      ; 2.707      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.721      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.514 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.723      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.515 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 2.721      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
+; 2.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.058      ; 2.733      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.438     ; 2.344      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.639 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.338      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.640 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.448     ; 2.336      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.342      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.343      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.641 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.341      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.343      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.345      ;
+; 3.645 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.444     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.445     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.338      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.345      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.647 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.455     ; 2.336      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.450     ; 2.343      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
+; 3.649 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.451     ; 2.342      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                         ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.742 ; 3.958        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.744 ; 3.974        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ;
+; 3.746 ; 3.962        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.748 ; 3.964        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[2]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[5]                                                                                                                                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.561 ; 9.745        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.585 ; 9.769        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.586 ; 9.770        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.587 ; 9.771        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.713 ; 9.713        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.721 ; 9.721        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|rClk[0]|clk                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 3.589 ; 4.163 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 3.589 ; 4.163 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 2.854 ; 3.325 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.848 ; 4.345 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.848 ; 4.345 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.647 ; 4.124 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.508 ; 3.941 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.418 ; 3.842 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.402 ; 3.831 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.177 ; 3.607 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.182 ; 3.617 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.163 ; 3.604 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.293 ; -1.708 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.317 ; -1.789 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.293 ; -1.708 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.565 ; -2.993 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.235 ; -3.721 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.030 ; -3.492 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.908 ; -3.334 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.811 ; -3.222 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.795 ; -3.211 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -2.579 ; -2.996 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.584 ; -3.006 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.565 ; -2.993 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.617  ; 6.571  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.617  ; 6.571  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.491  ; 6.343  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.764  ; 4.656  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.764  ; 4.656  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.013  ; 5.130  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.730  ; 3.594  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.702  ; 3.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.727  ; 3.594  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.587  ; 3.487  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.730  ; 3.586  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.574  ; 3.450  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.533  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.580  ; 3.438  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.373  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.536  ; 3.389  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.591  ; 3.458  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.526  ; 3.393  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.389  ; 3.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.546  ; 3.427  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.618  ; 3.475  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.558  ; 3.446  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.526  ; 7.148  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.603  ; 5.452  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.676  ; 5.541  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.607  ; 5.466  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.526  ; 7.148  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.522  ; 5.349  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.454  ; 5.296  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.944  ; 5.827  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.487  ; 5.303  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.446  ; 5.300  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.017  ; 4.898  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.452  ; 5.289  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.233  ; 5.055  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.444  ; 5.305  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.296  ; 5.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 5.806  ; 5.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.414  ; 5.226  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.587  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.721  ; 3.601  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.442  ; 3.301  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.583  ; 5.252  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.336  ; 6.187  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.455  ; 6.406  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.336  ; 6.187  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.676  ; 4.567  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.676  ; 4.567  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 4.910  ; 5.026  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.989  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.304  ; 3.159  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.329  ; 3.197  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.194  ; 3.093  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.330  ; 3.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.182  ; 3.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.141  ; 3.032  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.187  ; 3.046  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.989  ; 2.887  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.144  ; 2.999  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.198  ; 3.065  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.135  ; 3.003  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.004  ; 2.888  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.155  ; 3.036  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.225  ; 3.082  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.166  ; 3.053  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.286  ; 3.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.770  ; 3.622  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 4.360  ; 4.187  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.249  ; 4.128  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.187  ; 4.056  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 6.096  ; 5.728  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.828  ; 4.689  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.355  ; 4.245  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.512  ; 4.404  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.402  ; 4.261  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 4.140  ; 3.977  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 4.300  ; 4.168  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.675  ; 4.504  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 4.112  ; 3.961  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.770  ; 3.622  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.276  ; 4.132  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 4.316  ; 4.129  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.112  ; 3.947  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.193  ; 3.098  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.321  ; 3.201  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.055  ; 2.915  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.190  ; 4.858  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.777 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.922 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.119 ; 3.106 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.121 ; 3.108 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.591 ; 3.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.601 ; 3.588 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.404 ; 3.391 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.777 ; 3.764 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.591 ; 3.578 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.797 ; 3.784 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.766 ; 3.753 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.129 ; 3.116 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.129 ; 3.116 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.141 ; 3.128 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.119 ; 3.106 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.131 ; 3.118 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.141 ; 3.128 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.121 ; 3.108 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.777 ; 3.764 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.251 ; 2.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.252 ; 2.252 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.704 ; 2.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.714 ; 2.714 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.525 ; 2.525 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.882 ; 2.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.704 ; 2.704 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.902 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.872 ; 2.872 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.261 ; 2.261 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.261 ; 2.261 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.272 ; 2.272 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.251 ; 2.251 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.262 ; 2.262 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.272 ; 2.272 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.252 ; 2.252 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.882 ; 2.882 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.591     ; 3.591     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.601     ; 3.601     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.413     ; 3.413     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.769     ; 3.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.591     ; 3.591     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.789     ; 3.789     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.763     ; 3.763     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.140     ; 3.140     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.140     ; 3.140     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.146     ; 3.146     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.130     ; 3.130     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.136     ; 3.136     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.146     ; 3.146     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.126     ; 3.126     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.769     ; 3.769     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.714     ; 2.902     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.533     ; 2.721     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.875     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.704     ; 2.892     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.895     ; 3.083     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.869     ; 3.057     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.272     ; 2.460     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.272     ; 2.460     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.277     ; 2.465     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.262     ; 2.450     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.267     ; 2.455     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.277     ; 2.465     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.257     ; 2.445     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.875     ; 3.063     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.581 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.581                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.335        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.246        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.772                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.080        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.692        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.831                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.493        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.874                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.676        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.896                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.022        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.874        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.906                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.708        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.975                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.335        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.640        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.978                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.021        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.957        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.643        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.986                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.199        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.787        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.061                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.863        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.083                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.196        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.887        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.090                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.892        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.119                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.781        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.133                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.935        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.134                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.018        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.116        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.135                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.019        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.116        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.148                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.809        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.187                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.201        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.986        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.217                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.878        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.247                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.050        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.261                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.920        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.341        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.263                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.022        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.241        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.279                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.100        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.179        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.286                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.200        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.086        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.291                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.097        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.194        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.324                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.808        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.516        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.345                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.008        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.347                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.010        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.358                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.019        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.339        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.445                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.350        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.095        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.146        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.587                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.250        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.646                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.307        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.740                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.340        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.400        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.768                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.570        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.901                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.564        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.643        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.070                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.352        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.718        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.198                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.222        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.976        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.424  ; 0.000         ;
+; CLOCK_50                                            ; 17.244 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.116 ; 0.000         ;
+; CLOCK_50                                            ; 0.187 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.773  ; 0.000         ;
+; CLOCK_50                                            ; 17.090 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 0.904 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.414 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.748 ; 0.000         ;
+; CLOCK_50                                            ; 9.265 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 1.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.313     ; 1.270      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.445 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.319     ; 1.243      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.462 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.238      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.481 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.303     ; 1.223      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.485 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.307     ; 1.215      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.508 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.183      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.511 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.186      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.522 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.179      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.325     ; 1.069      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 1.613 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.310     ; 1.084      ;
+; 4.705 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.258      ;
+; 4.712 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.150      ; 3.445      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.733 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.226      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.739 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.414      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.748 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.146      ; 3.405      ;
+; 4.750 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.213      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.756 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.048     ; 3.203      ;
+; 4.757 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.206      ;
+; 4.764 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.044     ; 3.199      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.244 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.729      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.296 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.684      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.681      ;
+; 17.340 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.640      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.340 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.631      ;
+; 17.343 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.637      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.358 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.031     ; 2.618      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.361 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.619      ;
+; 17.382 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]         ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.591      ;
+; 17.405 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.575      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.410 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.035     ; 2.562      ;
+; 17.432 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]          ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                 ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.034     ; 2.541      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
+; 17.434 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.027     ; 2.546      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.116 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.433      ;
+; 0.123 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.440      ;
+; 0.162 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.487      ;
+; 0.164 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.481      ;
+; 0.165 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.482      ;
+; 0.172 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.496      ;
+; 0.173 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.497      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.500      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.500      ;
+; 0.186 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.313      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.314      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.316      ;
+; 0.189 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.316      ;
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.233      ; 0.507      ;
+; 0.192 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.319      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.193 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[19]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[11]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[9]                                                                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[18]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|WE_N                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[21]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[1]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[3]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[2]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[3]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[3]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[7]                                                                                                     ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]                                                                                                     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.187 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.195 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.314      ;
+; 0.199 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.319      ;
+; 0.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.208 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.268 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.388      ;
+; 0.271 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.391      ;
+; 0.294 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.413      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.309 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.428      ;
+; 0.310 ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.430      ;
+; 0.311 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.431      ;
+; 0.313 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.433      ;
+; 0.314 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.434      ;
+; 0.325 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.445      ;
+; 0.369 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.489      ;
+; 0.370 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.490      ;
+; 0.377 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.497      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
+; 0.435 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.555      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.773 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.842      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.775 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.846      ;
+; 0.809 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.860      ;
+; 0.811 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.354     ; 1.864      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.853 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.652      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.854 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.502     ; 1.651      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.654      ;
+; 0.855 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.655      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.498     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.858 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.653      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.504     ; 1.643      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.860 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.646      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
+; 0.861 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.643      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 17.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.978      ;
+; 17.093 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.975      ;
+; 17.155 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.913      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.796      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.182 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.793      ;
+; 17.204 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.856      ;
+; 17.228 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.061      ; 2.840      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.244 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.731      ;
+; 17.285 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.775      ;
+; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.772      ;
+; 17.288 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.772      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.674      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.032     ; 2.658      ;
+; 17.348 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.712      ;
+; 17.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; 0.053      ; 2.710      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
+; 17.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.040     ; 2.593      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.904 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.019      ;
+; 0.933 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.157      ; 1.174      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 0.986 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.031      ; 1.101      ;
+; 1.015 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.157      ; 1.256      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.350 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.473      ;
+; 1.379 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.165      ; 1.628      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.635      ;
+; 1.541 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.165      ; 1.790      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.039      ; 1.698      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
+; 1.588 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.714      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.489      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.487      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.416 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.005     ; 1.495      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.006     ; 1.495      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.496      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.015     ; 1.489      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.420 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.487      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.421 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.492      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.495      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.494      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.013     ; 1.495      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.011     ; 1.497      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
+; 2.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.494      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_address_reg0    ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_we_reg          ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.751 ; 3.981        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a6~porta_datain_reg0     ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ;
+; 3.782 ; 3.966        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                            ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                        ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]         ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]             ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                           ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                            ;
+; 9.265 ; 9.449        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                            ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]                  ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]                  ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]                   ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                          ;
+; 9.266 ; 9.450        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                            ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]               ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                ;
+; 9.279 ; 9.463        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                          ;
+; 9.357 ; 9.541        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                  ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0]           ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1]           ;
+; 9.425 ; 9.425        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|observablevcoout ;
+; 9.441 ; 9.441        ; 0.000          ; Low Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50~input|o                                              ;
++-------+--------------+----------------+-----------------+----------+------------+---------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 2.203 ; 3.113 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 2.203 ; 3.113 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 1.819 ; 2.590 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.569 ; 3.369 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.569 ; 3.369 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.420 ; 3.241 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.344 ; 3.086 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.289 ; 3.048 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.279 ; 3.037 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.147 ; 2.890 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.153 ; 2.902 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.137 ; 2.886 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.859 ; -1.656 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.164 ; -2.955 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.015 ; -2.819 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.949 ; -2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.891 ; -2.635 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.881 ; -2.624 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.754 ; -2.483 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.760 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.186  ; 4.306  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.186  ; 4.306  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.118  ; 4.091  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.959  ; 2.978  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.959  ; 2.978  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.218  ; 3.178  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.268  ; 2.285  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.233  ; 2.237  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.268  ; 2.285  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.192  ; 2.204  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.244  ; 2.273  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.168  ; 2.172  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.145  ; 2.152  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.161  ; 2.163  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.060  ; 2.058  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.125  ; 2.133  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.167  ; 2.176  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.142  ; 2.137  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.057  ; 2.060  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.156  ; 2.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.183  ; 2.200  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.140  ; 2.153  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.205  ; 2.203  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 5.019  ; 4.759  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.533  ; 3.460  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.588  ; 3.529  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.549  ; 3.512  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.019  ; 4.759  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 3.466  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.426  ; 3.430  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.769  ; 3.755  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 3.438  ; 3.426  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.339  ; 3.455  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.129  ; 3.157  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.327  ; 3.428  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.279  ; 3.193  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.442  ; 3.391  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 3.224  ; 3.315  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.656  ; 3.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.402  ; 3.371  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.164  ; 2.170  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.250  ; 2.268  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.082  ; 2.069  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.681  ; 3.498  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.313 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.366 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.082  ; 4.194  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.148  ; 3.113  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.967  ; 1.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.000  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.929  ; 1.937  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.977  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.904  ; 1.905  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.882  ; 1.886  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.897  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.802  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.862  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.903  ; 1.908  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.880  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.892  ; 1.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.918  ; 1.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.876  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.938  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.617  ; 2.649  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.573  ; 2.625  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.537  ; 2.592  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.994  ; 3.818  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.916  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.630  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.743  ; 2.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.644  ; 2.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.505  ; 2.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.610  ; 2.654  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.815  ; 2.798  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.486  ; 2.520  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.582  ; 2.618  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.580  ; 2.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.469  ; 2.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.900  ; 1.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.982  ; 1.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.822  ; 1.806  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.418  ; 3.230  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.878 ; 2.859 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.888 ; 2.869 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.774 ; 2.755 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.984 ; 2.965 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.878 ; 2.859 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.004 ; 2.985 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.981 ; 2.962 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.605 ; 2.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.605 ; 2.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.608 ; 2.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.595 ; 2.576 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.598 ; 2.579 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.608 ; 2.589 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.984 ; 2.965 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.746 ; 1.746 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.756 ; 1.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.646 ; 1.646 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.848 ; 1.848 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.746 ; 1.746 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.868 ; 1.868 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.845 ; 1.845 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.486 ; 1.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.486 ; 1.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.488 ; 1.488 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.476 ; 1.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.478 ; 1.478 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.488 ; 1.488 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.468 ; 1.468 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.848 ; 1.848 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.966     ; 2.966     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.976     ; 2.976     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.841     ; 2.841     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.081     ; 3.081     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.966     ; 2.966     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.101     ; 3.101     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.083     ; 3.083     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.651     ; 2.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.651     ; 2.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.652     ; 2.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.641     ; 2.641     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.642     ; 2.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.652     ; 2.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.632     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.081     ; 3.081     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.831     ; 1.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.841     ; 1.973     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.711     ; 1.843     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.941     ; 2.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.831     ; 1.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.961     ; 2.093     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.943     ; 2.075     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.529     ; 1.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.529     ; 1.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.530     ; 1.662     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.519     ; 1.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.520     ; 1.652     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.530     ; 1.662     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.510     ; 1.642     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.941     ; 2.073     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 13.232 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.232                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.589        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.643        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.350                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.443        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.907        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.383                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.790        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.435                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.400        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.035        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.440                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.916        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.456                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.932        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.483                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.588        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.895        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.493                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.902        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.503                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.102        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.535                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.009        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.536                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.011        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.176        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.581                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.991        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.585                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.183        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.594                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.522        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.072        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.596                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.003        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.602                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.077        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.615                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.088        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.626                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.102        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.653                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.451        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.202        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.659                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.067        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.664                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.404        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.260        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.672                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.325        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.347        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.689                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.166        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.691                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.164        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.702                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.450        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.252        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.721                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.472        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.734                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.142        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.735                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.145        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.736                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.334        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.793                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.599        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.194        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.821                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.230        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.899                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.308        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.926                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.333        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.971                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.378        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.024                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.497        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.082                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.490        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.127                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.535        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.191                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.600        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.591        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.273                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.747        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Clock                                                ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack                                     ; -0.454  ; 0.116 ; -1.497   ; 0.904   ; 3.736               ;
+;  CLOCK_50                                            ; 15.170  ; 0.187 ; 14.980   ; 0.904   ; 9.265               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.454  ; 0.116 ; -1.497   ; 2.414   ; 3.736               ;
+; Design-wide TNS                                      ; -22.246 ; 0.0   ; -338.162 ; 0.0     ; 0.0                 ;
+;  CLOCK_50                                            ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -22.246 ; 0.000 ; -338.162 ; 0.000   ; 0.000               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.050 ; 4.731 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.252 ; 3.792 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 4.454 ; 5.044 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 4.228 ; 4.804 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 4.088 ; 4.586 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.985 ; 4.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.971 ; 4.476 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.720 ; 4.223 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.722 ; 4.235 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.708 ; 4.219 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -0.859 ; -1.656 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -0.819 ; -1.598 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.164 ; -2.955 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.015 ; -2.819 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.949 ; -2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.891 ; -2.635 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.881 ; -2.624 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.754 ; -2.483 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.760 ; -2.494 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.744 ; -2.479 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 7.004  ; 7.069  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.882  ; 6.755  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 4.954  ; 4.908  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.291  ; 5.346  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.733  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.702  ; 3.596  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.732  ; 3.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.589  ; 3.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.733  ; 3.638  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.576  ; 3.509  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.533  ; 3.439  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.580  ; 3.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.373  ; 3.274  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.536  ; 3.433  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.594  ; 3.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.526  ; 3.425  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.389  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.546  ; 3.449  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.624  ; 3.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.569  ; 3.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.685  ; 3.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.853  ; 5.686  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.923  ; 5.772  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.841  ; 5.703  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.764  ; 7.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.747  ; 5.603  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.667  ; 5.552  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 6.210  ; 6.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.690  ; 5.589  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.631  ; 5.599  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.178  ; 5.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.631  ; 5.557  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.436  ; 5.269  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.663  ; 5.519  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.466  ; 5.409  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 6.063  ; 5.900  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.624  ; 5.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.597  ; 3.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.733  ; 3.650  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.442  ; 3.340  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.583  ; 5.291  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 4.082  ; 4.194  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 4.014  ; 3.986  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 2.902  ; 2.917  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.148  ; 3.113  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.967  ; 1.967  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.000  ; 2.014  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.929  ; 1.937  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.977  ; 2.002  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.904  ; 1.905  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.882  ; 1.886  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.897  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.802  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.862  ; 1.866  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.903  ; 1.908  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.880  ; 1.872  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.797  ; 1.796  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.892  ; 1.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.918  ; 1.931  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.876  ; 1.885  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.938  ; 1.933  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.617  ; 2.649  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.573  ; 2.625  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.537  ; 2.592  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.994  ; 3.818  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.916  ; 2.995  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.630  ; 2.706  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.743  ; 2.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.644  ; 2.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.505  ; 2.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.610  ; 2.654  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.815  ; 2.798  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.486  ; 2.520  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.265  ; 2.279  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.582  ; 2.618  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.580  ; 2.619  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.469  ; 2.493  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.900  ; 1.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.982  ; 1.996  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.822  ; 1.806  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.418  ; 3.230  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                       ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin              ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; GPIO_1_CLKIN[1]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[15]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[14]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[13]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[12]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[11]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[10]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[9]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[8]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[31]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[30]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[29]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[28]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[27]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[26]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[25]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[24]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[23]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[22]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[21]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[20]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[19]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[18]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[17]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[16]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[15]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[14]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[13]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[12]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[11]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1_CLKIN[0]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                       ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3186     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3186     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11681    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                           ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                            ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 3     ; 3    ;
+; Unconstrained Input Ports       ; 29    ; 29   ;
+; Unconstrained Input Port Paths  ; 102   ; 102  ;
+; Unconstrained Output Ports      ; 94    ; 94   ;
+; Unconstrained Output Port Paths ; 472   ; 472  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 10:02:46 2014
+Info: Command: quartus_sta DE0_D5M -c DE0_D5M
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.454
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.454             -22.246 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.170               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.214
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.214               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.358               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -1.497
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.497            -338.162 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.980               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.616
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.616               0.000 CLOCK_50 
+    Info (332119):     4.132               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.736
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.736               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.580               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.051 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 0.053
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.053               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.677               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.190
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.190               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.312               0.000 CLOCK_50 
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case recovery slack is -0.843
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.843            -150.984 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.539               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.477
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.477               0.000 CLOCK_50 
+    Info (332119):     3.638               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.741
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.741               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.561               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.581 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Fast 1200mV 0C Model
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 1.424
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.424               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.244               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.116
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.116               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.187               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is 0.773
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.773               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    17.090               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 0.904
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.904               0.000 CLOCK_50 
+    Info (332119):     2.414               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.748
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.748               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.265               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 13.232 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 23 warnings
+    Info: Peak virtual memory: 549 megabytes
+    Info: Processing ended: Mon Mar 17 10:02:50 2014
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary
new file mode 100644
index 0000000..4fbf355
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.sta.summary
@@ -0,0 +1,125 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.454
+TNS   : -22.246
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : 15.170
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.214
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.497
+TNS   : -338.162
+
+Type  : Slow 1200mV 85C Model Recovery 'CLOCK_50'
+Slack : 14.980
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'CLOCK_50'
+Slack : 1.616
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.132
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.736
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.580
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.053
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 15.677
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.190
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.843
+TNS   : -150.984
+
+Type  : Slow 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 15.539
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 1.477
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.638
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.741
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.561
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.424
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 17.244
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.116
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.187
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.773
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 17.090
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 0.904
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 2.414
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.748
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.265
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..8a35815
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v
new file mode 100644
index 0000000..91386f2
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v
@@ -0,0 +1,353 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[3:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[3:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[3:0]		VGA_B;   				//	VGA Blue[9:0]
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; //GPIO_1[0];
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:6];
+assign	VGA_G		=	oVGA_G[9:6];
+assign	VGA_B		=	oVGA_B[9:6];
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak
new file mode 100644
index 0000000..1ff6dd3
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE0_D5M.v.bak
@@ -0,0 +1,435 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE1 D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module DE1_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_24,						//	24 MHz
+		CLOCK_27,						//	27 MHz
+		CLOCK_50,						//	50 MHz
+		EXT_CLOCK,						//	External Clock
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[3:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[7:0]
+		LEDR,								//	LED Red[9:0]
+		////////////////////////	UART	////////////////////////
+		UART_TXD,						//	UART Transmitter
+		UART_RXD,						//	UART Receiver
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	Flash Interface		////////////////
+		FL_DQ,							//	FLASH Data bus 8 Bits
+		FL_ADDR,							//	FLASH Address bus 22 Bits
+		FL_WE_N,							//	FLASH Write Enable
+		FL_RST_N,						//	FLASH Reset
+		FL_OE_N,							//	FLASH Output Enable
+		FL_CE_N,							//	FLASH Chip Enable
+		////////////////////	SRAM Interface		////////////////
+		SRAM_DQ,							//	SRAM Data bus 16 Bits
+		SRAM_ADDR,						//	SRAM Address bus 18 Bits
+		SRAM_UB_N,						//	SRAM High-byte Data Mask 
+		SRAM_LB_N,						//	SRAM Low-byte Data Mask 
+		SRAM_WE_N,						//	SRAM Write Enable
+		SRAM_CE_N,						//	SRAM Chip Enable
+		SRAM_OE_N,						//	SRAM Output Enable
+		////////////////////	SD_Card Interface	////////////////
+		SD_DAT,							//	SD Card Data
+		SD_DAT3,							//	SD Card Data 3
+		SD_CMD,							//	SD Card Command Signal
+		SD_CLK,							//	SD Card Clock
+		////////////////////	USB JTAG link	////////////////////
+		TDI,  							// CPLD -> FPGA (data in)
+		TCK,  							// CPLD -> FPGA (clk)
+		TCS,  							// CPLD -> FPGA (CS)
+	    TDO,  							// FPGA -> CPLD (data out)
+		////////////////////	I2C		////////////////////////////
+		I2C_SDAT,						//	I2C Data
+		I2C_SCLK,						//	I2C Clock
+		////////////////////	PS2		////////////////////////////
+		PS2_DAT,							//	PS2 Data
+		PS2_CLK,							//	PS2 Clock
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		////////////////	Audio CODEC		////////////////////////
+		AUD_ADCLRCK,					//	Audio CODEC ADC LR Clock
+		AUD_ADCDAT,						//	Audio CODEC ADC Data
+		AUD_DACLRCK,					//	Audio CODEC DAC LR Clock
+		AUD_DACDAT,						//	Audio CODEC DAC Data
+		AUD_BCLK,						//	Audio CODEC Bit-Stream Clock
+		AUD_XCK,							//	Audio CODEC Chip Clock
+		////////////////////	GPIO	////////////////////////////
+		GPIO_0,							//	GPIO Connection 0
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input	[1:0]	CLOCK_24;				//	24 MHz
+input	[1:0]	CLOCK_27;				//	27 MHz
+input			CLOCK_50;				//	50 MHz
+input			EXT_CLOCK;				//	External Clock
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+////////////////////////////	LED		////////////////////////////
+output	[7:0]	LEDG;					//	LED Green[7:0]
+output	[9:0]	LEDR;					//	LED Red[9:0]
+////////////////////////////	UART	////////////////////////////
+output			UART_TXD;			//	UART Transmitter
+input				UART_RXD;			//	UART Receiver
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	Flash Interface	////////////////////////
+inout	[7:0]		FL_DQ;				//	FLASH Data bus 8 Bits
+output[21:0]	FL_ADDR;				//	FLASH Address bus 22 Bits
+output			FL_WE_N;				//	FLASH Write Enable
+output			FL_RST_N;			//	FLASH Reset
+output			FL_OE_N;				//	FLASH Output Enable
+output			FL_CE_N;				//	FLASH Chip Enable
+////////////////////////	SRAM Interface	////////////////////////
+inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
+output[17:0]	SRAM_ADDR;			//	SRAM Address bus 18 Bits
+output			SRAM_UB_N;			//	SRAM High-byte Data Mask 
+output			SRAM_LB_N;			//	SRAM Low-byte Data Mask 
+output			SRAM_WE_N;			// SRAM Write Enable
+output			SRAM_CE_N;			//	SRAM Chip Enable
+output			SRAM_OE_N;			//	SRAM Output Enable
+////////////////////	SD Card Interface	////////////////////////
+inout				SD_DAT;				//	SD Card Data
+inout				SD_DAT3;				//	SD Card Data 3
+inout				SD_CMD;				//	SD Card Command Signal
+output			SD_CLK;				//	SD Card Clock
+////////////////////////	I2C		////////////////////////////////
+inout				I2C_SDAT;			//	I2C Data
+output			I2C_SCLK;			//	I2C Clock
+////////////////////////	PS2		////////////////////////////////
+input		 		PS2_DAT;				//	PS2 Data
+input				PS2_CLK;				//	PS2 Clock
+////////////////////	USB JTAG link	////////////////////////////
+input  			TDI;					// CPLD -> FPGA (data in)
+input  			TCK;					// CPLD -> FPGA (clk)
+input  			TCS;					// CPLD -> FPGA (CS)
+output 			TDO;					// FPGA -> CPLD (data out)
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+////////////////////	Audio CODEC		////////////////////////////
+inout				AUD_ADCLRCK;		//	Audio CODEC ADC LR Clock
+input				AUD_ADCDAT;			//	Audio CODEC ADC Data
+inout				AUD_DACLRCK;		//	Audio CODEC DAC LR Clock
+output			AUD_DACDAT;			//	Audio CODEC DAC Data
+inout				AUD_BCLK;			//	Audio CODEC Bit-Stream Clock
+output			AUD_XCK;				//	Audio CODEC Chip Clock
+////////////////////////	GPIO	////////////////////////////////
+inout	[31:0]	GPIO_0;				//	GPIO Connection 0
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[3:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[3:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[3:0]		VGA_B;   				//	VGA Blue[9:0]
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[13];
+assign	CCD_DATA[1]	=	GPIO_1[12];
+assign	CCD_DATA[2]	=	GPIO_1[11];
+assign	CCD_DATA[3]	=	GPIO_1[10];
+assign	CCD_DATA[4]	=	GPIO_1[9];
+assign	CCD_DATA[5]	=	GPIO_1[8];
+assign	CCD_DATA[6]	=	GPIO_1[7];
+assign	CCD_DATA[7]	=	GPIO_1[6];
+assign	CCD_DATA[8]	=	GPIO_1[5];
+assign	CCD_DATA[9]	=	GPIO_1[4];
+assign	CCD_DATA[10]=	GPIO_1[3];
+assign	CCD_DATA[11]=	GPIO_1[1];
+assign	GPIO_1[16]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[22];
+assign	CCD_LVAL	   =	GPIO_1[21];
+assign	CCD_PIXCLK	=	GPIO_1[0];
+assign	GPIO_1[19]	=	1'b1;  // tRIGGER
+assign	GPIO_1[17]	=	DLY_RST_1;
+
+assign	LEDR		   =	SW;
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:6];
+assign	VGA_G		=	oVGA_G[9:6];
+assign	VGA_B		=	oVGA_B[9:6];
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!SW[3]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+assign	UART_TXD = UART_RXD;
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[8]),
+								 .iEXPOSURE_ADJ  (KEY[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[24]),
+								 .I2C_SDAT		  (GPIO_1[23])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf
new file mode 100644
index 0000000..cdf6850
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/DE1_D5M_assignment_defaults.qdf
@@ -0,0 +1,642 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Internal Build 220 05/13/2009 Service Pack 2 SJ Full Version
+# Date created = 19:24:48  May 26, 2009
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family ACEX1K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KA
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10K
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family APEX20KC
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX6000
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "APEX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family FLEX10KE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family ACEX1K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KA
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10K
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family APEX20KC
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX6000
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "APEX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family FLEX10KE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS Off
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name SAVE_INTERMEDIATE_FITTING_RESULTS Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family ACEX1K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KA
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10K
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family APEX20KC
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX6000
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "APEX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family FLEX10KE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -value OFF
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION -value OFF
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Line_Buffer.qip
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v
new file mode 100644
index 0000000..22e2411
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Control_4Port.v
@@ -0,0 +1,567 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Sdram_Control_4Port
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module Sdram_Control_4Port(
+		//	HOST Side
+        REF_CLK,
+        RESET_N,
+		CLK,
+		//	FIFO Write Side 1
+        WR1_DATA,
+		WR1,
+		WR1_ADDR,
+		WR1_MAX_ADDR,
+		WR1_LENGTH,
+		WR1_LOAD,
+		WR1_CLK,
+		//	FIFO Write Side 2
+        WR2_DATA,
+		WR2,
+		WR2_ADDR,
+		WR2_MAX_ADDR,
+		WR2_LENGTH,
+		WR2_LOAD,
+		WR2_CLK,
+		//	FIFO Read Side 1
+        RD1_DATA,
+		RD1,
+		RD1_ADDR,
+		RD1_MAX_ADDR,
+		RD1_LENGTH,
+		RD1_LOAD,	
+		RD1_CLK,
+		//	FIFO Read Side 2
+        RD2_DATA,
+		RD2,
+		RD2_ADDR,
+		RD2_MAX_ADDR,
+		RD2_LENGTH,
+		RD2_LOAD,
+		RD2_CLK,
+		//	SDRAM Side
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N,
+        DQ,
+        DQM,
+        );
+
+
+`include        "Sdram_Params.h"
+//	HOST Side
+input                           REF_CLK;                //System Clock
+input                           RESET_N;                //System Reset
+input 							CLK;
+//	FIFO Write Side 1
+input   [`DSIZE-1:0]            WR1_DATA;               //Data input
+input							WR1;					//Write Request
+input	[`ASIZE-1:0]			WR1_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR1_MAX_ADDR;			//Write max address
+input	[8:0]					WR1_LENGTH;				//Write length
+input							WR1_LOAD;				//Write register load & fifo clear
+input							WR1_CLK;				//Write fifo clock
+
+//	FIFO Write Side 2
+input   [`DSIZE-1:0]            WR2_DATA;               //Data input
+input							WR2;					//Write Request
+input	[`ASIZE-1:0]			WR2_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR2_MAX_ADDR;			//Write max address
+input	[8:0]					WR2_LENGTH;				//Write length
+input							WR2_LOAD;				//Write register load & fifo clear
+input							WR2_CLK;				//Write fifo clock
+
+//	FIFO Read Side 1
+output  [`DSIZE-1:0]            RD1_DATA;               //Data output
+input							RD1;					//Read Request
+input	[`ASIZE-1:0]			RD1_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD1_MAX_ADDR;			//Read max address
+input	[8:0]					RD1_LENGTH;				//Read length
+input							RD1_LOAD;				//Read register load & fifo clear
+input							RD1_CLK;				//Read fifo clock
+
+//	FIFO Read Side 2
+output  [`DSIZE-1:0]            RD2_DATA;               //Data output
+input							RD2;					//Read Request
+input	[`ASIZE-1:0]			RD2_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD2_MAX_ADDR;			//Read max address
+input	[8:0]					RD2_LENGTH;				//Read length
+input							RD2_LOAD;				//Read register load & fifo clear
+input							RD2_CLK;				//Read fifo clock
+
+//	SDRAM Side
+output  [11:0]                  SA;                     //SDRAM address output
+output  [1:0]                   BA;                     //SDRAM bank address
+output  [1:0]                   CS_N;                   //SDRAM Chip Selects
+output                          CKE;                    //SDRAM clock enable
+output                          RAS_N;                  //SDRAM Row address Strobe
+output                          CAS_N;                  //SDRAM Column address Strobe
+output                          WE_N;                   //SDRAM write enable
+inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
+output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+
+//	Internal Registers/Wires
+//	Controller
+reg		[`ASIZE-1:0]			mADDR;					//Internal address
+reg		[8:0]					mLENGTH;				//Internal length
+reg		[`ASIZE-1:0]			rWR1_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR1_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR1_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rWR2_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR2_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR2_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rRD1_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD1_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD1_LENGTH;			//Register read length
+reg		[`ASIZE-1:0]			rRD2_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD2_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD2_LENGTH;			//Register read length
+reg		[1:0]					WR_MASK;				//Write port active mask
+reg		[1:0]					RD_MASK;				//Read port active mask
+reg								mWR_DONE;				//Flag write done, 1 pulse SDR_CLK
+reg								mRD_DONE;				//Flag read done, 1 pulse SDR_CLK
+reg								mWR,Pre_WR;				//Internal WR edge capture
+reg								mRD,Pre_RD;				//Internal RD edge capture
+reg 	[9:0] 					ST;						//Controller status
+reg		[1:0] 					CMD;					//Controller command
+reg								PM_STOP;				//Flag page mode stop
+reg								PM_DONE;				//Flag page mode done
+reg								Read;					//Flag read active
+reg								Write;					//Flag write active
+reg	    [`DSIZE-1:0]           	mDATAOUT;               //Controller Data output
+wire    [`DSIZE-1:0]           	mDATAIN;                //Controller Data input
+wire    [`DSIZE-1:0]           	mDATAIN1;                //Controller Data input 1
+wire    [`DSIZE-1:0]           	mDATAIN2;                //Controller Data input 2
+wire                          	CMDACK;                 //Controller command acknowledgement
+//	DRAM Control
+reg  	[`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+reg     [11:0]                  SA;                     //SDRAM address output
+reg     [1:0]                   BA;                     //SDRAM bank address
+reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
+reg                             CKE;                    //SDRAM clock enable
+reg                             RAS_N;                  //SDRAM Row address Strobe
+reg                             CAS_N;                  //SDRAM Column address Strobe
+reg                             WE_N;                   //SDRAM write enable
+wire    [`DSIZE-1:0]            DQOUT;					//SDRAM data out link
+wire  	[`DSIZE/8-1:0]          IDQM;                   //SDRAM data mask lines
+wire    [11:0]                  ISA;                    //SDRAM address output
+wire    [1:0]                   IBA;                    //SDRAM bank address
+wire    [1:0]                   ICS_N;                  //SDRAM Chip Selects
+wire                            ICKE;                   //SDRAM clock enable
+wire                            IRAS_N;                 //SDRAM Row address Strobe
+wire                            ICAS_N;                 //SDRAM Column address Strobe
+wire                            IWE_N;                  //SDRAM write enable
+//	FIFO Control
+reg								OUT_VALID;				//Output data request to read side fifo
+reg								IN_REQ;					//Input	data request to write side fifo
+wire	[8:0]					write_side_fifo_rusedw1;
+wire	[8:0]					read_side_fifo_wusedw1;
+wire	[8:0]					write_side_fifo_rusedw2;
+wire	[8:0]					read_side_fifo_wusedw2;
+//	DRAM Internal Control
+wire    [`ASIZE-1:0]            saddr;
+wire                            load_mode;
+wire                            nop;
+wire                            reada;
+wire                            writea;
+wire                            refresh;
+wire                            precharge;
+wire                            oe;
+wire							ref_ack;
+wire							ref_req;
+wire							init_req;
+wire							cm_ack;
+wire							active;
+wire                            CLK;
+wire							CCD_CLK;
+
+control_interface control1 (
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .CMD(CMD),
+                .ADDR(mADDR),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+                .PRECHARGE(precharge),
+                .LOAD_MODE(load_mode),
+                .SADDR(saddr),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .CMD_ACK(CMDACK)
+                );
+
+command command1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .SADDR(saddr),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+				.LOAD_MODE(load_mode),
+                .PRECHARGE(precharge),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .OE(oe),
+				.PM_STOP(PM_STOP),
+				.PM_DONE(PM_DONE),
+                .SA(ISA),
+                .BA(IBA),
+                .CS_N(ICS_N),
+                .CKE(ICKE),
+                .RAS_N(IRAS_N),
+                .CAS_N(ICAS_N),
+                .WE_N(IWE_N)
+                );
+                
+sdr_data_path data_path1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .DATAIN(mDATAIN),
+                .DM(2'b00),
+                .DQOUT(DQOUT),
+                .DQM(IDQM)
+                );
+
+Sdram_FIFO 	write_fifo1(
+				.data(WR1_DATA),
+				.wrreq(WR1),
+				.wrclk(WR1_CLK),
+				.aclr(WR1_LOAD),
+				.rdreq(IN_REQ&WR_MASK[0]),
+				.rdclk(CLK),
+				.q(mDATAIN1),
+				.rdusedw(write_side_fifo_rusedw1)
+				);
+
+Sdram_FIFO 	write_fifo2(
+				.data(WR2_DATA),
+				.wrreq(WR2),
+				.wrclk(WR2_CLK),
+				.aclr(WR2_LOAD),
+				.rdreq(IN_REQ&WR_MASK[1]),
+				.rdclk(CLK),
+				.q(mDATAIN2),
+				.rdusedw(write_side_fifo_rusedw2)
+				);
+				
+assign	mDATAIN	=	(WR_MASK[0])	?	mDATAIN1	:
+										mDATAIN2	;
+
+Sdram_FIFO 	read_fifo1(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[0]),
+				.wrclk(CLK),
+				.aclr(RD1_LOAD),
+				.rdreq(RD1),
+				.rdclk(RD1_CLK),
+				.q(RD1_DATA),
+				.wrusedw(read_side_fifo_wusedw1)
+				);
+				
+Sdram_FIFO 	read_fifo2(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[1]),
+				.wrclk(CLK),
+				.aclr(RD2_LOAD),
+				.rdreq(RD2),
+				.rdclk(RD2_CLK),
+				.q(RD2_DATA),
+				.wrusedw(read_side_fifo_wusedw2)
+				);
+
+always @(posedge CLK)
+begin
+	SA      <= (ST==SC_CL+mLENGTH)			?	12'h200	:	ISA;
+    BA      <= IBA;
+    CS_N    <= ICS_N;
+    CKE     <= ICKE;
+    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
+    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
+    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
+	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
+	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
+	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
+	mDATAOUT<= DQ;
+end
+
+assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
+assign	active	=	Read | Write;
+
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(RESET_N==0)
+	begin
+		CMD			<=  0;
+		ST			<=  0;
+		Pre_RD		<=  0;
+		Pre_WR		<=  0;
+		Read		<=	0;
+		Write		<=	0;
+		OUT_VALID	<=	0;
+		IN_REQ		<=	0;
+		mWR_DONE	<=	0;
+		mRD_DONE	<=	0;
+	end
+	else
+	begin
+		Pre_RD	<=	mRD;
+		Pre_WR	<=	mWR;
+		case(ST)
+		0:	begin
+				if({Pre_RD,mRD}==2'b01)
+				begin
+					Read	<=	1;
+					Write	<=	0;
+					CMD		<=	2'b01;
+					ST		<=	1;
+				end
+				else if({Pre_WR,mWR}==2'b01)
+				begin
+					Read	<=	0;
+					Write	<=	1;
+					CMD		<=	2'b10;
+					ST		<=	1;
+				end
+			end
+		1:	begin
+				if(CMDACK==1)
+				begin
+					CMD<=2'b00;
+					ST<=2;
+				end
+			end
+		default:	
+			begin	
+				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
+				ST<=ST+1;
+				else
+				ST<=0;
+			end
+		endcase
+	
+		if(Read)
+		begin
+			if(ST==SC_CL+SC_RCD+1)
+			OUT_VALID	<=	1;
+			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
+			begin
+				OUT_VALID	<=	0;
+				Read		<=	0;
+				mRD_DONE	<=	1;
+			end
+		end
+		else
+		mRD_DONE	<=	0;
+		
+		if(Write)
+		begin
+			if(ST==SC_CL-1)
+			IN_REQ	<=	1;
+			else if(ST==SC_CL+mLENGTH-1)
+			IN_REQ	<=	0;
+			else if(ST==SC_CL+SC_RCD+mLENGTH)
+			begin
+				Write	<=	0;
+				mWR_DONE<=	1;
+			end
+		end
+		else
+		mWR_DONE<=	0;
+
+	end
+end
+//	Internal Address & Length Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		rWR1_ADDR		<=	0;
+		rWR2_ADDR		<=	22'h100000;
+		rRD1_ADDR		<=	0;
+		rRD2_ADDR		<=	22'h100000;
+		rWR1_MAX_ADDR	<=	640*480;
+		rWR2_MAX_ADDR	<=	22'h100000+640*480;
+		rRD1_MAX_ADDR	<=	640*480;
+		rRD2_MAX_ADDR	<=	22'h100000+640*480;
+		rWR1_LENGTH		<=	256;
+		rWR2_LENGTH		<=	256;
+		rRD1_LENGTH		<=	256;
+		rRD2_LENGTH		<=	256;
+	end
+	else
+	begin
+		//	Write Side 1
+		if(WR1_LOAD)
+		begin
+			rWR1_ADDR	<=	WR1_ADDR;
+			rWR1_LENGTH	<=	WR1_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[0])
+		begin
+			if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
+				rWR1_ADDR	<=	rWR1_ADDR+rWR1_LENGTH;
+			else
+				rWR1_ADDR	<=	WR1_ADDR;
+		end
+		//	Write Side 2
+		if(WR2_LOAD)
+		begin
+			rWR2_ADDR	<=	WR2_ADDR;
+			rWR2_LENGTH	<=	WR2_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[1])
+		begin
+			if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
+				rWR2_ADDR	<=	rWR2_ADDR+rWR2_LENGTH;
+			else
+				rWR2_ADDR	<=	WR2_ADDR;
+		end
+		//	Read Side 1
+		if(RD1_LOAD)
+		begin
+			rRD1_ADDR	<=	RD1_ADDR;
+			rRD1_LENGTH	<=	RD1_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[0])
+		begin
+			if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
+				rRD1_ADDR	<=	rRD1_ADDR+rRD1_LENGTH;
+			else
+				rRD1_ADDR	<=	RD1_ADDR;
+		end
+		//	Read Side 2
+		if(RD2_LOAD)
+		begin
+			rRD2_ADDR	<=	RD2_ADDR;
+			rRD2_LENGTH	<=	RD2_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[1])
+		begin
+			if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
+				rRD2_ADDR	<=	rRD2_ADDR+rRD2_LENGTH;
+			else
+				rRD2_ADDR	<=	RD2_ADDR;
+		end
+	end
+end
+//	Auto Read/Write Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		mWR		<=	0;
+		mRD		<=	0;
+		mADDR	<=	0;
+		mLENGTH	<=	0;
+	end
+	else
+	begin
+		if( (mWR==0) && (mRD==0) && (ST==0) &&
+			(WR_MASK==0)	&&	(RD_MASK==0) &&
+			(WR1_LOAD==0)	&&	(RD1_LOAD==0) &&
+			(WR2_LOAD==0)	&&	(RD2_LOAD==0) )
+		begin
+			//	Write Side 1
+			if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR1_ADDR;
+				mLENGTH	<=	rWR1_LENGTH;
+				WR_MASK	<=	2'b01;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Write Side 2
+			else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR2_ADDR;
+				mLENGTH	<=	rWR2_LENGTH;
+				WR_MASK	<=	2'b10;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Read Side 1
+			else if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
+			begin
+				mADDR	<=	rRD1_ADDR;
+				mLENGTH	<=	rRD1_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b01;
+				mWR		<=	0;
+				mRD		<=	1;				
+			end
+			//	Read Side 2
+			else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
+			begin
+				mADDR	<=	rRD2_ADDR;
+				mLENGTH	<=	rRD2_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b10;
+				mWR		<=	0;
+				mRD		<=	1;
+			end
+		end
+		if(mWR_DONE)
+		begin
+			WR_MASK	<=	0;
+			mWR		<=	0;
+		end
+		if(mRD_DONE)
+		begin
+			RD_MASK	<=	0;
+			mRD		<=	0;
+		end
+	end
+end
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip
new file mode 100644
index 0000000..ceca5c0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_FIFO.v"]
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v
new file mode 100644
index 0000000..af2662b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_FIFO.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: Sdram_FIFO.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Sdram_FIFO (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[8:0]  rdusedw;
+	output	  wrfull;
+	output	[8:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [15:0] sub_wire1;
+	wire  sub_wire2;
+	wire [8:0] sub_wire3;
+	wire [8:0] sub_wire4;
+	wire  wrfull = sub_wire0;
+	wire [15:0] q = sub_wire1[15:0];
+	wire  rdempty = sub_wire2;
+	wire [8:0] wrusedw = sub_wire3[8:0];
+	wire [8:0] rdusedw = sub_wire4[8:0];
+
+	dcfifo	dcfifo_component (
+				.rdclk (rdclk),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.aclr (aclr),
+				.data (data),
+				.rdreq (rdreq),
+				.wrfull (sub_wire0),
+				.q (sub_wire1),
+				.rdempty (sub_wire2),
+				.wrusedw (sub_wire3),
+				.rdusedw (sub_wire4),
+				.rdfull (),
+				.wrempty ());
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+ 	
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v
new file mode 100644
index 0000000..8b37dff
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/command.v
@@ -0,0 +1,482 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	command
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module command(
+        CLK,
+        RESET_N,
+        SADDR,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        REF_REQ,
+		INIT_REQ,
+		PM_STOP,
+		PM_DONE,
+        REF_ACK,
+        CM_ACK,
+        OE,
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`ASIZE-1:0]            SADDR;                  // Address
+input                           NOP;                    // Decoded NOP command
+input                           READA;                  // Decoded READA command
+input                           WRITEA;                 // Decoded WRITEA command
+input                           REFRESH;                // Decoded REFRESH command
+input                           PRECHARGE;              // Decoded PRECHARGE command
+input                           LOAD_MODE;              // Decoded LOAD_MODE command
+input                           REF_REQ;                // Hidden refresh request
+input							INIT_REQ;				// Hidden initial request
+input							PM_STOP;				// Page mode stop
+input							PM_DONE;				// Page mode done
+output                          REF_ACK;                // Refresh request acknowledge
+output                          CM_ACK;                 // Command acknowledge
+output                          OE;                     // OE signal for data path module
+output  [11:0]                  SA;                     // SDRAM address
+output  [1:0]                   BA;                     // SDRAM bank address
+output  [1:0]                   CS_N;                   // SDRAM chip selects
+output                          CKE;                    // SDRAM clock enable
+output                          RAS_N;                  // SDRAM RAS
+output                          CAS_N;                  // SDRAM CAS
+output                          WE_N;                   // SDRAM WE_N
+            
+reg                             CM_ACK;
+reg                             REF_ACK;
+reg                             OE;
+reg     [11:0]                  SA;
+reg     [1:0]                   BA;
+reg     [1:0]                   CS_N;
+reg                             CKE;
+reg                             RAS_N;
+reg                             CAS_N;
+reg                             WE_N;
+
+// Internal signals
+reg                             do_reada;
+reg                             do_writea;
+reg                             do_refresh;
+reg                             do_precharge;
+reg                             do_load_mode;
+reg								do_initial;
+reg                             command_done;
+reg     [7:0]                   command_delay;
+reg     [1:0]                   rw_shift;
+reg                             do_act;
+reg                             rw_flag;
+reg                             do_rw;
+reg     [6:0]                   oe_shift;
+reg                             oe1;
+reg                             oe2;
+reg                             oe3;
+reg                             oe4;
+reg     [3:0]                   rp_shift;
+reg                             rp_done;
+reg								ex_read;
+reg								ex_write;
+
+wire    [`ROWSIZE - 1:0]        rowaddr;
+wire    [`COLSIZE - 1:0]        coladdr;
+wire    [`BANKSIZE - 1:0]       bankaddr;
+
+assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
+assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
+assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
+
+// This always block monitors the individual command lines and issues a command
+// to the next stage if there currently another command already running.
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 0;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+        end
+        
+        else
+        begin
+
+//  Issue the appropriate command if the sdram is not currently busy
+			if( INIT_REQ == 1 )
+			begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 1;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+			end
+			else
+			begin
+				do_initial		<= 0;
+				
+                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
+                        & do_reada == 0 & do_writea == 0)
+                        do_refresh <= 1;         
+                else
+                        do_refresh <= 0;
+
+                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
+                begin
+				        do_reada <= 1;
+						ex_read <= 1;
+				end
+                else
+                        do_reada <= 0;
+                    
+                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
+                begin
+				        do_writea <= 1;
+						ex_write <= 1;
+				end
+                else
+                        do_writea <= 0;
+
+                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))	// PRECHARGE
+                        do_precharge <= 1;
+                else
+                        do_precharge <= 0;
+ 
+                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))	// LOADMODE
+                        do_load_mode <= 1;
+                else
+                        do_load_mode <= 0;
+                                               
+// set command_delay shift register and command_done flag
+// The command delay shift register is a timer that is used to ensure that
+// the SDRAM devices have had sufficient time to finish the last command.
+
+                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
+                     | (do_load_mode == 1))
+                begin
+                        command_delay <= 8'b11111111;
+                        command_done  <= 1;
+                        rw_flag <= do_reada;                                                  
+                end
+                
+                else
+                begin
+                        command_done        <= command_delay[0];                // the command_delay shift operation
+                        command_delay		<= (command_delay>>1);
+                end 
+                
+ 
+ // start additional timer that is used for the refresh, writea, reada commands               
+                if (command_delay[0] == 0 & command_done == 1)
+                begin
+                	rp_shift <= 4'b1111;
+                	rp_done <= 1;
+                end
+                else
+                begin						
+					if(SC_PM == 0)
+					begin
+						rp_shift	<= (rp_shift>>1);
+                    	rp_done		<= rp_shift[0];
+					end
+					else
+					begin
+						if( (ex_read == 0) && (ex_write == 0) )
+						begin
+							rp_shift	<= (rp_shift>>1);
+        	            	rp_done		<= rp_shift[0];
+						end
+						else
+						begin
+							if( PM_STOP==1 )
+							begin
+								rp_shift	<= (rp_shift>>1);
+        	      		      	rp_done     <= rp_shift[0];
+								ex_read		<= 1'b0;
+								ex_write	<= 1'b0;
+							end					
+						end
+					end
+                end
+			end
+        end
+end
+
+
+// logic that generates the OE signal for the data path module
+// For normal burst write he duration of OE is dependent on the configured burst length.
+// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
+// and is left on until a PRECHARGE(page burst terminate) is detected.
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                oe_shift <= 0;
+                oe1      <= 0;
+                oe2      <= 0;
+                OE       <= 0;
+        end
+        else
+        begin
+                if (SC_PM == 0)
+                begin
+                        if (do_writea == 1)
+                        begin
+                                if (SC_BL == 1)				//  Set the shift register to the appropriate
+                                        oe_shift <= 0;		// value based on burst length.
+                                else if (SC_BL == 2)
+                                        oe_shift <= 1;
+                                else if (SC_BL == 4)
+                                        oe_shift <= 7;
+                                else if (SC_BL == 8)
+                                        oe_shift <= 127;
+                                oe1 <= 1;
+                        end
+                        else 
+                        begin
+                                oe_shift <= (oe_shift>>1);
+                                oe1  <= oe_shift[0];
+                                oe2  <= oe1;
+                                oe3  <= oe2;
+                                oe4  <= oe3;
+                                if (SC_RCD == 2)
+                                        OE <= oe3;
+                                else
+                                        OE <= oe4;
+                        end
+                end
+                else
+                begin
+                        if (do_writea == 1)					 // OE generation for page mode accesses
+                                oe4   <= 1;
+                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
+                                oe4   <= 0;
+                        OE <= oe4;
+                end
+                               
+        end
+end
+
+
+
+
+// This always block tracks the time between the activate command and the
+// subsequent WRITEA or READA command, RC.  The shift register is set using
+// the configuration register setting SC_RCD. The shift register is loaded with
+// a single '1' with the position within the register dependent on SC_RCD.
+// When the '1' is shifted out of the register it sets so_rw which triggers
+// a writea or reada command
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                rw_shift <= 0;
+                do_rw    <= 0;
+        end
+        
+        else
+        begin
+                
+                if ((do_reada == 1) | (do_writea == 1))
+                begin
+                        if (SC_RCD == 1)                          // Set the shift register
+                                do_rw <= 1;
+                        else if (SC_RCD == 2)
+                                rw_shift <= 1;
+                        else if (SC_RCD == 3)
+                                rw_shift <= 2;
+                end
+                else
+                begin
+                        rw_shift <= (rw_shift>>1);
+                        do_rw    <= rw_shift[0];
+                end 
+        end
+end              
+
+// This always block generates the command acknowledge, CM_ACK, signal.
+// It also generates the acknowledge signal, REF_ACK, that acknowledges
+// a refresh request that was generated by the internal refresh timer circuit.
+always @(posedge CLK or negedge RESET_N) 
+begin
+
+        if (RESET_N == 0) 
+        begin
+                CM_ACK   <= 0;
+                REF_ACK  <= 0;
+        end
+        
+        else
+        begin
+                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
+                        REF_ACK <= 1;
+                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
+                         | (do_load_mode))
+                        CM_ACK <= 1;
+                else
+                begin
+                        REF_ACK <= 0;
+                        CM_ACK  <= 0;
+                end
+        end
+end 
+                    
+
+
+
+
+
+
+// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
+// 
+always @(posedge CLK ) begin
+        if (RESET_N==0) begin
+                SA    <= 0;
+                BA    <= 0;
+                CS_N  <= 1;
+                RAS_N <= 1;
+                CAS_N <= 1;
+                WE_N  <= 1;
+                CKE   <= 0;
+        end
+        else begin
+                CKE <= 1;
+
+// Generate SA 	
+                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
+                        SA <= rowaddr;
+                else
+                        SA <= coladdr;                 // else alway present column address
+                if ((do_rw==1) | (do_precharge))
+                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
+                                                       // don't set it if the controller is in page mode.           
+                if (do_precharge==1 | do_load_mode==1)
+                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
+                else
+                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
+		
+                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
+                        CS_N <= 0;                                    // Select both chip selects if performing
+                else                                                  // refresh, precharge(all) or load_mode
+                begin
+                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
+                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
+                end
+				
+				if(do_load_mode==1)
+				SA	  <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
+
+
+//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
+//depending on the issued command.
+//		
+                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 1;
+                end
+                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 0;
+                end
+                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
+                        RAS_N <= 1;
+                        CAS_N <= 0;
+                        WE_N  <= rw_flag;
+                end
+				else if (do_initial ==1) begin
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;				
+				end
+                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+        end 
+end
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v
new file mode 100644
index 0000000..d7930e2
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/control_interface.v
@@ -0,0 +1,240 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	control_interface
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module control_interface(
+        CLK,
+        RESET_N,
+        CMD,
+        ADDR,
+        REF_ACK,
+		INIT_ACK,
+        CM_ACK,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        SADDR,
+        REF_REQ,
+		INIT_REQ,
+        CMD_ACK
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [2:0]                   CMD;                    // Command input
+input   [`ASIZE-1:0]            ADDR;                   // Address
+input                           REF_ACK;                // Refresh request acknowledge
+input							INIT_ACK;				// Initial request acknowledge
+input                           CM_ACK;                 // Command acknowledge
+output                          NOP;                    // Decoded NOP command
+output                          READA;                  // Decoded READA command
+output                          WRITEA;                 // Decoded WRITEA command
+output                          REFRESH;                // Decoded REFRESH command
+output                          PRECHARGE;              // Decoded PRECHARGE command
+output                          LOAD_MODE;              // Decoded LOAD_MODE command
+output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
+output                          REF_REQ;                // Hidden refresh request
+output                          INIT_REQ;               // Hidden initial request
+output                          CMD_ACK;                // Command acknowledge
+
+
+            
+reg                             NOP;
+reg                             READA;
+reg                             WRITEA;
+reg                             REFRESH;
+reg                             PRECHARGE;
+reg                             LOAD_MODE;
+reg     [`ASIZE-1:0]            SADDR;
+reg                             REF_REQ;
+reg                             INIT_REQ;
+reg                             CMD_ACK;
+
+// Internal signals
+reg     [15:0]                  timer;
+reg		[15:0]					init_timer;
+
+
+
+// Command decode and ADDR register
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                NOP             <= 0;
+                READA           <= 0;
+                WRITEA          <= 0;
+                SADDR           <= 0;
+        end
+        
+        else
+        begin
+        
+                SADDR <= ADDR;                                  // register the address to keep proper
+                                                                // alignment with the command
+                                                             
+                if (CMD == 3'b000)                              // NOP command
+                        NOP <= 1;
+                else
+                        NOP <= 0;
+                        
+                if (CMD == 3'b001)                              // READA command
+                        READA <= 1;
+                else
+                        READA <= 0;
+                 
+                if (CMD == 3'b010)                              // WRITEA command
+                        WRITEA <= 1;
+                else
+                        WRITEA <= 0;
+                        
+        end
+end
+
+
+//  Generate CMD_ACK
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+                CMD_ACK <= 0;
+        else
+                if ((CM_ACK == 1) & (CMD_ACK == 0))
+                        CMD_ACK <= 1;
+                else
+                        CMD_ACK <= 0;
+end
+
+
+// refresh timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                timer           <= 0;
+                REF_REQ         <= 0;
+        end        
+        else 
+        begin
+                if (REF_ACK == 1)
+				begin
+                	timer <= REF_PER;
+					REF_REQ	<=0;
+				end
+				else if (INIT_REQ == 1)
+				begin
+                	timer <= REF_PER+200;
+					REF_REQ	<=0;					
+				end
+                else
+                	timer <= timer - 1'b1;
+
+                if (timer==0)
+                    REF_REQ    <= 1;
+
+        end
+end
+
+// initial timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                init_timer      <= 0;
+				REFRESH         <= 0;
+                PRECHARGE      	<= 0; 
+				LOAD_MODE		<= 0;
+				INIT_REQ		<= 0;
+        end        
+        else 
+        begin
+                if (init_timer < (INIT_PER+201))
+					init_timer 	<= init_timer+1;
+					
+				if (init_timer < INIT_PER)
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=1;
+				end
+				else if(init_timer == (INIT_PER+20))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=1;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if( 	(init_timer == (INIT_PER+40))	||
+							(init_timer == (INIT_PER+60))	||
+							(init_timer == (INIT_PER+80))	||
+							(init_timer == (INIT_PER+100))	||
+							(init_timer == (INIT_PER+120))	||
+							(init_timer == (INIT_PER+140))	||
+							(init_timer == (INIT_PER+160))	||
+							(init_timer == (INIT_PER+180))	)
+				begin
+					REFRESH		<=1;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if(init_timer == (INIT_PER+200))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=1;
+					INIT_REQ	<=0;				
+				end
+				else
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;									
+				end
+        end
+end
+
+endmodule
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v
new file mode 100644
index 0000000..b064bbe
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_Control_4Port/sdr_data_path.v
@@ -0,0 +1,76 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	sdr_data_path
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module sdr_data_path(
+        CLK,
+        RESET_N,
+        DATAIN,
+        DM,
+        DQOUT,
+        DQM
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`DSIZE-1:0]            DATAIN;                 // Data input from the host
+input   [`DSIZE/8-1:0]          DM;                     // byte data masks
+output  [`DSIZE-1:0]            DQOUT;
+output  [`DSIZE/8-1:0]          DQM;                    // SDRAM data mask ouputs
+reg     [`DSIZE/8-1:0]          DQM;
+            
+
+
+// Allign the input and output data to the SDRAM control path
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+		DQM		<= `DSIZE/8-1'hF;
+        else
+ 		DQM		<=	DM;                 
+end
+
+assign DQOUT = DATAIN;
+
+endmodule
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/Sdram_FIFO.qip
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf
new file mode 100644
index 0000000..f33dd49
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/TOP_CAMERA.bdf
@@ -0,0 +1,875 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 328 160 496 176)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 128 320 192 336))
+)
+(pin
+	(input)
+	(rect 416 192 584 208)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 288 224 344 240))
+)
+(pin
+	(input)
+	(rect 384 208 608 224)
+	(text "INPUT" (rect 180 6 208 16)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKIN[1..0]" (rect 6 4 109 16)(font "Arial" ))
+	(pt 224 8)
+	(drawing
+		(line (pt 139 4)(pt 164 4))
+		(line (pt 139 12)(pt 164 12))
+		(line (pt 168 8)(pt 223 8))
+		(line (pt 139 4)(pt 139 12))
+		(line (pt 164 12)(pt 168 8))
+		(line (pt 164 4)(pt 168 8))
+	)
+	(flipx)
+	(text "VCC" (rect 183 -1 203 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 504 280 560 296))
+)
+(pin
+	(input)
+	(rect 328 176 496 192)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "KEY[2..0]" (rect 5 0 53 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 176 432 232 448))
+)
+(pin
+	(output)
+	(rect 1064 160 1240 176)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "LEDG[9..0]" (rect 116 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 656 264 720 280))
+)
+(pin
+	(output)
+	(rect 1064 224 1240 240)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX3[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1032 336 1096 352))
+)
+(pin
+	(output)
+	(rect 1064 208 1240 224)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX2[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1256 216 1320 232))
+)
+(pin
+	(output)
+	(rect 1064 192 1240 208)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX1[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1272 176 1336 192))
+)
+(pin
+	(output)
+	(rect 1064 176 1240 192)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "HEX0[6..0]" (rect 118 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1016 352 1080 368))
+)
+(pin
+	(output)
+	(rect 1024 272 1200 288)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_LDQM" (rect 103 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1376 808 1440 824))
+)
+(pin
+	(output)
+	(rect 1024 288 1200 304)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_UDQM" (rect 101 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 704 1784 720))
+)
+(pin
+	(output)
+	(rect 1024 384 1200 400)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_1" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 800 1784 816))
+)
+(pin
+	(output)
+	(rect 1024 368 1200 384)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_0" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1376 776 1440 792))
+)
+(pin
+	(output)
+	(rect 1024 320 1200 336)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 736 1792 752))
+)
+(pin
+	(output)
+	(rect 1024 416 1200 432)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CKE" (rect 110 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 832 1792 848))
+)
+(pin
+	(output)
+	(rect 1024 352 1200 368)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CS_N" (rect 103 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 768 1784 784))
+)
+(pin
+	(output)
+	(rect 1024 336 1200 352)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_RAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 752 1784 768))
+)
+(pin
+	(output)
+	(rect 1024 304 1200 320)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_WE_N" (rect 101 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1728 720 1784 736))
+)
+(pin
+	(output)
+	(rect 1024 400 1200 416)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CLK" (rect 111 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 464 1200 528 1216))
+)
+(pin
+	(output)
+	(rect 1024 256 1233 272)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_ADDR[11..0] " (rect 98 0 203 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1664 656 1728 672))
+)
+(pin
+	(output)
+	(rect 1024 528 1234 544)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKOUT[1..0]" (rect 90 0 204 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1448 552 1504 568))
+)
+(pin
+	(output)
+	(rect 960 752 1136 768)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 37 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 768 1192 784))
+)
+(pin
+	(output)
+	(rect 960 704 1136 720)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_HS" (rect 43 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 720 1192 736))
+)
+(pin
+	(output)
+	(rect 960 720 1136 736)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_VS" (rect 44 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 736 1192 752))
+)
+(pin
+	(output)
+	(rect 960 656 1136 672)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_R[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 672 1192 688))
+)
+(pin
+	(output)
+	(rect 960 672 1136 688)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 688 1192 704))
+)
+(pin
+	(output)
+	(rect 960 688 1136 704)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_B[3..0]" (rect 5 0 66 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 1136 704 1192 720))
+)
+(pin
+	(bidir)
+	(rect 1024 240 1208 256)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "DRAM_DQ[15..0] " (rect 90 0 179 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1816 608 1880 624))
+)
+(pin
+	(bidir)
+	(rect 1024 544 1200 560)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1[31..0]" (rect 90 0 160 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1400 632 1456 648))
+)
+(symbol
+	(rect 640 136 928 600)
+	(text "DE0_D5M" (rect 5 0 54 12)(font "Arial" ))
+	(text "inst" (rect 8 448 25 460)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 55 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 76 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 48 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 69 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 64 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 103 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 124 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 221 27 276 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 276 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 223 59 276 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 276 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 276 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 101 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 182 123 283 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 210 139 278 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 70 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 208 155 278 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 69 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 209 171 278 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 205 187 279 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 205 203 279 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 211 219 278 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 214 235 277 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 214 251 277 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 218 267 277 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 60 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 217 283 277 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_HS" (rect 231 299 274 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_VS" (rect 232 315 274 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[3..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_R[3..0]" (rect 215 331 277 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[3..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_G[3..0]" (rect 215 347 277 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[3..0]" (rect 0 0 61 12)(font "Arial" ))
+		(text "VGA_B[3..0]" (rect 216 363 277 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 226 379 275 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 114 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 395 285 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 278 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 411 282 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 448))
+	)
+)
+(connector
+	(pt 608 216)
+	(pt 640 216)
+	(bus)
+)
+(connector
+	(pt 584 200)
+	(pt 640 200)
+	(bus)
+)
+(connector
+	(text "KEY[2..0]" (rect 506 168 554 180)(font "Arial" ))
+	(pt 496 184)
+	(pt 640 184)
+	(bus)
+)
+(connector
+	(text "CLOCK_50" (rect 506 152 561 164)(font "Arial" ))
+	(pt 496 168)
+	(pt 640 168)
+)
+(connector
+	(pt 928 168)
+	(pt 1064 168)
+	(bus)
+)
+(connector
+	(pt 928 232)
+	(pt 1064 232)
+	(bus)
+)
+(connector
+	(pt 928 216)
+	(pt 1064 216)
+	(bus)
+)
+(connector
+	(pt 928 200)
+	(pt 1064 200)
+	(bus)
+)
+(connector
+	(pt 928 184)
+	(pt 1064 184)
+	(bus)
+)
+(connector
+	(pt 928 248)
+	(pt 1024 248)
+	(bus)
+)
+(connector
+	(pt 928 264)
+	(pt 1024 264)
+	(bus)
+)
+(connector
+	(pt 928 280)
+	(pt 1024 280)
+)
+(connector
+	(pt 928 296)
+	(pt 1024 296)
+)
+(connector
+	(pt 928 312)
+	(pt 1024 312)
+)
+(connector
+	(pt 928 328)
+	(pt 1024 328)
+)
+(connector
+	(pt 928 344)
+	(pt 1024 344)
+)
+(connector
+	(pt 928 360)
+	(pt 1024 360)
+)
+(connector
+	(pt 928 376)
+	(pt 1024 376)
+)
+(connector
+	(pt 928 392)
+	(pt 1024 392)
+)
+(connector
+	(pt 928 408)
+	(pt 1024 408)
+)
+(connector
+	(pt 928 424)
+	(pt 1024 424)
+)
+(connector
+	(text "VGA_HS" (rect 938 424 981 436)(font "Arial" ))
+	(pt 928 440)
+	(pt 1008 440)
+)
+(connector
+	(text "VGA_VS" (rect 938 440 980 452)(font "Arial" ))
+	(pt 928 456)
+	(pt 1008 456)
+)
+(connector
+	(text "VGA_CLK" (rect 938 504 987 516)(font "Arial" ))
+	(pt 928 520)
+	(pt 1112 520)
+)
+(connector
+	(pt 928 536)
+	(pt 1024 536)
+	(bus)
+)
+(connector
+	(pt 928 552)
+	(pt 1024 552)
+	(bus)
+)
+(connector
+	(text "VGA_R[3..0]" (rect 938 456 1000 468)(font "Arial" ))
+	(pt 928 472)
+	(pt 1136 472)
+	(bus)
+)
+(connector
+	(text "VGA_G[3..0]" (rect 938 472 1000 484)(font "Arial" ))
+	(pt 928 488)
+	(pt 1136 488)
+	(bus)
+)
+(connector
+	(text "VGA_B[3..0]" (rect 938 488 999 500)(font "Arial" ))
+	(pt 928 504)
+	(pt 1136 504)
+	(bus)
+)
+(text "CLOCK_50" (rect 506 152 561 164)(font "Arial" ))
+(text "KEY[2..0]" (rect 506 168 554 180)(font "Arial" ))
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v
new file mode 100644
index 0000000..338ae75
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/CCD_Capture.v
@@ -0,0 +1,186 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	D5M CCD_Capture
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module CCD_Capture(	oDATA,
+					oDVAL,
+					oX_Cont,
+					oY_Cont,
+					oFrame_Cont,
+					iDATA,
+					iFVAL,
+					iLVAL,
+					iSTART,
+					iEND,
+					iCLK,
+					iRST
+					);
+					
+input	[11:0]	iDATA;
+input			iFVAL;
+input			iLVAL;
+input			iSTART;
+input			iEND;
+input			iCLK;
+input			iRST;
+output	[11:0]	oDATA;
+output	[15:0]	oX_Cont;
+output	[15:0]	oY_Cont;
+output	[31:0]	oFrame_Cont;
+output			oDVAL;
+reg				Pre_FVAL;
+reg				mCCD_FVAL;
+reg				mCCD_LVAL;
+reg		[11:0]	mCCD_DATA;
+reg		[15:0]	X_Cont;
+reg		[15:0]	Y_Cont;
+reg		[31:0]	Frame_Cont;
+reg				mSTART;
+
+parameter COLUMN_WIDTH = 1280;
+
+assign	oX_Cont		=	X_Cont;
+assign	oY_Cont		=	Y_Cont;
+assign	oFrame_Cont	=	Frame_Cont;
+assign	oDATA		=	mCCD_DATA;
+assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	mSTART	<=	0;
+	else
+	begin
+		if(iSTART)
+		mSTART	<=	1;
+		if(iEND)
+		mSTART	<=	0;		
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Pre_FVAL	<=	0;
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	0;
+
+		X_Cont		<=	0;
+		Y_Cont		<=	0;
+	end
+	else
+	begin
+		Pre_FVAL	<=	iFVAL;
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		mCCD_FVAL	<=	1;
+		else if({Pre_FVAL,iFVAL}==2'b10)
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	iLVAL;
+		if(mCCD_FVAL)
+		begin
+			if(mCCD_LVAL)
+			begin
+				if(X_Cont<(COLUMN_WIDTH-1))
+				X_Cont	<=	X_Cont+1;
+				else
+				begin
+					X_Cont	<=	0;
+					Y_Cont	<=	Y_Cont+1;
+				end
+			end
+		end
+		else
+		begin
+			X_Cont	<=	0;
+			Y_Cont	<=	0;
+		end
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	Frame_Cont	<=	0;
+	else
+	begin
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		Frame_Cont	<=	Frame_Cont+1;
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		mCCD_DATA	<=	0;
+	else if (iLVAL)
+		mCCD_DATA	<=	iDATA;
+	else
+		mCCD_DATA	<=	0;	
+end			
+
+reg	ifval_dealy;
+
+wire ifval_fedge;	
+reg	[15:0]	y_cnt_d;
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		y_cnt_d	<=	0;
+	else
+		y_cnt_d	<=	Y_Cont;	
+end
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		ifval_dealy	<=	0;
+	else
+		ifval_dealy	<=	iFVAL;	
+end
+
+assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  
+
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v
new file mode 100644
index 0000000..11d3a70
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v
@@ -0,0 +1,287 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| CCD config, spelling
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+
+// `define 	ENABLE_TEST_PATTERN 1
+
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	sensor_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			sensor_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((sensor_exposure < exposure_change_value)||
+							(sensor_exposure == 16'h0))
+							sensor_exposure <= 0;
+						else	
+							sensor_exposure <= sensor_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -sensor_exposure) <exposure_change_value)||
+							(sensor_exposure == 16'hffff))
+							sensor_exposure <= 16'hffff;
+						else
+							sensor_exposure <= sensor_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,sensor_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..81810a8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_CCD_Config.v.bak
@@ -0,0 +1,282 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	senosr_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			senosr_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((senosr_exposure < exposure_change_value)||
+							(senosr_exposure == 16'h0))
+							senosr_exposure <= 0;
+						else	
+							senosr_exposure <= senosr_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -senosr_exposure) <exposure_change_value)||
+							(senosr_exposure == 16'hffff))
+							senosr_exposure <= 16'hffff;
+						else
+							senosr_exposure <= senosr_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,senosr_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v
new file mode 100644
index 0000000..3740541
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/I2C_Controller.v
@@ -0,0 +1,150 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altrea Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL or Verilog source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Joe Yang          :| 05/07/10  :|      Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+	CLOCK,
+	I2C_SCLK,//I2C CLOCK
+ 	I2C_SDAT,//I2C DATA
+	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+	GO,      //GO transfor
+	END,     //END transfor 
+
+	ACK,      //ACK
+	RESET
+);
+	input  CLOCK;
+	input  [31:0]I2C_DATA;	
+	input  GO;
+	input  RESET;	
+ 	inout  I2C_SDAT;	
+	output I2C_SCLK;
+	output END;	
+	output ACK;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [31:0]SD;
+reg [6:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3,ACK4;
+wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0) 
+	SD_COUNTER=0;
+	else 
+	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
+end
+end
+//----
+
+always @(negedge RESET or  posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
+else
+case (SD_COUNTER)
+	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
+	//start
+	6'd1  : begin SD=I2C_DATA;SDO=0;end
+	6'd2  : SCLK=0;
+	//SLAVE ADDR
+	6'd3  : SDO=SD[31];
+	6'd4  : SDO=SD[30];
+	6'd5  : SDO=SD[29];
+	6'd6  : SDO=SD[28];
+	6'd7  : SDO=SD[27];
+	6'd8  : SDO=SD[26];
+	6'd9  : SDO=SD[25];
+	6'd10 : SDO=SD[24];	
+	6'd11 : SDO=1'b1;//ACK
+
+	//SUB ADDR
+	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
+	6'd13  : SDO=SD[22];
+	6'd14  : SDO=SD[21];
+	6'd15  : SDO=SD[20];
+	6'd16  : SDO=SD[19];
+	6'd17  : SDO=SD[18];
+	6'd18  : SDO=SD[17];
+	6'd19  : SDO=SD[16];
+	6'd20  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
+	6'd22  : SDO=SD[14];
+	6'd23  : SDO=SD[13];
+	6'd24  : SDO=SD[12];
+	6'd25  : SDO=SD[11];
+	6'd26  : SDO=SD[10];
+	6'd27  : SDO=SD[9];
+	6'd28  : SDO=SD[8];
+	6'd29  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
+	6'd31  : SDO=SD[6];
+	6'd32  : SDO=SD[5];
+	6'd33  : SDO=SD[4];
+	6'd34  : SDO=SD[3];
+	6'd35  : SDO=SD[2];
+	6'd36  : SDO=SD[1];
+	6'd37  : SDO=SD[0];
+	6'd38  : SDO=1'b1;//ACK
+
+	
+	//stop
+    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
+    6'd40 : SCLK=1'b1; 
+    6'd41 : begin SDO=1'b1; END=1; end 
+
+endcase
+end
+
+
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf
new file mode 100644
index 0000000..b7b5b56
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.bsf
@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 184 128)
+	(text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 184 40)
+		(output)
+		(text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8)))
+		(line (pt 184 40)(pt 168 40)(line_width 3))
+	)
+	(port
+		(pt 184 56)
+		(output)
+		(text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps1x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8)))
+		(line (pt 184 56)(pt 168 56)(line_width 3))
+	)
+	(port
+		(pt 184 72)
+		(output)
+		(text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps0x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8)))
+		(line (pt 184 72)(pt 168 72)(line_width 3))
+	)
+	(drawing
+		(text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8)))
+		(text "Number of taps 2" (rect 19 90 93 102)(font "Arial" ))
+		(text "Tap distance 1280" (rect 19 100 95 112)(font "Arial" ))
+		(line (pt 16 16)(pt 168 16)(line_width 1))
+		(line (pt 168 16)(pt 168 112)(line_width 1))
+		(line (pt 168 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v
new file mode 100644
index 0000000..09482ce
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Line_Buffer.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %Shift register (RAM-based)%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altshift_taps 
+
+// ============================================================
+// File Name: Line_Buffer.v
+// Megafunction Name(s):
+// 			altshift_taps
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Line_Buffer (
+	clken,
+	clock,
+	shiftin,
+	shiftout,
+	taps0x,
+	taps1x);
+
+	input	  clken;
+	input	  clock;
+	input	[11:0]  shiftin;
+	output	[11:0]  shiftout;
+	output	[11:0]  taps0x;
+	output	[11:0]  taps1x;
+
+	wire [23:0] sub_wire0;
+	wire [11:0] sub_wire3;
+	wire [23:12] sub_wire1 = sub_wire0[23:12];
+	wire [11:0] sub_wire2 = sub_wire0[11:0];
+	wire [11:0] taps1x = sub_wire1[23:12];
+	wire [11:0] taps0x = sub_wire2[11:0];
+	wire [11:0] shiftout = sub_wire3[11:0];
+
+	altshift_taps	altshift_taps_component (
+				.clken (clken),
+				.clock (clock),
+				.shiftin (shiftin),
+				.taps (sub_wire0),
+				.shiftout (sub_wire3));
+	defparam
+		altshift_taps_component.lpm_type = "altshift_taps",
+		altshift_taps_component.number_of_taps = 2,
+		altshift_taps_component.tap_distance = 1280,
+		altshift_taps_component.width = 12;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
+// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
+// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
+// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
+// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
+// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
+// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
+// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
+// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v
new file mode 100644
index 0000000..16493c7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/RAW2RGB.v
@@ -0,0 +1,128 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	RAW2RGB
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module RAW2RGB(	oRed,
+				oGreen,
+				oBlue,
+				oDVAL,
+				iX_Cont,
+				iY_Cont,
+				iDATA,
+				iDVAL,
+				iCLK,
+				iRST
+				);
+
+input	[10:0]	iX_Cont;
+input	[10:0]	iY_Cont;
+input	[11:0]	iDATA;
+input			iDVAL;
+input			iCLK;
+input			iRST;
+output	[11:0]	oRed;
+output	[11:0]	oGreen;
+output	[11:0]	oBlue;
+output			oDVAL;
+wire	[11:0]	mDATA_0;
+wire	[11:0]	mDATA_1;
+reg		[11:0]	mDATAd_0;
+reg		[11:0]	mDATAd_1;
+reg		[11:0]	mCCD_R;
+reg		[12:0]	mCCD_G;
+reg		[11:0]	mCCD_B;
+reg				mDVAL;
+
+assign	oRed	=	mCCD_R[11:0];
+assign	oGreen	=	mCCD_G[12:1];
+assign	oBlue	=	mCCD_B[11:0];
+assign	oDVAL	=	mDVAL;
+
+Line_Buffer 	u0	(	.clken(iDVAL),
+						.clock(iCLK),
+						.shiftin(iDATA),
+						.taps0x(mDATA_1),
+						.taps1x(mDATA_0)	);
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		mCCD_R	<=	0;
+		mCCD_G	<=	0;
+		mCCD_B	<=	0;
+		mDATAd_0<=	0;
+		mDATAd_1<=	0;
+		mDVAL	<=	0;
+	end
+	else
+	begin
+		mDATAd_0	<=	mDATA_0;
+		mDATAd_1	<=	mDATA_1;
+		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
+		if({iY_Cont[0],iX_Cont[0]}==2'b10)
+		begin
+			mCCD_R	<=	mDATA_0;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATAd_1;
+		end	
+		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
+		begin
+			mCCD_R	<=	mDATAd_0;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATA_1;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
+		begin
+			mCCD_R	<=	mDATA_1;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATAd_0;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
+		begin
+			mCCD_R	<=	mDATAd_1;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATA_0;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v
new file mode 100644
index 0000000..578a964
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/Reset_Delay.v
@@ -0,0 +1,74 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Reset_Delay
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
+input		iCLK;
+input		iRST;
+output reg	oRST_0;
+output reg	oRST_1;
+output reg	oRST_2;
+
+reg	[31:0]	Cont;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Cont	<=	0;
+		oRST_0	<=	0;
+		oRST_1	<=	0;
+		oRST_2	<=	0;
+	end
+	else
+	begin
+		if(Cont!=32'h11FFFFF)
+		Cont	<=	Cont+1;
+		if(Cont>=32'h1FFFFF)
+		oRST_0	<=	1;
+		if(Cont>=32'h2FFFFF)
+		oRST_1	<=	1;
+		if(Cont>=32'h11FFFFF)
+		oRST_2	<=	1;
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v
new file mode 100644
index 0000000..2756db0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT	(	oSEG,iDIG	);
+input	[3:0]	iDIG;
+output	[6:0]	oSEG;
+reg		[6:0]	oSEG;
+
+always @(iDIG)
+begin
+		case(iDIG)
+		4'h1: oSEG = 7'b1111001;	// ---t----
+		4'h2: oSEG = 7'b0100100; 	// |	  |
+		4'h3: oSEG = 7'b0110000; 	// lt	 rt
+		4'h4: oSEG = 7'b0011001; 	// |	  |
+		4'h5: oSEG = 7'b0010010; 	// ---m----
+		4'h6: oSEG = 7'b0000010; 	// |	  |
+		4'h7: oSEG = 7'b1111000; 	// lb	 rb
+		4'h8: oSEG = 7'b0000000; 	// |	  |
+		4'h9: oSEG = 7'b0011000; 	// ---b----
+		4'ha: oSEG = 7'b0001000;
+		4'hb: oSEG = 7'b0000011;
+		4'hc: oSEG = 7'b1000110;
+		4'hd: oSEG = 7'b0100001;
+		4'he: oSEG = 7'b0000110;
+		4'hf: oSEG = 7'b0001110;
+		4'h0: oSEG = 7'b1000000;
+		endcase
+end
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v
new file mode 100644
index 0000000..e84af4e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/SEG7_LUT_8.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT_8
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input	[31:0]	iDIG;
+output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
+SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
+SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
+SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
+SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
+SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
+SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
+SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v
new file mode 100644
index 0000000..c9c3537
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Controller.v
@@ -0,0 +1,122 @@
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		H_Cont	<=	H_Cont+1;
+		else
+		H_Cont	<=	0;
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+		oVGA_H_SYNC	<=	0;
+		else
+		oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h
new file mode 100644
index 0000000..9d0fd32
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/VGA_Param.h
@@ -0,0 +1,16 @@
+//	Horizontal Parameter	( Pixel )
+parameter	H_SYNC_CYC	=	96;
+parameter	H_SYNC_BACK	=	48;
+parameter	H_SYNC_ACT	=	640;	
+parameter	H_SYNC_FRONT=	16;
+parameter	H_SYNC_TOTAL=	800;
+
+//	Virtical Parameter		( Line )
+parameter	V_SYNC_CYC	=	2;
+parameter	V_SYNC_BACK	=	33;
+parameter	V_SYNC_ACT	=	480;	
+parameter	V_SYNC_FRONT=	10;
+parameter	V_SYNC_TOTAL=	525;
+//	Start Offset
+parameter	X_START		=	H_SYNC_CYC+H_SYNC_BACK;
+parameter	Y_START		=	V_SYNC_CYC+V_SYNC_BACK;
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf
new file mode 100644
index 0000000..a895305
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.bsf
@@ -0,0 +1,81 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 240 168)
+	(text "sdram_pll" (rect 92 0 158 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 240 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 240 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 178 152 401 315)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "5/2" (rect 77 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "5/2" (rect 77 121 165 253)(font "Arial" ))
+		(text "-117.00" (rect 98 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(line (pt 0 0)(pt 241 0))
+		(line (pt 241 0)(pt 241 169))
+		(line (pt 0 169)(pt 241 169))
+		(line (pt 0 0)(pt 0 169))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 91)(pt 48 132))
+		(line (pt 69 91)(pt 69 132)(line_width 3))
+		(line (pt 95 91)(pt 95 132)(line_width 3))
+		(line (pt 129 91)(pt 129 132)(line_width 3))
+		(line (pt 163 91)(pt 163 132))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 151))
+		(line (pt 40 151)(pt 207 151))
+		(line (pt 40 48)(pt 40 151))
+		(line (pt 239 64)(pt 207 64))
+		(line (pt 239 80)(pt 207 80))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf
new file mode 100644
index 0000000..a4a0f2e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="sdram_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip
new file mode 100644
index 0000000..7440d58
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"]
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v
new file mode 100644
index 0000000..6b4189b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-2600",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.60000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2600"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak
new file mode 100644
index 0000000..7fd74a1
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll.v.bak
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg
new file mode 100644
index 0000000..a48389a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_wave0.jpg
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html
new file mode 100644
index 0000000..2d27f12
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/V/sdram_pll_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for sdram_pll.v </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file sdram_pll.v </CENTER></h2>
+<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
+<CENTER><img src=sdram_pll_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat
new file mode 100644
index 0000000..c3a3f44
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.bat
@@ -0,0 +1,17 @@
+%QUARTUS_ROOTDIR%\\bin\\quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;DE1_D5M.sof"
+@ set SOPC_BUILDER_PATH_71=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_71%
+@ set SOPC_BUILDER_PATH_72=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_72%
+@ set SOPC_BUILDER_PATH_80=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_80%
+@ set SOPC_BUILDER_PATH_81=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_81%
+@ set SOPC_BUILDER_PATH_90=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_90%
+@ set SOPC_BUILDER_PATH_91=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_91%
+@ set SOPC_BUILDER_PATH_92=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_92%
+@ set SOPC_BUILDER_PATH_100=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_100%
+@ set SOPC_BUILDER_PATH_101=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_101%
+@ set SOPC_BUILDER_PATH_102=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_102%
+@ set SOPC_BUILDER_PATH_110=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_110%
+@ set SOPC_BUILDER_PATH_111=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_111%
+@ set SOPC_BUILDER_PATH_112=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_112%
+@ set SOPC_BUILDER_PATH_120=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_120%
+@ set SOPC_BUILDER_PATH_121=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_121%
+@ set SOPC_BUILDER_PATH_122=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH_122%
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof
new file mode 100644
index 0000000..9832b19
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/demo batch/DE1_D5M.sof
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..9ca2d87
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/greybox_tmp/cbx_args.txt
@@ -0,0 +1,63 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=2
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=5
+CLK0_PHASE_SHIFT=0
+CLK1_DIVIDE_BY=2
+CLK1_DUTY_CYCLE=50
+CLK1_MULTIPLY_BY=5
+CLK1_PHASE_SHIFT=-2600
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
+INTENDED_DEVICE_FAMILY="Cyclone III"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_UNUSED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_UNUSED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_USED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone III"
+CBX_AUTO_BLACKBOX=ALL
+inclk
+inclk
+clk
+clk
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt
new file mode 100644
index 0000000..1097973
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/qmegawiz_errors_log.txt
@@ -0,0 +1,28 @@
+
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:44:47>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:45:47>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
+
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.v
+
+Mar 16 05PM:45:55>: Error in CNX file format.
+
+Error messages are listed in file
+E:/work/teaching/1314_2T_ISE1PRJ/DE0_CAMERA_v2/V/sdram_pll.cnxerr.
+
+Can't create the custom megafunction variation file(s)
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA/sdram_pll.qip
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt
new file mode 100644
index 0000000..3b3173b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.asm.rpt
@@ -0,0 +1,130 @@
+Assembler report for DE0_D5M
+Mon Mar 17 11:17:25 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Assembler Summary
+  3. Assembler Settings
+  4. Assembler Generated Files
+  5. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
+  6. Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
+  7. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary                                             ;
++-----------------------+---------------------------------------+
+; Assembler Status      ; Successful - Mon Mar 17 11:17:25 2014 ;
+; Revision Name         ; DE0_D5M                               ;
+; Top-level Entity Name ; TOP_DE0_CAMERA_MOUSE                  ;
+; Family                ; Cyclone III                           ;
+; Device                ; EP3C16F484C6                          ;
++-----------------------+---------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------+
+; Assembler Settings                                                                                     ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Option                                                                      ; Setting  ; Default Value ;
++-----------------------------------------------------------------------------+----------+---------------+
+; Use smart compilation                                                       ; On       ; Off           ;
+; Use configuration device                                                    ; On       ; Off           ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation  ; On       ; On            ;
+; Enable compact report table                                                 ; Off      ; Off           ;
+; Generate compressed bitstreams                                              ; On       ; On            ;
+; Compression mode                                                            ; Off      ; Off           ;
+; Clock source for configuration device                                       ; Internal ; Internal      ;
+; Clock frequency of the configuration device                                 ; 10 MHZ   ; 10 MHz        ;
+; Divide clock frequency by                                                   ; 1        ; 1             ;
+; Auto user code                                                              ; On       ; On            ;
+; Configuration device                                                        ; Auto     ; Auto          ;
+; Configuration device auto user code                                         ; Off      ; Off           ;
+; Generate Tabular Text File (.ttf) For Target Device                         ; Off      ; Off           ;
+; Generate Raw Binary File (.rbf) For Target Device                           ; Off      ; Off           ;
+; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off      ; Off           ;
+; Hexadecimal Output File start address                                       ; 0        ; 0             ;
+; Hexadecimal Output File count direction                                     ; Up       ; Up            ;
+; Release clears before tri-states                                            ; Off      ; Off           ;
+; Auto-restart configuration after error                                      ; On       ; On            ;
+; Enable OCT_DONE                                                             ; Off      ; Off           ;
+; Generate Serial Vector Format File (.svf) for Target Device                 ; Off      ; Off           ;
+; Generate a JEDEC STAPL Format File (.jam) for Target Device                 ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off      ; Off           ;
+; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On       ; On            ;
++-----------------------------------------------------------------------------+----------+---------------+
+
+
++----------------------------------------------------------------------------+
+; Assembler Generated Files                                                  ;
++----------------------------------------------------------------------------+
+; File Name                                                                  ;
++----------------------------------------------------------------------------+
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof ;
+; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof ;
++----------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof ;
++----------------+-------------------------------------------------------------------------------------+
+; Option         ; Setting                                                                             ;
++----------------+-------------------------------------------------------------------------------------+
+; Device         ; EP3C16F484C6                                                                        ;
+; JTAG usercode  ; 0x0021C025                                                                          ;
+; Checksum       ; 0x0021C025                                                                          ;
++----------------+-------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof ;
++--------------------+---------------------------------------------------------------------------------+
+; Option             ; Setting                                                                         ;
++--------------------+---------------------------------------------------------------------------------+
+; Device             ; EPCS4                                                                           ;
+; JTAG usercode      ; 0x00000000                                                                      ;
+; Checksum           ; 0x05B2DBEB                                                                      ;
+; Compression Ratio  ; 3                                                                               ;
++--------------------+---------------------------------------------------------------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 11:17:23 2014
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 456 megabytes
+    Info: Processing ended: Mon Mar 17 11:17:25 2014
+    Info: Elapsed time: 00:00:02
+    Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf
new file mode 100644
index 0000000..94a0cff
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.bsf
@@ -0,0 +1,253 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 512)
+	(text "DE0_D5M" (rect 5 0 49 12)(font "Arial" ))
+	(text "inst" (rect 8 480 20 492)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 49 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 36 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 47 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 220 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 267 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 224 59 267 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 267 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 44 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 267 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 90 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 177 123 267 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 66 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 201 139 267 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 200 155 267 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160)(line_width 1))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 199 171 267 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176)(line_width 1))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 71 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 196 187 267 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192)(line_width 1))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 73 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 194 203 267 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208)(line_width 1))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 204 219 267 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224)(line_width 1))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 62 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 205 235 267 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240)(line_width 1))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 61 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 206 251 267 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256)(line_width 1))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 57 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 210 267 267 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272)(line_width 1))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 208 283 267 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288)(line_width 1))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_HS" (rect 225 299 267 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304)(line_width 1))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_VS" (rect 224 315 267 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320)(line_width 1))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[9..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_R[9..0]" (rect 210 331 267 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[9..0]" (rect 0 0 56 12)(font "Arial" ))
+		(text "VGA_G[9..0]" (rect 211 347 267 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "VGA_B[9..0]" (rect 212 363 267 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 218 379 267 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384)(line_width 1))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "VGA_X[11..0]" (rect 0 0 57 12)(font "Arial" ))
+		(text "VGA_X[11..0]" (rect 210 395 267 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(output)
+		(text "VGA_Y[11..0]" (rect 0 0 59 12)(font "Arial" ))
+		(text "VGA_Y[11..0]" (rect 208 411 267 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(port
+		(pt 288 432)
+		(output)
+		(text "VGA_ACTIVE" (rect 0 0 68 12)(font "Arial" ))
+		(text "VGA_ACTIVE" (rect 199 427 267 439)(font "Arial" ))
+		(line (pt 288 432)(pt 272 432)(line_width 1))
+	)
+	(port
+		(pt 288 448)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 443 267 455)(font "Arial" ))
+		(line (pt 288 448)(pt 272 448)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 267 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 464)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 459 267 471)(font "Arial" ))
+		(line (pt 288 464)(pt 272 464)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 480)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf
new file mode 100644
index 0000000..268964b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.cdf
@@ -0,0 +1,13 @@
+/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP3C16F484) Path("E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/") File("DE0_D5M.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done
new file mode 100644
index 0000000..bec9674
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.done
@@ -0,0 +1 @@
+Mon Mar 17 11:17:32 2014
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt
new file mode 100644
index 0000000..54e82eb
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.rpt
@@ -0,0 +1,3979 @@
+Fitter report for DE0_D5M
+Mon Mar 17 11:17:21 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Fitter Summary
+  3. Fitter Settings
+  4. Parallel Compilation
+  5. I/O Assignment Warnings
+  6. Ignored Assignments
+  7. Incremental Compilation Preservation Summary
+  8. Incremental Compilation Partition Settings
+  9. Incremental Compilation Placement Preservation
+ 10. Pin-Out File
+ 11. Fitter Resource Usage Summary
+ 12. Fitter Partition Statistics
+ 13. Input Pins
+ 14. Output Pins
+ 15. Bidir Pins
+ 16. Dual Purpose and Dedicated Pins
+ 17. I/O Bank Usage
+ 18. All Package Pins
+ 19. PLL Summary
+ 20. PLL Usage
+ 21. Fitter Resource Utilization by Entity
+ 22. Delay Chain Summary
+ 23. Pad To Core Delay Chain Fanout
+ 24. Control Signals
+ 25. Global & Other Fast Signals
+ 26. Non-Global High Fan-Out Signals
+ 27. Fitter RAM Summary
+ 28. Routing Usage Summary
+ 29. LAB Logic Elements
+ 30. LAB-wide Signals
+ 31. LAB Signals Sourced
+ 32. LAB Signals Sourced Out
+ 33. LAB Distinct Inputs
+ 34. I/O Rules Summary
+ 35. I/O Rules Details
+ 36. I/O Rules Matrix
+ 37. Fitter Device Options
+ 38. Operating Settings and Conditions
+ 39. Estimated Delay Added for Hold Timing Summary
+ 40. Estimated Delay Added for Hold Timing Details
+ 41. Fitter Messages
+ 42. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary                                                                   ;
++------------------------------------+---------------------------------------------+
+; Fitter Status                      ; Successful - Mon Mar 17 11:17:21 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                        ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 2,329 / 15,408 ( 15 % )                     ;
+;     Total combinational functions  ; 1,922 / 15,408 ( 12 % )                     ;
+;     Dedicated logic registers      ; 1,326 / 15,408 ( 9 % )                      ;
+; Total registers                    ; 1326                                        ;
+; Total pins                         ; 143 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 134,236 / 516,096 ( 26 % )                  ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings                                                                                                                                            ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option                                                                     ; Setting                               ; Default Value                         ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device                                                                     ; EP3C16F484C6                          ;                                       ;
+; Use smart compilation                                                      ; On                                    ; Off                                   ;
+; Minimum Core Junction Temperature                                          ; 0                                     ;                                       ;
+; Maximum Core Junction Temperature                                          ; 85                                    ;                                       ;
+; Fit Attempts to Skip                                                       ; 0                                     ; 0.0                                   ;
+; Device I/O Standard                                                        ; 3.3-V LVTTL                           ;                                       ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                                    ; On                                    ;
+; Enable compact report table                                                ; Off                                   ; Off                                   ;
+; Auto Merge PLLs                                                            ; On                                    ; On                                    ;
+; Router Timing Optimization Level                                           ; Normal                                ; Normal                                ;
+; Perform Clocking Topology Analysis During Routing                          ; Off                                   ; Off                                   ;
+; Placement Effort Multiplier                                                ; 1.0                                   ; 1.0                                   ;
+; Router Effort Multiplier                                                   ; 1.0                                   ; 1.0                                   ;
+; Optimize Hold Timing                                                       ; All Paths                             ; All Paths                             ;
+; Optimize Multi-Corner Timing                                               ; On                                    ; On                                    ;
+; PowerPlay Power Optimization                                               ; Normal compilation                    ; Normal compilation                    ;
+; SSN Optimization                                                           ; Off                                   ; Off                                   ;
+; Optimize Timing                                                            ; Normal compilation                    ; Normal compilation                    ;
+; Optimize Timing for ECOs                                                   ; Off                                   ; Off                                   ;
+; Regenerate full fit report during ECO compiles                             ; Off                                   ; Off                                   ;
+; Optimize IOC Register Placement for Timing                                 ; Normal                                ; Normal                                ;
+; Limit to One Fitting Attempt                                               ; Off                                   ; Off                                   ;
+; Final Placement Optimizations                                              ; Automatically                         ; Automatically                         ;
+; Fitter Aggressive Routability Optimizations                                ; Automatically                         ; Automatically                         ;
+; Fitter Initial Placement Seed                                              ; 1                                     ; 1                                     ;
+; PCI I/O                                                                    ; Off                                   ; Off                                   ;
+; Weak Pull-Up Resistor                                                      ; Off                                   ; Off                                   ;
+; Enable Bus-Hold Circuitry                                                  ; Off                                   ; Off                                   ;
+; Auto Packed Registers                                                      ; Auto                                  ; Auto                                  ;
+; Auto Delay Chains                                                          ; On                                    ; On                                    ;
+; Auto Delay Chains for High Fanout Input Pins                               ; Off                                   ; Off                                   ;
+; Allow Single-ended Buffer for Differential-XSTL Input                      ; Off                                   ; Off                                   ;
+; Treat Bidirectional Pin as Output Pin                                      ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                                   ; Off                                   ;
+; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                                   ; Off                                   ;
+; Perform Register Duplication for Performance                               ; Off                                   ; Off                                   ;
+; Perform Logic to Memory Mapping for Fitting                                ; Off                                   ; Off                                   ;
+; Perform Register Retiming for Performance                                  ; Off                                   ; Off                                   ;
+; Perform Asynchronous Signal Pipelining                                     ; Off                                   ; Off                                   ;
+; Fitter Effort                                                              ; Auto Fit                              ; Auto Fit                              ;
+; Physical Synthesis Effort Level                                            ; Normal                                ; Normal                                ;
+; Logic Cell Insertion - Logic Duplication                                   ; Auto                                  ; Auto                                  ;
+; Auto Register Duplication                                                  ; Auto                                  ; Auto                                  ;
+; Auto Global Clock                                                          ; On                                    ; On                                    ;
+; Auto Global Register Control Signals                                       ; On                                    ; On                                    ;
+; Reserve all unused pins                                                    ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification                                                ; Off                                   ; Off                                   ;
+; Enable Beneficial Skew Optimization                                        ; On                                    ; On                                    ;
+; Optimize Design for Metastability                                          ; On                                    ; On                                    ;
+; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                                   ; Off                                   ;
+; RAM Bit Reservation (Cyclone III)                                          ; Off                                   ; Off                                   ;
+; Enable input tri-state on active configuration pins in user mode           ; Off                                   ; Off                                   ;
++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.19        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ;   6.3%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-------------------------------------------+
+; I/O Assignment Warnings                   ;
++------------------+------------------------+
+; Pin Name         ; Reason                 ;
++------------------+------------------------+
+; DRAM_LDQM        ; Missing drive strength ;
+; DRAM_UDQM        ; Missing drive strength ;
+; DRAM_BA_1        ; Missing drive strength ;
+; DRAM_BA_0        ; Missing drive strength ;
+; DRAM_CAS_N       ; Missing drive strength ;
+; DRAM_CKE         ; Missing drive strength ;
+; DRAM_CS_N        ; Missing drive strength ;
+; DRAM_RAS_N       ; Missing drive strength ;
+; DRAM_WE_N        ; Missing drive strength ;
+; DRAM_CLK         ; Missing drive strength ;
+; VGA_CLK          ; Missing drive strength ;
+; VGA_HS           ; Missing drive strength ;
+; VGA_VS           ; Missing drive strength ;
+; DRAM_ADDR[11]    ; Missing drive strength ;
+; DRAM_ADDR[10]    ; Missing drive strength ;
+; DRAM_ADDR[9]     ; Missing drive strength ;
+; DRAM_ADDR[8]     ; Missing drive strength ;
+; DRAM_ADDR[7]     ; Missing drive strength ;
+; DRAM_ADDR[6]     ; Missing drive strength ;
+; DRAM_ADDR[5]     ; Missing drive strength ;
+; DRAM_ADDR[4]     ; Missing drive strength ;
+; DRAM_ADDR[3]     ; Missing drive strength ;
+; DRAM_ADDR[2]     ; Missing drive strength ;
+; DRAM_ADDR[1]     ; Missing drive strength ;
+; DRAM_ADDR[0]     ; Missing drive strength ;
+; GPIO_1_CLKOUT[1] ; Missing drive strength ;
+; GPIO_1_CLKOUT[0] ; Missing drive strength ;
+; HEX0[6]          ; Missing drive strength ;
+; HEX0[5]          ; Missing drive strength ;
+; HEX0[4]          ; Missing drive strength ;
+; HEX0[3]          ; Missing drive strength ;
+; HEX0[2]          ; Missing drive strength ;
+; HEX0[1]          ; Missing drive strength ;
+; HEX0[0]          ; Missing drive strength ;
+; HEX1[6]          ; Missing drive strength ;
+; HEX1[5]          ; Missing drive strength ;
+; HEX1[4]          ; Missing drive strength ;
+; HEX1[3]          ; Missing drive strength ;
+; HEX1[2]          ; Missing drive strength ;
+; HEX1[1]          ; Missing drive strength ;
+; HEX1[0]          ; Missing drive strength ;
+; HEX2[6]          ; Missing drive strength ;
+; HEX2[5]          ; Missing drive strength ;
+; HEX2[4]          ; Missing drive strength ;
+; HEX2[3]          ; Missing drive strength ;
+; HEX2[2]          ; Missing drive strength ;
+; HEX2[1]          ; Missing drive strength ;
+; HEX2[0]          ; Missing drive strength ;
+; HEX3[6]          ; Missing drive strength ;
+; HEX3[5]          ; Missing drive strength ;
+; HEX3[4]          ; Missing drive strength ;
+; HEX3[3]          ; Missing drive strength ;
+; HEX3[2]          ; Missing drive strength ;
+; HEX3[1]          ; Missing drive strength ;
+; HEX3[0]          ; Missing drive strength ;
+; LEDG[9]          ; Missing drive strength ;
+; LEDG[8]          ; Missing drive strength ;
+; LEDG[7]          ; Missing drive strength ;
+; LEDG[6]          ; Missing drive strength ;
+; LEDG[5]          ; Missing drive strength ;
+; LEDG[4]          ; Missing drive strength ;
+; LEDG[3]          ; Missing drive strength ;
+; LEDG[2]          ; Missing drive strength ;
+; LEDG[1]          ; Missing drive strength ;
+; LEDG[0]          ; Missing drive strength ;
+; VGA_B[3]         ; Missing drive strength ;
+; VGA_B[2]         ; Missing drive strength ;
+; VGA_B[1]         ; Missing drive strength ;
+; VGA_B[0]         ; Missing drive strength ;
+; VGA_G[3]         ; Missing drive strength ;
+; VGA_G[2]         ; Missing drive strength ;
+; VGA_G[1]         ; Missing drive strength ;
+; VGA_G[0]         ; Missing drive strength ;
+; VGA_R[3]         ; Missing drive strength ;
+; VGA_R[2]         ; Missing drive strength ;
+; VGA_R[1]         ; Missing drive strength ;
+; VGA_R[0]         ; Missing drive strength ;
+; DRAM_DQ[15]      ; Missing drive strength ;
+; DRAM_DQ[14]      ; Missing drive strength ;
+; DRAM_DQ[13]      ; Missing drive strength ;
+; DRAM_DQ[12]      ; Missing drive strength ;
+; DRAM_DQ[11]      ; Missing drive strength ;
+; DRAM_DQ[10]      ; Missing drive strength ;
+; DRAM_DQ[9]       ; Missing drive strength ;
+; DRAM_DQ[8]       ; Missing drive strength ;
+; DRAM_DQ[7]       ; Missing drive strength ;
+; DRAM_DQ[6]       ; Missing drive strength ;
+; DRAM_DQ[5]       ; Missing drive strength ;
+; DRAM_DQ[4]       ; Missing drive strength ;
+; DRAM_DQ[3]       ; Missing drive strength ;
+; DRAM_DQ[2]       ; Missing drive strength ;
+; DRAM_DQ[1]       ; Missing drive strength ;
+; DRAM_DQ[0]       ; Missing drive strength ;
+; GPIO_1[31]       ; Missing drive strength ;
+; GPIO_1[30]       ; Missing drive strength ;
+; GPIO_1[29]       ; Missing drive strength ;
+; GPIO_1[28]       ; Missing drive strength ;
+; GPIO_1[27]       ; Missing drive strength ;
+; GPIO_1[26]       ; Missing drive strength ;
+; GPIO_1[25]       ; Missing drive strength ;
+; GPIO_1[24]       ; Missing drive strength ;
+; GPIO_1[23]       ; Missing drive strength ;
+; GPIO_1[22]       ; Missing drive strength ;
+; GPIO_1[21]       ; Missing drive strength ;
+; GPIO_1[20]       ; Missing drive strength ;
+; GPIO_1[19]       ; Missing drive strength ;
+; GPIO_1[18]       ; Missing drive strength ;
+; GPIO_1[17]       ; Missing drive strength ;
+; GPIO_1[16]       ; Missing drive strength ;
+; GPIO_1[15]       ; Missing drive strength ;
+; GPIO_1[14]       ; Missing drive strength ;
+; GPIO_1[13]       ; Missing drive strength ;
+; GPIO_1[12]       ; Missing drive strength ;
+; GPIO_1[11]       ; Missing drive strength ;
+; GPIO_1[10]       ; Missing drive strength ;
+; GPIO_1[9]        ; Missing drive strength ;
+; GPIO_1[8]        ; Missing drive strength ;
+; GPIO_1[7]        ; Missing drive strength ;
+; GPIO_1[6]        ; Missing drive strength ;
+; GPIO_1[5]        ; Missing drive strength ;
+; GPIO_1[4]        ; Missing drive strength ;
+; GPIO_1[3]        ; Missing drive strength ;
+; GPIO_1[2]        ; Missing drive strength ;
+; GPIO_1[1]        ; Missing drive strength ;
+; GPIO_1[0]        ; Missing drive strength ;
+; PS2_DAT          ; Missing drive strength ;
+; PS2_CLK          ; Missing drive strength ;
++------------------+------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Ignored Assignments                                                                                          ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+; Name                ; Ignored Entity       ; Ignored From ; Ignored To      ; Ignored Value ; Ignored Source ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+; Location            ;                      ;              ; CLOCK_50_2      ; PIN_B12       ; QSF Assignment ;
+; Location            ;                      ;              ; DRAM_ADDR[12]   ; PIN_C8        ; QSF Assignment ;
+; Location            ;                      ;              ; HEX0_DP         ; PIN_D13       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX1_DP         ; PIN_B15       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX2_DP         ; PIN_A18       ; QSF Assignment ;
+; Location            ;                      ;              ; HEX3_DP         ; PIN_G16       ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_DATA       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_FVAL       ; ON            ; QSF Assignment ;
+; Fast Input Register ; TOP_DE0_CAMERA_MOUSE ;              ; rCCD_LVAL       ; ON            ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; AUD_ADCDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; AUD_ADCLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; AUD_BCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; AUD_DACDAT      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; AUD_DACLRCK     ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; AUD_XCK         ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; BUTTON[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; BUTTON[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; BUTTON[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; CLOCK_50_2      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; DRAM_ADDR[12]   ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[0]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[10]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[11]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[12]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[13]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[14]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[15]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[16]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[17]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[18]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[19]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[1]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[20]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[21]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[2]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[3]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[4]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[5]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[6]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[7]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[8]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_ADDR[9]      ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_BYTE_N       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_CE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ15_AM1     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[0]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[10]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[11]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[12]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[13]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[14]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[1]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[2]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[3]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[4]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[5]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[6]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[7]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[8]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_DQ[9]        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_OE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_RST_N        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_RY           ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_WE_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; FL_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO0_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO0_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO0_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO0_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO1_CLKIN[0]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO1_CLKIN[1]  ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO1_CLKOUT[0] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO1_CLKOUT[1] ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO_1[32]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO_1[33]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO_1[34]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; GPIO_1[35]      ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX0_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX1_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX2_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_DP         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[0]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[1]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[2]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[3]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[4]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[5]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; HEX3_D[6]       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; I2C_SCLK        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; I2C_SDAT        ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; KEY[3]          ; LVTTL         ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_BLON        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[0]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[1]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[2]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[3]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[4]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[5]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[6]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_DATA[7]     ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_EN          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_RS          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; LCD_RW          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; PS2_KBCLK       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; PS2_KBDAT       ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; SD_CLK          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; SD_CMD          ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; SD_DAT0         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; SD_DAT3         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; SD_WP_N         ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; UART_CTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; UART_RTS        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; UART_RXD        ; 3.3-V LVTTL   ; QSF Assignment ;
+; I/O Standard        ; TOP_DE0_CAMERA_MOUSE ;              ; UART_TXD        ; 3.3-V LVTTL   ; QSF Assignment ;
++---------------------+----------------------+--------------+-----------------+---------------+----------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary                                                      ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Type                ; Total [A + B]       ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+---------------------+----------------------------+--------------------------+
+; Placement (by node) ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 3780 ) ; 0.00 % ( 0 / 3780 )        ; 0.00 % ( 0 / 3780 )      ;
+;     -- Achieved     ; 0.00 % ( 0 / 3780 ) ; 0.00 % ( 0 / 3780 )        ; 0.00 % ( 0 / 3780 )      ;
+;                     ;                     ;                            ;                          ;
+; Routing (by net)    ;                     ;                            ;                          ;
+;     -- Requested    ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
+;     -- Achieved     ; 0.00 % ( 0 / 0 )    ; 0.00 % ( 0 / 0 )           ; 0.00 % ( 0 / 0 )         ;
++---------------------+---------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings                                                                                                                                             ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name                 ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents                       ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top                            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;                                ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File       ; N/A                     ; Source File            ; N/A                          ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation                                                                                     ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name                 ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top                            ; 0.00 % ( 0 / 3769 )   ; N/A                     ; Source File       ; N/A                 ;       ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 11 )     ; N/A                     ; Source File       ; N/A                 ;       ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin.
+
+
++--------------------------------------------------------------------------+
+; Fitter Resource Usage Summary                                            ;
++---------------------------------------------+----------------------------+
+; Resource                                    ; Usage                      ;
++---------------------------------------------+----------------------------+
+; Total logic elements                        ; 2,329 / 15,408 ( 15 % )    ;
+;     -- Combinational with no register       ; 1003                       ;
+;     -- Register only                        ; 407                        ;
+;     -- Combinational with a register        ; 919                        ;
+;                                             ;                            ;
+; Logic element usage by number of LUT inputs ;                            ;
+;     -- 4 input functions                    ; 595                        ;
+;     -- 3 input functions                    ; 759                        ;
+;     -- <=2 input functions                  ; 568                        ;
+;     -- Register only                        ; 407                        ;
+;                                             ;                            ;
+; Logic elements by mode                      ;                            ;
+;     -- normal mode                          ; 1085                       ;
+;     -- arithmetic mode                      ; 837                        ;
+;                                             ;                            ;
+; Total registers*                            ; 1,326 / 17,068 ( 8 % )     ;
+;     -- Dedicated logic registers            ; 1,326 / 15,408 ( 9 % )     ;
+;     -- I/O registers                        ; 0 / 1,660 ( 0 % )          ;
+;                                             ;                            ;
+; Total LABs:  partially or completely used   ; 195 / 963 ( 20 % )         ;
+; Virtual pins                                ; 0                          ;
+; I/O pins                                    ; 143 / 347 ( 41 % )         ;
+;     -- Clock pins                           ; 2 / 8 ( 25 % )             ;
+;     -- Dedicated input pins                 ; 0 / 9 ( 0 % )              ;
+;                                             ;                            ;
+; Global signals                              ; 11                         ;
+; M9Ks                                        ; 20 / 56 ( 36 % )           ;
+; Total block memory bits                     ; 134,236 / 516,096 ( 26 % ) ;
+; Total block memory implementation bits      ; 184,320 / 516,096 ( 36 % ) ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )            ;
+; PLLs                                        ; 1 / 4 ( 25 % )             ;
+; Global clocks                               ; 11 / 20 ( 55 % )           ;
+; JTAGs                                       ; 0 / 1 ( 0 % )              ;
+; CRC blocks                                  ; 0 / 1 ( 0 % )              ;
+; ASMI blocks                                 ; 0 / 1 ( 0 % )              ;
+; Impedance control blocks                    ; 0 / 4 ( 0 % )              ;
+; Average interconnect usage (total/H/V)      ; 4% / 4% / 4%               ;
+; Peak interconnect usage (total/H/V)         ; 13% / 13% / 13%            ;
+; Maximum fan-out                             ; 512                        ;
+; Highest non-global fan-out                  ; 262                        ;
+; Total fan-out                               ; 10981                      ;
+; Average fan-out                             ; 2.80                       ;
++---------------------------------------------+----------------------------+
+*  Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++------------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics                                                                          ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Statistic                                   ; Top                   ; hard_block:auto_generated_inst ;
++---------------------------------------------+-----------------------+--------------------------------+
+; Difficulty Clustering Region                ; Low                   ; Low                            ;
+;                                             ;                       ;                                ;
+; Total logic elements                        ; 2329 / 15408 ( 15 % ) ; 0 / 15408 ( 0 % )              ;
+;     -- Combinational with no register       ; 1003                  ; 0                              ;
+;     -- Register only                        ; 407                   ; 0                              ;
+;     -- Combinational with a register        ; 919                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic element usage by number of LUT inputs ;                       ;                                ;
+;     -- 4 input functions                    ; 595                   ; 0                              ;
+;     -- 3 input functions                    ; 759                   ; 0                              ;
+;     -- <=2 input functions                  ; 568                   ; 0                              ;
+;     -- Register only                        ; 407                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Logic elements by mode                      ;                       ;                                ;
+;     -- normal mode                          ; 1085                  ; 0                              ;
+;     -- arithmetic mode                      ; 837                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Total registers                             ; 1326                  ; 0                              ;
+;     -- Dedicated logic registers            ; 1326 / 15408 ( 9 % )  ; 0 / 15408 ( 0 % )              ;
+;     -- I/O registers                        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Total LABs:  partially or completely used   ; 195 / 963 ( 20 % )    ; 0 / 963 ( 0 % )                ;
+;                                             ;                       ;                                ;
+; Virtual pins                                ; 0                     ; 0                              ;
+; I/O pins                                    ; 143                   ; 0                              ;
+; Embedded Multiplier 9-bit elements          ; 0 / 112 ( 0 % )       ; 0 / 112 ( 0 % )                ;
+; Total memory bits                           ; 134236                ; 0                              ;
+; Total RAM block bits                        ; 184320                ; 0                              ;
+; PLL                                         ; 0 / 4 ( 0 % )         ; 1 / 4 ( 25 % )                 ;
+; M9K                                         ; 20 / 56 ( 35 % )      ; 0 / 56 ( 0 % )                 ;
+; Clock control block                         ; 9 / 24 ( 37 % )       ; 2 / 24 ( 8 % )                 ;
+;                                             ;                       ;                                ;
+; Connections                                 ;                       ;                                ;
+;     -- Input Connections                    ; 563                   ; 1                              ;
+;     -- Registered Input Connections         ; 512                   ; 0                              ;
+;     -- Output Connections                   ; 51                    ; 513                            ;
+;     -- Registered Output Connections        ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Internal Connections                        ;                       ;                                ;
+;     -- Total Connections                    ; 11211                 ; 521                            ;
+;     -- Registered Connections               ; 4987                  ; 0                              ;
+;                                             ;                       ;                                ;
+; External Connections                        ;                       ;                                ;
+;     -- Top                                  ; 100                   ; 514                            ;
+;     -- hard_block:auto_generated_inst       ; 514                   ; 0                              ;
+;                                             ;                       ;                                ;
+; Partition Interface                         ;                       ;                                ;
+;     -- Input Ports                          ; 16                    ; 1                              ;
+;     -- Output Ports                         ; 77                    ; 2                              ;
+;     -- Bidir Ports                          ; 50                    ; 0                              ;
+;                                             ;                       ;                                ;
+; Registered Ports                            ;                       ;                                ;
+;     -- Registered Input Ports               ; 0                     ; 0                              ;
+;     -- Registered Output Ports              ; 0                     ; 0                              ;
+;                                             ;                       ;                                ;
+; Port Connectivity                           ;                       ;                                ;
+;     -- Input Ports driven by GND            ; 0                     ; 0                              ;
+;     -- Output Ports driven by GND           ; 0                     ; 0                              ;
+;     -- Input Ports driven by VCC            ; 0                     ; 0                              ;
+;     -- Output Ports driven by VCC           ; 0                     ; 0                              ;
+;     -- Input Ports with no Source           ; 0                     ; 0                              ;
+;     -- Output Ports with no Source          ; 0                     ; 0                              ;
+;     -- Input Ports with no Fanout           ; 0                     ; 0                              ;
+;     -- Output Ports with no Fanout          ; 0                     ; 0                              ;
++---------------------------------------------+-----------------------+--------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins                                                                                                                                                                                                                                                                           ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; Name            ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+; CLOCK_50        ; G21   ; 6        ; 41           ; 15           ; 0            ; 106                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[0] ; AB11  ; 3        ; 21           ; 0            ; 14           ; 229                   ; 0                  ; yes    ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; GPIO_1_CLKIN[1] ; AA11  ; 3        ; 21           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[0]          ; H2    ; 1        ; 0            ; 21           ; 7            ; 262                   ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[1]          ; G3    ; 1        ; 0            ; 23           ; 14           ; 2                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; KEY[2]          ; F1    ; 1        ; 0            ; 23           ; 0            ; 1                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[0]           ; J6    ; 1        ; 0            ; 24           ; 0            ; 25                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[1]           ; H5    ; 1        ; 0            ; 27           ; 0            ; 6                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[2]           ; H6    ; 1        ; 0            ; 25           ; 21           ; 15                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[3]           ; G4    ; 1        ; 0            ; 23           ; 7            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[4]           ; G5    ; 1        ; 0            ; 27           ; 21           ; 22                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[5]           ; J7    ; 1        ; 0            ; 22           ; 14           ; 22                    ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[6]           ; H7    ; 1        ; 0            ; 25           ; 14           ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[7]           ; E3    ; 1        ; 0            ; 26           ; 7            ; 4                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[8]           ; E4    ; 1        ; 0            ; 26           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
+; SW[9]           ; D2    ; 1        ; 0            ; 25           ; 0            ; 0                     ; 0                  ; no     ; no             ; no            ; yes             ; no       ; Off          ; 3.3-V LVTTL  ; --                        ; User                 ;
++-----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name             ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; DRAM_ADDR[0]     ; C4    ; 8        ; 1            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[10]    ; B4    ; 8        ; 5            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[11]    ; A7    ; 8        ; 11           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[1]     ; A3    ; 8        ; 3            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[2]     ; B3    ; 8        ; 3            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[3]     ; C3    ; 8        ; 3            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[4]     ; A5    ; 8        ; 7            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[5]     ; C6    ; 8        ; 5            ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[6]     ; B6    ; 8        ; 11           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[7]     ; A6    ; 8        ; 11           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[8]     ; C7    ; 8        ; 9            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_ADDR[9]     ; B7    ; 8        ; 11           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_0        ; B5    ; 8        ; 7            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_BA_1        ; A4    ; 8        ; 5            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CAS_N       ; G8    ; 8        ; 5            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CKE         ; E6    ; 8        ; 1            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CLK         ; E5    ; 8        ; 1            ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_CS_N        ; G7    ; 8        ; 1            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_LDQM        ; E7    ; 8        ; 3            ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_RAS_N       ; F7    ; 8        ; 1            ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_UDQM        ; B8    ; 8        ; 14           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; DRAM_WE_N        ; D6    ; 8        ; 3            ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[0] ; R16   ; 4        ; 37           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; GPIO_1_CLKOUT[1] ; T16   ; 4        ; 37           ; 0            ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[0]          ; E11   ; 7        ; 21           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[1]          ; F11   ; 7        ; 21           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[2]          ; H12   ; 7        ; 26           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[3]          ; H13   ; 7        ; 28           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[4]          ; G12   ; 7        ; 26           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[5]          ; F12   ; 7        ; 28           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX0[6]          ; F13   ; 7        ; 26           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[0]          ; A13   ; 7        ; 21           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[1]          ; B13   ; 7        ; 21           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[2]          ; C13   ; 7        ; 23           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[3]          ; A14   ; 7        ; 23           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[4]          ; B14   ; 7        ; 23           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[5]          ; E14   ; 7        ; 28           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX1[6]          ; A15   ; 7        ; 26           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[0]          ; D15   ; 7        ; 32           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[1]          ; A16   ; 7        ; 30           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[2]          ; B16   ; 7        ; 28           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[3]          ; E15   ; 7        ; 30           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[4]          ; A17   ; 7        ; 30           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[5]          ; B17   ; 7        ; 30           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX2[6]          ; F14   ; 7        ; 37           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[0]          ; B18   ; 7        ; 32           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[1]          ; F15   ; 7        ; 39           ; 29           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[2]          ; A19   ; 7        ; 32           ; 29           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[3]          ; B19   ; 7        ; 32           ; 29           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[4]          ; C19   ; 7        ; 37           ; 29           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[5]          ; D19   ; 7        ; 37           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; HEX3[6]          ; G15   ; 7        ; 39           ; 29           ; 28           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[0]          ; J1    ; 1        ; 0            ; 20           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[1]          ; J2    ; 1        ; 0            ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[2]          ; J3    ; 1        ; 0            ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[3]          ; H1    ; 1        ; 0            ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[4]          ; F2    ; 1        ; 0            ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[5]          ; E1    ; 1        ; 0            ; 24           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[6]          ; C1    ; 1        ; 0            ; 26           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[7]          ; C2    ; 1        ; 0            ; 26           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[8]          ; B2    ; 1        ; 0            ; 27           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; LEDG[9]          ; B1    ; 1        ; 0            ; 27           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[0]         ; K22   ; 6        ; 41           ; 19           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[1]         ; K21   ; 6        ; 41           ; 19           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[2]         ; J22   ; 6        ; 41           ; 19           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_B[3]         ; K18   ; 6        ; 41           ; 21           ; 7            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_CLK          ; V14   ; 4        ; 30           ; 0            ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; Fitter               ; -                    ; -                   ;
+; VGA_G[0]         ; H22   ; 6        ; 41           ; 20           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[1]         ; J17   ; 6        ; 41           ; 24           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[2]         ; K17   ; 6        ; 41           ; 21           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_G[3]         ; J21   ; 6        ; 41           ; 20           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_HS           ; L21   ; 6        ; 41           ; 18           ; 14           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[0]         ; H19   ; 6        ; 41           ; 23           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[1]         ; H17   ; 6        ; 41           ; 25           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[2]         ; H20   ; 6        ; 41           ; 22           ; 0            ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_R[3]         ; H21   ; 6        ; 41           ; 21           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
+; VGA_VS           ; L22   ; 6        ; 41           ; 18           ; 21           ; no              ; no                     ; no            ; 2         ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off         ; --                        ; no                         ; no                          ; User                 ; -                    ; -                   ;
++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; Name        ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source                                               ; Output Enable Group ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+; DRAM_DQ[0]  ; D10   ; 8        ; 16           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[10] ; A9    ; 8        ; 16           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[11] ; C10   ; 8        ; 14           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[12] ; B10   ; 8        ; 16           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[13] ; A10   ; 8        ; 16           ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[14] ; E10   ; 8        ; 16           ; 29           ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[15] ; F10   ; 8        ; 7            ; 29           ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[1]  ; G10   ; 8        ; 9            ; 29           ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[2]  ; H10   ; 8        ; 9            ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[3]  ; E9    ; 8        ; 11           ; 29           ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[4]  ; F9    ; 8        ; 7            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[5]  ; G9    ; 8        ; 9            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[6]  ; H9    ; 8        ; 7            ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[7]  ; F8    ; 8        ; 5            ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[8]  ; A8    ; 8        ; 14           ; 29           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; DRAM_DQ[9]  ; B9    ; 8        ; 14           ; 29           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE (inverted) ; -                   ;
+; GPIO_1[0]   ; AA20  ; 4        ; 37           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[10]  ; U15   ; 4        ; 39           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[11]  ; T15   ; 4        ; 32           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[12]  ; W15   ; 4        ; 32           ; 0            ; 21           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[13]  ; V15   ; 4        ; 32           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[14]  ; AB9   ; 3        ; 16           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[15]  ; AA9   ; 3        ; 16           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[16]  ; AA7   ; 3        ; 11           ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[17]  ; AB7   ; 3        ; 11           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[18]  ; T14   ; 4        ; 32           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[19]  ; R14   ; 4        ; 39           ; 0            ; 14           ; 4                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO               ; -                   ;
+; GPIO_1[1]   ; AB20  ; 4        ; 37           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[20]  ; U12   ; 4        ; 26           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[21]  ; T12   ; 4        ; 28           ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[22]  ; R11   ; 3        ; 3            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[23]  ; R12   ; 3        ; 5            ; 0            ; 28           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[24]  ; U10   ; 3        ; 14           ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[25]  ; T10   ; 3        ; 14           ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[26]  ; U9    ; 3        ; 9            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[27]  ; T9    ; 3        ; 1            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[28]  ; Y7    ; 3        ; 9            ; 0            ; 7            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[29]  ; U8    ; 3        ; 3            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[2]   ; AA19  ; 4        ; 35           ; 0            ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[30]  ; V6    ; 3        ; 1            ; 0            ; 0            ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[31]  ; V7    ; 3        ; 7            ; 0            ; 14           ; 0                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[3]   ; AB19  ; 4        ; 35           ; 0            ; 14           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[4]   ; AB18  ; 4        ; 32           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[5]   ; AA18  ; 4        ; 35           ; 0            ; 28           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[6]   ; AA17  ; 4        ; 28           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[7]   ; AB17  ; 4        ; 28           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[8]   ; Y17   ; 4        ; 35           ; 0            ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; GPIO_1[9]   ; W17   ; 4        ; 35           ; 0            ; 7            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; -                                                                  ; -                   ;
+; PS2_CLK     ; P22   ; 5        ; 41           ; 11           ; 0            ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; yes        ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; ps2:inst6|ce~0 (inverted)                                          ; -                   ;
+; PS2_DAT     ; P21   ; 5        ; 41           ; 12           ; 21           ; 1                     ; 0                  ; no     ; no             ; no              ; no                     ; no            ; 2         ; yes             ; no         ; no       ; Off          ; 3.3-V LVTTL  ; 8mA              ; Off                ; --                        ; User                 ; 0 pF ; ps2:inst6|de~0 (inverted)                                          ; -                   ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+--------------------------------------------------------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins                                                                                                      ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name                                 ; Reserved As              ; User Signal Name        ; Pin Type                  ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+; E4       ; DIFFIO_L2p, nRESET                       ; Use as regular IO        ; SW[8]                   ; Dual Purpose Pin          ;
+; D1       ; DIFFIO_L4n, DATA1, ASDO                  ; As input tri-stated      ; ~ALTERA_ASDO_DATA1~     ; Dual Purpose Pin          ;
+; E2       ; DIFFIO_L6p, FLASH_nCE, nCSO              ; As input tri-stated      ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin          ;
+; K6       ; nSTATUS                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; K2       ; DCLK                                     ; As output driving ground ; ~ALTERA_DCLK~           ; Dual Purpose Pin          ;
+; K1       ; DATA0                                    ; As input tri-stated      ; ~ALTERA_DATA0~          ; Dual Purpose Pin          ;
+; K5       ; nCONFIG                                  ; -                        ; -                       ; Dedicated Programming Pin ;
+; L3       ; nCE                                      ; -                        ; -                       ; Dedicated Programming Pin ;
+; M18      ; CONF_DONE                                ; -                        ; -                       ; Dedicated Programming Pin ;
+; M17      ; MSEL0                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L18      ; MSEL1                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L17      ; MSEL2                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; K20      ; MSEL3                                    ; -                        ; -                       ; Dedicated Programming Pin ;
+; L22      ; DIFFIO_R17n, INIT_DONE                   ; Use as regular IO        ; VGA_VS                  ; Dual Purpose Pin          ;
+; L21      ; DIFFIO_R17p, CRC_ERROR                   ; Use as regular IO        ; VGA_HS                  ; Dual Purpose Pin          ;
+; K22      ; DIFFIO_R16n, nCEO                        ; Use as programming pin   ; VGA_B[0]                ; Dual Purpose Pin          ;
+; K21      ; DIFFIO_R16p, CLKUSR                      ; Use as regular IO        ; VGA_B[1]                ; Dual Purpose Pin          ;
+; B18      ; DIFFIO_T27p, PADD0                       ; Use as regular IO        ; HEX3[0]                 ; Dual Purpose Pin          ;
+; A17      ; DIFFIO_T25n, PADD1                       ; Use as regular IO        ; HEX2[4]                 ; Dual Purpose Pin          ;
+; B17      ; DIFFIO_T25p, PADD2                       ; Use as regular IO        ; HEX2[5]                 ; Dual Purpose Pin          ;
+; E14      ; DIFFIO_T23n, PADD3                       ; Use as regular IO        ; HEX1[5]                 ; Dual Purpose Pin          ;
+; F13      ; DIFFIO_T21p, PADD4, DQS2T/CQ3T,DPCLK8    ; Use as regular IO        ; HEX0[6]                 ; Dual Purpose Pin          ;
+; A15      ; DIFFIO_T20n, PADD5                       ; Use as regular IO        ; HEX1[6]                 ; Dual Purpose Pin          ;
+; C13      ; DIFFIO_T19n, PADD7                       ; Use as regular IO        ; HEX1[2]                 ; Dual Purpose Pin          ;
+; A14      ; DIFFIO_T18n, PADD9                       ; Use as regular IO        ; HEX1[3]                 ; Dual Purpose Pin          ;
+; B14      ; DIFFIO_T18p, PADD10                      ; Use as regular IO        ; HEX1[4]                 ; Dual Purpose Pin          ;
+; A13      ; DIFFIO_T17n, PADD11                      ; Use as regular IO        ; HEX1[0]                 ; Dual Purpose Pin          ;
+; B13      ; DIFFIO_T17p, PADD12, DQS4T/CQ5T,DPCLK9   ; Use as regular IO        ; HEX1[1]                 ; Dual Purpose Pin          ;
+; E11      ; DIFFIO_T16n, PADD13                      ; Use as regular IO        ; HEX0[0]                 ; Dual Purpose Pin          ;
+; F11      ; DIFFIO_T16p, PADD14                      ; Use as regular IO        ; HEX0[1]                 ; Dual Purpose Pin          ;
+; B10      ; DIFFIO_T14p, PADD15                      ; Use as regular IO        ; DRAM_DQ[12]             ; Dual Purpose Pin          ;
+; A9       ; DIFFIO_T13n, PADD16                      ; Use as regular IO        ; DRAM_DQ[10]             ; Dual Purpose Pin          ;
+; B9       ; DIFFIO_T13p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO        ; DRAM_DQ[9]              ; Dual Purpose Pin          ;
+; A8       ; DIFFIO_T12n, DATA2                       ; Use as regular IO        ; DRAM_DQ[8]              ; Dual Purpose Pin          ;
+; B8       ; DIFFIO_T12p, DATA3                       ; Use as regular IO        ; DRAM_UDQM               ; Dual Purpose Pin          ;
+; A7       ; DIFFIO_T11n, PADD18                      ; Use as regular IO        ; DRAM_ADDR[11]           ; Dual Purpose Pin          ;
+; B7       ; DIFFIO_T11p, DATA4                       ; Use as regular IO        ; DRAM_ADDR[9]            ; Dual Purpose Pin          ;
+; A6       ; DIFFIO_T10n, PADD19                      ; Use as regular IO        ; DRAM_ADDR[7]            ; Dual Purpose Pin          ;
+; B6       ; DIFFIO_T10p, DATA15                      ; Use as regular IO        ; DRAM_ADDR[6]            ; Dual Purpose Pin          ;
+; C7       ; DIFFIO_T9p, DATA13                       ; Use as regular IO        ; DRAM_ADDR[8]            ; Dual Purpose Pin          ;
+; A5       ; DATA5                                    ; Use as regular IO        ; DRAM_ADDR[4]            ; Dual Purpose Pin          ;
+; F10      ; DIFFIO_T6p, DATA6                        ; Use as regular IO        ; DRAM_DQ[15]             ; Dual Purpose Pin          ;
+; C6       ; DATA7                                    ; Use as regular IO        ; DRAM_ADDR[5]            ; Dual Purpose Pin          ;
+; B4       ; DIFFIO_T5p, DATA8                        ; Use as regular IO        ; DRAM_ADDR[10]           ; Dual Purpose Pin          ;
+; F8       ; DIFFIO_T4n, DATA9                        ; Use as regular IO        ; DRAM_DQ[7]              ; Dual Purpose Pin          ;
+; A3       ; DIFFIO_T3n, DATA10                       ; Use as regular IO        ; DRAM_ADDR[1]            ; Dual Purpose Pin          ;
+; B3       ; DIFFIO_T3p, DATA11                       ; Use as regular IO        ; DRAM_ADDR[2]            ; Dual Purpose Pin          ;
+; C4       ; DIFFIO_T2p, DATA12, DQS1T/CQ1T#,CDPCLK7  ; Use as regular IO        ; DRAM_ADDR[0]            ; Dual Purpose Pin          ;
++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+
+
+
++------------------------------------------------------------+
+; I/O Bank Usage                                             ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage            ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1        ; 27 / 33 ( 82 % ) ; 3.3V          ; --           ;
+; 2        ; 0 / 48 ( 0 % )   ; 3.3V          ; --           ;
+; 3        ; 16 / 46 ( 35 % ) ; 3.3V          ; --           ;
+; 4        ; 21 / 41 ( 51 % ) ; 3.3V          ; --           ;
+; 5        ; 2 / 46 ( 4 % )   ; 3.3V          ; --           ;
+; 6        ; 15 / 43 ( 35 % ) ; 3.3V          ; --           ;
+; 7        ; 28 / 47 ( 60 % ) ; 3.3V          ; --           ;
+; 8        ; 38 / 43 ( 88 % ) ; 3.3V          ; --           ;
++----------+------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins                                                                                                                                                                        ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage                                            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; A2       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A3       ; 354        ; 8        ; DRAM_ADDR[1]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A4       ; 350        ; 8        ; DRAM_BA_1                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A5       ; 345        ; 8        ; DRAM_ADDR[4]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A6       ; 336        ; 8        ; DRAM_ADDR[7]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A7       ; 334        ; 8        ; DRAM_ADDR[11]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A8       ; 332        ; 8        ; DRAM_DQ[8]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A9       ; 328        ; 8        ; DRAM_DQ[10]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A10      ; 326        ; 8        ; DRAM_DQ[13]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A11      ; 321        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A12      ; 319        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; A13      ; 314        ; 7        ; HEX1[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A14      ; 312        ; 7        ; HEX1[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A15      ; 307        ; 7        ; HEX1[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A16      ; 298        ; 7        ; HEX2[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A17      ; 296        ; 7        ; HEX2[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A18      ; 291        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A19      ; 290        ; 7        ; HEX3[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; A20      ; 284        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; A21      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; A22      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AA1      ; 76         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA2      ; 75         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA3      ; 102        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA4      ; 106        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA5      ; 108        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA6      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AA7      ; 115        ; 3        ; GPIO_1[16]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA8      ; 123        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA9      ; 126        ; 3        ; GPIO_1[15]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA10     ; 132        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA11     ; 134        ; 3        ; GPIO_1_CLKIN[1]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA12     ; 136        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AA13     ; 138        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA14     ; 140        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA15     ; 145        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA16     ; 149        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AA17     ; 151        ; 4        ; GPIO_1[6]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA18     ; 163        ; 4        ; GPIO_1[5]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA19     ; 164        ; 4        ; GPIO_1[2]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA20     ; 169        ; 4        ; GPIO_1[0]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AA21     ; 179        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AA22     ; 178        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; AB1      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB2      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB3      ; 103        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB4      ; 107        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB5      ; 109        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB6      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; AB7      ; 116        ; 3        ; GPIO_1[17]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB8      ; 124        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB9      ; 127        ; 3        ; GPIO_1[14]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB10     ; 133        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB11     ; 135        ; 3        ; GPIO_1_CLKIN[0]                                           ; input  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB12     ; 137        ; 4        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; AB13     ; 139        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB14     ; 141        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB15     ; 146        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB16     ; 150        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; AB17     ; 152        ; 4        ; GPIO_1[7]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB18     ; 162        ; 4        ; GPIO_1[4]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB19     ; 165        ; 4        ; GPIO_1[3]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB20     ; 170        ; 4        ; GPIO_1[1]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; AB21     ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; AB22     ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; B1       ; 2          ; 1        ; LEDG[9]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B2       ; 1          ; 1        ; LEDG[8]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; B3       ; 355        ; 8        ; DRAM_ADDR[2]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B4       ; 351        ; 8        ; DRAM_ADDR[10]                                             ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B5       ; 346        ; 8        ; DRAM_BA_0                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B6       ; 337        ; 8        ; DRAM_ADDR[6]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B7       ; 335        ; 8        ; DRAM_ADDR[9]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B8       ; 333        ; 8        ; DRAM_UDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B9       ; 329        ; 8        ; DRAM_DQ[9]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B10      ; 327        ; 8        ; DRAM_DQ[12]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B11      ; 322        ; 8        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B12      ; 320        ; 7        ; GND+                                                      ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; B13      ; 315        ; 7        ; HEX1[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B14      ; 313        ; 7        ; HEX1[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B15      ; 308        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B16      ; 299        ; 7        ; HEX2[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B17      ; 297        ; 7        ; HEX2[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B18      ; 292        ; 7        ; HEX3[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B19      ; 289        ; 7        ; HEX3[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; B20      ; 285        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; B21      ; 269        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; B22      ; 268        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C1       ; 7          ; 1        ; LEDG[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C2       ; 6          ; 1        ; LEDG[7]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; C3       ; 358        ; 8        ; DRAM_ADDR[3]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C4       ; 359        ; 8        ; DRAM_ADDR[0]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C6       ; 349        ; 8        ; DRAM_ADDR[5]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C7       ; 340        ; 8        ; DRAM_ADDR[8]                                              ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C8       ; 339        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C10      ; 330        ; 8        ; DRAM_DQ[11]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C13      ; 309        ; 7        ; HEX1[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C14      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C15      ; 300        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; C16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C17      ; 286        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; C18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; C19      ; 282        ; 7        ; HEX3[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; C20      ; 270        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C21      ; 267        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; C22      ; 266        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D1       ; 9          ; 1        ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; D2       ; 8          ; 1        ; SW[9]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; D3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D5       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D6       ; 356        ; 8        ; DRAM_WE_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D7       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; D9       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D10      ; 324        ; 8        ; DRAM_DQ[0]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D11      ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D12      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D13      ; 310        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; D14      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D15      ; 293        ; 7        ; HEX2[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D16      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D17      ; 281        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; D18      ;            ; 7        ; VCCIO7                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; D19      ; 283        ; 7        ; HEX3[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; D20      ; 271        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D21      ; 261        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; D22      ; 260        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E1       ; 14         ; 1        ; LEDG[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E2       ; 13         ; 1        ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; E3       ; 5          ; 1        ; SW[7]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E4       ; 4          ; 1        ; SW[8]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; E5       ; 363        ; 8        ; DRAM_CLK                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E6       ; 362        ; 8        ; DRAM_CKE                                                  ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E7       ; 357        ; 8        ; DRAM_LDQM                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E8       ;            ; 8        ; VCCIO8                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E9       ; 338        ; 8        ; DRAM_DQ[3]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E10      ; 325        ; 8        ; DRAM_DQ[14]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E11      ; 317        ; 7        ; HEX0[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E12      ; 316        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E13      ; 311        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E14      ; 301        ; 7        ; HEX1[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E15      ; 294        ; 7        ; HEX2[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; E16      ; 275        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; E17      ;            ;          ; VCCD_PLL2                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; E18      ;            ;          ; GNDA2                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; E20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; E21      ; 256        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; E22      ; 255        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F1       ; 16         ; 1        ; KEY[2]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F2       ; 15         ; 1        ; LEDG[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; F3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; F5       ;            ;          ; GNDA3                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; F6       ;            ;          ; VCCD_PLL3                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; F7       ; 360        ; 8        ; DRAM_RAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F8       ; 352        ; 8        ; DRAM_DQ[7]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F9       ; 347        ; 8        ; DRAM_DQ[4]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F10      ; 348        ; 8        ; DRAM_DQ[15]                                               ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F11      ; 318        ; 7        ; HEX0[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F12      ; 302        ; 7        ; HEX0[5]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F13      ; 306        ; 7        ; HEX0[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F14      ; 279        ; 7        ; HEX2[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F15      ; 276        ; 7        ; HEX3[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; F16      ; 274        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; F17      ; 272        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F18      ;            ; --       ; VCCA2                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; F19      ; 263        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F20      ; 262        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F21      ; 251        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; F22      ; 250        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G1       ; 39         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G2       ; 38         ; 1        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; G3       ; 18         ; 1        ; KEY[1]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G4       ; 17         ; 1        ; SW[3]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G5       ; 3          ; 1        ; SW[4]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G6       ;            ; --       ; VCCA3                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; G7       ; 361        ; 8        ; DRAM_CS_N                                                 ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G8       ; 353        ; 8        ; DRAM_CAS_N                                                ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G9       ; 342        ; 8        ; DRAM_DQ[5]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G10      ; 341        ; 8        ; DRAM_DQ[1]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G11      ; 331        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G12      ; 305        ; 7        ; HEX0[4]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G13      ; 295        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G14      ; 280        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G15      ; 278        ; 7        ; HEX3[6]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; G16      ; 277        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; G17      ; 273        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G18      ; 264        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; G19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; G20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; G21      ; 226        ; 6        ; CLOCK_50                                                  ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; G22      ; 225        ; 6        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H1       ; 26         ; 1        ; LEDG[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H2       ; 25         ; 1        ; KEY[0]                                                    ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; H5       ; 0          ; 1        ; SW[1]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H6       ; 11         ; 1        ; SW[2]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H7       ; 10         ; 1        ; SW[6]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H8       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; H9       ; 344        ; 8        ; DRAM_DQ[6]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H10      ; 343        ; 8        ; DRAM_DQ[2]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H11      ; 323        ; 8        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H12      ; 304        ; 7        ; HEX0[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H13      ; 303        ; 7        ; HEX0[3]                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; H14      ; 288        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H15      ; 287        ; 7        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; H16      ; 259        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; H17      ; 265        ; 6        ; VGA_R[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H18      ; 257        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; H19      ; 254        ; 6        ; VGA_R[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H20      ; 253        ; 6        ; VGA_R[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H21      ; 246        ; 6        ; VGA_R[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; H22      ; 245        ; 6        ; VGA_G[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J1       ; 29         ; 1        ; LEDG[0]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J2       ; 28         ; 1        ; LEDG[1]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J3       ; 27         ; 1        ; LEDG[2]                                                   ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J4       ; 24         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J6       ; 12         ; 1        ; SW[0]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J7       ; 22         ; 1        ; SW[5]                                                     ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J8       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; J15      ; 238        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J16      ; 243        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J17      ; 258        ; 6        ; VGA_G[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J18      ; 249        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; J19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; J20      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; J21      ; 242        ; 6        ; VGA_G[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; J22      ; 241        ; 6        ; VGA_B[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K1       ; 31         ; 1        ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP          ; input  ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K2       ; 30         ; 1        ; ~ALTERA_DCLK~                                             ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; N               ; no       ; On           ;
+; K3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K4       ;            ; 1        ; VCCIO1                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; K5       ; 32         ; 1        ; ^nCONFIG                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K6       ; 19         ; 1        ; ^nSTATUS                                                  ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K7       ; 23         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K8       ; 21         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; K14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; K15      ; 236        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K16      ; 244        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; K17      ; 247        ; 6        ; VGA_G[2]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K18      ; 248        ; 6        ; VGA_B[3]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K19      ; 237        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; K20      ; 231        ; 6        ; ^MSEL3                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; K21      ; 240        ; 6        ; VGA_B[1]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; K22      ; 239        ; 6        ; VGA_B[0]                                                  ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L1       ; 35         ; 1        ; #TMS                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L2       ; 34         ; 1        ; #TCK                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L3       ; 37         ; 1        ; ^nCE                                                      ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L4       ; 36         ; 1        ; #TDO                                                      ; output ;              ;         ; --         ;                 ; --       ; --           ;
+; L5       ; 33         ; 1        ; #TDI                                                      ; input  ;              ;         ; --         ;                 ; --       ; --           ;
+; L6       ; 42         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L7       ; 50         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L8       ; 20         ; 1        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; L15      ; 233        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L16      ; 232        ; 6        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; L17      ; 230        ; 6        ; ^MSEL2                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L18      ; 229        ; 6        ; ^MSEL1                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; L19      ;            ; 6        ; VCCIO6                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; L20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; L21      ; 235        ; 6        ; VGA_HS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; L22      ; 234        ; 6        ; VGA_VS                                                    ; output ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; M1       ; 45         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M2       ; 44         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M3       ; 47         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M4       ; 46         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M5       ; 51         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; M6       ; 43         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M7       ; 65         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M8       ; 66         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; M14      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; M15      ; 195        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M16      ; 222        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M17      ; 228        ; 6        ; ^MSEL0                                                    ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M18      ; 227        ; 6        ; ^CONF_DONE                                                ;        ;              ;         ; --         ;                 ; --       ; --           ;
+; M19      ; 221        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M20      ; 220        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M21      ; 219        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; M22      ; 218        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N1       ; 49         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N2       ; 48         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; N5       ; 56         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N6       ; 64         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N7       ; 73         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N8       ; 67         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; N10      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N13      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; N14      ; 189        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N15      ; 196        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N16      ; 205        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N17      ; 214        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N18      ; 215        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N19      ; 213        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N20      ; 212        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N21      ; 217        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; N22      ; 216        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P1       ; 53         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P2       ; 52         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P3       ; 58         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P4       ; 57         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P5       ; 63         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P6       ; 79         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P7       ; 74         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P8       ; 86         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P9       ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P10      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P11      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P12      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; P14      ; 180        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P15      ; 192        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P16      ; 193        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P17      ; 197        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; P18      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; P19      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; P20      ; 208        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; P21      ; 211        ; 5        ; PS2_DAT                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; P22      ; 210        ; 5        ; PS2_CLK                                                   ; bidir  ; 3.3-V LVTTL  ;         ; Row I/O    ; Y               ; no       ; Off          ;
+; R1       ; 55         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R2       ; 54         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; R4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; R5       ; 80         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R6       ; 83         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R7       ; 84         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R8       ; 87         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R9       ; 88         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R10      ; 90         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R11      ; 97         ; 3        ; GPIO_1[22]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R12      ; 98         ; 3        ; GPIO_1[23]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R13      ; 153        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R14      ; 175        ; 4        ; GPIO_1[19]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R15      ; 176        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; R16      ; 172        ; 4        ; GPIO_1_CLKOUT[0]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; R17      ; 194        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; R18      ; 203        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R19      ; 204        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R20      ; 200        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R21      ; 207        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; R22      ; 206        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T1       ; 41         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T2       ; 40         ; 2        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T3       ; 72         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T4       ; 81         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T5       ; 82         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T6       ;            ; --       ; VCCA1                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; T7       ; 85         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T8       ; 89         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T9       ; 91         ; 3        ; GPIO_1[27]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T10      ; 121        ; 3        ; GPIO_1[25]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T11      ; 125        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; T12      ; 148        ; 4        ; GPIO_1[21]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T13      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; T14      ; 160        ; 4        ; GPIO_1[18]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T15      ; 161        ; 4        ; GPIO_1[11]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T16      ; 171        ; 4        ; GPIO_1_CLKOUT[1]                                          ; output ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; T17      ; 181        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T18      ; 182        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; T19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; T20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; T21      ; 224        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; T22      ; 223        ; 5        ; GND+                                                      ;        ;              ;         ; Row I/O    ;                 ; --       ; --           ;
+; U1       ; 60         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U2       ; 59         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; U5       ;            ;          ; GNDA1                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; U6       ;            ;          ; VCCD_PLL1                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U7       ; 94         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U8       ; 95         ; 3        ; GPIO_1[29]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U9       ; 112        ; 3        ; GPIO_1[26]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U10      ; 122        ; 3        ; GPIO_1[24]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U11      ; 128        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U12      ; 147        ; 4        ; GPIO_1[20]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U13      ; 156        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U14      ; 174        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; U15      ; 173        ; 4        ; GPIO_1[10]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; U16      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U17      ;            ;          ; VCCINT                                                    ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; U18      ;            ; --       ; VCCA4                                                     ; power  ;              ; 2.5V    ; --         ;                 ; --       ; --           ;
+; U19      ; 188        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U20      ; 187        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U21      ; 202        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; U22      ; 201        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V1       ; 62         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V2       ; 61         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V3       ; 78         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V4       ; 77         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V5       ; 93         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V6       ; 92         ; 3        ; GPIO_1[30]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V7       ; 105        ; 3        ; GPIO_1[31]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V8       ; 113        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V9       ; 119        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V10      ; 120        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V11      ; 129        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V12      ; 142        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V13      ; 154        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; V14      ; 157        ; 4        ; VGA_CLK                                                   ; output ; 3.3-V LVTTL  ;         ; Column I/O ; N               ; no       ; Off          ;
+; V15      ; 158        ; 4        ; GPIO_1[13]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; V16      ; 168        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; V17      ;            ;          ; VCCD_PLL4                                                 ; power  ;              ; 1.2V    ; --         ;                 ; --       ; --           ;
+; V18      ;            ;          ; GNDA4                                                     ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; V20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; V21      ; 199        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; V22      ; 198        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W1       ; 69         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W2       ; 68         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W3       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; W4       ;            ; 2        ; VCCIO2                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W5       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W6       ; 104        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W7       ; 110        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W8       ; 114        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W9       ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W10      ; 130        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W11      ;            ; 3        ; VCCIO3                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W12      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W13      ; 143        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; W14      ; 155        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; W15      ; 159        ; 4        ; GPIO_1[12]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W16      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W17      ; 166        ; 4        ; GPIO_1[9]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; W18      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; W19      ; 184        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W20      ; 183        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W21      ; 191        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; W22      ; 190        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y1       ; 71         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y2       ; 70         ; 2        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y3       ; 99         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y4       ; 96         ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; --       ; --           ;
+; Y5       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y6       ; 101        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y7       ; 111        ; 3        ; GPIO_1[28]                                                ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y8       ; 117        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y9       ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y10      ; 131        ; 3        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y11      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y12      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y13      ; 144        ; 4        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Column I/O ;                 ; no       ; On           ;
+; Y14      ;            ; 4        ; VCCIO4                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y15      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y16      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y17      ; 167        ; 4        ; GPIO_1[8]                                                 ; bidir  ; 3.3-V LVTTL  ;         ; Column I/O ; Y               ; no       ; Off          ;
+; Y18      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y19      ;            ; 5        ; VCCIO5                                                    ; power  ;              ; 3.3V    ; --         ;                 ; --       ; --           ;
+; Y20      ;            ;          ; GND                                                       ; gnd    ;              ;         ; --         ;                 ; --       ; --           ;
+; Y21      ; 186        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
+; Y22      ; 185        ; 5        ; RESERVED_INPUT_WITH_WEAK_PULLUP                           ;        ;              ;         ; Row I/O    ;                 ; no       ; On           ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; PLL Summary                                                                                                       ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; Name                          ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1 ;
++-------------------------------+-----------------------------------------------------------------------------------+
+; SDC pin name                  ; inst|u6|altpll_component|auto_generated|pll1                                      ;
+; PLL mode                      ; Normal                                                                            ;
+; Compensate clock              ; clock0                                                                            ;
+; Compensated input/output pins ; --                                                                                ;
+; Switchover type               ; --                                                                                ;
+; Input frequency 0             ; 50.0 MHz                                                                          ;
+; Input frequency 1             ; --                                                                                ;
+; Nominal PFD frequency         ; 25.0 MHz                                                                          ;
+; Nominal VCO frequency         ; 625.0 MHz                                                                         ;
+; VCO post scale K counter      ; 2                                                                                 ;
+; VCO frequency control         ; Auto                                                                              ;
+; VCO phase shift step          ; 200 ps                                                                            ;
+; VCO multiply                  ; --                                                                                ;
+; VCO divide                    ; --                                                                                ;
+; Freq min lock                 ; 24.0 MHz                                                                          ;
+; Freq max lock                 ; 52.02 MHz                                                                         ;
+; M VCO Tap                     ; 5                                                                                 ;
+; M Initial                     ; 2                                                                                 ;
+; M value                       ; 25                                                                                ;
+; N value                       ; 2                                                                                 ;
+; Charge pump current           ; setting 1                                                                         ;
+; Loop filter resistance        ; setting 24                                                                        ;
+; Loop filter capacitance       ; setting 0                                                                         ;
+; Bandwidth                     ; 450 kHz to 980 kHz                                                                ;
+; Bandwidth type                ; Medium                                                                            ;
+; Real time reconfigurable      ; Off                                                                               ;
+; Scan chain MIF file           ; --                                                                                ;
+; Preserve PLL counter order    ; Off                                                                               ;
+; PLL location                  ; PLL_2                                                                             ;
+; Inclk0 signal                 ; CLOCK_50                                                                          ;
+; Inclk1 signal                 ; --                                                                                ;
+; Inclk0 signal type            ; Dedicated Pin                                                                     ;
+; Inclk1 signal type            ; --                                                                                ;
++-------------------------------+-----------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage                                                                                                                                                                                                                                                                                                             ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; Name                                                                                ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift     ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name                                        ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; clock0       ; 5    ; 2   ; 125.0 MHz        ; 0 (0 ps)        ; 9.00 (200 ps)    ; 50/50      ; C0      ; 5             ; 3/2 Odd    ; --            ; 2       ; 5       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; clock1       ; 5    ; 2   ; 125.0 MHz        ; -117 (-2600 ps) ; 9.00 (200 ps)    ; 50/50      ; C1      ; 5             ; 3/2 Odd    ; --            ; 1       ; 0       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------------------------------------------------------------------------+--------------+------+-----+------------------+-----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                               ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_DE0_CAMERA_MOUSE                                    ; 2329 (2)    ; 1326 (0)                  ; 0 (0)         ; 134236      ; 20   ; 0            ; 0       ; 0         ; 143  ; 0            ; 1003 (2)     ; 407 (0)           ; 919 (0)          ; |TOP_DE0_CAMERA_MOUSE                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                        ; 1450 (15)   ; 1013 (15)                 ; 0 (0)         ; 62416       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 437 (0)      ; 287 (14)          ; 726 (1)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                                   ; 42 (42)     ; 33 (33)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 9 (9)        ; 2 (2)             ; 31 (31)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                                ; 252 (171)   ; 132 (94)                  ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 120 (77)     ; 14 (3)            ; 118 (92)         ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                             ; 81 (81)     ; 38 (38)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 43 (43)      ; 11 (11)           ; 27 (27)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                       ; 87 (71)     ; 66 (55)                   ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 21 (16)      ; 3 (3)             ; 63 (52)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                                ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component|      ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|           ; 16 (0)      ; 11 (0)                    ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 11 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|          ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 30672       ; 6    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                       ; 16 (13)     ; 11 (11)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 11 (11)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|                    ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                                   ; 50 (50)     ; 35 (35)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 15 (15)      ; 0 (0)             ; 35 (35)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |Sdram_Control_4Port:u7|                           ; 924 (235)   ; 704 (137)                 ; 0 (0)         ; 31744       ; 4    ; 0            ; 0       ; 0         ; 0    ; 0            ; 220 (94)     ; 254 (21)          ; 450 (119)        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                         ; 140 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 58 (0)            ; 58 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 140 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (0)       ; 58 (0)            ; 58 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 140 (42)    ; 116 (30)                  ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (11)      ; 58 (23)           ; 58 (4)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 15 (15)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 1 (1)             ; 13 (13)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (0)            ; 2 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 18 (18)           ; 2 (2)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                         ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 56 (0)            ; 60 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 56 (0)            ; 60 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 139 (42)    ; 116 (30)                  ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (9)       ; 56 (26)           ; 60 (6)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 1 (1)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 6 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 7680        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                        ; 134 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (0)       ; 46 (0)            ; 70 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 134 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (0)       ; 46 (0)            ; 70 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 134 (41)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 18 (6)       ; 46 (18)           ; 70 (13)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 17 (17)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (0)            ; 6 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 14 (14)           ; 6 (6)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                        ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 55 (0)            ; 61 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 139 (0)     ; 116 (0)                   ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (0)       ; 55 (0)            ; 61 (0)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 139 (42)    ; 116 (30)                  ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 23 (9)       ; 55 (26)           ; 61 (6)           ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 8 (8)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 21 (21)     ; 14 (14)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 6 (6)        ; 1 (1)             ; 14 (14)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (0)            ; 5 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 15 (15)           ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 20 (0)      ; 20 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (0)            ; 7 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 20 (20)     ; 20 (20)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 13 (13)           ; 7 (7)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 8192        ; 1    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 9 (9)       ; 9 (9)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                              ; 62 (62)     ; 48 (48)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 14 (14)      ; 2 (2)             ; 46 (46)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|                    ; 80 (80)     ; 55 (55)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 24 (24)      ; 16 (16)           ; 40 (40)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                                ; 80 (80)     ; 28 (28)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 52 (52)      ; 0 (0)             ; 28 (28)          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                     ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                       ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|                 ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
+;    |altshift_taps:fifo_inst2|                            ; 15 (0)      ; 10 (0)                    ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 10 (0)           ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2                                                                                                                                       ; work         ;
+;       |shift_taps_lpm:auto_generated|                    ; 15 (0)      ; 10 (0)                    ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 10 (0)           ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated                                                                                                         ; work         ;
+;          |altsyncram_vp81:altsyncram2|                   ; 0 (0)       ; 0 (0)                     ; 0 (0)         ; 71820       ; 10   ; 0            ; 0       ; 0         ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2                                                                             ; work         ;
+;          |cntr_1tf:cntr1|                                ; 15 (12)     ; 10 (10)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (2)        ; 0 (0)             ; 10 (10)          ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1                                                                                          ; work         ;
+;             |cmpr_ugc:cmpr4|                             ; 3 (3)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4                                                                           ; work         ;
+;    |mean_vga:vga_blur_catapult_inst|                     ; 602 (0)     ; 192 (0)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 410 (0)      ; 83 (0)            ; 109 (0)          ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst                                                                                                                                ; work         ;
+;       |mean_vga_core:mean_vga_core_inst|                 ; 602 (575)   ; 192 (192)                 ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 410 (383)    ; 83 (83)           ; 109 (109)        ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst                                                                                               ; work         ;
+;          |lpm_mult:Mult0|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult1|                                ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult2|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult3|                                ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult4|                                ; 5 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult5|                                ; 4 (0)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (0)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core                                                             ; work         ;
+;    |ps2:inst6|                                           ; 139 (111)   ; 99 (99)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 40 (12)      ; 37 (37)           ; 62 (62)          ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6                                                                                                                                                      ; work         ;
+;       |SEG7_LUT:U1|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U2|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U3|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U4|                                      ; 7 (7)       ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4                                                                                                                                          ; work         ;
+;    |vga_mouse_square:vga_mouse_catapult_inst|            ; 101 (0)     ; 12 (0)                    ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 89 (0)       ; 0 (0)             ; 12 (0)           ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst                                                                                                                       ; work         ;
+;       |vga_mouse_square_core:vga_mouse_square_core_inst| ; 101 (101)   ; 12 (12)                   ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 89 (89)      ; 0 (0)             ; 12 (12)          ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst                                                                      ; work         ;
+;    |vga_mux:inst10|                                      ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 4 (0)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                                                                                                                                 ; work         ;
+;       |lpm_mux:LPM_MUX_component|                        ; 24 (0)      ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (0)       ; 0 (0)             ; 4 (0)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component                                                                                                                       ; work         ;
+;          |mux_u7e:auto_generated|                        ; 24 (24)     ; 0 (0)                     ; 0 (0)         ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; 20 (20)      ; 0 (0)             ; 4 (4)            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated                                                                                                ; work         ;
++----------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++--------------------------------------------------------------------------------------------------+
+; Delay Chain Summary                                                                              ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name             ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+; DRAM_LDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[1]  ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[9]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; SW[8]            ; Input    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_UDQM        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_1        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_BA_0        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CKE         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CS_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_RAS_N       ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_WE_N        ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_CLK         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_CLK          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_HS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_VS           ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[11]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[10]    ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[9]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[8]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[7]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[6]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[5]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[4]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[3]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[2]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[1]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_ADDR[0]     ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[1] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKOUT[0] ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX0[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX1[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX2[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; HEX3[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[9]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[8]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[7]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[6]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[5]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[4]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[3]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[2]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[1]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; LEDG[0]          ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_B[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_G[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[3]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[2]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[1]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; VGA_R[0]         ; Output   ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[15]      ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[14]      ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[13]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[12]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[11]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[10]      ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[9]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[8]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[7]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[6]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[5]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[4]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; DRAM_DQ[3]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[2]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[1]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; DRAM_DQ[0]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[31]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[30]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[29]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[28]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[27]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[26]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[25]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[24]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[23]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[22]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[21]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[20]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[19]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[18]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[17]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[16]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[15]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[14]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[13]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[12]       ; Bidir    ; --            ; --            ; --                    ; --  ; --   ;
+; GPIO_1[11]       ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[10]       ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[9]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[8]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[7]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[6]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[5]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[4]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; GPIO_1[3]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[2]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[1]        ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1[0]        ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; PS2_DAT          ; Bidir    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; PS2_CLK          ; Bidir    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[4]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[5]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; CLOCK_50         ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[0]           ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[7]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[6]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[3]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[2]            ; Input    ; --            ; (6) 1314 ps   ; --                    ; --  ; --   ;
+; SW[1]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; SW[0]            ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; KEY[1]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
+; GPIO_1_CLKIN[0]  ; Input    ; (0) 0 ps      ; --            ; --                    ; --  ; --   ;
+; KEY[2]           ; Input    ; (6) 1314 ps   ; --            ; --                    ; --  ; --   ;
++------------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout                                                                                                                                             ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout                                                                                                                          ; Pad To Core Index ; Setting ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; GPIO_1_CLKIN[1]                                                                                                                              ;                   ;         ;
+; SW[9]                                                                                                                                        ;                   ;         ;
+; SW[8]                                                                                                                                        ;                   ;         ;
+; DRAM_DQ[15]                                                                                                                                  ;                   ;         ;
+; DRAM_DQ[14]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]~feeder                                                                               ; 1                 ; 6       ;
+; DRAM_DQ[13]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[12]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                      ; 0                 ; 6       ;
+; DRAM_DQ[11]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[10]                                                                                                                                  ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]~feeder                                                                               ; 0                 ; 6       ;
+; DRAM_DQ[9]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[8]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[7]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[6]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[5]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[4]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]~feeder                                                                                ; 1                 ; 6       ;
+; DRAM_DQ[3]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[2]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2]                                                                                       ; 0                 ; 6       ;
+; DRAM_DQ[1]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]~feeder                                                                                ; 0                 ; 6       ;
+; DRAM_DQ[0]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]~feeder                                                                                ; 1                 ; 6       ;
+; GPIO_1[31]                                                                                                                                   ;                   ;         ;
+; GPIO_1[30]                                                                                                                                   ;                   ;         ;
+; GPIO_1[29]                                                                                                                                   ;                   ;         ;
+; GPIO_1[28]                                                                                                                                   ;                   ;         ;
+; GPIO_1[27]                                                                                                                                   ;                   ;         ;
+; GPIO_1[26]                                                                                                                                   ;                   ;         ;
+; GPIO_1[25]                                                                                                                                   ;                   ;         ;
+; GPIO_1[24]                                                                                                                                   ;                   ;         ;
+; GPIO_1[23]                                                                                                                                   ;                   ;         ;
+; GPIO_1[22]                                                                                                                                   ;                   ;         ;
+; GPIO_1[21]                                                                                                                                   ;                   ;         ;
+; GPIO_1[20]                                                                                                                                   ;                   ;         ;
+; GPIO_1[19]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1~3                                                                               ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2~1                                                                               ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3~2                                                                               ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4~9                                                                               ; 0                 ; 6       ;
+; GPIO_1[18]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_FVAL~feeder                                                                                                         ; 0                 ; 6       ;
+; GPIO_1[17]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_LVAL~feeder                                                                                                         ; 1                 ; 6       ;
+; GPIO_1[16]                                                                                                                                   ;                   ;         ;
+; GPIO_1[15]                                                                                                                                   ;                   ;         ;
+; GPIO_1[14]                                                                                                                                   ;                   ;         ;
+; GPIO_1[13]                                                                                                                                   ;                   ;         ;
+; GPIO_1[12]                                                                                                                                   ;                   ;         ;
+; GPIO_1[11]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[0]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[10]                                                                                                                                   ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[1]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[9]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[2]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[8]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[3]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[7]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[4]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[6]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[5]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[5]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[6]~feeder                                                                                                      ; 1                 ; 6       ;
+; GPIO_1[4]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[7]                                                                                                             ; 1                 ; 6       ;
+; GPIO_1[3]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[8]~feeder                                                                                                      ; 0                 ; 6       ;
+; GPIO_1[2]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[9]                                                                                                             ; 0                 ; 6       ;
+; GPIO_1[1]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[10]~feeder                                                                                                     ; 0                 ; 6       ;
+; GPIO_1[0]                                                                                                                                    ;                   ;         ;
+;      - DE0_D5M:inst|rCCD_DATA[11]~feeder                                                                                                     ; 1                 ; 6       ;
+; PS2_DAT                                                                                                                                      ;                   ;         ;
+;      - ps2:inst6|ps2_dat_syn0~0                                                                                                              ; 1                 ; 6       ;
+; PS2_CLK                                                                                                                                      ;                   ;         ;
+;      - ps2:inst6|ps2_clk_syn0~0                                                                                                              ; 0                 ; 6       ;
+; SW[4]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~9                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~9                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~9                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~9                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~1                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~5                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6                                                      ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8                                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~9                                                     ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~13                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~17                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~21                                                    ; 0                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22                                                    ; 0                 ; 6       ;
+; SW[5]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~11                                     ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~11                                     ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~11                                     ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~11                                     ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[9]~0                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~2                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[8]~3                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[7]~4                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~6                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[6]~7                                                      ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[19]~8                                                     ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~10                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[18]~11                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[17]~12                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~14                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[16]~15                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[29]~16                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~18                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[28]~19                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[27]~20                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~22                                                    ; 1                 ; 6       ;
+;      - vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated|result_node[26]~23                                                    ; 1                 ; 6       ;
+; CLOCK_50                                                                                                                                     ;                   ;         ;
+; KEY[0]                                                                                                                                       ;                   ;         ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|midlatch                                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|riglatch                                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|leflatch                                                                                                                    ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[6] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[7] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[8] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_2[9] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[6] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[7] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[8] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp_1[9] ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[6]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[7]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[8]   ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|reg_video_out_rsc_mgc_out_stdreg_d_tmp[9]   ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[0]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[1]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[2]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[3]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[4]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[5]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[6]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|x_latch[7]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[0]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[1]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[2]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[3]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[4]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[5]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[6]                                                                                                                  ; 1                 ; 6       ;
+;      - ps2:inst6|y_latch[7]                                                                                                                  ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[9]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[8]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[7]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_3[6]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[4]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[3]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[2]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp_1[1]                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[9]                                 ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[8]                                 ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[7]                                 ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_vout_rsc_mgc_out_stdreg_d_tmp[6]                                 ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[1]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[2]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[3]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[4]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[5]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[6]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[7]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[8]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[9]                                                                                                   ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[10]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[11]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[12]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[13]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[14]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[15]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[16]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[17]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[18]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[19]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[25]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[26]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[27]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[28]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[29]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[30]                                                                                                  ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[31]                                                                                                  ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[75]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[74]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[73]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[72]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[71]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[70]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[15]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[45]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[14]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[44]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[13]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[43]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[12]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[42]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[11]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[41]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[10]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[40]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[78]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[77]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[76]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[18]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[48]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[17]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[47]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[16]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[46]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_8_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_7_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_6_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[79]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[19]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[49]                                          ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[65]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[64]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[63]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[62]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[61]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[60]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[5]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[35]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[4]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[34]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[3]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[33]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[2]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[32]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[1]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[31]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[0]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[30]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[68]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[67]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[66]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[8]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[38]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[7]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[37]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[6]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[36]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_5_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_4_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_3_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[69]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[9]                                           ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[39]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[5]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[4]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[3]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[2]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[1]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[0]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[5]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[85]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[4]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[84]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[3]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[83]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[2]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[82]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[1]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[81]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[0]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[80]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[25]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[55]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[24]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[54]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[23]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[53]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[22]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[52]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[21]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[51]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[20]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[50]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[8]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[7]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[6]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[8]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[88]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[7]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[87]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[6]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[86]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[28]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[58]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[27]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[57]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[26]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[56]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_2_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_1_itm[9]                                             ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|slc_regs_regs_2_itm[9]                                               ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[89]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[29]                                          ; 1                 ; 6       ;
+;      - mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[59]                                          ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                   ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.listen                                                                                                            ; 1                 ; 6       ;
+;      - DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.pullclk                                                                                                           ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.trans                                                                                                             ; 1                 ; 6       ;
+;      - ps2:inst6|cur_state.pulldat                                                                                                           ; 1                 ; 6       ;
+; SW[7]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~15                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~15                                     ; 0                 ; 6       ;
+; SW[6]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~13                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~13                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~13                                     ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~13                                     ; 0                 ; 6       ;
+; SW[3]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~7                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~7                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~7                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~7                                      ; 1                 ; 6       ;
+; SW[2]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~5                                      ; 1                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~5                                      ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux13~1                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux16~2                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux23~5                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~17                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~18                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~19                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux18~2                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~4                                                                                                ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~23                                                                                               ; 1                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~25                                                                                               ; 1                 ; 6       ;
+; SW[1]                                                                                                                                        ;                   ;         ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~3                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~3                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~3                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~3                                      ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; 0                 ; 6       ;
+; SW[0]                                                                                                                                        ;                   ;         ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]~44                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]~23                                                                                  ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                    ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]~34                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]~32                                                                                  ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]~38                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]~36                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]~21                                                                                  ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~40                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]~42                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                     ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]~19                                                                                  ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]~15                                                                                  ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]~17                                                                                  ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add1~1                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add3~1                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add5~1                                      ; 0                 ; 6       ;
+;      - vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|Add7~1                                      ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~25                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~28                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]~46                                                                                  ; 0                 ; 6       ;
+;      - SW[0]~_wirecell                                                                                                                       ; 0                 ; 6       ;
+; KEY[1]                                                                                                                                       ;                   ;         ;
+;      - ps2:inst6|Selector1~0                                                                                                                 ; 0                 ; 6       ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                                                                                                  ; 0                 ; 6       ;
+; GPIO_1_CLKIN[0]                                                                                                                              ;                   ;         ;
+; KEY[2]                                                                                                                                       ;                   ;         ;
+;      - DE0_D5M:inst|CCD_Capture:u3|mSTART~0                                                                                                  ; 0                 ; 6       ;
++----------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals                                                                                                                                                                                                                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; Name                                                                                                                                  ; Location           ; Fan-Out ; Usage                      ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 5       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; CLOCK_50                                                                                                                              ; PIN_G21            ; 102     ; Clock                      ; yes    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~18                                                                                             ; LCCOMB_X24_Y14_N6  ; 16      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~19                                                                                             ; LCCOMB_X24_Y14_N0  ; 16      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[14]~3                                                                                              ; LCCOMB_X24_Y14_N30 ; 1       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                 ; FF_X24_Y14_N17     ; 7       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                     ; LCCOMB_X24_Y14_N20 ; 17      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                             ; LCCOMB_X36_Y15_N14 ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]~1                                                                      ; LCCOMB_X37_Y15_N12 ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                           ; FF_X35_Y19_N19     ; 34      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                           ; FF_X35_Y19_N23     ; 36      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                         ; LCCOMB_X36_Y16_N12 ; 5       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                            ; LCCOMB_X32_Y16_N24 ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                            ; LCCOMB_X36_Y16_N0  ; 6       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                              ; LCCOMB_X36_Y16_N10 ; 14      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                              ; LCCOMB_X36_Y16_N6  ; 43      ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                 ; FF_X36_Y16_N3      ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                          ; FF_X40_Y15_N3      ; 72      ; Clock                      ; yes    ; Global Clock         ; GCLK5            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                        ; LCCOMB_X36_Y16_N8  ; 24      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31                                                                                 ; LCCOMB_X37_Y21_N4  ; 14      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual ; LCCOMB_X24_Y10_N26 ; 11      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]~36                                                                                                  ; LCCOMB_X21_Y14_N8  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                 ; LCCOMB_X19_Y26_N4  ; 32      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                    ; FF_X19_Y26_N3      ; 468     ; Async. clear               ; yes    ; Global Clock         ; GCLK10           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                    ; FF_X19_Y26_N15     ; 55      ; Async. clear               ; yes    ; Global Clock         ; GCLK16           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                    ; FF_X19_Y26_N21     ; 106     ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0                                                                                          ; LCCOMB_X15_Y27_N12 ; 2       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                     ; LCCOMB_X19_Y26_N24 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                      ; LCCOMB_X19_Y27_N2  ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X16_Y13_N0  ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X12_Y12_N8  ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0            ; LCCOMB_X12_Y17_N0  ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0            ; LCCOMB_X12_Y16_N8  ; 18      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X10_Y22_N24 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X12_Y21_N14 ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0           ; LCCOMB_X15_Y23_N20 ; 18      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0           ; LCCOMB_X14_Y24_N0  ; 19      ; Clock enable, Write enable ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                               ; FF_X9_Y27_N1       ; 16      ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1                                                                    ; LCCOMB_X10_Y28_N4  ; 4       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                               ; FF_X9_Y28_N27      ; 26      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                            ; LCCOMB_X8_Y28_N18  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                              ; LCCOMB_X9_Y28_N20  ; 16      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR~3                                                                                             ; LCCOMB_X19_Y27_N20 ; 3       ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~45                                                                                  ; LCCOMB_X15_Y26_N30 ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46                                                                                  ; LCCOMB_X19_Y26_N8  ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46                                                                                  ; LCCOMB_X19_Y25_N30 ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~47                                                                                  ; LCCOMB_X19_Y26_N30 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~45                                                                                  ; LCCOMB_X17_Y26_N30 ; 15      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46                                                                                  ; LCCOMB_X19_Y26_N22 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46                                                                                  ; LCCOMB_X20_Y27_N0  ; 15      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47                                                                                  ; LCCOMB_X19_Y27_N10 ; 15      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                               ; LCCOMB_X29_Y21_N28 ; 13      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                            ; LCCOMB_X28_Y20_N30 ; 13      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                            ; LCCOMB_X31_Y20_N30 ; 12      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|VGA_Controller:u1|active                                                                                                 ; FF_X28_Y20_N31     ; 20      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                                                                  ; FF_X40_Y15_N31     ; 342     ; Clock                      ; yes    ; Global Clock         ; GCLK18           ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0]                                                   ; PLL_2              ; 512     ; Clock                      ; yes    ; Global Clock         ; GCLK8            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                                                                       ; PIN_AB11           ; 229     ; Clock                      ; yes    ; Global Clock         ; GCLK19           ; --                        ;
+; KEY[0]                                                                                                                                ; PIN_H2             ; 262     ; Async. clear               ; no     ; --                   ; --               ; --                        ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cout_actual                                                     ; LCCOMB_X14_Y15_N2  ; 10      ; Sync. load                 ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|Equal2~0                                                                                                                    ; LCCOMB_X30_Y15_N0  ; 8       ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|Equal3~2                                                                                                                    ; LCCOMB_X27_Y15_N28 ; 6       ; Async. clear               ; yes    ; Global Clock         ; GCLK13           ; --                        ;
+; ps2:inst6|always5~1                                                                                                                   ; LCCOMB_X27_Y15_N24 ; 19      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|clk_div[8]                                                                                                                  ; FF_X40_Y15_N21     ; 38      ; Clock                      ; yes    ; Global Clock         ; GCLK6            ; --                        ;
+; ps2:inst6|clk_div[8]                                                                                                                  ; FF_X40_Y15_N21     ; 3       ; Clock                      ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|cur_state.listen                                                                                                            ; FF_X30_Y15_N29     ; 38      ; Clock enable               ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|cur_state.trans                                                                                                             ; FF_X30_Y15_N7      ; 17      ; Sync. clear                ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|de~0                                                                                                                        ; LCCOMB_X30_Y15_N20 ; 1       ; Output enable              ; no     ; --                   ; --               ; --                        ;
+; ps2:inst6|ps2_clk_in                                                                                                                  ; FF_X39_Y15_N17     ; 51      ; Clock                      ; yes    ; Global Clock         ; GCLK14           ; --                        ;
++---------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals                                                                                                                                                                                                     ;
++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name                                                                                ; Location           ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; CLOCK_50                                                                            ; PIN_G21            ; 102     ; 0                                    ; Global Clock         ; GCLK7            ; --                        ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                        ; FF_X40_Y15_N3      ; 72      ; 0                                    ; Global Clock         ; GCLK5            ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                  ; FF_X19_Y26_N3      ; 468     ; 0                                    ; Global Clock         ; GCLK10           ; --                        ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                  ; FF_X19_Y26_N15     ; 55      ; 0                                    ; Global Clock         ; GCLK16           ; --                        ;
+; DE0_D5M:inst|rClk[0]                                                                ; FF_X40_Y15_N31     ; 342     ; 0                                    ; Global Clock         ; GCLK18           ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ; PLL_2              ; 512     ; 228                                  ; Global Clock         ; GCLK8            ; --                        ;
+; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] ; PLL_2              ; 1       ; 0                                    ; Global Clock         ; GCLK9            ; --                        ;
+; GPIO_1_CLKIN[0]                                                                     ; PIN_AB11           ; 229     ; 0                                    ; Global Clock         ; GCLK19           ; --                        ;
+; ps2:inst6|Equal3~2                                                                  ; LCCOMB_X27_Y15_N28 ; 6       ; 0                                    ; Global Clock         ; GCLK13           ; --                        ;
+; ps2:inst6|clk_div[8]                                                                ; FF_X40_Y15_N21     ; 38      ; 0                                    ; Global Clock         ; GCLK6            ; --                        ;
+; ps2:inst6|ps2_clk_in                                                                ; FF_X39_Y15_N17     ; 51      ; 0                                    ; Global Clock         ; GCLK14           ; --                        ;
++-------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals                                                                                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Name                                                                                                                                                                      ; Fan-Out ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; KEY[0]~input                                                                                                                                                              ; 262     ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_2                                                                                                                                        ; 106     ;
+; ~GND                                                                                                                                                                      ; 63      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|i2c_reset                                                                                                                                  ; 43      ;
+; DE0_D5M:inst|VGA_Controller:u1|always0~1                                                                                                                                  ; 39      ;
+; ps2:inst6|cur_state.listen                                                                                                                                                ; 38      ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R~0                                                                                                                                   ; 38      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[1]                                                                                                                               ; 37      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[4]                                                                                                                               ; 36      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[0]                                                                                                                               ; 34      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[2]                                                                                                                               ; 34      ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[0]                                                                                                                                     ; 34      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[3]                                                                                                                               ; 33      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[0]                                                                                                                                     ; 33      ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~11                                                                                                                                     ; 32      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; 31      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3]                                                                                                                     ; 26      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|INIT_REQ                                                                                                   ; 26      ;
+; SW[0]~input                                                                                                                                                               ; 25      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[23]~1                                                                                                                            ; 24      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~2                                                                                                                 ; 24      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD~0                                                                                                                                 ; 23      ;
+; SW[5]~input                                                                                                                                                               ; 22      ;
+; SW[4]~input                                                                                                                                                               ; 22      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]~0                                                                                                                           ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                                            ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[9]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[8]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[7]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[6]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[5]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[4]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[3]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[2]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[1]                                                                                  ; 22      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|counter_reg_bit[0]                                                                                  ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                               ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_writea                                                                                                            ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_reada                                                                                                             ; 20      ;
+; DE0_D5M:inst|VGA_Controller:u1|active                                                                                                                                     ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                               ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                                            ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_wrreq~0                                                ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|valid_rdreq~0                                                ; 19      ;
+; ps2:inst6|always5~1                                                                                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]                                                                                                                               ; 19      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~0                                                                                                                              ; 18      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; 18      ;
+; DE0_D5M:inst|CCD_Capture:u3|oDVAL                                                                                                                                         ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan2~4                                                                                                                                ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                                            ; 17      ;
+; ps2:inst6|cur_state.trans                                                                                                                                                 ; 17      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~19                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]~18                                                                                                                                 ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ~1                                                                                                  ; 16      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|OE                                                                                                                   ; 16      ;
+; SW[2]~input                                                                                                                                                               ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~3                                                                                                ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~45                                                                                                                      ; 15      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~10                                                                                                                         ; 15      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|always1~2                                                                                                                                  ; 14      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]~31                                                                                                                     ; 14      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal6~0                                                                                                                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[10]                             ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[9]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[8]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[7]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[6]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[5]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[4]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[3]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[2]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[1]                              ; 14      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|counter_reg_bit[0]                              ; 14      ;
+; DE0_D5M:inst|rCCD_LVAL                                                                                                                                                    ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                                            ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~2                                                                                                                                ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~3                                                                                                                                   ; 13      ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan8~4                                                                                                                                ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                                            ; 12      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~1                                                                                                            ; 12      ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cout_actual                                     ; 11      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[6]                                                                                                            ; 11      ;
+; DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]~36                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~5                                                                                                            ; 10      ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cout_actual                                                                                         ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~2                                                                                                                               ; 10      ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                                                        ; 10      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 10      ;
+; ps2:inst6|y_latch[7]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[6]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[5]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[4]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[3]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[2]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[1]                                                                                                                                                      ; 10      ;
+; ps2:inst6|y_latch[0]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[7]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[6]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[5]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[4]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[3]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[2]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[1]                                                                                                                                                      ; 10      ;
+; ps2:inst6|x_latch[0]                                                                                                                                                      ; 10      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_GO                                                                                                                                    ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_done                                                                                                         ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]~0                                                                                                                               ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[2]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_1~16                                                     ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; 9       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; 9       ;
+; SW[0]~_wirecell                                                                                                                                                           ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; 8       ;
+; ps2:inst6|cur_state.pullclk                                                                                                                                               ; 8       ;
+; ps2:inst6|Equal2~0                                                                                                                                                        ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~3                                                                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                       ; 8       ;
+; vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst|or_itm~0                                                                        ; 8       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[9]~18                                                                                 ; 8       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[9]~18                                                                              ; 8       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[9]~18                                                                              ; 8       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                      ; 7       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_FVAL                                                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[0]                                                                                                     ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                       ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[9]                                                                                              ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[12]~24                                                                                ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[10]~20                                                                                ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[12]~24                                                                             ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[10]~20                                                                             ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[12]~24                                                                             ; 7       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[10]~20                                                                             ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[9]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[1]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[0]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[9]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[8]                                                                                                                                  ; 7       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[7]                                                                                                                                  ; 7       ;
+; SW[1]~input                                                                                                                                                               ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~7                                                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~1                                                                                                                                ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                      ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]~1                                                                                                          ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                                      ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal10~0                                                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                       ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[2]                                                                                              ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[15]                                                                                             ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[14]                                                                                             ; 6       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[11]~22                                                                                ; 6       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[11]~22                                                                             ; 6       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[11]~22                                                                             ; 6       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[6]                                                                                                                                  ; 6       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[5]                                                                                                                                  ; 6       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[3]~2                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux10~2                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~5                                                                                                                                    ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LUT_INDEX[5]~7                                                                                                                             ; 5       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                      ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                      ; 5       ;
+; ps2:inst6|delay[0]                                                                                                                                                        ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|IN_REQ                                                                                                                                ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; 5       ;
+; ps2:inst6|byte_cnt[0]                                                                                                                                                     ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|PM_STOP                                                                                                                               ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~1                                                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[2]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[3]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[5]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[6]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[7]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[4]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[9]                             ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[10]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[11]                            ; 5       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[8]                             ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[5]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[3]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[4]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[8]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[7]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[6]                                                                                              ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|op_2~16                                                      ; 5       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                                                                                                                                      ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add7~0                                                                                                   ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_15_sdt[1]~2                                                                                       ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add46~0                                                                                                  ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_19_sdt[1]~2                                                                                       ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add33~0                                                                                                  ; 5       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_29_sdt[1]~2                                                                                       ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[0]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[3]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[2]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[1]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[5]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[8]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[7]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[6]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[4]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[3]                                                                                                                                  ; 5       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[2]                                                                                                                                  ; 5       ;
+; SW[3]~input                                                                                                                                                               ; 4       ;
+; SW[6]~input                                                                                                                                                               ; 4       ;
+; SW[7]~input                                                                                                                                                               ; 4       ;
+; CLOCK_50~input                                                                                                                                                            ; 4       ;
+; GPIO_1[19]~input                                                                                                                                                          ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~6                                                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0001                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0010                                                                                                                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~3                             ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; 4       ;
+; DE0_D5M:inst|CCD_Capture:u3|mCCD_LVAL                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~1                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; 4       ;
+; ps2:inst6|delay[1]                                                                                                                                                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~1                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor3                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin|xor6                        ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor3                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin|xor6                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~2                              ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                          ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~8                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_RD                                                                                                                                ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|oRequest                                                                                                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]                                                                                                                        ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                                         ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[14]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[15]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[17]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[18]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[19]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[16]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[21]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[22]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[23]                            ; 4       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[20]                            ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[13]                                                                                             ; 4       ;
+; ps2:inst6|byte_cnt[1]                                                                                                                                                     ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                                                                                                                                      ; 4       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                                                                                                                                      ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add56~8                                                                                                  ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add11~10                                                                                                 ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_15_sdt[2]~4                                                                                       ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add15~8                                                                                                  ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add50~10                                                                                                 ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_19_sdt[2]~4                                                                                       ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add22~8                                                                                                  ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add37~10                                                                                                 ; 4       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_acc_29_sdt[2]~4                                                                                       ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[56]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[57]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[58]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[37]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[38]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[39]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[46]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[47]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[48]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[49]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[59]                                                                                ; 4       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[36]                                                                                ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[11]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|V_Cont[10]                                                                                                                                 ; 4       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[4]                                                                                                                                  ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK~_wirecell                                                                                                    ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~0                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK2                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|cntr_cout[5]~0                  ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_1[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[2]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[3]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[4]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[5]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[6]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[7]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[8]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[9]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[10]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDATAd_0[11]                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~5                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]~0                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~1                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~0                                                                                                ; 3       ;
+; ps2:inst6|delay[2]                                                                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~2                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR~3                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|cntr_cout[5]~0                   ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~7                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                                                                                                                                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always4~0                                                                                                            ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                       ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ; 3       ;
+; ps2:inst6|Equal3~0                                                                                                                                                        ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~2                                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[6]~3                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[7]~2                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[8]~1                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_G[9]~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan5~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~0                                                                                                                                ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~0                                                                                                                                   ; 3       ;
+; DE0_D5M:inst|rClk[0]                                                                                                                                                      ; 3       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]                                                                                                                        ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[1]                             ; 3       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[0]                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[1]                                                                                              ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ; 3       ;
+; ps2:inst6|byte_cnt[2]                                                                                                                                                     ; 3       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add57~14                                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add52~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[8]~16                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[7]~14                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_psp_sva[6]~12                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[26]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[27]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[28]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[29]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[20]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[22]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[23]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[24]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[25]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[50]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[51]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[21]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[53]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[54]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[55]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[52]                                                                                ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add16~14                                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add51~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[8]~16                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[7]~14                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_20_psp_sva[6]~12                                                                              ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[1]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[2]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[3]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[4]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[5]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[0]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[31]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[32]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[33]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[34]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[30]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[7]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[8]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[9]                                                                                 ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[19]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[35]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[6]                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add23~14                                                                                                 ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Add38~0                                                                                                  ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[8]~16                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[7]~14                                                                              ; 3       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|nl_ACC_acc_21_psp_sva[6]~12                                                                              ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[11]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[12]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[16]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[17]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[18]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[10]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[14]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[15]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[40]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[41]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[42]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[13]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[44]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[45]                                                                                ; 3       ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[43]                                                                                ; 3       ;
+; ps2:inst6|cnt[7]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[6]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[5]                                                                                                                                                          ; 3       ;
+; ps2:inst6|cnt[0]                                                                                                                                                          ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[11]                                                                                                                                 ; 3       ;
+; DE0_D5M:inst|VGA_Controller:u1|H_Cont[10]                                                                                                                                 ; 3       ;
+; KEY[1]~input                                                                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~26                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~11                                                                                                                         ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux12~9                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux1~1                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Mux8~0                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST.0000                                                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK~0                                                                                                                    ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK4                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK3                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|ACK1                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~2                             ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|LessThan0~4                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|mSTART                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|rCCD_FVAL                                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan0~2                                                                                                ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[23]~1                                                                                                                 ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|LessThan3~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~6                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[0]                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~4                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|always3~0                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LOAD_MODE~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~2                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|LessThan1~1                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|PRECHARGE~0                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always3~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal8~0                                                                                                                              ; 2       ;
+; ps2:inst6|nex_state.pulldat~0                                                                                                                                             ; 2       ;
+; ps2:inst6|delay[3]                                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|Mux0~16                                                                                                                  ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~2                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK~0                                                                                                                   ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|LessThan2~1                                                                                                              ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2]                                                                                                                     ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|Equal4~7                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0              ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|mDVAL                                                                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[0]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[2]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[5]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|_~3                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[10]                                                                                                                          ; 2       ;
+; ps2:inst6|Selector1~0                                                                                                                                                     ; 2       ;
+; ps2:inst6|Selector0~0                                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~9                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~4                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|always0~3                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|oRST_1                                                                                                                                        ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|_~4                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal7~0                                                                                                                              ; 2       ;
+; ps2:inst6|Equal3~1                                                                                                                                                        ; 2       ;
+; ps2:inst6|ct[0]                                                                                                                                                           ; 2       ;
+; ps2:inst6|ps2_dat_in                                                                                                                                                      ; 2       ;
+; ps2:inst6|clk_div[0]                                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|LessThan2~0                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~6                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Reset_Delay:u2|Equal0~1                                                                                                                                      ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_initial                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag~0                                                                                                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|WE_N~0                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal4~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~14                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal2~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]~1                                                                                                                               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Pre_WR                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~5                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp|aneb_result_wire[0]~0                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][7]~1                                                         ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core|romout[0][8]~0                                                         ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core|_~0                                                                    ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[59]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[29]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[89]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[56]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[26]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[57]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[27]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[58]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[28]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[86]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[87]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[88]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[50]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[20]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[51]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[21]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[52]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[22]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[53]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[23]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[54]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[24]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[55]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[25]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[80]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[81]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[82]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[83]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[84]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[85]                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[11]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[13]                                                                                                                          ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[14]                                                                                                                          ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][7]~1                                                         ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|romout[0][8]~0                                                         ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core|_~0                                                                    ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[39]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[9]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[69]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[36]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[6]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[37]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[7]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[38]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[8]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[66]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[67]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[68]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[30]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[0]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[31]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[1]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[32]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[2]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[33]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[3]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[34]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[4]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[35]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[5]                                                                               ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[60]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[61]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[62]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[63]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[64]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[65]                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[6]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[7]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[8]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_b[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|ram_address_a[8]                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~5               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp|aneb_result_wire[0]~0               ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][7]~1                                                         ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|romout[0][8]~0                                                         ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|_~0                                                                    ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[49]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[19]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[79]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[46]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[16]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[47]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[17]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[48]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[18]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[76]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[77]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[78]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[40]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[10]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[41]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[11]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[42]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[12]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[43]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[13]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[44]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[14]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[45]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[15]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[70]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[71]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[72]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[73]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[74]                                                                              ; 2       ;
+; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|reg_regs_regs_0_sva_cse[75]                                                                              ; 2       ;
+; ps2:inst6|shift_reg[2]                                                                                                                                                    ; 2       ;
+; ps2:inst6|shift_reg[3]                                                                                                                                                    ; 2       ;
+; ps2:inst6|shift_reg[30]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[29]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[28]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[27]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[26]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[25]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[24]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[23]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[19]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[18]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[17]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[16]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[15]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[14]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[13]                                                                                                                                                   ; 2       ;
+; ps2:inst6|shift_reg[12]                                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|Equal0~1                                                                                                                                   ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan6~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|DQM~0                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal0~1                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Equal5~0                                                                                                                              ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[5]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[6]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[7]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                                                                                                                                 ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[6]~4                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[7]~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[8]~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_R[9]~1                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[6]~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[7]~2                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[8]~1                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_B[9]~0                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|LessThan4~3                                                                                                                                ; 2       ;
+; DE0_D5M:inst|VGA_Controller:u1|oVGA_V_SYNC                                                                                                                                ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[3]                                                                                                          ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[10]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[9]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[8]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[7]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[6]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[5]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[4]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[3]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[2]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[1]                                                                                                                                     ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[14]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[13]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[12]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|CCD_Capture:u3|X_Cont[11]                                                                                                                                    ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[13]                            ; 2       ;
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|q_b[12]                            ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[15]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[14]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[13]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[12]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[11]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[10]                                                                                                  ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[8]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[7]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[6]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[5]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[4]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[3]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[2]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[1]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[0]                                                                                                   ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[12]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[11]                                                                                             ; 2       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[10]                                                                                             ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]                                                                                                                           ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]                                                                                                                            ; 2       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]                                                                                                                            ; 2       ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; Name                                                                                                                                              ; Type ; Mode             ; Clock Mode   ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size   ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF  ; Location                                                                                                                                                       ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1278         ; 24           ; 1278         ; 24           ; yes                    ; no                      ; yes                    ; yes                     ; 30672  ; 1278                        ; 24                          ; 1278                        ; 24                          ; 30672               ; 6    ; None ; M9K_X25_Y7_N0, M9K_X25_Y11_N0, M9K_X25_Y8_N0, M9K_X25_Y10_N0, M9K_X25_Y12_N0, M9K_X25_Y9_N0                                                                    ; Old data             ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 15                          ; 512                         ; 15                          ; 7680                ; 1    ; None ; M9K_X13_Y13_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 15                          ; 512                         ; 15                          ; 7680                ; 1    ; None ; M9K_X13_Y16_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y22_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks  ; 512          ; 16           ; 512          ; 16           ; yes                    ; no                      ; yes                    ; yes                     ; 8192   ; 512                         ; 16                          ; 512                         ; 16                          ; 8192                ; 1    ; None ; M9K_X13_Y23_N0                                                                                                                                                 ; Don't care           ; Old data        ; Old data        ; No - Unknown  ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; Single Clock ; 798          ; 150          ; 798          ; 150          ; yes                    ; no                      ; yes                    ; yes                     ; 119700 ; 798                         ; 90                          ; 798                         ; 90                          ; 71820               ; 10   ; None ; M9K_X25_Y18_N0, M9K_X13_Y18_N0, M9K_X13_Y17_N0, M9K_X25_Y17_N0, M9K_X25_Y16_N0, M9K_X25_Y15_N0, M9K_X13_Y19_N0, M9K_X25_Y21_N0, M9K_X25_Y20_N0, M9K_X25_Y19_N0 ; Old data             ; Old data        ; Old data        ; No - Unknown  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+---------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++------------------------------------------------+
+; Routing Usage Summary                          ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage                  ;
++-----------------------+------------------------+
+; Block interconnects   ; 3,017 / 47,787 ( 6 % ) ;
+; C16 interconnects     ; 67 / 1,804 ( 4 % )     ;
+; C4 interconnects      ; 1,365 / 31,272 ( 4 % ) ;
+; Direct links          ; 635 / 47,787 ( 1 % )   ;
+; Global clocks         ; 11 / 20 ( 55 % )       ;
+; Local interconnects   ; 1,194 / 15,408 ( 8 % ) ;
+; R24 interconnects     ; 71 / 1,775 ( 4 % )     ;
+; R4 interconnects      ; 1,727 / 41,310 ( 4 % ) ;
++-----------------------+------------------------+
+
+
++-----------------------------------------------------------------------------+
+; LAB Logic Elements                                                          ;
++---------------------------------------------+-------------------------------+
+; Number of Logic Elements  (Average = 11.94) ; Number of LABs  (Total = 195) ;
++---------------------------------------------+-------------------------------+
+; 1                                           ; 24                            ;
+; 2                                           ; 2                             ;
+; 3                                           ; 2                             ;
+; 4                                           ; 3                             ;
+; 5                                           ; 4                             ;
+; 6                                           ; 5                             ;
+; 7                                           ; 1                             ;
+; 8                                           ; 3                             ;
+; 9                                           ; 9                             ;
+; 10                                          ; 2                             ;
+; 11                                          ; 4                             ;
+; 12                                          ; 11                            ;
+; 13                                          ; 11                            ;
+; 14                                          ; 15                            ;
+; 15                                          ; 12                            ;
+; 16                                          ; 87                            ;
++---------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals                                                   ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals  (Average = 1.58) ; Number of LABs  (Total = 195) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear                     ; 100                           ;
+; 1 Clock                            ; 131                           ;
+; 1 Clock enable                     ; 44                            ;
+; 1 Sync. clear                      ; 8                             ;
+; 1 Sync. load                       ; 3                             ;
+; 2 Async. clears                    ; 1                             ;
+; 2 Clock enables                    ; 4                             ;
+; 2 Clocks                           ; 18                            ;
++------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced  (Average = 17.58) ; Number of LABs  (Total = 195) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 9                             ;
+; 2                                            ; 16                            ;
+; 3                                            ; 3                             ;
+; 4                                            ; 4                             ;
+; 5                                            ; 3                             ;
+; 6                                            ; 5                             ;
+; 7                                            ; 1                             ;
+; 8                                            ; 2                             ;
+; 9                                            ; 7                             ;
+; 10                                           ; 0                             ;
+; 11                                           ; 3                             ;
+; 12                                           ; 11                            ;
+; 13                                           ; 7                             ;
+; 14                                           ; 7                             ;
+; 15                                           ; 8                             ;
+; 16                                           ; 5                             ;
+; 17                                           ; 6                             ;
+; 18                                           ; 4                             ;
+; 19                                           ; 1                             ;
+; 20                                           ; 6                             ;
+; 21                                           ; 6                             ;
+; 22                                           ; 6                             ;
+; 23                                           ; 5                             ;
+; 24                                           ; 4                             ;
+; 25                                           ; 7                             ;
+; 26                                           ; 8                             ;
+; 27                                           ; 7                             ;
+; 28                                           ; 8                             ;
+; 29                                           ; 6                             ;
+; 30                                           ; 11                            ;
+; 31                                           ; 12                            ;
+; 32                                           ; 7                             ;
++----------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out                                                         ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out  (Average = 8.31) ; Number of LABs  (Total = 195) ;
++-------------------------------------------------+-------------------------------+
+; 0                                               ; 0                             ;
+; 1                                               ; 30                            ;
+; 2                                               ; 9                             ;
+; 3                                               ; 10                            ;
+; 4                                               ; 12                            ;
+; 5                                               ; 15                            ;
+; 6                                               ; 10                            ;
+; 7                                               ; 8                             ;
+; 8                                               ; 11                            ;
+; 9                                               ; 7                             ;
+; 10                                              ; 9                             ;
+; 11                                              ; 11                            ;
+; 12                                              ; 12                            ;
+; 13                                              ; 11                            ;
+; 14                                              ; 12                            ;
+; 15                                              ; 8                             ;
+; 16                                              ; 11                            ;
+; 17                                              ; 2                             ;
+; 18                                              ; 1                             ;
+; 19                                              ; 2                             ;
+; 20                                              ; 0                             ;
+; 21                                              ; 0                             ;
+; 22                                              ; 0                             ;
+; 23                                              ; 1                             ;
+; 24                                              ; 1                             ;
+; 25                                              ; 0                             ;
+; 26                                              ; 1                             ;
+; 27                                              ; 1                             ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs                                                          ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs  (Average = 12.65) ; Number of LABs  (Total = 195) ;
++----------------------------------------------+-------------------------------+
+; 0                                            ; 0                             ;
+; 1                                            ; 0                             ;
+; 2                                            ; 15                            ;
+; 3                                            ; 7                             ;
+; 4                                            ; 24                            ;
+; 5                                            ; 8                             ;
+; 6                                            ; 9                             ;
+; 7                                            ; 5                             ;
+; 8                                            ; 7                             ;
+; 9                                            ; 12                            ;
+; 10                                           ; 8                             ;
+; 11                                           ; 9                             ;
+; 12                                           ; 5                             ;
+; 13                                           ; 6                             ;
+; 14                                           ; 7                             ;
+; 15                                           ; 2                             ;
+; 16                                           ; 7                             ;
+; 17                                           ; 4                             ;
+; 18                                           ; 4                             ;
+; 19                                           ; 6                             ;
+; 20                                           ; 3                             ;
+; 21                                           ; 2                             ;
+; 22                                           ; 12                            ;
+; 23                                           ; 12                            ;
+; 24                                           ; 4                             ;
+; 25                                           ; 7                             ;
+; 26                                           ; 1                             ;
+; 27                                           ; 1                             ;
+; 28                                           ; 2                             ;
+; 29                                           ; 1                             ;
+; 30                                           ; 0                             ;
+; 31                                           ; 2                             ;
+; 32                                           ; 0                             ;
+; 33                                           ; 2                             ;
+; 34                                           ; 0                             ;
+; 35                                           ; 0                             ;
+; 36                                           ; 0                             ;
+; 37                                           ; 1                             ;
++----------------------------------------------+-------------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary                        ;
++----------------------------------+-------+
+; I/O Rules Statistic              ; Total ;
++----------------------------------+-------+
+; Total I/O Rules                  ; 30    ;
+; Number of I/O Rules Passed       ; 10    ;
+; Number of I/O Rules Failed       ; 0     ;
+; Number of I/O Rules Unchecked    ; 0     ;
+; Number of I/O Rules Inapplicable ; 20    ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details                                                                                                                                                                                                                                                                    ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status       ; ID        ; Category                          ; Rule Description                                                                                     ; Severity ; Information                                                              ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Pass         ; IO_000001 ; Capacity Checks                   ; Number of pins in an I/O bank should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000002 ; Capacity Checks                   ; Number of clocks in an I/O bank should not exceed the number of clocks available.                    ; Critical ; No Global Signal assignments found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000003 ; Capacity Checks                   ; Number of pins in a Vrefgroup should not exceed the number of locations available.                   ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks      ; The I/O bank should support the requested VCCIO.                                                     ; Critical ; No IOBANK_VCCIO assignments found.                                       ; I/O  ;                   ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VREF values.                                                  ; Critical ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
+; Pass         ; IO_000006 ; Voltage Compatibility Checks      ; The I/O bank should not have competing VCCIO values.                                                 ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000007 ; Valid Location Checks             ; Checks for unavailable locations.                                                                    ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000008 ; Valid Location Checks             ; Checks for reserved locations.                                                                       ; Critical ; No reserved LogicLock region found.                                      ; I/O  ;                   ;
+; Pass         ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard.                                              ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Pass         ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction.                                             ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength.                                          ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value.                                 ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value.                                            ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value.                                        ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Pass         ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode.                                           ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength.                                      ; Critical ; No Current Strength assignments found.                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value.                             ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Pass         ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode.                                       ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value.                                    ; Critical ; No Weak Pull-Up Resistor assignments found.                              ; I/O  ;                   ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value.                                        ; Critical ; No Enable Bus-Hold Circuitry assignments found.                          ; I/O  ;                   ;
+; Pass         ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value.                                                ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value.                                      ; Critical ; No Termination assignments found.                                        ; I/O  ;                   ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time.                        ; Critical ; No Current Strength or Termination assignments found.                    ; I/O  ;                   ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time.                                       ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O  ;                   ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value.                                       ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value.                                           ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time.                               ; Critical ; No Slew Rate assignments found.                                          ; I/O  ;                   ;
+; Pass         ; IO_000033 ; Electromigration Checks           ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found.                                                   ; I/O  ;                   ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks        ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O.                            ; High     ; No Differential I/O Standard assignments found.                          ; I/O  ;                   ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks       ; No more than 20 outputs are allowed in a VREF group when VREF is being read from.                    ; High     ; No VREF I/O Standard assignments found.                                  ; I/O  ;                   ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules          ; IO_000001    ; IO_000002    ; IO_000003    ; IO_000004    ; IO_000005    ; IO_000006 ; IO_000007    ; IO_000008    ; IO_000009 ; IO_000010 ; IO_000011    ; IO_000012    ; IO_000013    ; IO_000014    ; IO_000015    ; IO_000018    ; IO_000019    ; IO_000020    ; IO_000021    ; IO_000022    ; IO_000023    ; IO_000024    ; IO_000026    ; IO_000027    ; IO_000045    ; IO_000046    ; IO_000047    ; IO_000033 ; IO_000034    ; IO_000042    ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass         ; 142          ; 0            ; 142          ; 0            ; 0            ; 143       ; 142          ; 0            ; 143       ; 143       ; 0            ; 0            ; 0            ; 0            ; 66           ; 0            ; 0            ; 66           ; 0            ; 0            ; 30           ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 143       ; 0            ; 0            ;
+; Total Unchecked    ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; Total Inapplicable ; 1            ; 143          ; 1            ; 143          ; 143          ; 0         ; 1            ; 143          ; 0         ; 0         ; 143          ; 143          ; 143          ; 143          ; 77           ; 143          ; 143          ; 77           ; 143          ; 143          ; 113          ; 143          ; 143          ; 143          ; 143          ; 143          ; 143          ; 0         ; 143          ; 143          ;
+; Total Fail         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ; 0         ; 0         ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0            ; 0         ; 0            ; 0            ;
+; DRAM_LDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[1]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[9]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[8]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_UDQM          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_1          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_BA_0          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CKE           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CS_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_RAS_N         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_WE_N          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_CLK           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_CLK            ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_HS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_VS             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[11]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[10]      ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[9]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[8]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[7]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[6]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[5]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[4]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[3]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[2]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[1]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_ADDR[0]       ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[1]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKOUT[0]   ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX0[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX1[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX2[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; HEX3[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[9]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[8]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[7]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[6]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[5]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[4]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[3]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[2]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[1]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; LEDG[0]            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_B[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_G[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[3]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[2]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[1]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; VGA_R[0]           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[15]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[14]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[13]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[12]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[11]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[10]        ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[9]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[8]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[7]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[6]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[5]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[4]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[3]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[2]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[1]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; DRAM_DQ[0]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[31]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[30]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[29]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[28]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[27]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[26]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[25]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[24]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[23]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[22]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[21]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[20]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[19]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[18]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[17]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[16]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[15]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[14]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[13]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[12]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[11]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[10]         ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[9]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[8]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[7]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[6]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[5]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[4]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[3]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[2]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[1]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1[0]          ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_DAT            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; PS2_CLK            ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[4]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[5]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; CLOCK_50           ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[0]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[7]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[6]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[3]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[2]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[1]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; SW[0]              ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[1]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; GPIO_1_CLKIN[0]    ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
+; KEY[2]             ; Pass         ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass      ; Pass         ; Inapplicable ; Pass      ; Pass      ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Pass         ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass      ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options                                                                       ;
++------------------------------------------------------------------+--------------------------+
+; Option                                                           ; Setting                  ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR)                     ; Off                      ;
+; Enable device-wide reset (DEV_CLRn)                              ; Off                      ;
+; Enable device-wide output enable (DEV_OE)                        ; Off                      ;
+; Enable INIT_DONE output                                          ; Off                      ;
+; Configuration scheme                                             ; Active Serial            ;
+; Error detection CRC                                              ; Off                      ;
+; Enable open drain on CRC_ERROR pin                               ; Off                      ;
+; Enable input tri-state on active configuration pins in user mode ; Off                      ;
+; Configuration Voltage Level                                      ; Auto                     ;
+; Force Configuration Voltage Level                                ; Off                      ;
+; nCEO                                                             ; Unreserved               ;
+; Data[0]                                                          ; As input tri-stated      ;
+; Data[1]/ASDO                                                     ; As input tri-stated      ;
+; Data[7..2]                                                       ; Unreserved               ;
+; FLASH_nCE/nCSO                                                   ; As input tri-stated      ;
+; Other Active Parallel pins                                       ; Unreserved               ;
+; DCLK                                                             ; As output driving ground ;
+; Base pin-out file on sameframe device                            ; Off                      ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions  ;
++---------------------------+--------+
+; Setting                   ; Value  ;
++---------------------------+--------+
+; Nominal Core Voltage      ; 1.20 V ;
+; Low Junction Temperature  ; 0 °C   ;
+; High Junction Temperature ; 85 °C  ;
++---------------------------+--------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Summary                                                                                 ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; Source Clock(s)                                     ; Destination Clock(s)                                ; Delay Added in ns ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.8               ;
++-----------------------------------------------------+-----------------------------------------------------+-------------------+
+Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
+This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing Details                                                                                                                                                                                                                                                                                                       ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; Source Register                                                                                                                                      ; Destination Register                                                                                                                                                     ; Delay Added in ns ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.218             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.218             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.218             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.216             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.216             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.107             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a15~portb_address_reg0 ; 0.107             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a4~porta_datain_reg0    ; 0.092             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 0.019             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 0.016             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                     ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                      ; 0.015             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                ; 0.014             ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                ; 0.012             ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
+Note: This table only shows the top 15 path(s) that have the largest delay added for hold.
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (119006): Selected device EP3C16F484C6 for design "DE0_D5M"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (15535): Implemented PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" as Cyclone III PLL type
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of 0 degrees (0 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] port
+    Info (15099): Implementing clock multiplication of 5, clock division of 2, and phase shift of -117 degrees (-2600 ps) for DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] port
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+    Info (176445): Device EP3C40F484C6 is compatible
+    Info (176445): Device EP3C55F484C6 is compatible
+    Info (176445): Device EP3C80F484C6 is compatible
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+    Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1
+    Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+    Info (169125): Pin ~ALTERA_DCLK~ is reserved at location K2
+    Info (169125): Pin ~ALTERA_DATA0~ is reserved at location K1
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 143 total pins
+    Info (169086): Pin VGA_CLK not assigned to an exact location on the device
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 3 clocks
+    Info (332111):   Period   Clock Name
+    Info (332111): ======== ============
+    Info (332111):   20.000     CLOCK_50
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[0]
+    Info (332111):    8.000 inst|u6|altpll_component|auto_generated|pll1|clk[1]
+Info (176353): Automatically promoted node CLOCK_50~input (placed in PIN G21 (CLK4, DIFFCLK_2p))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]
+        Info (176357): Destination node ps2:inst6|clk_div[8]
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] (placed in counter C0 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8
+Info (176353): Automatically promoted node DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[1] (placed in counter C1 of PLL_2)
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
+Info (176353): Automatically promoted node GPIO_1_CLKIN[0]~input (placed in PIN AB11 (CLK14, DIFFCLK_6n))
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (176353): Automatically promoted node DE0_D5M:inst|rClk[0] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|rClk[0]~0
+        Info (176357): Destination node GPIO_1_CLKOUT[0]~output
+        Info (176357): Destination node VGA_CLK~output
+Info (176353): Automatically promoted node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|I2C_SCLK~1
+        Info (176357): Destination node DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK~0
+Info (176353): Automatically promoted node ps2:inst6|ps2_clk_in 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node ps2:inst6|Equal2~0
+Info (176353): Automatically promoted node ps2:inst6|clk_div[8] 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node ps2:inst6|clk_div[8]~22
+        Info (176357): Destination node ps2:inst6|ps2_clk_in
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_0 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]~6
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]~47
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~43
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~46
+        Info (176357): Destination node DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]~47
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_0~2
+Info (176353): Automatically promoted node DE0_D5M:inst|Reset_Delay:u2|oRST_1 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+    Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
+        Info (176357): Destination node GPIO_1[14]~output
+        Info (176357): Destination node DE0_D5M:inst|Reset_Delay:u2|oRST_1~1
+Info (176353): Automatically promoted node ps2:inst6|Equal3~2 
+    Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+    Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+        Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+    Info (176214): Statistics of I/O banks
+        Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used --  6 pins available
+        Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  48 pins available
+        Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 16 total pin(s) used --  30 pins available
+        Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used --  21 pins available
+        Info (176213): I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used --  44 pins available
+        Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used --  28 pins available
+        Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 28 total pin(s) used --  19 pins available
+        Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used --  5 pins available
+Warning (15064): PLL "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "CLOCK_50_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX0_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX1_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX2_DP" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "HEX3_DP" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:03
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 4% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X10_Y10 to location X20_Y19
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 1.98 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169177): 66 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+    Info (169178): Pin GPIO_1_CLKIN[1] uses I/O standard 3.3-V LVTTL at AA11
+    Info (169178): Pin SW[9] uses I/O standard 3.3-V LVTTL at D2
+    Info (169178): Pin SW[8] uses I/O standard 3.3-V LVTTL at E4
+    Info (169178): Pin DRAM_DQ[15] uses I/O standard 3.3-V LVTTL at F10
+    Info (169178): Pin DRAM_DQ[14] uses I/O standard 3.3-V LVTTL at E10
+    Info (169178): Pin DRAM_DQ[13] uses I/O standard 3.3-V LVTTL at A10
+    Info (169178): Pin DRAM_DQ[12] uses I/O standard 3.3-V LVTTL at B10
+    Info (169178): Pin DRAM_DQ[11] uses I/O standard 3.3-V LVTTL at C10
+    Info (169178): Pin DRAM_DQ[10] uses I/O standard 3.3-V LVTTL at A9
+    Info (169178): Pin DRAM_DQ[9] uses I/O standard 3.3-V LVTTL at B9
+    Info (169178): Pin DRAM_DQ[8] uses I/O standard 3.3-V LVTTL at A8
+    Info (169178): Pin DRAM_DQ[7] uses I/O standard 3.3-V LVTTL at F8
+    Info (169178): Pin DRAM_DQ[6] uses I/O standard 3.3-V LVTTL at H9
+    Info (169178): Pin DRAM_DQ[5] uses I/O standard 3.3-V LVTTL at G9
+    Info (169178): Pin DRAM_DQ[4] uses I/O standard 3.3-V LVTTL at F9
+    Info (169178): Pin DRAM_DQ[3] uses I/O standard 3.3-V LVTTL at E9
+    Info (169178): Pin DRAM_DQ[2] uses I/O standard 3.3-V LVTTL at H10
+    Info (169178): Pin DRAM_DQ[1] uses I/O standard 3.3-V LVTTL at G10
+    Info (169178): Pin DRAM_DQ[0] uses I/O standard 3.3-V LVTTL at D10
+    Info (169178): Pin GPIO_1[31] uses I/O standard 3.3-V LVTTL at V7
+    Info (169178): Pin GPIO_1[30] uses I/O standard 3.3-V LVTTL at V6
+    Info (169178): Pin GPIO_1[29] uses I/O standard 3.3-V LVTTL at U8
+    Info (169178): Pin GPIO_1[28] uses I/O standard 3.3-V LVTTL at Y7
+    Info (169178): Pin GPIO_1[27] uses I/O standard 3.3-V LVTTL at T9
+    Info (169178): Pin GPIO_1[26] uses I/O standard 3.3-V LVTTL at U9
+    Info (169178): Pin GPIO_1[25] uses I/O standard 3.3-V LVTTL at T10
+    Info (169178): Pin GPIO_1[24] uses I/O standard 3.3-V LVTTL at U10
+    Info (169178): Pin GPIO_1[23] uses I/O standard 3.3-V LVTTL at R12
+    Info (169178): Pin GPIO_1[22] uses I/O standard 3.3-V LVTTL at R11
+    Info (169178): Pin GPIO_1[21] uses I/O standard 3.3-V LVTTL at T12
+    Info (169178): Pin GPIO_1[20] uses I/O standard 3.3-V LVTTL at U12
+    Info (169178): Pin GPIO_1[19] uses I/O standard 3.3-V LVTTL at R14
+    Info (169178): Pin GPIO_1[18] uses I/O standard 3.3-V LVTTL at T14
+    Info (169178): Pin GPIO_1[17] uses I/O standard 3.3-V LVTTL at AB7
+    Info (169178): Pin GPIO_1[16] uses I/O standard 3.3-V LVTTL at AA7
+    Info (169178): Pin GPIO_1[15] uses I/O standard 3.3-V LVTTL at AA9
+    Info (169178): Pin GPIO_1[14] uses I/O standard 3.3-V LVTTL at AB9
+    Info (169178): Pin GPIO_1[13] uses I/O standard 3.3-V LVTTL at V15
+    Info (169178): Pin GPIO_1[12] uses I/O standard 3.3-V LVTTL at W15
+    Info (169178): Pin GPIO_1[11] uses I/O standard 3.3-V LVTTL at T15
+    Info (169178): Pin GPIO_1[10] uses I/O standard 3.3-V LVTTL at U15
+    Info (169178): Pin GPIO_1[9] uses I/O standard 3.3-V LVTTL at W17
+    Info (169178): Pin GPIO_1[8] uses I/O standard 3.3-V LVTTL at Y17
+    Info (169178): Pin GPIO_1[7] uses I/O standard 3.3-V LVTTL at AB17
+    Info (169178): Pin GPIO_1[6] uses I/O standard 3.3-V LVTTL at AA17
+    Info (169178): Pin GPIO_1[5] uses I/O standard 3.3-V LVTTL at AA18
+    Info (169178): Pin GPIO_1[4] uses I/O standard 3.3-V LVTTL at AB18
+    Info (169178): Pin GPIO_1[3] uses I/O standard 3.3-V LVTTL at AB19
+    Info (169178): Pin GPIO_1[2] uses I/O standard 3.3-V LVTTL at AA19
+    Info (169178): Pin GPIO_1[1] uses I/O standard 3.3-V LVTTL at AB20
+    Info (169178): Pin GPIO_1[0] uses I/O standard 3.3-V LVTTL at AA20
+    Info (169178): Pin PS2_DAT uses I/O standard 3.3-V LVTTL at P21
+    Info (169178): Pin PS2_CLK uses I/O standard 3.3-V LVTTL at P22
+    Info (169178): Pin SW[4] uses I/O standard 3.3-V LVTTL at G5
+    Info (169178): Pin SW[5] uses I/O standard 3.3-V LVTTL at J7
+    Info (169178): Pin CLOCK_50 uses I/O standard 3.3-V LVTTL at G21
+    Info (169178): Pin KEY[0] uses I/O standard 3.3-V LVTTL at H2
+    Info (169178): Pin SW[7] uses I/O standard 3.3-V LVTTL at E3
+    Info (169178): Pin SW[6] uses I/O standard 3.3-V LVTTL at H7
+    Info (169178): Pin SW[3] uses I/O standard 3.3-V LVTTL at G4
+    Info (169178): Pin SW[2] uses I/O standard 3.3-V LVTTL at H6
+    Info (169178): Pin SW[1] uses I/O standard 3.3-V LVTTL at H5
+    Info (169178): Pin SW[0] uses I/O standard 3.3-V LVTTL at J6
+    Info (169178): Pin KEY[1] uses I/O standard 3.3-V LVTTL at G3
+    Info (169178): Pin GPIO_1_CLKIN[0] uses I/O standard 3.3-V LVTTL at AB11
+    Info (169178): Pin KEY[2] uses I/O standard 3.3-V LVTTL at F1
+Warning (169064): Following 31 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin GPIO_1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[20] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[15] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[14] has a permanently enabled output enable
+    Info (169065): Pin GPIO_1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO_1[0] has a permanently disabled output enable
+Info (144001): Generated suppressed messages file E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 22 warnings
+    Info: Peak virtual memory: 1199 megabytes
+    Info: Processing ended: Mon Mar 17 11:17:22 2014
+    Info: Elapsed time: 00:00:17
+    Info: Total CPU time (on all processors): 00:00:20
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg.
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary
new file mode 100644
index 0000000..ddeb7c8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Mon Mar 17 11:17:21 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_DE0_CAMERA_MOUSE
+Family : Cyclone III
+Device : EP3C16F484C6
+Timing Models : Final
+Total logic elements : 2,329 / 15,408 ( 15 % )
+    Total combinational functions : 1,922 / 15,408 ( 12 % )
+    Dedicated logic registers : 1,326 / 15,408 ( 9 % )
+Total registers : 1326
+Total pins : 143 / 347 ( 41 % )
+Total virtual pins : 0
+Total memory bits : 134,236 / 516,096 ( 26 % )
+Embedded Multiplier 9-bit elements : 0 / 112 ( 0 % )
+Total PLLs : 1 / 4 ( 25 % )
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt
new file mode 100644
index 0000000..a2ffcd8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.flow.rpt
@@ -0,0 +1,130 @@
+Flow report for DE0_D5M
+Mon Mar 17 11:17:31 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Flow Summary
+  3. Flow Settings
+  4. Flow Non-Default Global Settings
+  5. Flow Elapsed Time
+  6. Flow OS Summary
+  7. Flow Log
+  8. Flow Messages
+  9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary                                                                     ;
++------------------------------------+---------------------------------------------+
+; Flow Status                        ; Successful - Mon Mar 17 11:17:25 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                        ;
+; Family                             ; Cyclone III                                 ;
+; Device                             ; EP3C16F484C6                                ;
+; Timing Models                      ; Final                                       ;
+; Total logic elements               ; 2,329 / 15,408 ( 15 % )                     ;
+;     Total combinational functions  ; 1,922 / 15,408 ( 12 % )                     ;
+;     Dedicated logic registers      ; 1,326 / 15,408 ( 9 % )                      ;
+; Total registers                    ; 1326                                        ;
+; Total pins                         ; 143 / 347 ( 41 % )                          ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 134,236 / 516,096 ( 26 % )                  ;
+; Embedded Multiplier 9-bit elements ; 0 / 112 ( 0 % )                             ;
+; Total PLLs                         ; 1 / 4 ( 25 % )                              ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings                           ;
++-------------------+---------------------+
+; Option            ; Setting             ;
++-------------------+---------------------+
+; Start date & time ; 03/17/2014 11:16:54 ;
+; Main task         ; Compilation         ;
+; Revision Name     ; DE0_D5M             ;
++-------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings                                                                                                ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+; Assignment Name                     ; Value                                 ; Default Value ; Entity Name          ; Section Id ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+; COMPILER_SIGNATURE_ID               ; 135308249136.139505501406800          ; --            ; --                   ; --         ;
+; IP_TOOL_NAME                        ; LPM_MUX                               ; --            ; --                   ; --         ;
+; IP_TOOL_VERSION                     ; 13.1                                  ; --            ; --                   ; --         ;
+; MAX_CORE_JUNCTION_TEMP              ; 85                                    ; --            ; --                   ; --         ;
+; MIN_CORE_JUNCTION_TEMP              ; 0                                     ; --            ; --                   ; --         ;
+; MISC_FILE                           ; vga_mux.bsf                           ; --            ; --                   ; --         ;
+; MISC_FILE                           ; vga_mux.cmp                           ; --            ; --                   ; --         ;
+; PARTITION_COLOR                     ; 14622752                              ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING                 ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; PARTITION_NETLIST_TYPE              ; SOURCE                                ; --            ; TOP_DE0_CAMERA_MOUSE ; Top        ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                   ; --            ; --                   ; --         ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --                   ; --         ;
+; SMART_RECOMPILE                     ; On                                    ; Off           ; --                   ; --         ;
+; TOP_LEVEL_ENTITY                    ; TOP_DE0_CAMERA_MOUSE                  ; DE0_D5M       ; --                   ; --         ;
+; USE_GENERATED_PHYSICAL_CONSTRAINTS  ; Off                                   ; --            ; --                   ; eda_palace ;
++-------------------------------------+---------------------------------------+---------------+----------------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time                                                                                                             ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name               ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis      ; 00:00:09     ; 1.0                     ; 587 MB              ; 00:00:08                           ;
+; Fitter                    ; 00:00:16     ; 1.2                     ; 1199 MB             ; 00:00:19                           ;
+; Assembler                 ; 00:00:02     ; 1.0                     ; 456 MB              ; 00:00:01                           ;
+; TimeQuest Timing Analyzer ; 00:00:04     ; 1.0                     ; 555 MB              ; 00:00:03                           ;
+; Total                     ; 00:00:31     ; --                      ; --                  ; 00:00:31                           ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary                                                                        ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name               ; Machine Hostname ; OS Name   ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis      ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Fitter                    ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; Assembler                 ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
+; TimeQuest Timing Analyzer ; ee-rad09-02      ; Windows 7 ; 6.1        ; x86_64         ;
++---------------------------+------------------+-----------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_fit --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_asm --read_settings_files=off --write_settings_files=off DE0_D5M -c DE0_D5M
+quartus_sta DE0_D5M -c DE0_D5M
+
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi
new file mode 100644
index 0000000..d8a97f3
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.jdi
@@ -0,0 +1,8 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="2607f159488999301fce"/>
+  </project>
+  <file_info>
+    <file device="EP3C16F484C6" path="DE0_D5M.sof" usercode="0xFFFFFFFF"/>
+  </file_info>
+</sld_project_info>
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt
new file mode 100644
index 0000000..1621cb1
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.rpt
@@ -0,0 +1,3187 @@
+Analysis & Synthesis report for DE0_D5M
+Mon Mar 17 11:17:03 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. Analysis & Synthesis Summary
+  3. Analysis & Synthesis Settings
+  4. Parallel Compilation
+  5. Analysis & Synthesis Source Files Read
+  6. Analysis & Synthesis Resource Usage Summary
+  7. Analysis & Synthesis Resource Utilization by Entity
+  8. Analysis & Synthesis RAM Summary
+  9. Analysis & Synthesis IP Cores Summary
+ 10. State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state
+ 11. State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST
+ 12. Registers Removed During Synthesis
+ 13. Removed Registers Triggering Further Register Optimizations
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 17. Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2
+ 18. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 19. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 20. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 21. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 22. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 23. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 24. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 25. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 26. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 27. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 28. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 29. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 30. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 31. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 32. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 33. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 34. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 35. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 36. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 37. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 38. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 39. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 40. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 41. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 42. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 43. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 44. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 45. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 46. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 47. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 48. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 49. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 50. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 51. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 52. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 53. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 54. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 55. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 56. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 57. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 58. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated
+ 59. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p
+ 60. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p
+ 61. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram
+ 62. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp
+ 63. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp
+ 64. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp
+ 65. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13
+ 66. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp
+ 67. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp
+ 68. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp
+ 69. Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16
+ 70. Source assignments for altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2
+ 71. Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1
+ 72. Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3
+ 73. Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component
+ 74. Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component
+ 75. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7
+ 76. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1
+ 77. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1
+ 78. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1
+ 79. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component
+ 80. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component
+ 81. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component
+ 82. Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component
+ 83. Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8
+ 84. Parameter Settings for User Entity Instance: ps2:inst6
+ 85. Parameter Settings for User Entity Instance: vga_mux:inst10|LPM_MUX:LPM_MUX_component
+ 86. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire
+ 87. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire
+ 88. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire
+ 89. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire
+ 90. Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg
+ 91. Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire
+ 92. Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg
+ 93. Parameter Settings for User Entity Instance: altshift_taps:fifo_inst2
+ 94. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3
+ 95. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1
+ 96. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5
+ 97. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2
+ 98. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0
+ 99. Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4
+100. altshift_taps Parameter Settings by Entity Instance
+101. altpll Parameter Settings by Entity Instance
+102. dcfifo Parameter Settings by Entity Instance
+103. lpm_mult Parameter Settings by Entity Instance
+104. Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"
+105. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"
+106. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"
+107. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"
+108. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+109. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+110. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+111. Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"
+112. Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5"
+113. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+114. Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"
+115. Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"
+116. Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"
+117. Elapsed Time Per Partition
+118. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary                                                     ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status        ; Successful - Mon Mar 17 11:17:03 2014       ;
+; Quartus II 64-Bit Version          ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name                      ; DE0_D5M                                     ;
+; Top-level Entity Name              ; TOP_DE0_CAMERA_MOUSE                        ;
+; Family                             ; Cyclone III                                 ;
+; Total logic elements               ; 2,517                                       ;
+;     Total combinational functions  ; 1,922                                       ;
+;     Dedicated logic registers      ; 1,326                                       ;
+; Total registers                    ; 1326                                        ;
+; Total pins                         ; 143                                         ;
+; Total virtual pins                 ; 0                                           ;
+; Total memory bits                  ; 134,236                                     ;
+; Embedded Multiplier 9-bit elements ; 0                                           ;
+; Total PLLs                         ; 1                                           ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings                                                                                          ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+; Option                                                                     ; Setting              ; Default Value      ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+; Device                                                                     ; EP3C16F484C6         ;                    ;
+; Top-level entity name                                                      ; TOP_DE0_CAMERA_MOUSE ; DE0_D5M            ;
+; Family name                                                                ; Cyclone III          ; Cyclone IV GX      ;
+; Use smart compilation                                                      ; On                   ; Off                ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                   ; On                 ;
+; Enable compact report table                                                ; Off                  ; Off                ;
+; Restructure Multiplexers                                                   ; Auto                 ; Auto               ;
+; Create Debugging Nodes for IP Cores                                        ; Off                  ; Off                ;
+; Preserve fewer node names                                                  ; On                   ; On                 ;
+; Disable OpenCore Plus hardware evaluation                                  ; Off                  ; Off                ;
+; Verilog Version                                                            ; Verilog_2001         ; Verilog_2001       ;
+; VHDL Version                                                               ; VHDL_1993            ; VHDL_1993          ;
+; State Machine Processing                                                   ; Auto                 ; Auto               ;
+; Safe State Machine                                                         ; Off                  ; Off                ;
+; Extract Verilog State Machines                                             ; On                   ; On                 ;
+; Extract VHDL State Machines                                                ; On                   ; On                 ;
+; Ignore Verilog initial constructs                                          ; Off                  ; Off                ;
+; Iteration limit for constant Verilog loops                                 ; 5000                 ; 5000               ;
+; Iteration limit for non-constant Verilog loops                             ; 250                  ; 250                ;
+; Add Pass-Through Logic to Inferred RAMs                                    ; On                   ; On                 ;
+; Infer RAMs from Raw Logic                                                  ; On                   ; On                 ;
+; Parallel Synthesis                                                         ; On                   ; On                 ;
+; DSP Block Balancing                                                        ; Auto                 ; Auto               ;
+; NOT Gate Push-Back                                                         ; On                   ; On                 ;
+; Power-Up Don't Care                                                        ; On                   ; On                 ;
+; Remove Redundant Logic Cells                                               ; Off                  ; Off                ;
+; Remove Duplicate Registers                                                 ; On                   ; On                 ;
+; Ignore CARRY Buffers                                                       ; Off                  ; Off                ;
+; Ignore CASCADE Buffers                                                     ; Off                  ; Off                ;
+; Ignore GLOBAL Buffers                                                      ; Off                  ; Off                ;
+; Ignore ROW GLOBAL Buffers                                                  ; Off                  ; Off                ;
+; Ignore LCELL Buffers                                                       ; Off                  ; Off                ;
+; Ignore SOFT Buffers                                                        ; On                   ; On                 ;
+; Limit AHDL Integers to 32 Bits                                             ; Off                  ; Off                ;
+; Optimization Technique                                                     ; Balanced             ; Balanced           ;
+; Carry Chain Length                                                         ; 70                   ; 70                 ;
+; Auto Carry Chains                                                          ; On                   ; On                 ;
+; Auto Open-Drain Pins                                                       ; On                   ; On                 ;
+; Perform WYSIWYG Primitive Resynthesis                                      ; Off                  ; Off                ;
+; Auto ROM Replacement                                                       ; On                   ; On                 ;
+; Auto RAM Replacement                                                       ; On                   ; On                 ;
+; Auto DSP Block Replacement                                                 ; On                   ; On                 ;
+; Auto Shift Register Replacement                                            ; Auto                 ; Auto               ;
+; Allow Shift Register Merging across Hierarchies                            ; Auto                 ; Auto               ;
+; Auto Clock Enable Replacement                                              ; On                   ; On                 ;
+; Strict RAM Replacement                                                     ; Off                  ; Off                ;
+; Allow Synchronous Control Signals                                          ; On                   ; On                 ;
+; Force Use of Synchronous Clear Signals                                     ; Off                  ; Off                ;
+; Auto RAM Block Balancing                                                   ; On                   ; On                 ;
+; Auto RAM to Logic Cell Conversion                                          ; Off                  ; Off                ;
+; Auto Resource Sharing                                                      ; Off                  ; Off                ;
+; Allow Any RAM Size For Recognition                                         ; Off                  ; Off                ;
+; Allow Any ROM Size For Recognition                                         ; Off                  ; Off                ;
+; Allow Any Shift Register Size For Recognition                              ; Off                  ; Off                ;
+; Use LogicLock Constraints during Resource Balancing                        ; On                   ; On                 ;
+; Ignore translate_off and synthesis_off directives                          ; Off                  ; Off                ;
+; Timing-Driven Synthesis                                                    ; On                   ; On                 ;
+; Report Parameter Settings                                                  ; On                   ; On                 ;
+; Report Source Assignments                                                  ; On                   ; On                 ;
+; Report Connectivity Checks                                                 ; On                   ; On                 ;
+; Ignore Maximum Fan-Out Assignments                                         ; Off                  ; Off                ;
+; Synchronization Register Chain Length                                      ; 2                    ; 2                  ;
+; PowerPlay Power Optimization                                               ; Normal compilation   ; Normal compilation ;
+; HDL message level                                                          ; Level2               ; Level2             ;
+; Suppress Register Optimization Related Messages                            ; Off                  ; Off                ;
+; Number of Removed Registers Reported in Synthesis Report                   ; 5000                 ; 5000               ;
+; Number of Swept Nodes Reported in Synthesis Report                         ; 5000                 ; 5000               ;
+; Number of Inverted Registers Reported in Synthesis Report                  ; 100                  ; 100                ;
+; Clock MUX Protection                                                       ; On                   ; On                 ;
+; Auto Gated Clock Conversion                                                ; Off                  ; Off                ;
+; Block Design Naming                                                        ; Auto                 ; Auto               ;
+; SDC constraint protection                                                  ; Off                  ; Off                ;
+; Synthesis Effort                                                           ; Auto                 ; Auto               ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                   ; On                 ;
+; Pre-Mapping Resynthesis Optimization                                       ; Off                  ; Off                ;
+; Analysis & Synthesis Message Level                                         ; Medium               ; Medium             ;
+; Disable Register Merging Across Hierarchies                                ; Auto                 ; Auto               ;
+; Resource Aware Inference For Block RAM                                     ; On                   ; On                 ;
+; Synthesis Seed                                                             ; 1                    ; 1                  ;
++----------------------------------------------------------------------------+----------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read                                                                                                                                                                                ;
++-------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path          ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                             ; Library ;
++-------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------------------+---------+
+; catapult_ip/blur3x3/rtl.v                 ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v                 ;         ;
+; V/ps2.v                                   ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v                                   ;         ;
+; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h        ;         ;
+; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v             ;         ;
+; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v   ;         ;
+; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v       ;         ;
+; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v ;         ;
+; Sdram_Control_4Port/Sdram_FIFO.v          ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v          ;         ;
+; V/VGA_Param.h                             ; yes             ; User Unspecified File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h                             ;         ;
+; V/CCD_Capture.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v                           ;         ;
+; V/I2C_CCD_Config.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v                        ;         ;
+; V/I2C_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v                        ;         ;
+; V/Line_Buffer.v                           ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v                           ;         ;
+; V/RAW2RGB.v                               ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v                               ;         ;
+; V/Reset_Delay.v                           ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v                           ;         ;
+; V/sdram_pll.v                             ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v                             ;         ;
+; V/SEG7_LUT.v                              ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v                              ;         ;
+; V/SEG7_LUT_8.v                            ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v                            ;         ;
+; V/VGA_Controller.v                        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v                        ;         ;
+; DE0_D5M.v                                 ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v                                 ;         ;
+; V/TOP_DE0_CAMERA_MOUSE.bdf                ; yes             ; User Block Diagram/Schematic File  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf                ;         ;
+; vga_mux.vhd                               ; yes             ; User Wizard-Generated File         ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd                               ;         ;
+; catapult_ip/mouse/rtl_mgc_ioport.v        ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v        ;         ;
+; catapult_ip/mouse/rtl.v                   ; yes             ; User Verilog HDL File              ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v                   ;         ;
+; altshift_taps.tdf                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altshift_taps.tdf                                         ;         ;
+; altdpram.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altdpram.inc                                              ;         ;
+; lpm_counter.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_counter.inc                                           ;         ;
+; lpm_compare.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_compare.inc                                           ;         ;
+; lpm_constant.inc                          ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_constant.inc                                          ;         ;
+; db/shift_taps_rnn.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_rnn.tdf                     ;         ;
+; db/altsyncram_lp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_lp81.tdf                    ;         ;
+; db/cntr_cuf.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_cuf.tdf                           ;         ;
+; db/cmpr_vgc.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_vgc.tdf                           ;         ;
+; altpll.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altpll.tdf                                                ;         ;
+; aglobal131.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/aglobal131.inc                                            ;         ;
+; stratix_pll.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratix_pll.inc                                           ;         ;
+; stratixii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/stratixii_pll.inc                                         ;         ;
+; cycloneii_pll.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                         ;         ;
+; db/altpll_9ee2.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/altpll_9ee2.tdf                        ;         ;
+; dcfifo.tdf                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dcfifo.tdf                                                ;         ;
+; lpm_add_sub.inc                           ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_add_sub.inc                                           ;         ;
+; a_graycounter.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_graycounter.inc                                         ;         ;
+; a_fefifo.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_fefifo.inc                                              ;         ;
+; a_gray2bin.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/a_gray2bin.inc                                            ;         ;
+; dffpipe.inc                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/dffpipe.inc                                               ;         ;
+; alt_sync_fifo.inc                         ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_sync_fifo.inc                                         ;         ;
+; altsyncram_fifo.inc                       ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altsyncram_fifo.inc                                       ;         ;
+; db/dcfifo_v5o1.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/dcfifo_v5o1.tdf                        ;         ;
+; db/a_gray2bin_tgb.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/a_gray2bin_tgb.tdf                     ;         ;
+; db/a_graycounter_s57.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_s57.tdf                  ;         ;
+; db/a_graycounter_ojc.tdf                  ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/a_graycounter_ojc.tdf                  ;         ;
+; db/altsyncram_de51.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_de51.tdf                    ;         ;
+; db/dffpipe_oe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_oe9.tdf                        ;         ;
+; db/alt_synch_pipe_qld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_qld.tdf                 ;         ;
+; db/dffpipe_pe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_pe9.tdf                        ;         ;
+; db/alt_synch_pipe_rld.tdf                 ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/alt_synch_pipe_rld.tdf                 ;         ;
+; db/dffpipe_qe9.tdf                        ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/dffpipe_qe9.tdf                        ;         ;
+; db/cmpr_e66.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_e66.tdf                           ;         ;
+; lpm_mux.tdf                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mux.tdf                                               ;         ;
+; muxlut.inc                                ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/muxlut.inc                                                ;         ;
+; bypassff.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/bypassff.inc                                              ;         ;
+; altshift.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.inc                                              ;         ;
+; db/mux_u7e.tdf                            ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/mux_u7e.tdf                            ;         ;
+; db/shift_taps_lpm.tdf                     ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/shift_taps_lpm.tdf                     ;         ;
+; db/altsyncram_vp81.tdf                    ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/altsyncram_vp81.tdf                    ;         ;
+; db/cntr_1tf.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/cntr_1tf.tdf                           ;         ;
+; db/cmpr_ugc.tdf                           ; yes             ; Auto-Generated Megafunction        ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/db/cmpr_ugc.tdf                           ;         ;
+; lpm_mult.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/lpm_mult.tdf                                              ;         ;
+; multcore.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.inc                                              ;         ;
+; multcore.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/multcore.tdf                                              ;         ;
+; csa_add.inc                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/csa_add.inc                                               ;         ;
+; mpar_add.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/mpar_add.inc                                              ;         ;
+; muleabz.inc                               ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/muleabz.inc                                               ;         ;
+; mul_lfrg.inc                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/mul_lfrg.inc                                              ;         ;
+; mul_boothc.inc                            ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/mul_boothc.inc                                            ;         ;
+; alt_ded_mult.inc                          ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_ded_mult.inc                                          ;         ;
+; alt_ded_mult_y.inc                        ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/alt_ded_mult_y.inc                                        ;         ;
+; mpar_add.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/mpar_add.tdf                                              ;         ;
+; altshift.tdf                              ; yes             ; Megafunction                       ; c:/altera/13.1/quartus/libraries/megafunctions/altshift.tdf                                              ;         ;
++-------------------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------------------------------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary                                                                                       ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Resource                                    ; Usage                                                                               ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+; Estimated Total logic elements              ; 2,517                                                                               ;
+;                                             ;                                                                                     ;
+; Total combinational functions               ; 1922                                                                                ;
+; Logic element usage by number of LUT inputs ;                                                                                     ;
+;     -- 4 input functions                    ; 595                                                                                 ;
+;     -- 3 input functions                    ; 759                                                                                 ;
+;     -- <=2 input functions                  ; 568                                                                                 ;
+;                                             ;                                                                                     ;
+; Logic elements by mode                      ;                                                                                     ;
+;     -- normal mode                          ; 1085                                                                                ;
+;     -- arithmetic mode                      ; 837                                                                                 ;
+;                                             ;                                                                                     ;
+; Total registers                             ; 1326                                                                                ;
+;     -- Dedicated logic registers            ; 1326                                                                                ;
+;     -- I/O registers                        ; 0                                                                                   ;
+;                                             ;                                                                                     ;
+; I/O pins                                    ; 143                                                                                 ;
+; Total memory bits                           ; 134236                                                                              ;
+; Embedded Multiplier 9-bit elements          ; 0                                                                                   ;
+; Total PLLs                                  ; 1                                                                                   ;
+;     -- PLLs                                 ; 1                                                                                   ;
+;                                             ;                                                                                     ;
+; Maximum fan-out node                        ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated|clk[0] ;
+; Maximum fan-out                             ; 572                                                                                 ;
+; Total fan-out                               ; 13262                                                                               ;
+; Average fan-out                             ; 3.53                                                                                ;
++---------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                        ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node                               ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+; |TOP_DE0_CAMERA_MOUSE                                    ; 1922 (2)          ; 1326 (0)     ; 134236      ; 0            ; 0       ; 0         ; 143  ; 0            ; |TOP_DE0_CAMERA_MOUSE                                                                                                                                                                ; work         ;
+;    |DE0_D5M:inst|                                        ; 1163 (1)          ; 1013 (15)    ; 62416       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst                                                                                                                                                   ; work         ;
+;       |CCD_Capture:u3|                                   ; 40 (40)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3                                                                                                                                    ; work         ;
+;       |I2C_CCD_Config:u8|                                ; 238 (169)         ; 132 (94)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8                                                                                                                                 ; work         ;
+;          |I2C_Controller:u0|                             ; 69 (69)           ; 38 (38)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0                                                                                                               ; work         ;
+;       |RAW2RGB:u4|                                       ; 84 (68)           ; 66 (55)      ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4                                                                                                                                        ; work         ;
+;          |Line_Buffer:u0|                                ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                                                                                                                         ; work         ;
+;             |altshift_taps:altshift_taps_component|      ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component                                                                                   ; work         ;
+;                |shift_taps_rnn:auto_generated|           ; 16 (0)            ; 11 (0)       ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated                                                     ; work         ;
+;                   |altsyncram_lp81:altsyncram2|          ; 0 (0)             ; 0 (0)        ; 30672       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2                         ; work         ;
+;                   |cntr_cuf:cntr1|                       ; 16 (13)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1                                      ; work         ;
+;                      |cmpr_vgc:cmpr4|                    ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4                       ; work         ;
+;       |Reset_Delay:u2|                                   ; 50 (50)           ; 35 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Reset_Delay:u2                                                                                                                                    ; work         ;
+;       |Sdram_Control_4Port:u7|                           ; 670 (213)         ; 704 (137)    ; 31744       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7                                                                                                                            ; work         ;
+;          |Sdram_FIFO:read_fifo1|                         ; 82 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 82 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 82 (15)           ; 116 (30)     ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:read_fifo2|                         ; 83 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2                                                                                                      ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 83 (0)            ; 116 (0)      ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component                                                                              ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 83 (15)           ; 116 (30)     ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                   ; work         ;
+;                   |a_gray2bin_tgb:wrptr_g_gray2bin|      ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin                   ; work         ;
+;                   |a_gray2bin_tgb:ws_dgrp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin                   ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                       ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                       ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                        ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13  ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                        ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16  ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 7680        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                          ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                          ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                           ; work         ;
+;                   |dffpipe_oe9:ws_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp                                ; work         ;
+;                   |dffpipe_oe9:ws_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp                                ; work         ;
+;          |Sdram_FIFO:write_fifo1|                        ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |Sdram_FIFO:write_fifo2|                        ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2                                                                                                     ; work         ;
+;             |dcfifo:dcfifo_component|                    ; 84 (0)            ; 116 (0)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component                                                                             ; work         ;
+;                |dcfifo_v5o1:auto_generated|              ; 84 (15)           ; 116 (30)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated                                                  ; work         ;
+;                   |a_gray2bin_tgb:rdptr_g_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin                  ; work         ;
+;                   |a_gray2bin_tgb:rs_dgwp_gray2bin|      ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rs_dgwp_gray2bin                  ; work         ;
+;                   |a_graycounter_ojc:wrptr_g1p|          ; 19 (19)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p                      ; work         ;
+;                   |a_graycounter_s57:rdptr_g1p|          ; 20 (20)           ; 14 (14)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p                      ; work         ;
+;                   |alt_synch_pipe_qld:rs_dgwp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp                       ; work         ;
+;                      |dffpipe_pe9:dffpipe13|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ; work         ;
+;                   |alt_synch_pipe_rld:ws_dgrp|           ; 0 (0)             ; 20 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp                       ; work         ;
+;                      |dffpipe_qe9:dffpipe16|             ; 0 (0)             ; 20 (20)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ; work         ;
+;                   |altsyncram_de51:fifo_ram|             ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram                         ; work         ;
+;                   |cmpr_e66:rdempty_eq_comp|             ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp                         ; work         ;
+;                   |cmpr_e66:wrfull_eq_comp|              ; 6 (6)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:wrfull_eq_comp                          ; work         ;
+;                   |dffpipe_oe9:rs_brp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp                               ; work         ;
+;                   |dffpipe_oe9:rs_bwp|                   ; 0 (0)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp                               ; work         ;
+;          |command:command1|                              ; 60 (60)           ; 48 (48)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1                                                                                                           ; work         ;
+;          |control_interface:control1|                    ; 64 (64)           ; 55 (55)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1                                                                                                 ; work         ;
+;       |VGA_Controller:u1|                                ; 80 (80)           ; 28 (28)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|VGA_Controller:u1                                                                                                                                 ; work         ;
+;       |sdram_pll:u6|                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                                                                                                                      ; work         ;
+;          |altpll:altpll_component|                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component                                                                                                              ; work         ;
+;             |altpll_9ee2:auto_generated|                 ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated                                                                                   ; work         ;
+;    |altshift_taps:fifo_inst2|                            ; 15 (0)            ; 10 (0)       ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2                                                                                                                                       ; work         ;
+;       |shift_taps_lpm:auto_generated|                    ; 15 (0)            ; 10 (0)       ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated                                                                                                         ; work         ;
+;          |altsyncram_vp81:altsyncram2|                   ; 0 (0)             ; 0 (0)        ; 71820       ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2                                                                             ; work         ;
+;          |cntr_1tf:cntr1|                                ; 15 (12)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1                                                                                          ; work         ;
+;             |cmpr_ugc:cmpr4|                             ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4                                                                           ; work         ;
+;    |mean_vga:vga_blur_catapult_inst|                     ; 519 (0)           ; 192 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst                                                                                                                                ; work         ;
+;       |mean_vga_core:mean_vga_core_inst|                 ; 519 (492)         ; 192 (192)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst                                                                                               ; work         ;
+;          |lpm_mult:Mult0|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult1|                                ; 4 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult2|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult3|                                ; 4 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult4|                                ; 5 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 5 (5)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4|multcore:mult_core                                                             ; work         ;
+;          |lpm_mult:Mult5|                                ; 4 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5                                                                                ; work         ;
+;             |multcore:mult_core|                         ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5|multcore:mult_core                                                             ; work         ;
+;    |ps2:inst6|                                           ; 102 (74)          ; 99 (99)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6                                                                                                                                                      ; work         ;
+;       |SEG7_LUT:U1|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U1                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U2|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U2                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U3|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U3                                                                                                                                          ; work         ;
+;       |SEG7_LUT:U4|                                      ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|ps2:inst6|SEG7_LUT:U4                                                                                                                                          ; work         ;
+;    |vga_mouse_square:vga_mouse_catapult_inst|            ; 97 (0)            ; 12 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst                                                                                                                       ; work         ;
+;       |vga_mouse_square_core:vga_mouse_square_core_inst| ; 97 (97)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst                                                                      ; work         ;
+;    |vga_mux:inst10|                                      ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                                                                                                                                 ; work         ;
+;       |lpm_mux:LPM_MUX_component|                        ; 24 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component                                                                                                                       ; work         ;
+;          |mux_u7e:auto_generated|                        ; 24 (24)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10|lpm_mux:LPM_MUX_component|mux_u7e:auto_generated                                                                                                ; work         ;
++----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+; Name                                                                                                                                              ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF  ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1278         ; 24           ; 1278         ; 24           ; 30672  ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM  ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512          ; 16           ; 512          ; 16           ; 8192   ; None ;
+; altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|ALTSYNCRAM                                                     ; AUTO ; Simple Dual Port ; 798          ; 150          ; 798          ; 150          ; 119700 ; None ;
++---------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                            ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+
+; Vendor ; IP Core Name               ; Version ; Release Date ; License Type ; Entity Instance                                                                  ; IP Include File                                                                                 ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+
+; Altera ; Shift register (RAM-based) ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0                     ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v                  ;
+; Altera ; ALTPLL                     ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|sdram_pll:u6                                  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v                    ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2  ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; FIFO                       ; N/A     ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2 ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v ;
+; Altera ; LPM_MUX                    ; 13.1    ; N/A          ; N/A          ; |TOP_DE0_CAMERA_MOUSE|vga_mux:inst10                                             ; E:/work/teaching/1314_2T_ISE1PRJ/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd                      ;
++--------+----------------------------+---------+--------------+--------------+----------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+
+
+
+Encoding Type:  One-Hot
++------------------------------------------------------------------------------------------------+
+; State Machine - |TOP_DE0_CAMERA_MOUSE|ps2:inst6|cur_state                                      ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+; Name              ; cur_state.trans ; cur_state.pulldat ; cur_state.pullclk ; cur_state.listen ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+; cur_state.listen  ; 0               ; 0                 ; 0                 ; 0                ;
+; cur_state.pullclk ; 0               ; 0                 ; 1                 ; 1                ;
+; cur_state.pulldat ; 0               ; 1                 ; 0                 ; 1                ;
+; cur_state.trans   ; 1               ; 0                 ; 0                 ; 1                ;
++-------------------+-----------------+-------------------+-------------------+------------------+
+
+
+Encoding Type:  One-Hot
++--------------------------------------------------------------------------------+
+; State Machine - |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST ;
++----------------+----------------+----------------+-----------------------------+
+; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001              ;
++----------------+----------------+----------------+-----------------------------+
+; mSetup_ST.0000 ; 0              ; 0              ; 0                           ;
+; mSetup_ST.0001 ; 1              ; 0              ; 1                           ;
+; mSetup_ST.0010 ; 1              ; 1              ; 0                           ;
++----------------+----------------+----------------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis                                                                                                                                                                                                ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; Register name                                                                                                                               ; Reason for Removal                                                                  ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+; ps2:inst6|dout_reg[9]                                                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[8]                                                                                          ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_LENGTH[0..7]                                                                                       ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[15]                                                                                            ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE                                                                                    ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27..29]                                                                                            ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]                                                                                                ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27..29]                                                                                 ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                                                                                     ; Stuck at VCC due to stuck port data_in                                              ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9]  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[0..6]                                                                                         ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                        ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[0..6]                                                                                           ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                          ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[0..6]                                                                                             ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                            ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[0..6]                                                                  ; Merged with DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7] ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[1,2]                                                                                         ; Merged with DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]                       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[7]                                                                                            ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7]                                                                                              ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7]                                                                                                ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7]                                                                     ; Stuck at GND due to stuck port data_in                                              ;
+; DE0_D5M:inst|rClk[1]                                                                                                                        ; Lost fanout                                                                         ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                                                                                              ; Stuck at VCC due to stuck port data_in                                              ;
+; ps2:inst6|cur_state~4                                                                                                                       ; Lost fanout                                                                         ;
+; ps2:inst6|cur_state~5                                                                                                                       ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~9                                                                                                  ; Lost fanout                                                                         ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mSetup_ST~10                                                                                                 ; Lost fanout                                                                         ;
+; DE0_D5M:inst|CCD_Capture:u3|Y_Cont[1..15]                                                                                                   ; Lost fanout                                                                         ;
+; Total Number of Removed Registers = 143                                                                                                     ;                                                                                     ;
++---------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations                                                                                                     ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register                                   ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_LENGTH[8]       ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[7],                          ;
+;                                                          ; due to stuck port data_in ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[7],                            ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[7], ;
+;                                                          ;                           ; DE0_D5M:inst|Sdram_Control_4Port:u7|mLENGTH[8]                           ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CKE ; Stuck at VCC              ; DE0_D5M:inst|Sdram_Control_4Port:u7|CKE                                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[31]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[31]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[30]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[30]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[29]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[29]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[28]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[28]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[27]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[27]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[26]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[26]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[25]             ; Stuck at VCC              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[25]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[24]             ; Stuck at GND              ; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD[24]                  ;
+;                                                          ; due to stuck port data_in ;                                                                          ;
++----------------------------------------------------------+---------------------------+--------------------------------------------------------------------------+
+
+
++------------------------------------------------------+
+; General Register Statistics                          ;
++----------------------------------------------+-------+
+; Statistic                                    ; Value ;
++----------------------------------------------+-------+
+; Total registers                              ; 1326  ;
+; Number of registers using Synchronous Clear  ; 131   ;
+; Number of registers using Synchronous Load   ; 91    ;
+; Number of registers using Asynchronous Clear ; 932   ;
+; Number of registers using Asynchronous Load  ; 0     ;
+; Number of registers using Clock Enable       ; 430   ;
+; Number of registers using Preset             ; 0     ;
++----------------------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Inverted Register Statistics                                                                                                                                   ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; Inverted Register                                                                                                                                    ; Fan out ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]                                                                                                   ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]                                                                                                    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                                                                                                    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0  ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0  ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6     ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]                                                                                       ; 12      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[4]                                                                                       ; 13      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[3]                                                                                       ; 22      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[2]                                                                                       ; 19      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SCLK                                                                                                ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SDO                                                                                                 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9     ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[1]                                                                                       ; 17      ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[0]                                                                                       ; 20      ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0 ; 6       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6    ; 4       ;
+; DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|END                                                                                                 ; 5       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9    ; 4       ;
+; Total number of inverted registers = 30                                                                                                              ;         ;
++------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                              ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+; 3:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[2]              ;
+; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|timer[9] ;
+; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|command_delay[6]   ;
+; 4:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|mCCD_G[5]                                       ;
+; 4:1                ; 20 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|RAW2RGB:u4|mCCD_R[2]                                       ;
+; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]                      ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3|X_Cont[15]                                  ;
+; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|CCD_Capture:u3|Y_Cont[14]                                  ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                       ;
+; 4:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                       ;
+; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]        ;
+; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]                           ;
+; 64:1               ; 5 bits    ; 210 LEs       ; 60 LEs               ; 150 LEs                ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_DATA[3]                             ;
+; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|CMD[1]                              ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                          ;
+; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                 ;
+; 7:1                ; 10 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|Sdram_Control_4Port:u7|ST[9]                               ;
+; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0|SD_COUNTER[5]          ;
+; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]                       ;
+; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |TOP_DE0_CAMERA_MOUSE|DE0_D5M:inst|I2C_CCD_Config:u8|Mux12                                    ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2 ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                       ;
++---------------------------------+-------+------+----------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                        ;
++---------------------------------+-------+------+----------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                            ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                             ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                             ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                             ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                       ;
++---------------------------------------+-------+------+-------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                               ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                       ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                          ;
++----------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                              ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                               ;
++---------------------------------+--------------------+------+-------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                     ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                      ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                                ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                 ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                 ;
++-----------------------------+------------------------+------+---------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                   ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                    ;
++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                      ;
++---------------------------------+-------+------+---------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                       ;
++---------------------------------+-------+------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; Assignment                            ; Value ; From ; To                                                                           ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION       ; OFF   ; -    ; -                                                                            ;
+; REMOVE_DUPLICATE_REGISTERS            ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZER_IDENTIFICATION           ; OFF   ; -    ; -                                                                            ;
+; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 2     ; -    ; -                                                                            ;
+; POWER_UP_LEVEL                        ; LOW   ; -    ; wrptr_g                                                                      ;
++---------------------------------------+-------+------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter5a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity6                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; Assignment     ; Value ; From ; To                                                                                                                              ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+; POWER_UP_LEVEL ; HIGH  ; -    ; counter8a0                                                                                                                      ;
+; POWER_UP_LEVEL ; HIGH  ; -    ; parity9                                                                                                                         ;
++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                                                                             ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                              ;
++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                    ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                     ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; Assignment                  ; Value                  ; From ; To                                                                                               ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+; X_ON_VIOLATION_OPTION       ; OFF                    ; -    ; -                                                                                                ;
+; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; -                                                                                                ;
++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16 ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; Assignment                      ; Value ; From ; To                                                                                                                                  ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                   ;
++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Source assignments for altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2 ;
++---------------------------------+--------------------+------+---------------------------------------------+
+; Assignment                      ; Value              ; From ; To                                          ;
++---------------------------------+--------------------+------+---------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                           ;
++---------------------------------+--------------------+------+---------------------------------------------+
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|VGA_Controller:u1 ;
++----------------+-------+----------------------------------------------------+
+; Parameter Name ; Value ; Type                                               ;
++----------------+-------+----------------------------------------------------+
+; H_SYNC_CYC     ; 96    ; Signed Integer                                     ;
+; H_SYNC_BACK    ; 48    ; Signed Integer                                     ;
+; H_SYNC_ACT     ; 640   ; Signed Integer                                     ;
+; H_SYNC_FRONT   ; 16    ; Signed Integer                                     ;
+; H_SYNC_TOTAL   ; 800   ; Signed Integer                                     ;
+; V_SYNC_CYC     ; 2     ; Signed Integer                                     ;
+; V_SYNC_BACK    ; 33    ; Signed Integer                                     ;
+; V_SYNC_ACT     ; 480   ; Signed Integer                                     ;
+; V_SYNC_FRONT   ; 10    ; Signed Integer                                     ;
+; V_SYNC_TOTAL   ; 525   ; Signed Integer                                     ;
+; X_START        ; 144   ; Signed Integer                                     ;
+; Y_START        ; 35    ; Signed Integer                                     ;
++----------------+-------+----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|CCD_Capture:u3 ;
++----------------+-------+-------------------------------------------------+
+; Parameter Name ; Value ; Type                                            ;
++----------------+-------+-------------------------------------------------+
+; COLUMN_WIDTH   ; 1280  ; Signed Integer                                  ;
++----------------+-------+-------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; Parameter Name ; Value          ; Type                                                                                    ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                                                                                 ;
+; NUMBER_OF_TAPS ; 2              ; Signed Integer                                                                          ;
+; TAP_DISTANCE   ; 1280           ; Signed Integer                                                                          ;
+; WIDTH          ; 12             ; Signed Integer                                                                          ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                                                                                 ;
+; CBXI_PARAMETER ; shift_taps_rnn ; Untyped                                                                                 ;
++----------------+----------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
++-------------------------------+-------------------+--------------------------------------------+
+; Parameter Name                ; Value             ; Type                                       ;
++-------------------------------+-------------------+--------------------------------------------+
+; OPERATION_MODE                ; NORMAL            ; Untyped                                    ;
+; PLL_TYPE                      ; AUTO              ; Untyped                                    ;
+; LPM_HINT                      ; UNUSED            ; Untyped                                    ;
+; QUALIFY_CONF_DONE             ; OFF               ; Untyped                                    ;
+; COMPENSATE_CLOCK              ; CLK0              ; Untyped                                    ;
+; SCAN_CHAIN                    ; LONG              ; Untyped                                    ;
+; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                                    ;
+; INCLK0_INPUT_FREQUENCY        ; 20000             ; Signed Integer                             ;
+; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                                    ;
+; GATE_LOCK_SIGNAL              ; NO                ; Untyped                                    ;
+; GATE_LOCK_COUNTER             ; 0                 ; Untyped                                    ;
+; LOCK_HIGH                     ; 1                 ; Untyped                                    ;
+; LOCK_LOW                      ; 1                 ; Untyped                                    ;
+; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                                    ;
+; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                                    ;
+; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                                    ;
+; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                                    ;
+; SKIP_VCO                      ; OFF               ; Untyped                                    ;
+; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                                    ;
+; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                                    ;
+; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                                    ;
+; BANDWIDTH                     ; 0                 ; Untyped                                    ;
+; BANDWIDTH_TYPE                ; AUTO              ; Untyped                                    ;
+; SPREAD_FREQUENCY              ; 0                 ; Untyped                                    ;
+; DOWN_SPREAD                   ; 0                 ; Untyped                                    ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                                    ;
+; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                                    ;
+; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                                    ;
+; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK4_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK3_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK2_MULTIPLY_BY              ; 1                 ; Untyped                                    ;
+; CLK1_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK0_MULTIPLY_BY              ; 5                 ; Signed Integer                             ;
+; CLK9_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK8_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK7_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK6_DIVIDE_BY                ; 0                 ; Untyped                                    ;
+; CLK5_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK4_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK3_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK2_DIVIDE_BY                ; 1                 ; Untyped                                    ;
+; CLK1_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK0_DIVIDE_BY                ; 2                 ; Signed Integer                             ;
+; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK4_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK3_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK2_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK1_PHASE_SHIFT              ; -2600             ; Untyped                                    ;
+; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                                    ;
+; CLK5_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK4_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK3_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK2_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK1_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK0_TIME_DELAY               ; 0                 ; Untyped                                    ;
+; CLK9_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK8_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK7_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK6_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK5_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK4_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK3_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK2_DUTY_CYCLE               ; 50                ; Untyped                                    ;
+; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer                             ;
+; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                                    ;
+; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                                    ;
+; LOCK_WINDOW_UI                ;  0.05             ; Untyped                                    ;
+; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                                    ;
+; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                                    ;
+; DPA_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; DPA_DIVIDE_BY                 ; 1                 ; Untyped                                    ;
+; DPA_DIVIDER                   ; 0                 ; Untyped                                    ;
+; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                                    ;
+; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                                    ;
+; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                                    ;
+; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                                    ;
+; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                                    ;
+; VCO_MULTIPLY_BY               ; 0                 ; Untyped                                    ;
+; VCO_DIVIDE_BY                 ; 0                 ; Untyped                                    ;
+; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                                    ;
+; VCO_MIN                       ; 0                 ; Untyped                                    ;
+; VCO_MAX                       ; 0                 ; Untyped                                    ;
+; VCO_CENTER                    ; 0                 ; Untyped                                    ;
+; PFD_MIN                       ; 0                 ; Untyped                                    ;
+; PFD_MAX                       ; 0                 ; Untyped                                    ;
+; M_INITIAL                     ; 0                 ; Untyped                                    ;
+; M                             ; 0                 ; Untyped                                    ;
+; N                             ; 1                 ; Untyped                                    ;
+; M2                            ; 1                 ; Untyped                                    ;
+; N2                            ; 1                 ; Untyped                                    ;
+; SS                            ; 1                 ; Untyped                                    ;
+; C0_HIGH                       ; 0                 ; Untyped                                    ;
+; C1_HIGH                       ; 0                 ; Untyped                                    ;
+; C2_HIGH                       ; 0                 ; Untyped                                    ;
+; C3_HIGH                       ; 0                 ; Untyped                                    ;
+; C4_HIGH                       ; 0                 ; Untyped                                    ;
+; C5_HIGH                       ; 0                 ; Untyped                                    ;
+; C6_HIGH                       ; 0                 ; Untyped                                    ;
+; C7_HIGH                       ; 0                 ; Untyped                                    ;
+; C8_HIGH                       ; 0                 ; Untyped                                    ;
+; C9_HIGH                       ; 0                 ; Untyped                                    ;
+; C0_LOW                        ; 0                 ; Untyped                                    ;
+; C1_LOW                        ; 0                 ; Untyped                                    ;
+; C2_LOW                        ; 0                 ; Untyped                                    ;
+; C3_LOW                        ; 0                 ; Untyped                                    ;
+; C4_LOW                        ; 0                 ; Untyped                                    ;
+; C5_LOW                        ; 0                 ; Untyped                                    ;
+; C6_LOW                        ; 0                 ; Untyped                                    ;
+; C7_LOW                        ; 0                 ; Untyped                                    ;
+; C8_LOW                        ; 0                 ; Untyped                                    ;
+; C9_LOW                        ; 0                 ; Untyped                                    ;
+; C0_INITIAL                    ; 0                 ; Untyped                                    ;
+; C1_INITIAL                    ; 0                 ; Untyped                                    ;
+; C2_INITIAL                    ; 0                 ; Untyped                                    ;
+; C3_INITIAL                    ; 0                 ; Untyped                                    ;
+; C4_INITIAL                    ; 0                 ; Untyped                                    ;
+; C5_INITIAL                    ; 0                 ; Untyped                                    ;
+; C6_INITIAL                    ; 0                 ; Untyped                                    ;
+; C7_INITIAL                    ; 0                 ; Untyped                                    ;
+; C8_INITIAL                    ; 0                 ; Untyped                                    ;
+; C9_INITIAL                    ; 0                 ; Untyped                                    ;
+; C0_MODE                       ; BYPASS            ; Untyped                                    ;
+; C1_MODE                       ; BYPASS            ; Untyped                                    ;
+; C2_MODE                       ; BYPASS            ; Untyped                                    ;
+; C3_MODE                       ; BYPASS            ; Untyped                                    ;
+; C4_MODE                       ; BYPASS            ; Untyped                                    ;
+; C5_MODE                       ; BYPASS            ; Untyped                                    ;
+; C6_MODE                       ; BYPASS            ; Untyped                                    ;
+; C7_MODE                       ; BYPASS            ; Untyped                                    ;
+; C8_MODE                       ; BYPASS            ; Untyped                                    ;
+; C9_MODE                       ; BYPASS            ; Untyped                                    ;
+; C0_PH                         ; 0                 ; Untyped                                    ;
+; C1_PH                         ; 0                 ; Untyped                                    ;
+; C2_PH                         ; 0                 ; Untyped                                    ;
+; C3_PH                         ; 0                 ; Untyped                                    ;
+; C4_PH                         ; 0                 ; Untyped                                    ;
+; C5_PH                         ; 0                 ; Untyped                                    ;
+; C6_PH                         ; 0                 ; Untyped                                    ;
+; C7_PH                         ; 0                 ; Untyped                                    ;
+; C8_PH                         ; 0                 ; Untyped                                    ;
+; C9_PH                         ; 0                 ; Untyped                                    ;
+; L0_HIGH                       ; 1                 ; Untyped                                    ;
+; L1_HIGH                       ; 1                 ; Untyped                                    ;
+; G0_HIGH                       ; 1                 ; Untyped                                    ;
+; G1_HIGH                       ; 1                 ; Untyped                                    ;
+; G2_HIGH                       ; 1                 ; Untyped                                    ;
+; G3_HIGH                       ; 1                 ; Untyped                                    ;
+; E0_HIGH                       ; 1                 ; Untyped                                    ;
+; E1_HIGH                       ; 1                 ; Untyped                                    ;
+; E2_HIGH                       ; 1                 ; Untyped                                    ;
+; E3_HIGH                       ; 1                 ; Untyped                                    ;
+; L0_LOW                        ; 1                 ; Untyped                                    ;
+; L1_LOW                        ; 1                 ; Untyped                                    ;
+; G0_LOW                        ; 1                 ; Untyped                                    ;
+; G1_LOW                        ; 1                 ; Untyped                                    ;
+; G2_LOW                        ; 1                 ; Untyped                                    ;
+; G3_LOW                        ; 1                 ; Untyped                                    ;
+; E0_LOW                        ; 1                 ; Untyped                                    ;
+; E1_LOW                        ; 1                 ; Untyped                                    ;
+; E2_LOW                        ; 1                 ; Untyped                                    ;
+; E3_LOW                        ; 1                 ; Untyped                                    ;
+; L0_INITIAL                    ; 1                 ; Untyped                                    ;
+; L1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G0_INITIAL                    ; 1                 ; Untyped                                    ;
+; G1_INITIAL                    ; 1                 ; Untyped                                    ;
+; G2_INITIAL                    ; 1                 ; Untyped                                    ;
+; G3_INITIAL                    ; 1                 ; Untyped                                    ;
+; E0_INITIAL                    ; 1                 ; Untyped                                    ;
+; E1_INITIAL                    ; 1                 ; Untyped                                    ;
+; E2_INITIAL                    ; 1                 ; Untyped                                    ;
+; E3_INITIAL                    ; 1                 ; Untyped                                    ;
+; L0_MODE                       ; BYPASS            ; Untyped                                    ;
+; L1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G0_MODE                       ; BYPASS            ; Untyped                                    ;
+; G1_MODE                       ; BYPASS            ; Untyped                                    ;
+; G2_MODE                       ; BYPASS            ; Untyped                                    ;
+; G3_MODE                       ; BYPASS            ; Untyped                                    ;
+; E0_MODE                       ; BYPASS            ; Untyped                                    ;
+; E1_MODE                       ; BYPASS            ; Untyped                                    ;
+; E2_MODE                       ; BYPASS            ; Untyped                                    ;
+; E3_MODE                       ; BYPASS            ; Untyped                                    ;
+; L0_PH                         ; 0                 ; Untyped                                    ;
+; L1_PH                         ; 0                 ; Untyped                                    ;
+; G0_PH                         ; 0                 ; Untyped                                    ;
+; G1_PH                         ; 0                 ; Untyped                                    ;
+; G2_PH                         ; 0                 ; Untyped                                    ;
+; G3_PH                         ; 0                 ; Untyped                                    ;
+; E0_PH                         ; 0                 ; Untyped                                    ;
+; E1_PH                         ; 0                 ; Untyped                                    ;
+; E2_PH                         ; 0                 ; Untyped                                    ;
+; E3_PH                         ; 0                 ; Untyped                                    ;
+; M_PH                          ; 0                 ; Untyped                                    ;
+; C1_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C2_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C3_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C4_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C5_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C6_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C7_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C8_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; C9_USE_CASC_IN                ; OFF               ; Untyped                                    ;
+; CLK0_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK1_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK2_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK3_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK4_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK5_COUNTER                  ; G0                ; Untyped                                    ;
+; CLK6_COUNTER                  ; E0                ; Untyped                                    ;
+; CLK7_COUNTER                  ; E1                ; Untyped                                    ;
+; CLK8_COUNTER                  ; E2                ; Untyped                                    ;
+; CLK9_COUNTER                  ; E3                ; Untyped                                    ;
+; L0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; L1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; G3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E0_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E1_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E2_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; E3_TIME_DELAY                 ; 0                 ; Untyped                                    ;
+; M_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; N_TIME_DELAY                  ; 0                 ; Untyped                                    ;
+; EXTCLK3_COUNTER               ; E3                ; Untyped                                    ;
+; EXTCLK2_COUNTER               ; E2                ; Untyped                                    ;
+; EXTCLK1_COUNTER               ; E1                ; Untyped                                    ;
+; EXTCLK0_COUNTER               ; E0                ; Untyped                                    ;
+; ENABLE0_COUNTER               ; L0                ; Untyped                                    ;
+; ENABLE1_COUNTER               ; L0                ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                                    ;
+; LOOP_FILTER_R                 ;  1.000000         ; Untyped                                    ;
+; LOOP_FILTER_C                 ; 5                 ; Untyped                                    ;
+; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                                    ;
+; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                                    ;
+; VCO_POST_SCALE                ; 0                 ; Untyped                                    ;
+; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                                    ;
+; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                                    ;
+; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK0                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK1                     ; PORT_USED         ; Untyped                                    ;
+; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_INCLK0                   ; PORT_USED         ; Untyped                                    ;
+; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                                    ;
+; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                                    ;
+; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                                    ;
+; M_TEST_SOURCE                 ; 5                 ; Untyped                                    ;
+; C0_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C1_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C2_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C3_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C4_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C5_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C6_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C7_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C8_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; C9_TEST_SOURCE                ; 5                 ; Untyped                                    ;
+; CBXI_PARAMETER                ; altpll_9ee2       ; Untyped                                    ;
+; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                                    ;
+; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                                    ;
+; WIDTH_CLOCK                   ; 5                 ; Signed Integer                             ;
+; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                                    ;
+; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                                    ;
+; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                                    ;
+; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                                    ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                                    ;
+; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                 ;
+; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                               ;
+; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                               ;
+; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                             ;
++-------------------------------+-------------------+--------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7 ;
++----------------+-------+---------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                    ;
++----------------+-------+---------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                          ;
+; REF_PER        ; 1024  ; Signed Integer                                          ;
+; SC_CL          ; 3     ; Signed Integer                                          ;
+; SC_RCD         ; 3     ; Signed Integer                                          ;
+; SC_RRD         ; 7     ; Signed Integer                                          ;
+; SC_PM          ; 1     ; Signed Integer                                          ;
+; SC_BL          ; 1     ; Signed Integer                                          ;
+; SDR_BL         ; 111   ; Unsigned Binary                                         ;
+; SDR_BT         ; 0     ; Unsigned Binary                                         ;
+; SDR_CL         ; 011   ; Unsigned Binary                                         ;
++----------------+-------+---------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1 ;
++----------------+-------+------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                               ;
++----------------+-------+------------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                     ;
+; REF_PER        ; 1024  ; Signed Integer                                                                     ;
+; SC_CL          ; 3     ; Signed Integer                                                                     ;
+; SC_RCD         ; 3     ; Signed Integer                                                                     ;
+; SC_RRD         ; 7     ; Signed Integer                                                                     ;
+; SC_PM          ; 1     ; Signed Integer                                                                     ;
+; SC_BL          ; 1     ; Signed Integer                                                                     ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                    ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                    ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                    ;
++----------------+-------+------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1 ;
++----------------+-------+--------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                     ;
++----------------+-------+--------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                           ;
+; REF_PER        ; 1024  ; Signed Integer                                                           ;
+; SC_CL          ; 3     ; Signed Integer                                                           ;
+; SC_RCD         ; 3     ; Signed Integer                                                           ;
+; SC_RRD         ; 7     ; Signed Integer                                                           ;
+; SC_PM          ; 1     ; Signed Integer                                                           ;
+; SC_BL          ; 1     ; Signed Integer                                                           ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                          ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                          ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                          ;
++----------------+-------+--------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1 ;
++----------------+-------+----------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                             ;
++----------------+-------+----------------------------------------------------------------------------------+
+; INIT_PER       ; 24000 ; Signed Integer                                                                   ;
+; REF_PER        ; 1024  ; Signed Integer                                                                   ;
+; SC_CL          ; 3     ; Signed Integer                                                                   ;
+; SC_RCD         ; 3     ; Signed Integer                                                                   ;
+; SC_RRD         ; 7     ; Signed Integer                                                                   ;
+; SC_PM          ; 1     ; Signed Integer                                                                   ;
+; SC_BL          ; 1     ; Signed Integer                                                                   ;
+; SDR_BL         ; 111   ; Unsigned Binary                                                                  ;
+; SDR_BT         ; 0     ; Unsigned Binary                                                                  ;
+; SDR_CL         ; 011   ; Unsigned Binary                                                                  ;
++----------------+-------+----------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                    ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                 ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                              ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                            ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                            ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                          ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                          ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                          ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                          ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                 ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                 ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                 ;
+; USE_EAB                 ; ON          ; Untyped                                                                                 ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                 ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                 ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                 ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                 ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                 ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                 ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                 ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                 ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                 ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                 ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                 ;
++-------------------------+-------------+-----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; Parameter Name          ; Value       ; Type                                                                                   ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+; WIDTH_BYTEENA           ; 1           ; Untyped                                                                                ;
+; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                             ;
+; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                           ;
+; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                           ;
+; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                         ;
+; LPM_WIDTH               ; 16          ; Signed Integer                                                                         ;
+; LPM_NUMWORDS            ; 512         ; Signed Integer                                                                         ;
+; LPM_WIDTHU              ; 9           ; Signed Integer                                                                         ;
+; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                ;
+; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                                ;
+; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                                ;
+; USE_EAB                 ; ON          ; Untyped                                                                                ;
+; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                ;
+; DELAY_RDUSEDW           ; 1           ; Untyped                                                                                ;
+; DELAY_WRUSEDW           ; 1           ; Untyped                                                                                ;
+; RDSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; WRSYNC_DELAYPIPE        ; 3           ; Untyped                                                                                ;
+; CLOCKS_ARE_SYNCHRONIZED ; FALSE       ; Untyped                                                                                ;
+; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                ;
+; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                                ;
+; ADD_USEDW_MSB_BIT       ; OFF         ; Untyped                                                                                ;
+; WRITE_ACLR_SYNCH        ; OFF         ; Untyped                                                                                ;
+; READ_ACLR_SYNCH         ; OFF         ; Untyped                                                                                ;
+; CBXI_PARAMETER          ; dcfifo_v5o1 ; Untyped                                                                                ;
++-------------------------+-------------+----------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: DE0_D5M:inst|I2C_CCD_Config:u8 ;
++-----------------------+------------------+----------------------------------+
+; Parameter Name        ; Value            ; Type                             ;
++-----------------------+------------------+----------------------------------+
+; default_exposure      ; 0000011111000000 ; Unsigned Binary                  ;
+; exposure_change_value ; 0000000011001000 ; Unsigned Binary                  ;
+; CLK_Freq              ; 50000000         ; Signed Integer                   ;
+; I2C_Freq              ; 20000            ; Signed Integer                   ;
+; LUT_SIZE              ; 25               ; Signed Integer                   ;
++-----------------------+------------------+----------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------+
+; Parameter Settings for User Entity Instance: ps2:inst6 ;
++----------------+-----------+---------------------------+
+; Parameter Name ; Value     ; Type                      ;
++----------------+-----------+---------------------------+
+; enable_byte    ; 011110100 ; Unsigned Binary           ;
+; listen         ; 00        ; Unsigned Binary           ;
+; pullclk        ; 01        ; Unsigned Binary           ;
+; pulldat        ; 10        ; Unsigned Binary           ;
+; trans          ; 11        ; Unsigned Binary           ;
++----------------+-----------+---------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mux:inst10|LPM_MUX:LPM_MUX_component ;
++------------------------+-------------+------------------------------------------------+
+; Parameter Name         ; Value       ; Type                                           ;
++------------------------+-------------+------------------------------------------------+
+; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                     ;
+; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                   ;
+; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                   ;
+; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                 ;
+; LPM_WIDTH              ; 30          ; Signed Integer                                 ;
+; LPM_SIZE               ; 4           ; Signed Integer                                 ;
+; LPM_WIDTHS             ; 2           ; Signed Integer                                 ;
+; LPM_PIPELINE           ; 0           ; Signed Integer                                 ;
+; CBXI_PARAMETER         ; mux_u7e     ; Untyped                                        ;
+; DEVICE_FAMILY          ; Cyclone III ; Untyped                                        ;
++------------------------+-------------+------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                            ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                                                  ;
+; width          ; 20    ; Signed Integer                                                                                  ;
++----------------+-------+-------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                                                    ;
+; width          ; 20    ; Signed Integer                                                                                    ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                 ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+; rscid          ; 3     ; Signed Integer                                                                                       ;
+; width          ; 8     ; Signed Integer                                                                                       ;
++----------------+-------+------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                              ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+; rscid          ; 4     ; Signed Integer                                                                                    ;
+; width          ; 30    ; Signed Integer                                                                                    ;
++----------------+-------+---------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                                     ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+; rscid          ; 5     ; Signed Integer                                                                                           ;
+; width          ; 30    ; Signed Integer                                                                                           ;
++----------------+-------+----------------------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire ;
++----------------+-------+-------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                ;
++----------------+-------+-------------------------------------------------------------------------------------+
+; rscid          ; 1     ; Signed Integer                                                                      ;
+; width          ; 90    ; Signed Integer                                                                      ;
++----------------+-------+-------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg ;
++----------------+-------+--------------------------------------------------------------------------------------------+
+; Parameter Name ; Value ; Type                                                                                       ;
++----------------+-------+--------------------------------------------------------------------------------------------+
+; rscid          ; 2     ; Signed Integer                                                                             ;
+; width          ; 30    ; Signed Integer                                                                             ;
++----------------+-------+--------------------------------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: altshift_taps:fifo_inst2 ;
++----------------+----------------+-------------------------------------+
+; Parameter Name ; Value          ; Type                                ;
++----------------+----------------+-------------------------------------+
+; WIDTH_BYTEENA  ; 1              ; Untyped                             ;
+; NUMBER_OF_TAPS ; 5              ; Untyped                             ;
+; TAP_DISTANCE   ; 800            ; Untyped                             ;
+; WIDTH          ; 30             ; Untyped                             ;
+; POWER_UP_STATE ; CLEARED        ; Untyped                             ;
+; CBXI_PARAMETER ; shift_taps_lpm ; Untyped                             ;
++----------------+----------------+-------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 2           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 11          ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 11          ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4 ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; Parameter Name                                 ; Value       ; Type                                                              ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+; AUTO_CARRY_CHAINS                              ; ON          ; AUTO_CARRY                                                        ;
+; IGNORE_CARRY_BUFFERS                           ; OFF         ; IGNORE_CARRY                                                      ;
+; AUTO_CASCADE_CHAINS                            ; ON          ; AUTO_CASCADE                                                      ;
+; IGNORE_CASCADE_BUFFERS                         ; OFF         ; IGNORE_CASCADE                                                    ;
+; LPM_WIDTHA                                     ; 3           ; Untyped                                                           ;
+; LPM_WIDTHB                                     ; 6           ; Untyped                                                           ;
+; LPM_WIDTHP                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHR                                     ; 9           ; Untyped                                                           ;
+; LPM_WIDTHS                                     ; 1           ; Untyped                                                           ;
+; LPM_REPRESENTATION                             ; UNSIGNED    ; Untyped                                                           ;
+; LPM_PIPELINE                                   ; 0           ; Untyped                                                           ;
+; LATENCY                                        ; 0           ; Untyped                                                           ;
+; INPUT_A_IS_CONSTANT                            ; NO          ; Untyped                                                           ;
+; INPUT_B_IS_CONSTANT                            ; YES         ; Untyped                                                           ;
+; USE_EAB                                        ; OFF         ; Untyped                                                           ;
+; MAXIMIZE_SPEED                                 ; 5           ; Untyped                                                           ;
+; DEVICE_FAMILY                                  ; Cyclone III ; Untyped                                                           ;
+; CARRY_CHAIN                                    ; MANUAL      ; Untyped                                                           ;
+; APEX20K_TECHNOLOGY_MAPPER                      ; LUT         ; TECH_MAPPER_APEX20K                                               ;
+; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO        ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0           ; Untyped                                                           ;
+; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0           ; Untyped                                                           ;
+; CBXI_PARAMETER                                 ; NOTHING     ; Untyped                                                           ;
+; INPUT_A_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; INPUT_B_FIXED_VALUE                            ; Bx          ; Untyped                                                           ;
+; USE_AHDL_IMPLEMENTATION                        ; OFF         ; Untyped                                                           ;
++------------------------------------------------+-------------+-------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------------------------------+
+; altshift_taps Parameter Settings by Entity Instance                                                       ;
++----------------------------+------------------------------------------------------------------------------+
+; Name                       ; Value                                                                        ;
++----------------------------+------------------------------------------------------------------------------+
+; Number of entity instances ; 2                                                                            ;
+; Entity Instance            ; DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component ;
+;     -- NUMBER_OF_TAPS      ; 2                                                                            ;
+;     -- TAP_DISTANCE        ; 1280                                                                         ;
+;     -- WIDTH               ; 12                                                                           ;
+; Entity Instance            ; altshift_taps:fifo_inst2                                                     ;
+;     -- NUMBER_OF_TAPS      ; 5                                                                            ;
+;     -- TAP_DISTANCE        ; 800                                                                          ;
+;     -- WIDTH               ; 30                                                                           ;
++----------------------------+------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance                                      ;
++-------------------------------+---------------------------------------------------+
+; Name                          ; Value                                             ;
++-------------------------------+---------------------------------------------------+
+; Number of entity instances    ; 1                                                 ;
+; Entity Instance               ; DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component ;
+;     -- OPERATION_MODE         ; NORMAL                                            ;
+;     -- PLL_TYPE               ; AUTO                                              ;
+;     -- PRIMARY_CLOCK          ; INCLK0                                            ;
+;     -- INCLK0_INPUT_FREQUENCY ; 20000                                             ;
+;     -- INCLK1_INPUT_FREQUENCY ; 0                                                 ;
+;     -- VCO_MULTIPLY_BY        ; 0                                                 ;
+;     -- VCO_DIVIDE_BY          ; 0                                                 ;
++-------------------------------+---------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; dcfifo Parameter Settings by Entity Instance                                                                    ;
++----------------------------+------------------------------------------------------------------------------------+
+; Name                       ; Value                                                                              ;
++----------------------------+------------------------------------------------------------------------------------+
+; Number of entity instances ; 4                                                                                  ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
+; Entity Instance            ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component  ;
+;     -- FIFO Type           ; Dual Clock                                                                         ;
+;     -- LPM_WIDTH           ; 16                                                                                 ;
+;     -- LPM_NUMWORDS        ; 512                                                                                ;
+;     -- LPM_SHOWAHEAD       ; OFF                                                                                ;
+;     -- USE_EAB             ; ON                                                                                 ;
++----------------------------+------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; lpm_mult Parameter Settings by Entity Instance                                                                          ;
++---------------------------------------+---------------------------------------------------------------------------------+
+; Name                                  ; Value                                                                           ;
++---------------------------------------+---------------------------------------------------------------------------------+
+; Number of entity instances            ; 6                                                                               ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3 ;
+;     -- LPM_WIDTHA                     ; 2                                                                               ;
+;     -- LPM_WIDTHB                     ; 9                                                                               ;
+;     -- LPM_WIDTHP                     ; 11                                                                              ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult1 ;
+;     -- LPM_WIDTHA                     ; 2                                                                               ;
+;     -- LPM_WIDTHB                     ; 9                                                                               ;
+;     -- LPM_WIDTHP                     ; 11                                                                              ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult5 ;
+;     -- LPM_WIDTHA                     ; 2                                                                               ;
+;     -- LPM_WIDTHB                     ; 9                                                                               ;
+;     -- LPM_WIDTHP                     ; 11                                                                              ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2 ;
+;     -- LPM_WIDTHA                     ; 3                                                                               ;
+;     -- LPM_WIDTHB                     ; 6                                                                               ;
+;     -- LPM_WIDTHP                     ; 9                                                                               ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult0 ;
+;     -- LPM_WIDTHA                     ; 3                                                                               ;
+;     -- LPM_WIDTHB                     ; 6                                                                               ;
+;     -- LPM_WIDTHP                     ; 9                                                                               ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
+; Entity Instance                       ; mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult4 ;
+;     -- LPM_WIDTHA                     ; 3                                                                               ;
+;     -- LPM_WIDTHB                     ; 6                                                                               ;
+;     -- LPM_WIDTHP                     ; 9                                                                               ;
+;     -- LPM_REPRESENTATION             ; UNSIGNED                                                                        ;
+;     -- INPUT_A_IS_CONSTANT            ; NO                                                                              ;
+;     -- INPUT_B_IS_CONSTANT            ; YES                                                                             ;
+;     -- USE_EAB                        ; OFF                                                                             ;
+;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                            ;
+;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                              ;
+;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                              ;
++---------------------------------------+---------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|I2C_CCD_Config:u8"                                                                                                                   ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port       ; Type  ; Severity ; Details                                                                                                                                      ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; iUART_CTRL ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++------------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1"                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; rdusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"                                                 ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port    ; Type   ; Severity ; Details                                                                                                  ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; rdempty ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrfull  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; wrusedw ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++---------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"                       ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; Port ; Type   ; Severity ; Details                                                                             ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+; DM   ; Input  ; Info     ; Stuck at GND                                                                        ;
+; DQM  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"                                                                                 ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; Port     ; Type  ; Severity ; Details                                                                                                                                      ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+; CMD      ; Input ; Warning  ; Input port expression (2 bits) is smaller than the input port (3 bits) it drives.  Extra input bit(s) "CMD[2..2]" will be connected to GND.  ;
+; INIT_ACK ; Input ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
++----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|Sdram_Control_4Port:u7"                                                                                                                                                               ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port                 ; Type   ; Severity ; Details                                                                                                                                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; RESET_N              ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_DATA[15]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "WR2_ADDR[22..22]" will be connected to GND.                               ;
+; WR2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; WR2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; WR2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; WR2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD1_ADDR             ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_ADDR[22..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD1_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[22..19] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD1_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD1_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_DATA[15]         ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; RD2_ADDR             ; Input  ; Warning  ; Input port expression (22 bits) is smaller than the input port (23 bits) it drives.  Extra input bit(s) "RD2_ADDR[22..22]" will be connected to GND.                               ;
+; RD2_ADDR[19..0]      ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[22]         ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_ADDR[21]         ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR         ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (23 bits) it drives.  The 9 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; RD2_MAX_ADDR[13..12] ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[22..21] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[17..16] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[11..0]  ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[20]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[19]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_MAX_ADDR[18]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[15]     ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; RD2_MAX_ADDR[14]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[7..0]     ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
+; RD2_LENGTH[8]        ; Input  ; Info     ; Stuck at VCC                                                                                                                                                                       ;
+; CS_N                 ; Output ; Warning  ; Output or bidir port (2 bits) is wider than the port expression (1 bits) it drives; bit(s) "CS_N[1..1]" have no fanouts                                                            ;
++----------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|SEG7_LUT_8:u5" ;
++-------+--------+----------+----------------------------+
+; Port  ; Type   ; Severity ; Details                    ;
++-------+--------+----------+----------------------------+
+; oSEG4 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG5 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG6 ; Output ; Info     ; Explicitly unconnected     ;
+; oSEG7 ; Output ; Info     ; Explicitly unconnected     ;
++-------+--------+----------+----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"                                                                      ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port     ; Type   ; Severity ; Details                                                                                                  ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; shiftout ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++----------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|RAW2RGB:u4"                                                                                                                                                                   ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port         ; Type   ; Severity ; Details                                                                                                                                                                            ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; oRed[1..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oGreen[1..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; oBlue[1..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                                                                                                ;
+; iX_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; iY_Cont      ; Input  ; Warning  ; Input port expression (16 bits) is wider than the input port (11 bits) it drives.  The 5 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
++--------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|CCD_Capture:u3"                                                                   ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; Port            ; Type   ; Severity ; Details                                                                             ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+; oX_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+; oY_Cont[15..11] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
++-----------------+--------+----------+-------------------------------------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "DE0_D5M:inst|VGA_Controller:u1"                                                                                ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; Port       ; Type   ; Severity ; Details                                                                                                  ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+; oVGA_SYNC  ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_BLANK ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+; oVGA_CLOCK ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
++------------+--------+----------+----------------------------------------------------------------------------------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition    ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top            ; 00:00:04     ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 11:16:53 2014
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE0_D5M -c DE0_D5M
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (12021): Found 2 design units, including 2 entities, in source file catapult_ip/blur3x3/rtl.v
+    Info (12023): Found entity 1: mean_vga_core
+    Info (12023): Found entity 2: mean_vga
+Info (12021): Found 1 design units, including 1 entities, in source file v/ps2.v
+    Info (12023): Found entity 1: ps2
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/command.v
+    Info (12023): Found entity 1: command
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/control_interface.v
+    Info (12023): Found entity 1: control_interface
+Warning (10229): Verilog HDL Expression warning at sdr_data_path.v(68): truncated literal to match 1 bits
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdr_data_path.v
+    Info (12023): Found entity 1: sdr_data_path
+Warning (10238): Verilog Module Declaration warning at Sdram_Control_4Port.v(90): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "Sdram_Control_4Port"
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_control_4port.v
+    Info (12023): Found entity 1: Sdram_Control_4Port
+Info (12021): Found 1 design units, including 1 entities, in source file sdram_control_4port/sdram_fifo.v
+    Info (12023): Found entity 1: Sdram_FIFO
+Warning (12019): Can't analyze file -- file V/async_receiver.v is missing
+Info (12021): Found 1 design units, including 1 entities, in source file v/ccd_capture.v
+    Info (12023): Found entity 1: CCD_Capture
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_ccd_config.v
+    Info (12023): Found entity 1: I2C_CCD_Config
+Info (12021): Found 1 design units, including 1 entities, in source file v/i2c_controller.v
+    Info (12023): Found entity 1: I2C_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file v/line_buffer.v
+    Info (12023): Found entity 1: Line_Buffer
+Info (12021): Found 1 design units, including 1 entities, in source file v/raw2rgb.v
+    Info (12023): Found entity 1: RAW2RGB
+Info (12021): Found 1 design units, including 1 entities, in source file v/reset_delay.v
+    Info (12023): Found entity 1: Reset_Delay
+Info (12021): Found 1 design units, including 1 entities, in source file v/sdram_pll.v
+    Info (12023): Found entity 1: sdram_pll
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut.v
+    Info (12023): Found entity 1: SEG7_LUT
+Info (12021): Found 1 design units, including 1 entities, in source file v/seg7_lut_8.v
+    Info (12023): Found entity 1: SEG7_LUT_8
+Info (12021): Found 1 design units, including 1 entities, in source file v/vga_controller.v
+    Info (12023): Found entity 1: VGA_Controller
+Info (12021): Found 1 design units, including 1 entities, in source file de0_d5m.v
+    Info (12023): Found entity 1: DE0_D5M
+Info (12021): Found 1 design units, including 1 entities, in source file v/top_de0_camera_mouse.bdf
+    Info (12023): Found entity 1: TOP_DE0_CAMERA_MOUSE
+Info (12021): Found 2 design units, including 1 entities, in source file vga_mux.vhd
+    Info (12022): Found design unit 1: vga_mux-SYN
+    Info (12023): Found entity 1: vga_mux
+Info (12021): Found 7 design units, including 7 entities, in source file catapult_ip/mouse/rtl_mgc_ioport_v2001.v
+    Info (12023): Found entity 1: mgc_out_reg_pos
+    Info (12023): Found entity 2: mgc_out_reg_neg
+    Info (12023): Found entity 3: mgc_out_reg
+    Info (12023): Found entity 4: mgc_out_buf_wait
+    Info (12023): Found entity 5: mgc_out_fifo_wait
+    Info (12023): Found entity 6: mgc_out_fifo_wait_core
+    Info (12023): Found entity 7: mgc_pipe
+Info (12021): Found 20 design units, including 20 entities, in source file catapult_ip/mouse/rtl_mgc_ioport.v
+    Info (12023): Found entity 1: mgc_in_wire
+    Info (12023): Found entity 2: mgc_in_wire_en
+    Info (12023): Found entity 3: mgc_in_wire_wait
+    Info (12023): Found entity 4: mgc_chan_in
+    Info (12023): Found entity 5: mgc_out_stdreg
+    Info (12023): Found entity 6: mgc_out_stdreg_en
+    Info (12023): Found entity 7: mgc_out_stdreg_wait
+    Info (12023): Found entity 8: mgc_out_prereg_en
+    Info (12023): Found entity 9: mgc_inout_stdreg_en
+    Info (12023): Found entity 10: hid_tribuf
+    Info (12023): Found entity 11: mgc_inout_stdreg_wait
+    Info (12023): Found entity 12: mgc_inout_buf_wait
+    Info (12023): Found entity 13: mgc_inout_fifo_wait
+    Info (12023): Found entity 14: mgc_io_sync
+    Info (12023): Found entity 15: mgc_bsync_rdy
+    Info (12023): Found entity 16: mgc_bsync_vld
+    Info (12023): Found entity 17: mgc_bsync_rv
+    Info (12023): Found entity 18: mgc_sync
+    Info (12023): Found entity 19: funccall_inout
+    Info (12023): Found entity 20: modulario_en_in
+Info (12021): Found 2 design units, including 2 entities, in source file catapult_ip/mouse/rtl.v
+    Info (12023): Found entity 1: vga_mouse_square_core
+    Info (12023): Found entity 2: vga_mouse_square
+Info (12127): Elaborating entity "TOP_DE0_CAMERA_MOUSE" for the top level hierarchy
+Warning (275002): No superset bus at connection
+Info (12128): Elaborating entity "DE0_D5M" for hierarchy "DE0_D5M:inst"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(118): the port and data declarations for array port "VGA_R" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(166): see declaration for object "VGA_R"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(119): the port and data declarations for array port "VGA_G" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(167): see declaration for object "VGA_G"
+Critical Warning (10169): Verilog HDL warning at DE0_D5M.v(120): the port and data declarations for array port "VGA_B" do not specify the same range for each dimension
+Warning (10359): HDL warning at DE0_D5M.v(168): see declaration for object "VGA_B"
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(197): truncated value with size 16 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at DE0_D5M.v(202): truncated value with size 32 to match size of target (2)
+Warning (10034): Output port "GPIO_1_CLKOUT[1]" at DE0_D5M.v(128) has no driver
+Info (12128): Elaborating entity "VGA_Controller" for hierarchy "DE0_D5M:inst|VGA_Controller:u1"
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(70): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(73): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(76): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(115): truncated value with size 32 to match size of target (12)
+Warning (10230): Verilog HDL assignment warning at VGA_Controller.v(146): truncated value with size 32 to match size of target (12)
+Info (12128): Elaborating entity "Reset_Delay" for hierarchy "DE0_D5M:inst|Reset_Delay:u2"
+Info (12128): Elaborating entity "CCD_Capture" for hierarchy "DE0_D5M:inst|CCD_Capture:u3"
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(162): object "ifval_fedge" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at CCD_Capture.v(163): object "y_cnt_d" assigned a value but never read
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(123): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(127): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at CCD_Capture.v(183): truncated value with size 32 to match size of target (1)
+Info (12128): Elaborating entity "RAW2RGB" for hierarchy "DE0_D5M:inst|RAW2RGB:u4"
+Info (12128): Elaborating entity "Line_Buffer" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0"
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component" with the following parameter:
+    Info (12134): Parameter "lpm_type" = "altshift_taps"
+    Info (12134): Parameter "number_of_taps" = "2"
+    Info (12134): Parameter "tap_distance" = "1280"
+    Info (12134): Parameter "width" = "12"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_rnn.tdf
+    Info (12023): Found entity 1: shift_taps_rnn
+Info (12128): Elaborating entity "shift_taps_rnn" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_lp81.tdf
+    Info (12023): Found entity 1: altsyncram_lp81
+Info (12128): Elaborating entity "altsyncram_lp81" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|altsyncram_lp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_cuf.tdf
+    Info (12023): Found entity 1: cntr_cuf
+Info (12128): Elaborating entity "cntr_cuf" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_vgc.tdf
+    Info (12023): Found entity 1: cmpr_vgc
+Info (12128): Elaborating entity "cmpr_vgc" for hierarchy "DE0_D5M:inst|RAW2RGB:u4|Line_Buffer:u0|altshift_taps:altshift_taps_component|shift_taps_rnn:auto_generated|cntr_cuf:cntr1|cmpr_vgc:cmpr4"
+Info (12128): Elaborating entity "SEG7_LUT_8" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5"
+Info (12128): Elaborating entity "SEG7_LUT" for hierarchy "DE0_D5M:inst|SEG7_LUT_8:u5|SEG7_LUT:u0"
+Info (12128): Elaborating entity "sdram_pll" for hierarchy "DE0_D5M:inst|sdram_pll:u6"
+Info (12128): Elaborating entity "altpll" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component" with the following parameter:
+    Info (12134): Parameter "bandwidth_type" = "AUTO"
+    Info (12134): Parameter "clk0_divide_by" = "2"
+    Info (12134): Parameter "clk0_duty_cycle" = "50"
+    Info (12134): Parameter "clk0_multiply_by" = "5"
+    Info (12134): Parameter "clk0_phase_shift" = "0"
+    Info (12134): Parameter "clk1_divide_by" = "2"
+    Info (12134): Parameter "clk1_duty_cycle" = "50"
+    Info (12134): Parameter "clk1_multiply_by" = "5"
+    Info (12134): Parameter "clk1_phase_shift" = "-2600"
+    Info (12134): Parameter "compensate_clock" = "CLK0"
+    Info (12134): Parameter "inclk0_input_frequency" = "20000"
+    Info (12134): Parameter "intended_device_family" = "Cyclone III"
+    Info (12134): Parameter "lpm_type" = "altpll"
+    Info (12134): Parameter "operation_mode" = "NORMAL"
+    Info (12134): Parameter "pll_type" = "AUTO"
+    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
+    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
+    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
+    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
+    Info (12134): Parameter "port_inclk0" = "PORT_USED"
+    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
+    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
+    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
+    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk0" = "PORT_USED"
+    Info (12134): Parameter "port_clk1" = "PORT_USED"
+    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
+    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
+    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
+    Info (12134): Parameter "width_clock" = "5"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9ee2.tdf
+    Info (12023): Found entity 1: altpll_9ee2
+Info (12128): Elaborating entity "altpll_9ee2" for hierarchy "DE0_D5M:inst|sdram_pll:u6|altpll:altpll_component|altpll_9ee2:auto_generated"
+Info (12128): Elaborating entity "Sdram_Control_4Port" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7"
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(385): truncated value with size 32 to match size of target (10)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(431): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(432): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(433): truncated value with size 32 to match size of target (23)
+Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(434): truncated value with size 32 to match size of target (23)
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(423): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rRD1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR2_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[0]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[1]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[2]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[3]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[4]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[5]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[6]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[7]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[8]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[9]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[10]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[11]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[12]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[13]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[14]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[15]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[16]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[17]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[18]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[19]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[20]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[21]" at Sdram_Control_4Port.v(423)
+Info (10041): Inferred latch for "rWR1_MAX_ADDR[22]" at Sdram_Control_4Port.v(423)
+Info (12128): Elaborating entity "control_interface" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1"
+Warning (10230): Verilog HDL assignment warning at control_interface.v(162): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(167): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at control_interface.v(192): truncated value with size 32 to match size of target (16)
+Info (12128): Elaborating entity "command" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1"
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
+Warning (10240): Verilog HDL Always Construct warning at command.v(275): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
+Info (12128): Elaborating entity "sdr_data_path" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|sdr_data_path:data_path1"
+Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(68): truncated value with size 32 to match size of target (2)
+Info (12128): Elaborating entity "Sdram_FIFO" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1"
+Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (272007): Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12128): Elaborating entity "dcfifo" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12130): Elaborated megafunction instantiation "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component"
+Info (12133): Instantiated megafunction "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component" with the following parameter:
+    Info (12134): Parameter "add_ram_output_register" = "OFF"
+    Info (12134): Parameter "clocks_are_synchronized" = "FALSE"
+    Info (12134): Parameter "intended_device_family" = "Cyclone"
+    Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M4K"
+    Info (12134): Parameter "lpm_numwords" = "512"
+    Info (12134): Parameter "lpm_showahead" = "OFF"
+    Info (12134): Parameter "lpm_type" = "dcfifo"
+    Info (12134): Parameter "lpm_width" = "16"
+    Info (12134): Parameter "lpm_widthu" = "9"
+    Info (12134): Parameter "overflow_checking" = "ON"
+    Info (12134): Parameter "underflow_checking" = "ON"
+    Info (12134): Parameter "use_eab" = "ON"
+Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2
+Warning (287001): Assertion warning: Device family Cyclone III does not have M4K blocks -- using available memory blocks
+Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_v5o1.tdf
+    Info (12023): Found entity 1: dcfifo_v5o1
+Info (12128): Elaborating entity "dcfifo_v5o1" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf
+    Info (12023): Found entity 1: a_gray2bin_tgb
+Info (12128): Elaborating entity "a_gray2bin_tgb" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_gray2bin_tgb:rdptr_g_gray2bin"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf
+    Info (12023): Found entity 1: a_graycounter_s57
+Info (12128): Elaborating entity "a_graycounter_s57" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf
+    Info (12023): Found entity 1: a_graycounter_ojc
+Info (12128): Elaborating entity "a_graycounter_ojc" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_de51.tdf
+    Info (12023): Found entity 1: altsyncram_de51
+Info (12128): Elaborating entity "altsyncram_de51" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
+    Info (12023): Found entity 1: dffpipe_oe9
+Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_qld
+Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
+    Info (12023): Found entity 1: dffpipe_pe9
+Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13"
+Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf
+    Info (12023): Found entity 1: alt_synch_pipe_rld
+Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp"
+Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
+    Info (12023): Found entity 1: dffpipe_qe9
+Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_e66.tdf
+    Info (12023): Found entity 1: cmpr_e66
+Info (12128): Elaborating entity "cmpr_e66" for hierarchy "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|cmpr_e66:rdempty_eq_comp"
+Info (12128): Elaborating entity "I2C_CCD_Config" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8"
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(126): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(127): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(160): truncated value with size 32 to match size of target (25)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(165): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(190): truncated value with size 32 to match size of target (16)
+Warning (10230): Verilog HDL assignment warning at I2C_CCD_Config.v(240): truncated value with size 32 to match size of target (6)
+Info (12128): Elaborating entity "I2C_Controller" for hierarchy "DE0_D5M:inst|I2C_CCD_Config:u8|I2C_Controller:u0"
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(70): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(69): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(82): truncated value with size 32 to match size of target (7)
+Info (12128): Elaborating entity "ps2" for hierarchy "ps2:inst6"
+Warning (10230): Verilog HDL assignment warning at ps2.v(120): truncated value with size 32 to match size of target (9)
+Warning (10230): Verilog HDL assignment warning at ps2.v(188): truncated value with size 32 to match size of target (8)
+Warning (10230): Verilog HDL assignment warning at ps2.v(195): truncated value with size 32 to match size of target (1)
+Warning (10230): Verilog HDL assignment warning at ps2.v(201): truncated value with size 32 to match size of target (6)
+Warning (10230): Verilog HDL assignment warning at ps2.v(229): truncated value with size 32 to match size of target (4)
+Warning (10230): Verilog HDL assignment warning at ps2.v(245): truncated value with size 32 to match size of target (4)
+Info (12128): Elaborating entity "vga_mux" for hierarchy "vga_mux:inst10"
+Info (12128): Elaborating entity "LPM_MUX" for hierarchy "vga_mux:inst10|LPM_MUX:LPM_MUX_component"
+Info (12130): Elaborated megafunction instantiation "vga_mux:inst10|LPM_MUX:LPM_MUX_component"
+Info (12133): Instantiated megafunction "vga_mux:inst10|LPM_MUX:LPM_MUX_component" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTH" = "30"
+    Info (12134): Parameter "LPM_SIZE" = "4"
+    Info (12134): Parameter "LPM_WIDTHS" = "2"
+    Info (12134): Parameter "LPM_PIPELINE" = "0"
+    Info (12134): Parameter "LPM_TYPE" = "LPM_MUX"
+    Info (12134): Parameter "LPM_HINT" = "UNUSED"
+Info (12021): Found 1 design units, including 1 entities, in source file db/mux_u7e.tdf
+    Info (12023): Found entity 1: mux_u7e
+Info (12128): Elaborating entity "mux_u7e" for hierarchy "vga_mux:inst10|LPM_MUX:LPM_MUX_component|mux_u7e:auto_generated"
+Info (12128): Elaborating entity "vga_mouse_square" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:vga_xy_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:mouse_xy_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:cursor_size_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_in_wire:video_in_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|mgc_out_stdreg:video_out_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "vga_mouse_square_core" for hierarchy "vga_mouse_square:vga_mouse_catapult_inst|vga_mouse_square_core:vga_mouse_square_core_inst"
+Info (12128): Elaborating entity "mean_vga" for hierarchy "mean_vga:vga_blur_catapult_inst"
+Info (12128): Elaborating entity "mgc_in_wire" for hierarchy "mean_vga:vga_blur_catapult_inst|mgc_in_wire:vin_rsc_mgc_in_wire"
+Info (12128): Elaborating entity "mgc_out_stdreg" for hierarchy "mean_vga:vga_blur_catapult_inst|mgc_out_stdreg:vout_rsc_mgc_out_stdreg"
+Info (12128): Elaborating entity "mean_vga_core" for hierarchy "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst"
+Warning (10230): Verilog HDL assignment warning at rtl.v(153): truncated value with size 11 to match size of target (10)
+Info (12128): Elaborating entity "altshift_taps" for hierarchy "altshift_taps:fifo_inst2"
+Info (12130): Elaborated megafunction instantiation "altshift_taps:fifo_inst2"
+Info (12133): Instantiated megafunction "altshift_taps:fifo_inst2" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "5"
+    Info (12134): Parameter "TAP_DISTANCE" = "800"
+    Info (12134): Parameter "WIDTH" = "30"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_lpm.tdf
+    Info (12023): Found entity 1: shift_taps_lpm
+Info (12128): Elaborating entity "shift_taps_lpm" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_vp81.tdf
+    Info (12023): Found entity 1: altsyncram_vp81
+Info (12128): Elaborating entity "altsyncram_vp81" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1tf.tdf
+    Info (12023): Found entity 1: cntr_1tf
+Info (12128): Elaborating entity "cntr_1tf" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1"
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ugc.tdf
+    Info (12023): Found entity 1: cmpr_ugc
+Info (12128): Elaborating entity "cmpr_ugc" for hierarchy "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|cntr_1tf:cntr1|cmpr_ugc:cmpr4"
+Warning (14284): Synthesized away the following node(s):
+    Warning (14285): Synthesized away the following RAM node(s):
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[90]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[91]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[92]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[93]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[94]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[95]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[96]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[97]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[98]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[99]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[100]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[101]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[102]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[103]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[104]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[105]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[106]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[107]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[108]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[109]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[110]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[111]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[112]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[113]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[114]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[115]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[116]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[117]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[118]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[119]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[120]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[121]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[122]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[123]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[124]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[125]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[126]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[127]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[128]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[129]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[130]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[131]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[132]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[133]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[134]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[135]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[136]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[137]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[138]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[139]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[140]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[141]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[142]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[143]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[144]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[145]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[146]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[147]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[148]"
+        Warning (14320): Synthesized away node "altshift_taps:fifo_inst2|shift_taps_lpm:auto_generated|altsyncram_vp81:altsyncram2|q_b[149]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+        Warning (14320): Synthesized away node "DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]"
+Info (278001): Inferred 6 megafunctions from design logic
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult3"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult1"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult5"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult2"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult0"
+    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|Mult4"
+Info (12130): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3"
+Info (12133): Instantiated megafunction "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "2"
+    Info (12134): Parameter "LPM_WIDTHB" = "9"
+    Info (12134): Parameter "LPM_WIDTHP" = "11"
+    Info (12134): Parameter "LPM_WIDTHR" = "11"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3|altshift:external_latency_ffs", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult3"
+Info (12130): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2"
+Info (12133): Instantiated megafunction "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2" with the following parameter:
+    Info (12134): Parameter "LPM_WIDTHA" = "3"
+    Info (12134): Parameter "LPM_WIDTHB" = "6"
+    Info (12134): Parameter "LPM_WIDTHP" = "9"
+    Info (12134): Parameter "LPM_WIDTHR" = "9"
+    Info (12134): Parameter "LPM_WIDTHS" = "1"
+    Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
+    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
+    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES"
+    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2"
+Info (12131): Elaborated megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2|altshift:external_latency_ffs", which is child of megafunction instantiation "mean_vga:vga_blur_catapult_inst|mean_vga_core:mean_vga_core_inst|lpm_mult:Mult2"
+Warning (12241): 10 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[20]" and its non-tri-state driver.
+    Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[14]" and its non-tri-state driver.
+Warning (13039): The following bidir pins have no drivers
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+    Warning (13040): Bidir "GPIO_1" has no driver
+Warning (13032): The following tri-state nodes are fed by constants
+    Warning (13033): The pin "GPIO_1[15]" is fed by VCC
+Info (13000): Registers with preset signals will power-up high
+Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
+Warning (13009): TRI or OPNDRN buffers permanently enabled
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+    Warning (13010): Node "GPIO_1~synth"
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "DRAM_CKE" is stuck at VCC
+    Warning (13410): Pin "GPIO_1_CLKOUT[1]" is stuck at GND
+    Warning (13410): Pin "LEDG[9]" is stuck at GND
+    Warning (13410): Pin "LEDG[8]" is stuck at GND
+    Warning (13410): Pin "LEDG[7]" is stuck at GND
+    Warning (13410): Pin "LEDG[6]" is stuck at GND
+    Warning (13410): Pin "LEDG[5]" is stuck at GND
+    Warning (13410): Pin "LEDG[4]" is stuck at GND
+    Warning (13410): Pin "LEDG[3]" is stuck at GND
+Info (286030): Timing-Driven Synthesis is running
+Info (17049): 29 registers lost all their fanouts during netlist optimizations.
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 3 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "GPIO_1_CLKIN[1]"
+    Warning (15610): No output dependent on input pin "SW[9]"
+    Warning (15610): No output dependent on input pin "SW[8]"
+Info (21057): Implemented 2869 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 16 input pins
+    Info (21059): Implemented 77 output pins
+    Info (21060): Implemented 50 bidirectional pins
+    Info (21061): Implemented 2549 logic cells
+    Info (21064): Implemented 176 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 176 warnings
+    Info: Peak virtual memory: 587 megabytes
+    Info: Processing ended: Mon Mar 17 11:17:03 2014
+    Info: Elapsed time: 00:00:10
+    Info: Total CPU time (on all processors): 00:00:09
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary
new file mode 100644
index 0000000..96e24fe
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Mon Mar 17 11:17:03 2014
+Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
+Revision Name : DE0_D5M
+Top-level Entity Name : TOP_DE0_CAMERA_MOUSE
+Family : Cyclone III
+Total logic elements : 2,517
+    Total combinational functions : 1,922
+    Dedicated logic registers : 1,326
+Total registers : 1326
+Total pins : 143
+Total virtual pins : 0
+Total memory bits : 134,236
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 1
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin
new file mode 100644
index 0000000..5c03fbc
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pin
@@ -0,0 +1,554 @@
+ -- Copyright (C) 1991-2013 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+ -- (including device programming or simulation files), and any 
+ -- associated documentation or information are expressly subject 
+ -- to the terms and conditions of the Altera Program License 
+ -- Subscription Agreement, Altera MegaCore Function License 
+ -- Agreement, or other applicable license agreement, including, 
+ -- without limitation, that your use is for the sole purpose of 
+ -- programming logic devices manufactured by Altera and sold by 
+ -- Altera or its authorized distributors.  Please refer to the 
+ -- applicable agreement for further details.
+ -- 
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC            : No Connect. This pin has no internal connection to the device.
+ -- DNU           : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT        : Dedicated power pin, which MUST be connected to VCC  (1.2V).
+ -- VCCIO         : Dedicated power pin, which MUST be connected to VCC
+ --                 of its bank.
+ --					Bank 1:		3.3V
+ --					Bank 2:		3.3V
+ --					Bank 3:		3.3V
+ --					Bank 4:		3.3V
+ --					Bank 5:		3.3V
+ --					Bank 6:		3.3V
+ --					Bank 7:		3.3V
+ --					Bank 8:		3.3V
+ -- GND           : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ --					It can also be used to report unused dedicated pins. The connection
+ --					on the board for unused dedicated pins depends on whether this will
+ --					be used in a future design. One example is device migration. When
+ --					using device migration, refer to the device pin-tables. If it is a
+ --					GND pin in the pin table or if it will not be used in a future design
+ --					for another purpose the it MUST be connected to GND. If it is an unused
+ --					dedicated pin, then it can be connected to a valid signal on the board
+ --					(low, high, or toggling) if that signal is required for a different
+ --					revision of the design.
+ -- GND+          : Unused input pin. It can also be used to report unused dual-purpose pins.
+ --					This pin should be connected to GND. It may also be connected  to a
+ --					valid signal  on the board  (low, high, or toggling)  if that signal
+ --					is required for a different revision of the design.
+ -- GND*          : Unused  I/O  pin. Connect each pin marked GND* directly to GND
+ --           	    or leave it unconnected.
+ -- RESERVED      : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT    : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP    : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD       : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH        : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+CHIP  "DE0_D5M"  ASSIGNED TO AN: EP3C16F484C6
+
+Pin Name/Usage               : Location  : Dir.   : I/O Standard      : Voltage : I/O Bank  : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND                          : A1        : gnd    :                   :         :           :                
+VCCIO8                       : A2        : power  :                   : 3.3V    : 8         :                
+DRAM_ADDR[1]                 : A3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_1                    : A4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[4]                 : A5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[7]                 : A6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[11]                : A7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[8]                   : A8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[10]                  : A9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[13]                  : A10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : A11       :        :                   :         : 8         :                
+GND+                         : A12       :        :                   :         : 7         :                
+HEX1[0]                      : A13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[3]                      : A14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[6]                      : A15       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[1]                      : A16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[4]                      : A17       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18       :        :                   :         : 7         :                
+HEX3[2]                      : A19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : A20       :        :                   :         : 7         :                
+VCCIO7                       : A21       : power  :                   : 3.3V    : 7         :                
+GND                          : A22       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA1       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA2       :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5       :        :                   :         : 3         :                
+VCCIO3                       : AA6       : power  :                   : 3.3V    : 3         :                
+GPIO_1[16]                   : AA7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8       :        :                   :         : 3         :                
+GPIO_1[15]                   : AA9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[1]              : AA11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AA12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16      :        :                   :         : 4         :                
+GPIO_1[6]                    : AA17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[5]                    : AA18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[2]                    : AA19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[0]                    : AA20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21      :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22      :        :                   :         : 5         :                
+GND                          : AB1       : gnd    :                   :         :           :                
+VCCIO3                       : AB2       : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5       :        :                   :         : 3         :                
+GND                          : AB6       : gnd    :                   :         :           :                
+GPIO_1[17]                   : AB7       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8       :        :                   :         : 3         :                
+GPIO_1[14]                   : AB9       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10      :        :                   :         : 3         :                
+GPIO_1_CLKIN[0]              : AB11      : input  : 3.3-V LVTTL       :         : 3         : Y              
+GND+                         : AB12      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15      :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16      :        :                   :         : 4         :                
+GPIO_1[7]                    : AB17      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[4]                    : AB18      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[3]                    : AB19      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[1]                    : AB20      : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : AB21      : power  :                   : 3.3V    : 4         :                
+GND                          : AB22      : gnd    :                   :         :           :                
+LEDG[9]                      : B1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[8]                      : B2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[2]                 : B3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[10]                : B4        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_BA_0                    : B5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[6]                 : B6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[9]                 : B7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_UDQM                    : B8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[9]                   : B9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[12]                  : B10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND+                         : B11       :        :                   :         : 8         :                
+GND+                         : B12       :        :                   :         : 7         :                
+HEX1[1]                      : B13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX1[4]                      : B14       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B15       :        :                   :         : 7         :                
+HEX2[2]                      : B16       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[5]                      : B17       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[0]                      : B18       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[3]                      : B19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : B20       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22       :        :                   :         : 6         :                
+LEDG[6]                      : C1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[7]                      : C2        : output : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_ADDR[3]                 : C3        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[0]                 : C4        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C5        : gnd    :                   :         :           :                
+DRAM_ADDR[5]                 : C6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_ADDR[8]                 : C7        : output : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8        :        :                   :         : 8         :                
+GND                          : C9        : gnd    :                   :         :           :                
+DRAM_DQ[11]                  : C10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : C11       : gnd    :                   :         :           :                
+GND                          : C12       : gnd    :                   :         :           :                
+HEX1[2]                      : C13       : output : 3.3-V LVTTL       :         : 7         : Y              
+GND                          : C14       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15       :        :                   :         : 7         :                
+GND                          : C16       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17       :        :                   :         : 7         :                
+GND                          : C18       : gnd    :                   :         :           :                
+HEX3[4]                      : C19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22       :        :                   :         : 6         :                
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D1        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[9]                        : D2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : D3        : gnd    :                   :         :           :                
+VCCIO1                       : D4        : power  :                   : 3.3V    : 1         :                
+VCCIO8                       : D5        : power  :                   : 3.3V    : 8         :                
+DRAM_WE_N                    : D6        : output : 3.3-V LVTTL       :         : 8         : Y              
+GND                          : D7        : gnd    :                   :         :           :                
+GND                          : D8        : gnd    :                   :         :           :                
+VCCIO8                       : D9        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[0]                   : D10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : D11       : power  :                   : 3.3V    : 8         :                
+VCCIO7                       : D12       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13       :        :                   :         : 7         :                
+VCCIO7                       : D14       : power  :                   : 3.3V    : 7         :                
+HEX2[0]                      : D15       : output : 3.3-V LVTTL       :         : 7         : Y              
+VCCIO7                       : D16       : power  :                   : 3.3V    : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17       :        :                   :         : 7         :                
+VCCIO7                       : D18       : power  :                   : 3.3V    : 7         :                
+HEX3[5]                      : D19       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22       :        :                   :         : 6         :                
+LEDG[5]                      : E1        : output : 3.3-V LVTTL       :         : 1         : Y              
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2        : input  : 3.3-V LVTTL       :         : 1         : N              
+SW[7]                        : E3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[8]                        : E4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+DRAM_CLK                     : E5        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CKE                     : E6        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_LDQM                    : E7        : output : 3.3-V LVTTL       :         : 8         : Y              
+VCCIO8                       : E8        : power  :                   : 3.3V    : 8         :                
+DRAM_DQ[3]                   : E9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[14]                  : E10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[0]                      : E11       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E13       :        :                   :         : 7         :                
+HEX1[5]                      : E14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[3]                      : E15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : E16       :        :                   :         : 7         :                
+VCCD_PLL2                    : E17       : power  :                   : 1.2V    :           :                
+GNDA2                        : E18       : gnd    :                   :         :           :                
+VCCIO6                       : E19       : power  :                   : 3.3V    : 6         :                
+GND                          : E20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22       :        :                   :         : 6         :                
+KEY[2]                       : F1        : input  : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[4]                      : F2        : output : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : F3        : gnd    :                   :         :           :                
+VCCIO1                       : F4        : power  :                   : 3.3V    : 1         :                
+GNDA3                        : F5        : gnd    :                   :         :           :                
+VCCD_PLL3                    : F6        : power  :                   : 1.2V    :           :                
+DRAM_RAS_N                   : F7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[7]                   : F8        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[4]                   : F9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[15]                  : F10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+HEX0[1]                      : F11       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[5]                      : F12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[6]                      : F13       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX2[6]                      : F14       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX3[1]                      : F15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : F16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17       :        :                   :         : 6         :                
+VCCA2                        : F18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F19       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F20       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F21       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22       :        :                   :         : 6         :                
+GND+                         : G1        :        :                   :         : 1         :                
+GND+                         : G2        :        :                   :         : 1         :                
+KEY[1]                       : G3        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[3]                        : G4        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[4]                        : G5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCA3                        : G6        : power  :                   : 2.5V    :           :                
+DRAM_CS_N                    : G7        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_CAS_N                   : G8        : output : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[5]                   : G9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[1]                   : G10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11       :        :                   :         : 8         :                
+HEX0[4]                      : G12       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14       :        :                   :         : 7         :                
+HEX3[6]                      : G15       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18       :        :                   :         : 6         :                
+VCCIO6                       : G19       : power  :                   : 3.3V    : 6         :                
+GND                          : G20       : gnd    :                   :         :           :                
+CLOCK_50                     : G21       : input  : 3.3-V LVTTL       :         : 6         : Y              
+GND+                         : G22       :        :                   :         : 6         :                
+LEDG[3]                      : H1        : output : 3.3-V LVTTL       :         : 1         : Y              
+KEY[0]                       : H2        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H3        : gnd    :                   :         :           :                
+VCCIO1                       : H4        : power  :                   : 3.3V    : 1         :                
+SW[1]                        : H5        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[2]                        : H6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[6]                        : H7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+GND                          : H8        : gnd    :                   :         :           :                
+DRAM_DQ[6]                   : H9        : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+DRAM_DQ[2]                   : H10       : bidir  : 3.3-V LVTTL       :         : 8         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H11       :        :                   :         : 8         :                
+HEX0[2]                      : H12       : output : 3.3-V LVTTL       :         : 7         : Y              
+HEX0[3]                      : H13       : output : 3.3-V LVTTL       :         : 7         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15       :        :                   :         : 7         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16       :        :                   :         : 6         :                
+VGA_R[1]                     : H17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : H18       :        :                   :         : 6         :                
+VGA_R[0]                     : H19       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[2]                     : H20       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_R[3]                     : H21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_G[0]                     : H22       : output : 3.3-V LVTTL       :         : 6         : Y              
+LEDG[0]                      : J1        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[1]                      : J2        : output : 3.3-V LVTTL       :         : 1         : Y              
+LEDG[2]                      : J3        : output : 3.3-V LVTTL       :         : 1         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4        :        :                   :         : 1         :                
+GND                          : J5        : gnd    :                   :         :           :                
+SW[0]                        : J6        : input  : 3.3-V LVTTL       :         : 1         : Y              
+SW[5]                        : J7        : input  : 3.3-V LVTTL       :         : 1         : Y              
+VCCINT                       : J8        : power  :                   : 1.2V    :           :                
+GND                          : J9        : gnd    :                   :         :           :                
+VCCINT                       : J10       : power  :                   : 1.2V    :           :                
+VCCINT                       : J11       : power  :                   : 1.2V    :           :                
+VCCINT                       : J12       : power  :                   : 1.2V    :           :                
+VCCINT                       : J13       : power  :                   : 1.2V    :           :                
+VCCINT                       : J14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16       :        :                   :         : 6         :                
+VGA_G[1]                     : J17       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : J18       :        :                   :         : 6         :                
+GND                          : J19       : gnd    :                   :         :           :                
+VCCIO6                       : J20       : power  :                   : 3.3V    : 6         :                
+VGA_G[3]                     : J21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[2]                     : J22       : output : 3.3-V LVTTL       :         : 6         : Y              
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : K1        : input  : 3.3-V LVTTL       :         : 1         : N              
+~ALTERA_DCLK~                : K2        : output : 3.3-V LVTTL       :         : 1         : N              
+GND                          : K3        : gnd    :                   :         :           :                
+VCCIO1                       : K4        : power  :                   : 3.3V    : 1         :                
+nCONFIG                      : K5        :        :                   :         : 1         :                
+nSTATUS                      : K6        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7        :        :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8        :        :                   :         : 1         :                
+VCCINT                       : K9        : power  :                   : 1.2V    :           :                
+GND                          : K10       : gnd    :                   :         :           :                
+GND                          : K11       : gnd    :                   :         :           :                
+GND                          : K12       : gnd    :                   :         :           :                
+GND                          : K13       : gnd    :                   :         :           :                
+VCCINT                       : K14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : K16       :        :                   :         : 6         :                
+VGA_G[2]                     : K17       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[3]                     : K18       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : K19       :        :                   :         : 6         :                
+MSEL3                        : K20       :        :                   :         : 6         :                
+VGA_B[1]                     : K21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_B[0]                     : K22       : output : 3.3-V LVTTL       :         : 6         : Y              
+TMS                          : L1        : input  :                   :         : 1         :                
+TCK                          : L2        : input  :                   :         : 1         :                
+nCE                          : L3        :        :                   :         : 1         :                
+TDO                          : L4        : output :                   :         : 1         :                
+TDI                          : L5        : input  :                   :         : 1         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8        :        :                   :         : 1         :                
+VCCINT                       : L9        : power  :                   : 1.2V    :           :                
+GND                          : L10       : gnd    :                   :         :           :                
+GND                          : L11       : gnd    :                   :         :           :                
+GND                          : L12       : gnd    :                   :         :           :                
+GND                          : L13       : gnd    :                   :         :           :                
+VCCINT                       : L14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L15       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : L16       :        :                   :         : 6         :                
+MSEL2                        : L17       :        :                   :         : 6         :                
+MSEL1                        : L18       :        :                   :         : 6         :                
+VCCIO6                       : L19       : power  :                   : 3.3V    : 6         :                
+GND                          : L20       : gnd    :                   :         :           :                
+VGA_HS                       : L21       : output : 3.3-V LVTTL       :         : 6         : Y              
+VGA_VS                       : L22       : output : 3.3-V LVTTL       :         : 6         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8        :        :                   :         : 2         :                
+VCCINT                       : M9        : power  :                   : 1.2V    :           :                
+GND                          : M10       : gnd    :                   :         :           :                
+GND                          : M11       : gnd    :                   :         :           :                
+GND                          : M12       : gnd    :                   :         :           :                
+GND                          : M13       : gnd    :                   :         :           :                
+VCCINT                       : M14       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M16       :        :                   :         : 5         :                
+MSEL0                        : M17       :        :                   :         : 6         :                
+CONF_DONE                    : M18       :        :                   :         : 6         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : M22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N2        :        :                   :         : 2         :                
+GND                          : N3        : gnd    :                   :         :           :                
+VCCIO2                       : N4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8        :        :                   :         : 2         :                
+VCCINT                       : N9        : power  :                   : 1.2V    :           :                
+GND                          : N10       : gnd    :                   :         :           :                
+GND                          : N11       : gnd    :                   :         :           :                
+GND                          : N12       : gnd    :                   :         :           :                
+GND                          : N13       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : N22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P8        :        :                   :         : 2         :                
+VCCINT                       : P9        : power  :                   : 1.2V    :           :                
+VCCINT                       : P10       : power  :                   : 1.2V    :           :                
+VCCINT                       : P11       : power  :                   : 1.2V    :           :                
+VCCINT                       : P12       : power  :                   : 1.2V    :           :                
+VCCINT                       : P13       : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P14       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P15       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P16       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P17       :        :                   :         : 5         :                
+VCCIO5                       : P18       : power  :                   : 3.3V    : 5         :                
+GND                          : P19       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : P20       :        :                   :         : 5         :                
+PS2_DAT                      : P21       : bidir  : 3.3-V LVTTL       :         : 5         : Y              
+PS2_CLK                      : P22       : bidir  : 3.3-V LVTTL       :         : 5         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2        :        :                   :         : 2         :                
+GND                          : R3        : gnd    :                   :         :           :                
+VCCIO2                       : R4        : power  :                   : 3.3V    : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R8        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R10       :        :                   :         : 3         :                
+GPIO_1[22]                   : R11       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[23]                   : R12       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R13       :        :                   :         : 4         :                
+GPIO_1[19]                   : R14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R15       :        :                   :         : 4         :                
+GPIO_1_CLKOUT[0]             : R16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : R17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R18       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22       :        :                   :         : 5         :                
+GND+                         : T1        :        :                   :         : 2         :                
+GND+                         : T2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T5        :        :                   :         : 2         :                
+VCCA1                        : T6        : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8        :        :                   :         : 3         :                
+GPIO_1[27]                   : T9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[25]                   : T10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T11       :        :                   :         : 3         :                
+GPIO_1[21]                   : T12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : T13       : power  :                   : 1.2V    :           :                
+GPIO_1[18]                   : T14       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1[11]                   : T15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GPIO_1_CLKOUT[1]             : T16       : output : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : T17       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : T18       :        :                   :         : 5         :                
+VCCIO5                       : T19       : power  :                   : 3.3V    : 5         :                
+GND                          : T20       : gnd    :                   :         :           :                
+GND+                         : T21       :        :                   :         : 5         :                
+GND+                         : T22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2        :        :                   :         : 2         :                
+GND                          : U3        : gnd    :                   :         :           :                
+VCCIO2                       : U4        : power  :                   : 3.3V    : 2         :                
+GNDA1                        : U5        : gnd    :                   :         :           :                
+VCCD_PLL1                    : U6        : power  :                   : 1.2V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7        :        :                   :         : 3         :                
+GPIO_1[29]                   : U8        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[26]                   : U9        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[24]                   : U10       : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U11       :        :                   :         : 3         :                
+GPIO_1[20]                   : U12       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : U13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U14       :        :                   :         : 4         :                
+GPIO_1[10]                   : U15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCINT                       : U16       : power  :                   : 1.2V    :           :                
+VCCINT                       : U17       : power  :                   : 1.2V    :           :                
+VCCA4                        : U18       : power  :                   : 2.5V    :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5        :        :                   :         : 3         :                
+GPIO_1[30]                   : V6        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+GPIO_1[31]                   : V7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V9        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V10       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V11       :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V12       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V13       :        :                   :         : 4         :                
+VGA_CLK                      : V14       : output : 3.3-V LVTTL       :         : 4         : N              
+GPIO_1[13]                   : V15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : V16       :        :                   :         : 4         :                
+VCCD_PLL4                    : V17       : power  :                   : 1.2V    :           :                
+GNDA4                        : V18       : gnd    :                   :         :           :                
+VCCIO5                       : V19       : power  :                   : 3.3V    : 5         :                
+GND                          : V20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2        :        :                   :         : 2         :                
+GND                          : W3        : gnd    :                   :         :           :                
+VCCIO2                       : W4        : power  :                   : 3.3V    : 2         :                
+VCCIO3                       : W5        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W6        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8        :        :                   :         : 3         :                
+VCCIO3                       : W9        : power  :                   : 3.3V    : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W10       :        :                   :         : 3         :                
+VCCIO3                       : W11       : power  :                   : 3.3V    : 3         :                
+VCCIO4                       : W12       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W13       :        :                   :         : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W14       :        :                   :         : 4         :                
+GPIO_1[12]                   : W15       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W16       : power  :                   : 3.3V    : 4         :                
+GPIO_1[9]                    : W17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+VCCIO4                       : W18       : power  :                   : 3.3V    : 4         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W19       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W20       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y1        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y2        :        :                   :         : 2         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3        :        :                   :         : 3         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4        :        :                   :         : 3         :                
+GND                          : Y5        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6        :        :                   :         : 3         :                
+GPIO_1[28]                   : Y7        : bidir  : 3.3-V LVTTL       :         : 3         : Y              
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y8        :        :                   :         : 3         :                
+GND                          : Y9        : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10       :        :                   :         : 3         :                
+GND                          : Y11       : gnd    :                   :         :           :                
+GND                          : Y12       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13       :        :                   :         : 4         :                
+VCCIO4                       : Y14       : power  :                   : 3.3V    : 4         :                
+GND                          : Y15       : gnd    :                   :         :           :                
+GND                          : Y16       : gnd    :                   :         :           :                
+GPIO_1[8]                    : Y17       : bidir  : 3.3-V LVTTL       :         : 4         : Y              
+GND                          : Y18       : gnd    :                   :         :           :                
+VCCIO5                       : Y19       : power  :                   : 3.3V    : 5         :                
+GND                          : Y20       : gnd    :                   :         :           :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y21       :        :                   :         : 5         :                
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22       :        :                   :         : 5         :                
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
new file mode 100644
index 0000000..622e3fa
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.pof
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf
new file mode 100644
index 0000000..fad5fa0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "13.1"
+DATE = "14:14:24  April 30, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE0_D5M"
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf
new file mode 100644
index 0000000..4fc8ee8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf
@@ -0,0 +1,574 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_DE0_CAMERA_MOUSE
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+# mouse connected as keyboard ...
+set_location_assignment PIN_P22 -to PS2_CLK
+set_location_assignment PIN_P21 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+
+set_global_assignment -name VERILOG_FILE catapult_ip/blur3x3/rtl.v
+set_global_assignment -name VERILOG_FILE V/ps2.v
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name BDF_FILE V/TOP_DE0_CAMERA_MOUSE.bdf
+set_global_assignment -name QIP_FILE vga_mux.qip
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE catapult_ip/mouse/rtl.v
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak
new file mode 100644
index 0000000..8404697
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qsf.bak
@@ -0,0 +1,571 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		DE0_D5M_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16F484C6
+set_global_assignment -name TOP_LEVEL_ENTITY TOP_DE0_CAMERA_MOUSE
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:14:24  APRIL 30, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+
+
+
+#set_instance_assignment -name CLOCK_SETTINGS CLK50 -to CLOCK_50
+
+
+
+
+
+
+
+
+set_location_assignment PIN_V7 -to GPIO_1[31]
+set_location_assignment PIN_V6 -to GPIO_1[30]
+set_location_assignment PIN_U8 -to GPIO_1[29]
+set_location_assignment PIN_Y7 -to GPIO_1[28]
+set_location_assignment PIN_T9 -to GPIO_1[27]
+set_location_assignment PIN_U9 -to GPIO_1[26]
+set_location_assignment PIN_T10 -to GPIO_1[25]
+set_location_assignment PIN_U10 -to GPIO_1[24]
+set_location_assignment PIN_R12 -to GPIO_1[23]
+set_location_assignment PIN_R11 -to GPIO_1[22]
+set_location_assignment PIN_T12 -to GPIO_1[21]
+set_location_assignment PIN_U12 -to GPIO_1[20]
+set_location_assignment PIN_R14 -to GPIO_1[19]
+set_location_assignment PIN_T14 -to GPIO_1[18]
+set_location_assignment PIN_AB7 -to GPIO_1[17]
+set_location_assignment PIN_AA7 -to GPIO_1[16]
+set_location_assignment PIN_AA9 -to GPIO_1[15]
+set_location_assignment PIN_AB9 -to GPIO_1[14]
+set_location_assignment PIN_V15 -to GPIO_1[13]
+set_location_assignment PIN_W15 -to GPIO_1[12]
+set_location_assignment PIN_T15 -to GPIO_1[11]
+set_location_assignment PIN_U15 -to GPIO_1[10]
+set_location_assignment PIN_W17 -to GPIO_1[9]
+set_location_assignment PIN_Y17 -to GPIO_1[8]
+set_location_assignment PIN_AB17 -to GPIO_1[7]
+set_location_assignment PIN_AA17 -to GPIO_1[6]
+set_location_assignment PIN_AA18 -to GPIO_1[5]
+set_location_assignment PIN_AB18 -to GPIO_1[4]
+set_location_assignment PIN_AB19 -to GPIO_1[3]
+set_location_assignment PIN_AA19 -to GPIO_1[2]
+set_location_assignment PIN_AB20 -to GPIO_1[1]
+set_location_assignment PIN_AA20 -to GPIO_1[0]
+
+set_location_assignment PIN_AA11 -to GPIO_1_CLKIN[1]
+set_location_assignment PIN_AB11 -to GPIO_1_CLKIN[0]
+
+set_location_assignment PIN_T16 -to GPIO_1_CLKOUT[1]
+set_location_assignment PIN_R16 -to GPIO_1_CLKOUT[0]
+
+
+set_location_assignment PIN_D2 -to SW[9]
+set_location_assignment PIN_E4 -to SW[8]
+set_location_assignment PIN_E3 -to SW[7]
+set_location_assignment PIN_H7 -to SW[6]
+set_location_assignment PIN_J7 -to SW[5]
+set_location_assignment PIN_G5 -to SW[4]
+set_location_assignment PIN_G4 -to SW[3]
+set_location_assignment PIN_H6 -to SW[2]
+set_location_assignment PIN_H5 -to SW[1]
+set_location_assignment PIN_J6 -to SW[0]
+
+
+set_location_assignment PIN_H2 -to KEY[0]
+set_location_assignment PIN_G3 -to KEY[1]
+set_location_assignment PIN_F1 -to KEY[2]
+
+
+set_location_assignment PIN_B1 -to LEDG[9]
+set_location_assignment PIN_B2 -to LEDG[8]
+set_location_assignment PIN_C2 -to LEDG[7]
+set_location_assignment PIN_C1 -to LEDG[6]
+set_location_assignment PIN_E1 -to LEDG[5]
+set_location_assignment PIN_F2 -to LEDG[4]
+set_location_assignment PIN_H1 -to LEDG[3]
+set_location_assignment PIN_J3 -to LEDG[2]
+set_location_assignment PIN_J2 -to LEDG[1]
+set_location_assignment PIN_J1 -to LEDG[0]
+
+
+
+
+set_location_assignment PIN_E11 -to HEX0[0]
+set_location_assignment PIN_F11 -to HEX0[1]
+set_location_assignment PIN_H12 -to HEX0[2]
+set_location_assignment PIN_H13 -to HEX0[3]
+set_location_assignment PIN_G12 -to HEX0[4]
+set_location_assignment PIN_F12 -to HEX0[5]
+set_location_assignment PIN_F13 -to HEX0[6]
+set_location_assignment PIN_D13 -to HEX0_DP
+
+set_location_assignment PIN_A15 -to HEX1[6]
+set_location_assignment PIN_E14 -to HEX1[5]
+set_location_assignment PIN_B14 -to HEX1[4]
+set_location_assignment PIN_A14 -to HEX1[3]
+set_location_assignment PIN_C13 -to HEX1[2]
+set_location_assignment PIN_B13 -to HEX1[1]
+set_location_assignment PIN_A13 -to HEX1[0]
+set_location_assignment PIN_B15 -to HEX1_DP
+
+set_location_assignment PIN_F14 -to HEX2[6]
+set_location_assignment PIN_B17 -to HEX2[5]
+set_location_assignment PIN_A17 -to HEX2[4]
+set_location_assignment PIN_E15 -to HEX2[3]
+set_location_assignment PIN_B16 -to HEX2[2]
+set_location_assignment PIN_A16 -to HEX2[1]
+set_location_assignment PIN_D15 -to HEX2[0]
+set_location_assignment PIN_A18 -to HEX2_DP
+
+set_location_assignment PIN_G15 -to HEX3[6]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_C19 -to HEX3[4]
+set_location_assignment PIN_B19 -to HEX3[3]
+set_location_assignment PIN_A19 -to HEX3[2]
+set_location_assignment PIN_F15 -to HEX3[1]
+set_location_assignment PIN_B18 -to HEX3[0]
+set_location_assignment PIN_G16 -to HEX3_DP
+
+
+
+set_location_assignment PIN_G21 -to CLOCK_50
+
+set_location_assignment PIN_R21 -to PS2_CLK
+set_location_assignment PIN_R22 -to PS2_DAT
+
+#set_location_assignment PIN_F14 -to UART_RXD
+#set_location_assignment PIN_G12 -to UART_TXD
+
+set_location_assignment PIN_J21 -to VGA_G[3]
+set_location_assignment PIN_K17 -to VGA_G[2]
+set_location_assignment PIN_J17 -to VGA_G[1]
+set_location_assignment PIN_H22 -to VGA_G[0]
+set_location_assignment PIN_L21 -to VGA_HS
+set_location_assignment PIN_L22 -to VGA_VS
+set_location_assignment PIN_H21 -to VGA_R[3]
+set_location_assignment PIN_H20 -to VGA_R[2]
+set_location_assignment PIN_H17 -to VGA_R[1]
+set_location_assignment PIN_H19 -to VGA_R[0]
+set_location_assignment PIN_K18 -to VGA_B[3]
+set_location_assignment PIN_J22 -to VGA_B[2]
+set_location_assignment PIN_K21 -to VGA_B[1]
+set_location_assignment PIN_K22 -to VGA_B[0]
+
+set_location_assignment PIN_G7 -to DRAM_CS_N
+set_location_assignment PIN_E5 -to DRAM_CLK
+set_location_assignment PIN_E6 -to DRAM_CKE
+set_location_assignment PIN_B5 -to DRAM_BA_0
+set_location_assignment PIN_A4 -to DRAM_BA_1
+set_location_assignment PIN_E7 -to DRAM_LDQM
+set_location_assignment PIN_B8 -to DRAM_UDQM
+set_location_assignment PIN_F7 -to DRAM_RAS_N
+set_location_assignment PIN_G8 -to DRAM_CAS_N
+set_location_assignment PIN_D6 -to DRAM_WE_N
+
+set_location_assignment PIN_F10 -to DRAM_DQ[15]
+set_location_assignment PIN_E10 -to DRAM_DQ[14]
+set_location_assignment PIN_A10 -to DRAM_DQ[13]
+set_location_assignment PIN_B10 -to DRAM_DQ[12]
+set_location_assignment PIN_C10 -to DRAM_DQ[11]
+set_location_assignment PIN_A9 -to DRAM_DQ[10]
+set_location_assignment PIN_B9 -to DRAM_DQ[9]
+set_location_assignment PIN_A8 -to DRAM_DQ[8]
+set_location_assignment PIN_F8 -to DRAM_DQ[7]
+set_location_assignment PIN_H9 -to DRAM_DQ[6]
+set_location_assignment PIN_G9 -to DRAM_DQ[5]
+set_location_assignment PIN_F9 -to DRAM_DQ[4]
+set_location_assignment PIN_E9 -to DRAM_DQ[3]
+set_location_assignment PIN_H10 -to DRAM_DQ[2]
+set_location_assignment PIN_G10 -to DRAM_DQ[1]
+set_location_assignment PIN_D10 -to DRAM_DQ[0]
+
+set_location_assignment PIN_C8 -to DRAM_ADDR[12]
+set_location_assignment PIN_A7 -to DRAM_ADDR[11]
+set_location_assignment PIN_B4 -to DRAM_ADDR[10]
+set_location_assignment PIN_B7 -to DRAM_ADDR[9]
+set_location_assignment PIN_C7 -to DRAM_ADDR[8]
+set_location_assignment PIN_A6 -to DRAM_ADDR[7]
+set_location_assignment PIN_B6 -to DRAM_ADDR[6]
+set_location_assignment PIN_C6 -to DRAM_ADDR[5]
+set_location_assignment PIN_A5 -to DRAM_ADDR[4]
+set_location_assignment PIN_C3 -to DRAM_ADDR[3]
+set_location_assignment PIN_B3 -to DRAM_ADDR[2]
+set_location_assignment PIN_A3 -to DRAM_ADDR[1]
+set_location_assignment PIN_C4 -to DRAM_ADDR[0]
+
+
+set_location_assignment PIN_B12 -to CLOCK_50_2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
+
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl_mgc_ioport_v2001.v
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl_mgc_ioport.v
+set_global_assignment -name VERILOG_FILE catapult_ip/rtl.v
+set_global_assignment -name VERILOG_FILE V/ps2.v
+set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
+set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_FIFO.v
+set_global_assignment -name SOURCE_FILE V/VGA_Param.h
+set_global_assignment -name VERILOG_FILE V/async_receiver.v
+set_global_assignment -name VERILOG_FILE V/CCD_Capture.v
+set_global_assignment -name VERILOG_FILE V/I2C_CCD_Config.v
+set_global_assignment -name VERILOG_FILE V/I2C_Controller.v
+set_global_assignment -name VERILOG_FILE V/Line_Buffer.v
+set_global_assignment -name VERILOG_FILE V/RAW2RGB.v
+set_global_assignment -name VERILOG_FILE V/Reset_Delay.v
+set_global_assignment -name VERILOG_FILE V/sdram_pll.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE V/SEG7_LUT_8.v
+set_global_assignment -name VERILOG_FILE V/VGA_Controller.v
+set_global_assignment -name VERILOG_FILE DE0_D5M.v
+set_global_assignment -name SDC_FILE DE0_D5M.sdc
+set_global_assignment -name BDF_FILE V/TOP_DE0_CAMERA_MOUSE.bdf
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_DATA"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|Pre_FVAL"
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to "CCD_Capture:u3|mCCD_LVAL"
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_DATA
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_FVAL
+set_instance_assignment -name TSU_REQUIREMENT "4 ns" -from * -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_DATA
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_LVAL
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to rCCD_FVAL
+set_instance_assignment -name CLOCK_SETTINGS CCD_PIXCLK -to GPIO_1_CLKIN[0]
+set_instance_assignment -name CLOCK_SETTINGS CCD_MCLK -to GPIO_1_CLKOUT[0]
+set_instance_assignment -name TCO_REQUIREMENT "1 ns" -from * -to DRAM_DQ
+set_instance_assignment -name TSU_REQUIREMENT "1 ns" -from DRAM_DQ -to *
+
+
+
+
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BUTTON[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_BYTE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKOUT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_CLKIN[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ15_AM1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_DP
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_KBCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws
new file mode 100644
index 0000000..63563b7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.qws
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc
new file mode 100644
index 0000000..6a9d418
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sdc
@@ -0,0 +1,41 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 10.0 Build 218 06/27/2010 SJ Full Version
+#
+#************************************************************
+
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "CLOCK_50" -period 20ns [get_ports {CLOCK_50}] -waveform {0.000ns 10.000ns}
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+#derive_clock_uncertainty
+# Not supported for family Cyclone II
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
new file mode 100644
index 0000000..340cc84
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sof
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt
new file mode 100644
index 0000000..87ac1ea
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.rpt
@@ -0,0 +1,10440 @@
+TimeQuest Timing Analyzer report for DE0_D5M
+Mon Mar 17 11:17:31 2014
+Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+  1. Legal Notice
+  2. TimeQuest Timing Analyzer Summary
+  3. Parallel Compilation
+  4. SDC File List
+  5. Clocks
+  6. Slow 1200mV 85C Model Fmax Summary
+  7. Timing Closure Recommendations
+  8. Slow 1200mV 85C Model Setup Summary
+  9. Slow 1200mV 85C Model Hold Summary
+ 10. Slow 1200mV 85C Model Recovery Summary
+ 11. Slow 1200mV 85C Model Removal Summary
+ 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 13. Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'
+ 15. Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 16. Slow 1200mV 85C Model Hold: 'CLOCK_50'
+ 17. Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 18. Slow 1200mV 85C Model Recovery: 'CLOCK_50'
+ 19. Slow 1200mV 85C Model Removal: 'CLOCK_50'
+ 20. Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 22. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'
+ 23. Setup Times
+ 24. Hold Times
+ 25. Clock to Output Times
+ 26. Minimum Clock to Output Times
+ 27. Propagation Delay
+ 28. Minimum Propagation Delay
+ 29. Output Enable Times
+ 30. Minimum Output Enable Times
+ 31. Output Disable Times
+ 32. Minimum Output Disable Times
+ 33. MTBF Summary
+ 34. Synchronizer Summary
+ 35. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+ 36. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+ 37. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+ 38. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+ 39. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+ 40. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+ 41. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+ 42. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+ 43. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+ 44. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+ 45. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+ 46. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+ 47. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+ 48. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+ 49. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+ 50. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+ 51. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+ 52. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+ 53. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+ 54. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+ 55. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+ 56. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+ 57. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+ 58. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+ 59. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+ 60. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+ 61. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+ 62. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+ 63. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+ 64. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+ 65. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+ 66. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+ 67. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+ 68. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+ 69. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+ 70. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+ 71. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+ 72. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+ 73. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+ 74. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+ 75. Slow 1200mV 0C Model Fmax Summary
+ 76. Slow 1200mV 0C Model Setup Summary
+ 77. Slow 1200mV 0C Model Hold Summary
+ 78. Slow 1200mV 0C Model Recovery Summary
+ 79. Slow 1200mV 0C Model Removal Summary
+ 80. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 81. Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 82. Slow 1200mV 0C Model Setup: 'CLOCK_50'
+ 83. Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 84. Slow 1200mV 0C Model Hold: 'CLOCK_50'
+ 85. Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 86. Slow 1200mV 0C Model Recovery: 'CLOCK_50'
+ 87. Slow 1200mV 0C Model Removal: 'CLOCK_50'
+ 88. Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 89. Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+ 90. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+ 91. Setup Times
+ 92. Hold Times
+ 93. Clock to Output Times
+ 94. Minimum Clock to Output Times
+ 95. Propagation Delay
+ 96. Minimum Propagation Delay
+ 97. Output Enable Times
+ 98. Minimum Output Enable Times
+ 99. Output Disable Times
+100. Minimum Output Disable Times
+101. MTBF Summary
+102. Synchronizer Summary
+103. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+104. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+105. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+106. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+107. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+108. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+109. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+110. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+111. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+112. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+113. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+114. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+115. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+116. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+117. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+118. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+119. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+120. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+121. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+122. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+123. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+124. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+125. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+126. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+127. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+128. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+129. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+130. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+131. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+132. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+133. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+134. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+135. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+136. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+137. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+138. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+139. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+140. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+141. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+142. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+143. Fast 1200mV 0C Model Setup Summary
+144. Fast 1200mV 0C Model Hold Summary
+145. Fast 1200mV 0C Model Recovery Summary
+146. Fast 1200mV 0C Model Removal Summary
+147. Fast 1200mV 0C Model Minimum Pulse Width Summary
+148. Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+149. Fast 1200mV 0C Model Setup: 'CLOCK_50'
+150. Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+151. Fast 1200mV 0C Model Hold: 'CLOCK_50'
+152. Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+153. Fast 1200mV 0C Model Recovery: 'CLOCK_50'
+154. Fast 1200mV 0C Model Removal: 'CLOCK_50'
+155. Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+156. Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+157. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'
+158. Setup Times
+159. Hold Times
+160. Clock to Output Times
+161. Minimum Clock to Output Times
+162. Propagation Delay
+163. Minimum Propagation Delay
+164. Output Enable Times
+165. Minimum Output Enable Times
+166. Output Disable Times
+167. Minimum Output Disable Times
+168. MTBF Summary
+169. Synchronizer Summary
+170. Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+171. Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+172. Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+173. Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+174. Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+175. Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+176. Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+177. Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+178. Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+179. Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+180. Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+181. Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+182. Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+183. Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+184. Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+185. Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+186. Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+187. Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+188. Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+189. Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+190. Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+191. Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+192. Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+193. Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+194. Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+195. Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+196. Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+197. Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+198. Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+199. Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+200. Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+201. Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+202. Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+203. Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+204. Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+205. Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+206. Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+207. Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+208. Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+209. Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+210. Multicorner Timing Analysis Summary
+211. Setup Times
+212. Hold Times
+213. Clock to Output Times
+214. Minimum Clock to Output Times
+215. Propagation Delay
+216. Minimum Propagation Delay
+217. Board Trace Model Assignments
+218. Input Transition Times
+219. Slow Corner Signal Integrity Metrics
+220. Fast Corner Signal Integrity Metrics
+221. Setup Transfers
+222. Hold Transfers
+223. Recovery Transfers
+224. Removal Transfers
+225. Report TCCS
+226. Report RSKM
+227. Unconstrained Paths
+228. TimeQuest Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+
+
+
++--------------------------------------------------------------------------+
+; TimeQuest Timing Analyzer Summary                                        ;
++--------------------+-----------------------------------------------------+
+; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Full Version ;
+; Revision Name      ; DE0_D5M                                             ;
+; Device Family      ; Cyclone III                                         ;
+; Device Name        ; EP3C16F484C6                                        ;
+; Timing Models      ; Final                                               ;
+; Delay Model        ; Combined                                            ;
+; Rise/Fall Delays   ; Enabled                                             ;
++--------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation                     ;
++----------------------------+-------------+
+; Processors                 ; Number      ;
++----------------------------+-------------+
+; Number detected on machine ; 8           ;
+; Maximum allowed            ; 4           ;
+;                            ;             ;
+; Average used               ; 1.00        ;
+; Maximum used               ; 4           ;
+;                            ;             ;
+; Usage by Processor         ; % Time Used ;
+;     Processor 1            ; 100.0%      ;
+;     Processors 2-4         ; < 0.1%      ;
+;     Processors 5-8         ;   0.0%      ;
++----------------------------+-------------+
+
+
++---------------------------------------------------+
+; SDC File List                                     ;
++---------------+--------+--------------------------+
+; SDC File Path ; Status ; Read at                  ;
++---------------+--------+--------------------------+
+; DE0_D5M.sdc   ; OK     ; Mon Mar 17 11:17:29 2014 ;
++---------------+--------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks                                                                                                                                                                                                                                                                                                                           ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; Clock Name                                          ; Type      ; Period ; Frequency ; Rise   ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase  ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                 ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+; CLOCK_50                                            ; Base      ; 20.000 ; 50.0 MHz  ; 0.000  ; 10.000 ;            ;           ;             ;        ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                            ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8.000  ; 125.0 MHz ; 0.000  ; 4.000  ; 50.00      ; 2         ; 5           ;        ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[0] } ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.000  ; 125.0 MHz ; -2.600 ; 1.400  ; 50.00      ; 2         ; 5           ; -117.0 ;        ;           ;            ; false    ; CLOCK_50 ; inst|u6|altpll_component|auto_generated|pll1|inclk[0] ; { inst|u6|altpll_component|auto_generated|pll1|clk[1] } ;
++-----------------------------------------------------+-----------+--------+-----------+--------+--------+------------+-----------+-------------+--------+--------+-----------+------------+----------+----------+-------------------------------------------------------+---------------------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Fmax Summary                                                        ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 174.31 MHz ; 174.31 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 192.01 MHz ; 192.01 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup Summary                                          ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.490 ; -24.984       ;
+; CLOCK_50                                            ; 14.792 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold Summary                                          ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.332 ; 0.000         ;
+; CLOCK_50                                            ; 0.358 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery Summary                                       ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -1.484 ; -348.952      ;
+; CLOCK_50                                            ; 14.000 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal Summary                                       ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.548 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.100 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.733 ; 0.000         ;
+; CLOCK_50                                            ; 9.580 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.490 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.298      ;
+; -0.490 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.298      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.452 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.545     ; 1.922      ;
+; -0.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.235      ;
+; -0.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.207     ; 2.235      ;
+; -0.384 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.217     ; 2.182      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.381 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.209      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.344 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.187     ; 2.172      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.215 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.211     ; 2.019      ;
+; -0.151 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 1.963      ;
+; -0.151 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 1.963      ;
+; -0.151 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.203     ; 1.963      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.186     ; 1.972      ;
+; -0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.176     ; 1.924      ;
+; -0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.176     ; 1.924      ;
+; -0.085 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.176     ; 1.924      ;
+; -0.059 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 1.858      ;
+; -0.059 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 1.858      ;
+; -0.059 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.216     ; 1.858      ;
+; 2.263  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.652      ;
+; 2.263  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.652      ;
+; 2.263  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.291      ; 6.043      ;
+; 2.269  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 6.006      ;
+; 2.269  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 6.006      ;
+; 2.276  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.290      ; 6.029      ;
+; 2.326  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.589      ;
+; 2.326  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.589      ;
+; 2.332  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 5.943      ;
+; 2.332  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.260      ; 5.943      ;
+; 2.334  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.581      ;
+; 2.334  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.581      ;
+; 2.357  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.099     ; 5.559      ;
+; 2.357  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.099     ; 5.559      ;
+; 2.369  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.110     ; 5.536      ;
+; 2.372  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.291      ; 5.934      ;
+; 2.375  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.250      ; 5.890      ;
+; 2.382  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.533      ;
+; 2.382  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.100     ; 5.533      ;
++--------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                          ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.792 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.149      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.801 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.140      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.897 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.044      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.936 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.073     ; 5.006      ;
+; 14.941 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 5.000      ;
+; 14.950 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.074     ; 4.991      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.977 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.976      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 14.980 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.062     ; 4.973      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
+; 15.017 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.059     ; 4.939      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.332 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.914      ;
+; 0.341 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.378      ; 0.906      ;
+; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.577      ;
+; 0.343 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.577      ;
+; 0.344 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.378      ; 0.910      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.345 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.346 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 0.577      ;
+; 0.348 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.374      ; 0.909      ;
+; 0.357 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.590      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.592      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.359 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.577      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.594      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.360 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.593      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.593      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.593      ;
+; 0.361 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.594      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.595      ;
+; 0.362 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 0.594      ;
+; 0.371 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.425      ; 0.953      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.590      ;
+; 0.372 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.590      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.373 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[15]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[17]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 0.608      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.592      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.593      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.608      ;
+; 0.375 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.594      ;
+; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.609      ;
+; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 0.594      ;
+; 0.376 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.595      ;
+; 0.377 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 0.610      ;
+; 0.378 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.597      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Hold: 'CLOCK_50'                                                                                                                                                      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.358 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.577      ;
+; 0.361 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.361 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.580      ;
+; 0.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
+; 0.374 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.593      ;
+; 0.382 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.577      ;
+; 0.385 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.580      ;
+; 0.389 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.608      ;
+; 0.390 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.609      ;
+; 0.434 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.038      ; 0.629      ;
+; 0.523 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.742      ;
+; 0.550 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.769      ;
+; 0.551 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.769      ;
+; 0.551 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.770      ;
+; 0.552 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.771      ;
+; 0.553 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.772      ;
+; 0.555 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.774      ;
+; 0.555 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.774      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.775      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.557 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.776      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.558 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.777      ;
+; 0.559 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.778      ;
+; 0.559 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.778      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.560 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.779      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.561 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.780      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.562 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.781      ;
+; 0.563 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.782      ;
+; 0.564 ; ps2:inst6|clk_div[1]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.783      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.569 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.788      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.570 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.789      ;
+; 0.571 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.571 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.790      ;
+; 0.572 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.572 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.791      ;
+; 0.573 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.792      ;
+; 0.574 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.792      ;
+; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.574 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.575 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.061      ; 0.793      ;
+; 0.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.800      ;
+; 0.586 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.805      ;
+; 0.587 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.806      ;
+; 0.587 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.806      ;
+; 0.589 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.808      ;
+; 0.590 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.809      ;
+; 0.592 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.811      ;
+; 0.697 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.062      ; 0.916      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.484 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.296     ; 3.137      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.474 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.288     ; 3.135      ;
+; -1.424 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.293     ; 3.179      ;
+; -1.414 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.285     ; 3.177      ;
+; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.544     ; 2.804      ;
+; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.544     ; 2.804      ;
+; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.544     ; 2.804      ;
+; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.544     ; 2.804      ;
+; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.544     ; 2.804      ;
+; -1.333 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.544     ; 2.804      ;
+; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.804      ;
+; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.804      ;
+; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.804      ;
+; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.804      ;
+; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.804      ;
+; -1.332 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.543     ; 2.804      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.781      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.781      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.781      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.781      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.551     ; 2.781      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.317 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.549     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.548     ; 2.783      ;
+; -1.316 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.550     ; 2.781      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.787      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.787      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.787      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.787      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.539     ; 2.786      ;
+; -1.310 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.537     ; 2.788      ;
+; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.786      ;
+; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.786      ;
+; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.786      ;
+; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.786      ;
+; -1.309 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.538     ; 2.786      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Recovery: 'CLOCK_50'                                                                                                                                    ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.000 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 5.213      ;
+; 14.009 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 5.204      ;
+; 14.105 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 5.108      ;
+; 14.144 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 5.070      ;
+; 14.243 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.970      ;
+; 14.287 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.927      ;
+; 14.289 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.925      ;
+; 14.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.917      ;
+; 14.384 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.830      ;
+; 14.392 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.822      ;
+; 14.523 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.691      ;
+; 14.524 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.690      ;
+; 14.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.683      ;
+; 14.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.682      ;
+; 14.629 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.585      ;
+; 14.766 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.801     ; 4.448      ;
+; 14.836 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.377      ;
+; 14.979 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.234      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.020 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.931      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.029 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.922      ;
+; 15.041 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.172      ;
+; 15.050 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.163      ;
+; 15.090 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.123      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.125 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.826      ;
+; 15.142 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.071      ;
+; 15.146 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.802     ; 4.067      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.164 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.063     ; 4.788      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
+; 15.263 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.064     ; 4.688      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'CLOCK_50'                                                                                                                                                   ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.548 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.765      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 1.764 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.060      ; 1.981      ;
+; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.412      ;
+; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.412      ;
+; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.412      ;
+; 2.181 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.412      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.201 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.074      ; 2.432      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.263 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.075      ; 2.495      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.486 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.063      ; 2.706      ;
+; 2.550 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.664     ; 2.043      ;
+; 2.758 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.664     ; 2.251      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 2.969 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.072      ; 3.198      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
+; 3.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.059      ; 3.339      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 4.100 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.671     ; 2.586      ;
+; 4.100 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.671     ; 2.586      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.118 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.680     ; 2.595      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.692     ; 2.589      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.124 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.690     ; 2.591      ;
+; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.593      ;
+; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.593      ;
+; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.593      ;
+; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.593      ;
+; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.593      ;
+; 4.127 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.691     ; 2.593      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.128 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.689     ; 2.596      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.129 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.696     ; 2.590      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.137 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.686     ; 2.608      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.592      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.592      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.592      ;
+; 4.138 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.703     ; 2.592      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.707     ; 2.595      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.707     ; 2.595      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.707     ; 2.595      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.707     ; 2.595      ;
+; 4.145 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.707     ; 2.595      ;
+; 4.147 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.694     ; 2.610      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.149 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.700     ; 2.606      ;
+; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.701     ; 2.606      ;
+; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.701     ; 2.606      ;
+; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.701     ; 2.606      ;
+; 4.150 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.701     ; 2.606      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.733 ; 3.963        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.733 ; 3.963        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.733 ; 3.963        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.734 ; 3.964        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.734 ; 3.964        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.734 ; 3.964        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.745 ; 3.975        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.747 ; 3.977        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[12]                                                                                                                          ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22]                                                                                                                         ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]                                                                                                                          ;
+; 3.755 ; 3.971        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]                                                                                                                          ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; 3.756 ; 3.972        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'                                                                                   ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ;
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                  ;
+; 9.580 ; 9.764        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[8]                                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.592 ; 9.776        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                    ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.593 ; 9.777        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.162 ; 4.886 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.162 ; 4.886 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 4.039 ; 4.609 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.195 ; 4.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.989 ; 4.558 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.703 ; 4.276 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.849 ; 4.364 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.867 ; 4.442 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 4.195 ; 4.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.689 ; 4.201 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.971 ; 4.530 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.696 ; 4.203 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.713 ; 4.224 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.663 ; 4.241 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.721 ; 4.230 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.722 ; 4.233 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.874 ; 4.393 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.710 ; 4.224 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.905 ; 4.446 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -2.087 ; -2.671 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -2.090 ; -2.682 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -2.087 ; -2.671 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.958 ; -3.503 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -3.298 ; -3.846 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -2.998 ; -3.549 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -3.175 ; -3.681 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -3.167 ; -3.731 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -3.470 ; -4.011 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -3.010 ; -3.503 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -3.282 ; -3.820 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -3.017 ; -3.504 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -3.034 ; -3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.958 ; -3.514 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -3.042 ; -3.533 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -3.042 ; -3.534 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -3.201 ; -3.711 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -3.031 ; -3.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -3.218 ; -3.738 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.431  ; 6.267  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.284  ; 6.232  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.431  ; 6.267  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.650  ; 5.688  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.650  ; 5.688  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.538  ; 5.554  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.411  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.411  ; 3.281  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.406  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.385  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.389  ; 3.280  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.195  ; 3.089  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.177  ; 3.073  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.996  ; 2.898  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.010  ; 2.913  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.001  ; 2.902  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.997  ; 2.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.250  ; 3.155  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.988  ; 2.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.075  ; 2.992  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.238  ; 3.151  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.180  ; 3.078  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.582  ; 3.529  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.477  ; 7.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.872  ; 5.694  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.872  ; 5.846  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.578  ; 5.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.477  ; 7.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.679  ; 5.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.894  ; 5.773  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.858  ; 5.642  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.792  ; 5.739  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.729  ; 5.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.790  ; 5.709  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.922  ; 5.821  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.990  ; 5.797  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 6.015  ; 5.897  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.995  ; 5.873  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 5.870  ; 5.693  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.824  ; 5.740  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.439  ; 3.316  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.393  ; 3.282  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.336  ; 3.248  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.226  ; 4.902  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.575 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.703 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.133  ; 6.078  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.133  ; 6.078  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.275  ; 6.112  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.525  ; 5.556  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.525  ; 5.556  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.412  ; 5.432  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.568  ; 2.474  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.975  ; 2.845  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.971  ; 2.863  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.950  ; 2.837  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.953  ; 2.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.769  ; 2.661  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.749  ; 2.645  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.577  ; 2.478  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.590  ; 2.492  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.580  ; 2.481  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.577  ; 2.481  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.820  ; 2.723  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.568  ; 2.474  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.651  ; 2.567  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.808  ; 2.720  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.751  ; 2.648  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.137  ; 3.081  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.606  ; 3.480  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.606  ; 3.480  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.421  ; 4.387  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.079  ; 4.021  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.955  ; 5.620  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.156  ; 4.053  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.296  ; 4.214  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.136  ; 4.032  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.323  ; 4.259  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.944  ; 3.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.982  ; 3.895  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.106  ; 3.999  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.999  ; 3.903  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.434  ; 4.307  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.200  ; 4.075  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.878  ; 3.761  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 4.004  ; 3.940  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.000  ; 2.878  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.956  ; 2.844  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.901  ; 2.812  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 4.796  ; 4.472  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.948 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.075 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++------------------------------------------------------------+
+; Propagation Delay                                          ;
++------------+-------------+-------+-------+--------+--------+
+; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
++------------+-------------+-------+-------+--------+--------+
+; SW[4]      ; VGA_B[0]    ; 8.598 ; 8.436 ; 9.243  ; 9.072  ;
+; SW[4]      ; VGA_B[1]    ; 8.447 ; 8.325 ; 9.042  ; 8.914  ;
+; SW[4]      ; VGA_B[2]    ; 8.575 ; 8.414 ; 9.221  ; 9.051  ;
+; SW[4]      ; VGA_B[3]    ; 8.667 ; 8.584 ; 9.283  ; 9.242  ;
+; SW[4]      ; VGA_G[0]    ; 8.652 ; 8.475 ; 9.234  ; 9.066  ;
+; SW[4]      ; VGA_G[1]    ; 9.016 ; 8.875 ; 9.652  ; 9.511  ;
+; SW[4]      ; VGA_G[2]    ; 8.756 ; 8.632 ; 9.342  ; 9.227  ;
+; SW[4]      ; VGA_G[3]    ; 9.210 ; 9.093 ; 9.844  ; 9.730  ;
+; SW[4]      ; VGA_R[0]    ; 8.916 ; 8.791 ; 9.563  ; 9.429  ;
+; SW[4]      ; VGA_R[1]    ; 9.140 ; 9.076 ; 9.701  ; 9.628  ;
+; SW[4]      ; VGA_R[2]    ; 8.626 ; 8.470 ; 9.215  ; 9.063  ;
+; SW[4]      ; VGA_R[3]    ; 8.836 ; 8.685 ; 9.435  ; 9.279  ;
+; SW[5]      ; VGA_B[0]    ; 8.150 ; 7.979 ; 8.767  ; 8.596  ;
+; SW[5]      ; VGA_B[1]    ; 8.882 ; 8.754 ; 9.475  ; 9.347  ;
+; SW[5]      ; VGA_B[2]    ; 8.247 ; 8.086 ; 8.912  ; 8.742  ;
+; SW[5]      ; VGA_B[3]    ; 9.227 ; 9.142 ; 9.829  ; 9.788  ;
+; SW[5]      ; VGA_G[0]    ; 8.549 ; 8.372 ; 9.098  ; 8.924  ;
+; SW[5]      ; VGA_G[1]    ; 9.002 ; 8.861 ; 9.616  ; 9.475  ;
+; SW[5]      ; VGA_G[2]    ; 8.653 ; 8.529 ; 9.203  ; 9.084  ;
+; SW[5]      ; VGA_G[3]    ; 9.192 ; 9.078 ; 9.808  ; 9.694  ;
+; SW[5]      ; VGA_R[0]    ; 8.583 ; 8.458 ; 9.256  ; 9.122  ;
+; SW[5]      ; VGA_R[1]    ; 9.959 ; 9.909 ; 10.554 ; 10.517 ;
+; SW[5]      ; VGA_R[2]    ; 8.412 ; 8.256 ; 9.035  ; 8.879  ;
+; SW[5]      ; VGA_R[3]    ; 9.269 ; 9.113 ; 9.869  ; 9.713  ;
++------------+-------------+-------+-------+--------+--------+
+
+
++------------------------------------------------------------+
+; Minimum Propagation Delay                                  ;
++------------+-------------+-------+-------+--------+--------+
+; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
++------------+-------------+-------+-------+--------+--------+
+; SW[4]      ; VGA_B[0]    ; 8.318 ; 8.157 ; 8.906  ; 8.740  ;
+; SW[4]      ; VGA_B[1]    ; 7.917 ; 7.781 ; 8.472  ; 8.379  ;
+; SW[4]      ; VGA_B[2]    ; 8.296 ; 8.135 ; 8.886  ; 8.725  ;
+; SW[4]      ; VGA_B[3]    ; 7.775 ; 7.655 ; 8.329  ; 8.241  ;
+; SW[4]      ; VGA_G[0]    ; 8.311 ; 8.144 ; 8.924  ; 8.748  ;
+; SW[4]      ; VGA_G[1]    ; 8.317 ; 8.168 ; 8.884  ; 8.778  ;
+; SW[4]      ; VGA_G[2]    ; 8.411 ; 8.294 ; 9.025  ; 8.899  ;
+; SW[4]      ; VGA_G[3]    ; 8.009 ; 7.899 ; 8.621  ; 8.452  ;
+; SW[4]      ; VGA_R[0]    ; 8.621 ; 8.496 ; 9.214  ; 9.089  ;
+; SW[4]      ; VGA_R[1]    ; 8.479 ; 8.359 ; 9.031  ; 8.943  ;
+; SW[4]      ; VGA_R[2]    ; 8.381 ; 8.235 ; 8.964  ; 8.813  ;
+; SW[4]      ; VGA_R[3]    ; 8.287 ; 8.124 ; 8.846  ; 8.726  ;
+; SW[5]      ; VGA_B[0]    ; 7.751 ; 7.574 ; 8.324  ; 8.190  ;
+; SW[5]      ; VGA_B[1]    ; 8.626 ; 8.506 ; 9.174  ; 9.054  ;
+; SW[5]      ; VGA_B[2]    ; 7.611 ; 7.449 ; 8.184  ; 8.052  ;
+; SW[5]      ; VGA_B[3]    ; 8.857 ; 8.761 ; 9.438  ; 9.342  ;
+; SW[5]      ; VGA_G[0]    ; 7.926 ; 7.758 ; 8.482  ; 8.344  ;
+; SW[5]      ; VGA_G[1]    ; 8.684 ; 8.551 ; 9.273  ; 9.131  ;
+; SW[5]      ; VGA_G[2]    ; 8.027 ; 7.909 ; 8.581  ; 8.493  ;
+; SW[5]      ; VGA_G[3]    ; 8.836 ; 8.731 ; 9.457  ; 9.277  ;
+; SW[5]      ; VGA_R[0]    ; 7.938 ; 7.812 ; 8.509  ; 8.413  ;
+; SW[5]      ; VGA_R[1]    ; 9.562 ; 9.469 ; 10.169 ; 10.046 ;
+; SW[5]      ; VGA_R[2]    ; 8.006 ; 7.844 ; 8.579  ; 8.460  ;
+; SW[5]      ; VGA_R[3]    ; 8.997 ; 8.850 ; 9.552  ; 9.405  ;
++------------+-------------+-------+-------+--------+--------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.156 ; 3.156 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.622 ; 3.622 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.156 ; 3.156 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.166 ; 3.166 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.325 ; 3.325 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.361 ; 3.361 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.156 ; 3.156 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.381 ; 3.381 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.342 ; 3.342 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.659 ; 3.659 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.659 ; 3.659 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.642 ; 3.642 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.649 ; 3.649 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.632 ; 3.632 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.642 ; 3.642 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.622 ; 3.622 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.361 ; 3.361 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.448 ; 2.448 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.895 ; 2.895 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.448 ; 2.448 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.458 ; 2.458 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.610 ; 2.610 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.644 ; 2.644 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.448 ; 2.448 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.664 ; 2.664 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.626 ; 2.626 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.931 ; 2.931 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.931 ; 2.931 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.915 ; 2.915 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.921 ; 2.921 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.905 ; 2.905 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.915 ; 2.915 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.895 ; 2.895 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.644 ; 2.644 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.089     ; 3.191     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.549     ; 3.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.089     ; 3.191     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.099     ; 3.201     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.246     ; 3.348     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.284     ; 3.386     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.089     ; 3.191     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.304     ; 3.406     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.275     ; 3.377     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.584     ; 3.686     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.584     ; 3.686     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.569     ; 3.671     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.574     ; 3.676     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.559     ; 3.661     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.569     ; 3.671     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.549     ; 3.651     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.284     ; 3.386     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.482     ; 2.578     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.923     ; 3.019     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.482     ; 2.578     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.492     ; 2.588     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.632     ; 2.728     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.668     ; 2.764     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.482     ; 2.578     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.688     ; 2.784     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.660     ; 2.756     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.957     ; 3.053     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.957     ; 3.053     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.943     ; 3.039     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.947     ; 3.043     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.933     ; 3.029     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.943     ; 3.039     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.923     ; 3.019     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.668     ; 2.764     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 10.993 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 10.993                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.819        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.174        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.140                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 3.888        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.182                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 3.931        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.264                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 6.820        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.444        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.295                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.190        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.451                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.248        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.203        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.541                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.288        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.556                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.305        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.687                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.249        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.438        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.706                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.252        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.454        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.782                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 4.677        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.861                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.755        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.872                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.647        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.225        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.875                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.625        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.923                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 4.818        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.944                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.174        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 4.770        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.975                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 6.900        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.075        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.011                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.251        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 4.760        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.049                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.943        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.061                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 4.955        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.110                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.267        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 4.843        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.112                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 6.989        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.123        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.122                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 6.901        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.221        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.181                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.121        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.060        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.189                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.106        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.083        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.191                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.118        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.073        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.254                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 6.900        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.354        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.262                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 6.995        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.267        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.267                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.123        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.144        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.281                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 6.992        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.289        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.296                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.148        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.148        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.330                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.108        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.222        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.373                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 6.970        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.403        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.381                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.122        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.259        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.499                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.105        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.394        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.502                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.104        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.398        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.539                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.140        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.399        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.564                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.250        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.314        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.604                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 6.900        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.704        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.668                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.969        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.699        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Fmax Summary                                                         ;
++------------+-----------------+-----------------------------------------------------+------+
+; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
++------------+-----------------+-----------------------------------------------------+------+
+; 194.78 MHz ; 194.78 MHz      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;      ;
+; 215.47 MHz ; 215.47 MHz      ; CLOCK_50                                            ;      ;
++------------+-----------------+-----------------------------------------------------+------+
+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.022  ; 0.000         ;
+; CLOCK_50                                            ; 15.359 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.298 ; 0.000         ;
+; CLOCK_50                                            ; 0.312 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.828 ; -158.364      ;
+; CLOCK_50                                            ; 14.667 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 1.412 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.602 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.739 ; 0.000         ;
+; CLOCK_50                                            ; 9.562 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.900     ; 2.093      ;
+; 0.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.900     ; 2.093      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.077 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.210     ; 1.728      ;
+; 0.083 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 2.033      ;
+; 0.083 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.899     ; 2.033      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.992      ;
+; 0.143 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.909     ; 1.963      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.167 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.880     ; 1.968      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.282 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.903     ; 1.830      ;
+; 0.340 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.780      ;
+; 0.340 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.780      ;
+; 0.340 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.895     ; 1.780      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.350 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.879     ; 1.786      ;
+; 0.399 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.870     ; 1.746      ;
+; 0.399 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.870     ; 1.746      ;
+; 0.399 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.870     ; 1.746      ;
+; 0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.681      ;
+; 0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.681      ;
+; 0.426 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.908     ; 1.681      ;
+; 2.866 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.239      ; 5.388      ;
+; 2.866 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.239      ; 5.388      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.090     ; 5.048      ;
+; 2.877 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.090     ; 5.048      ;
+; 2.895 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.090     ; 5.030      ;
+; 2.895 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.090     ; 5.030      ;
+; 2.913 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.240      ; 5.342      ;
+; 2.913 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.240      ; 5.342      ;
+; 2.916 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.269      ; 5.368      ;
+; 2.928 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.269      ; 5.356      ;
+; 2.930 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.089     ; 4.996      ;
+; 2.930 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.089     ; 4.996      ;
+; 2.938 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.089     ; 4.988      ;
+; 2.938 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.089     ; 4.988      ;
+; 2.942 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.089     ; 4.984      ;
+; 2.942 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.089     ; 4.984      ;
+; 2.950 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.230      ; 5.295      ;
+; 2.977 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 4.950      ;
+; 2.977 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.088     ; 4.950      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.359 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.590      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.368 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.581      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.418 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.542      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.429 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.055     ; 4.531      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.448 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.066     ; 4.501      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.449 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.512      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
+; 15.460 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.054     ; 4.501      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.298 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.299 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.300 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 0.511      ;
+; 0.302 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.386      ; 0.832      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.311 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.054      ; 0.511      ;
+; 0.317 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.529      ;
+; 0.319 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.519      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.320 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.519      ;
+; 0.325 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.537      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.326 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.538      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.327 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.539      ;
+; 0.328 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.540      ;
+; 0.330 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.529      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.530      ;
+; 0.331 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.338      ; 0.838      ;
+; 0.333 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.545      ;
+; 0.333 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.545      ;
+; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.334      ; 0.838      ;
+; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.547      ;
+; 0.335 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.338      ; 0.842      ;
+; 0.336 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.548      ;
+; 0.337 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.536      ;
+; 0.338 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.539      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 0.539      ;
+; 0.339 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.538      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[15]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[17]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.386      ; 0.870      ;
+; 0.340 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.539      ;
+; 0.342 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.055      ; 0.541      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.312 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.511      ;
+; 0.313 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.511      ;
+; 0.320 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
+; 0.320 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.519      ;
+; 0.333 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.511      ;
+; 0.339 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.538      ;
+; 0.340 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.539      ;
+; 0.341 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.519      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.545      ;
+; 0.347 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.546      ;
+; 0.386 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.564      ;
+; 0.470 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.669      ;
+; 0.495 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.694      ;
+; 0.495 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.694      ;
+; 0.496 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.695      ;
+; 0.497 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.696      ;
+; 0.498 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.697      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
+; 0.499 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.698      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.500 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.699      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.501 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.700      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.502 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.701      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.503 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.702      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.504 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.703      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.704      ;
+; 0.505 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.704      ;
+; 0.506 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.705      ;
+; 0.508 ; ps2:inst6|clk_div[1]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.707      ;
+; 0.508 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.707      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.511 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.710      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.512 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.711      ;
+; 0.513 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.513 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.712      ;
+; 0.514 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.514 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.713      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.515 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.714      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.516 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.715      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.517 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.716      ;
+; 0.520 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.055      ; 0.719      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.724      ;
+; 0.526 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.724      ;
+; 0.530 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.728      ;
+; 0.530 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.728      ;
+; 0.531 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.729      ;
+; 0.532 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.730      ;
+; 0.639 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 0.837      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack  ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.828 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.992     ; 2.794      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.815 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.984     ; 2.789      ;
+; -0.784 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.990     ; 2.834      ;
+; -0.771 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.982     ; 2.829      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.492      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.492      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.492      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.492      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.492      ;
+; -0.683 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.492      ;
+; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.491      ;
+; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.491      ;
+; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.491      ;
+; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.491      ;
+; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.491      ;
+; -0.682 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.206     ; 2.491      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.474      ;
+; -0.674 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.213     ; 2.476      ;
+; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.473      ;
+; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.473      ;
+; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.473      ;
+; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.473      ;
+; -0.673 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.215     ; 2.473      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.201     ; 2.477      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.201     ; 2.477      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.201     ; 2.477      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.201     ; 2.477      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.200     ; 2.478      ;
+; -0.663 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -2.201     ; 2.477      ;
++--------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 14.667 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 4.648      ;
+; 14.676 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 4.639      ;
+; 14.756 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 4.559      ;
+; 14.800 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.516      ;
+; 14.875 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 4.440      ;
+; 14.926 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.390      ;
+; 14.928 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.388      ;
+; 14.935 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.381      ;
+; 15.006 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.310      ;
+; 15.013 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.303      ;
+; 15.134 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.182      ;
+; 15.136 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.180      ;
+; 15.142 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.174      ;
+; 15.143 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.173      ;
+; 15.223 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 4.093      ;
+; 15.336 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.979      ;
+; 15.349 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.699     ; 3.967      ;
+; 15.462 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.853      ;
+; 15.554 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.761      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.556 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.402      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.565 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.393      ;
+; 15.583 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.732      ;
+; 15.592 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.723      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.645 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.313      ;
+; 15.671 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.644      ;
+; 15.674 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.700     ; 3.641      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.689 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.056     ; 4.270      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
+; 15.772 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.057     ; 4.186      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.412 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.610      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 1.581 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 1.779      ;
+; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.209      ;
+; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.209      ;
+; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.209      ;
+; 2.000 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.209      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.022 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.065      ; 2.231      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.071 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.066      ; 2.281      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.286 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.054      ; 2.484      ;
+; 2.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.578     ; 1.865      ;
+; 2.450 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.578     ; 2.016      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.703 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.064      ; 2.911      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
+; 2.834 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.053      ; 3.031      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 3.602 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.427     ; 2.319      ;
+; 3.602 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.427     ; 2.319      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.616 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.433     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.325      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.325      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.325      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.325      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.325      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.321      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.443     ; 2.325      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.624 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.441     ; 2.327      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.625 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.446     ; 2.323      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.629 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.321      ;
+; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.323      ;
+; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.323      ;
+; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.323      ;
+; 3.636 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.457     ; 2.323      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.638 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.442     ; 2.340      ;
+; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.327      ;
+; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.327      ;
+; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.327      ;
+; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.327      ;
+; 3.642 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.459     ; 2.327      ;
+; 3.644 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.447     ; 2.341      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.452     ; 2.338      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
+; 3.646 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.453     ; 2.337      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                         ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.739 ; 3.955        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; 3.740 ; 3.970        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.740 ; 3.970        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ;
+; 3.740 ; 3.956        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.741 ; 3.971        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.741 ; 3.971        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]                                                                                                                             ;
+; 3.741 ; 3.957        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]                                                                                                                             ;
+; 3.742 ; 3.972        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.743 ; 3.973        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[3]                                                                                                                           ;
+; 3.743 ; 3.959        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[4]                                                                                                                           ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                           ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                           ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                           ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                           ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]                                                                                                                             ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]                                                                                                                             ;
+; 3.744 ; 3.960        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[1]                                                                                                                           ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]                                                                                                                             ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]                                                                                                                             ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22]                                                                                                                         ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]                                                                                                                          ;
+; 3.745 ; 3.961        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]                                                                                                                          ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]                                                                                                                            ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]                                                                                                                            ;
+; 3.749 ; 3.965        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR                                                                                                                                   ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[1]                                                                                                                                 ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[3]                                                                                                                                 ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[4]                                                                                                                                 ;
+; 3.750 ; 3.966        ; 0.216          ; High Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[8]                                                                                                                                 ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.750 ; 3.980        ; 0.230          ; Low Pulse Width  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
++-------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.562 ; 9.746        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ;
+; 9.562 ; 9.746        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|rClk[0]                                  ;
+; 9.562 ; 9.746        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[8]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                    ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.588 ; 9.772        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.589 ; 9.773        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.590 ; 9.774        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 3.692 ; 4.270 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 3.692 ; 4.270 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 3.554 ; 4.069 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.612 ; 4.078 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.418 ; 3.906 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.162 ; 3.645 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.288 ; 3.732 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.311 ; 3.818 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.612 ; 4.078 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.144 ; 3.579 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.414 ; 3.881 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.143 ; 3.582 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.168 ; 3.602 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.130 ; 3.608 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.169 ; 3.610 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.169 ; 3.611 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.313 ; 3.766 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.165 ; 3.601 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.348 ; 3.793 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.802 ; -2.295 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.802 ; -2.295 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.816 ; -2.303 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -2.507 ; -2.968 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -2.810 ; -3.283 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -2.540 ; -3.008 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -2.696 ; -3.131 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -2.694 ; -3.191 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -2.972 ; -3.424 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -2.546 ; -2.968 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -2.807 ; -3.260 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -2.544 ; -2.970 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -2.570 ; -2.991 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -2.507 ; -2.970 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -2.571 ; -2.999 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -2.571 ; -3.000 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -2.722 ; -3.166 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -2.567 ; -2.990 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -2.744 ; -3.175 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.098  ; 5.915  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.946  ; 5.878  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.098  ; 5.915  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.416  ; 5.365  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.416  ; 5.365  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.228  ; 5.321  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.434  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.430  ; 3.268  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.434  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.410  ; 3.255  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.410  ; 3.256  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.228  ; 3.089  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.207  ; 3.075  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.040  ; 2.920  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.050  ; 2.930  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.042  ; 2.918  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.035  ; 2.919  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.278  ; 3.144  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.026  ; 2.912  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.104  ; 3.009  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.264  ; 3.154  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.210  ; 3.074  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.572  ; 3.481  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.279  ; 6.943  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.621  ; 5.416  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.638  ; 5.572  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.364  ; 5.227  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.279  ; 6.943  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.466  ; 5.343  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.649  ; 5.523  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.615  ; 5.397  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.565  ; 5.460  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.504  ; 5.380  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.559  ; 5.455  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.684  ; 5.550  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.733  ; 5.551  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 5.769  ; 5.642  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.749  ; 5.623  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 5.620  ; 5.420  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.587  ; 5.458  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.456  ; 3.298  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.401  ; 3.247  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.348  ; 3.232  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.256  ; 4.904  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 5.810  ; 5.740  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 5.810  ; 5.740  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 5.957  ; 5.775  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.301  ; 5.248  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.301  ; 5.248  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.116  ; 5.210  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.656  ; 2.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.043  ; 2.882  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.047  ; 2.888  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.025  ; 2.871  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.024  ; 2.871  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 2.850  ; 2.712  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 2.829  ; 2.697  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 2.669  ; 2.549  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 2.679  ; 2.559  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 2.670  ; 2.546  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 2.665  ; 2.548  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 2.898  ; 2.765  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 2.656  ; 2.540  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 2.730  ; 2.635  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 2.884  ; 2.774  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 2.831  ; 2.696  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.178  ; 3.085  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 3.594  ; 3.423  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.594  ; 3.423  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 4.355  ; 4.265  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 4.040  ; 3.912  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 5.925  ; 5.573  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 4.109  ; 3.971  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 4.238  ; 4.134  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 4.091  ; 3.943  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 4.260  ; 4.135  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.912  ; 3.768  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.950  ; 3.822  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 4.069  ; 3.911  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.961  ; 3.827  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 4.359  ; 4.203  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 4.146  ; 4.005  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.853  ; 3.683  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.971  ; 3.837  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.067  ; 2.911  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.015  ; 2.862  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.964  ; 2.848  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 4.876  ; 4.525  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.777 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.922 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 7.976 ; 7.791 ; 8.504 ; 8.311 ;
+; SW[4]      ; VGA_B[1]    ; 7.840 ; 7.650 ; 8.336 ; 8.138 ;
+; SW[4]      ; VGA_B[2]    ; 7.955 ; 7.759 ; 8.484 ; 8.280 ;
+; SW[4]      ; VGA_B[3]    ; 8.033 ; 7.902 ; 8.552 ; 8.463 ;
+; SW[4]      ; VGA_G[0]    ; 8.023 ; 7.815 ; 8.508 ; 8.308 ;
+; SW[4]      ; VGA_G[1]    ; 8.353 ; 8.150 ; 8.874 ; 8.671 ;
+; SW[4]      ; VGA_G[2]    ; 8.110 ; 7.933 ; 8.593 ; 8.424 ;
+; SW[4]      ; VGA_G[3]    ; 8.539 ; 8.342 ; 9.042 ; 8.865 ;
+; SW[4]      ; VGA_R[0]    ; 8.270 ; 8.075 ; 8.800 ; 8.597 ;
+; SW[4]      ; VGA_R[1]    ; 8.480 ; 8.328 ; 8.958 ; 8.798 ;
+; SW[4]      ; VGA_R[2]    ; 7.996 ; 7.803 ; 8.491 ; 8.302 ;
+; SW[4]      ; VGA_R[3]    ; 8.201 ; 8.016 ; 8.701 ; 8.508 ;
+; SW[5]      ; VGA_B[0]    ; 7.569 ; 7.382 ; 8.078 ; 7.885 ;
+; SW[5]      ; VGA_B[1]    ; 8.249 ; 8.057 ; 8.735 ; 8.537 ;
+; SW[5]      ; VGA_B[2]    ; 7.658 ; 7.462 ; 8.200 ; 7.996 ;
+; SW[5]      ; VGA_B[3]    ; 8.565 ; 8.428 ; 9.045 ; 8.956 ;
+; SW[5]      ; VGA_G[0]    ; 7.940 ; 7.734 ; 8.398 ; 8.198 ;
+; SW[5]      ; VGA_G[1]    ; 8.338 ; 8.135 ; 8.828 ; 8.625 ;
+; SW[5]      ; VGA_G[2]    ; 8.027 ; 7.854 ; 8.486 ; 8.317 ;
+; SW[5]      ; VGA_G[3]    ; 8.523 ; 8.328 ; 8.996 ; 8.819 ;
+; SW[5]      ; VGA_R[0]    ; 7.974 ; 7.779 ; 8.516 ; 8.313 ;
+; SW[5]      ; VGA_R[1]    ; 9.235 ; 9.102 ; 9.712 ; 9.593 ;
+; SW[5]      ; VGA_R[2]    ; 7.813 ; 7.622 ; 8.323 ; 8.126 ;
+; SW[5]      ; VGA_R[3]    ; 8.608 ; 8.420 ; 9.102 ; 8.909 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 7.730 ; 7.546 ; 8.213 ; 8.023 ;
+; SW[4]      ; VGA_B[1]    ; 7.362 ; 7.166 ; 7.831 ; 7.670 ;
+; SW[4]      ; VGA_B[2]    ; 7.707 ; 7.513 ; 8.196 ; 8.002 ;
+; SW[4]      ; VGA_B[3]    ; 7.241 ; 7.081 ; 7.716 ; 7.585 ;
+; SW[4]      ; VGA_G[0]    ; 7.728 ; 7.530 ; 8.230 ; 8.026 ;
+; SW[4]      ; VGA_G[1]    ; 7.726 ; 7.525 ; 8.195 ; 8.029 ;
+; SW[4]      ; VGA_G[2]    ; 7.812 ; 7.643 ; 8.309 ; 8.134 ;
+; SW[4]      ; VGA_G[3]    ; 7.449 ; 7.281 ; 7.953 ; 7.736 ;
+; SW[4]      ; VGA_R[0]    ; 8.010 ; 7.817 ; 8.500 ; 8.307 ;
+; SW[4]      ; VGA_R[1]    ; 7.887 ; 7.698 ; 8.361 ; 8.201 ;
+; SW[4]      ; VGA_R[2]    ; 7.787 ; 7.597 ; 8.272 ; 8.079 ;
+; SW[4]      ; VGA_R[3]    ; 7.704 ; 7.512 ; 8.180 ; 8.023 ;
+; SW[5]      ; VGA_B[0]    ; 7.214 ; 7.022 ; 7.679 ; 7.522 ;
+; SW[5]      ; VGA_B[1]    ; 8.030 ; 7.839 ; 8.479 ; 8.291 ;
+; SW[5]      ; VGA_B[2]    ; 7.094 ; 6.898 ; 7.563 ; 7.395 ;
+; SW[5]      ; VGA_B[3]    ; 8.233 ; 8.100 ; 8.707 ; 8.574 ;
+; SW[5]      ; VGA_G[0]    ; 7.380 ; 7.180 ; 7.830 ; 7.658 ;
+; SW[5]      ; VGA_G[1]    ; 8.066 ; 7.873 ; 8.527 ; 8.328 ;
+; SW[5]      ; VGA_G[2]    ; 7.464 ; 7.293 ; 7.913 ; 7.770 ;
+; SW[5]      ; VGA_G[3]    ; 8.210 ; 8.046 ; 8.679 ; 8.455 ;
+; SW[5]      ; VGA_R[0]    ; 7.395 ; 7.200 ; 7.864 ; 7.697 ;
+; SW[5]      ; VGA_R[1]    ; 8.881 ; 8.721 ; 9.373 ; 9.182 ;
+; SW[5]      ; VGA_R[2]    ; 7.445 ; 7.250 ; 7.911 ; 7.751 ;
+; SW[5]      ; VGA_R[3]    ; 8.375 ; 8.190 ; 8.830 ; 8.646 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.114 ; 3.101 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.548 ; 3.535 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.114 ; 3.101 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.124 ; 3.111 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.271 ; 3.258 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.307 ; 3.294 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.114 ; 3.101 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.327 ; 3.314 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.291 ; 3.278 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.582 ; 3.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.582 ; 3.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.568 ; 3.555 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.572 ; 3.559 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.558 ; 3.545 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.568 ; 3.555 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.548 ; 3.535 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.307 ; 3.294 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.246 ; 2.246 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.663 ; 2.663 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.246 ; 2.246 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.256 ; 2.256 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.398 ; 2.398 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.432 ; 2.432 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.246 ; 2.246 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.452 ; 2.452 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.417 ; 2.417 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.697 ; 2.697 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.697 ; 2.697 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.683 ; 2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.687 ; 2.687 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.673 ; 2.673 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.683 ; 2.683 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.663 ; 2.663 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.432 ; 2.432 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 3.128     ; 3.128     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.550     ; 3.550     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.128     ; 3.128     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.138     ; 3.138     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.266     ; 3.266     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 3.299     ; 3.299     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.128     ; 3.128     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.319     ; 3.319     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.289     ; 3.289     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.579     ; 3.579     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.579     ; 3.579     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.570     ; 3.570     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.569     ; 3.569     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.560     ; 3.560     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.570     ; 3.570     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.550     ; 3.550     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 3.299     ; 3.299     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.260     ; 2.448     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.665     ; 2.853     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.260     ; 2.448     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.270     ; 2.458     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.393     ; 2.581     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.424     ; 2.612     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.260     ; 2.448     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.444     ; 2.632     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.415     ; 2.603     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.693     ; 2.881     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.693     ; 2.881     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.685     ; 2.873     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.683     ; 2.871     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.675     ; 2.863     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.685     ; 2.873     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.665     ; 2.853     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.424     ; 2.612     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 11.499 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.499                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 6.941        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 4.558        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.633                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 4.294        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.677                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 4.340        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.741                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 6.945        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 4.796        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.771                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.199        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 4.572        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.907                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.334        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 4.573        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 11.986                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.338        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 4.648        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 11.987                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.336        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 4.651        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.128                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.336        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 4.792        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.144                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.339        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 4.805        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.200                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.003        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.274                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.336        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 4.938        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.279                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.081        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.281                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 6.783        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.498        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.320                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.123        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.330                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.269        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.061        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.389                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.017        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.372        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.400                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.337        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.063        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.436                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.199        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.237        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.459                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.199        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 5.260        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.462                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.352        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.110        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.511                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.095        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.416        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.515                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.018        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.497        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.536                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.211        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 5.325        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.577                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 5.379        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.588                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.218        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.370        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.615                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.017        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.598        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.635                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.214        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 5.421        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.637                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.098        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.539        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.662                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.253        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.409        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.685                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.200        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 5.485        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.702                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.112        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 5.590        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.735                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.222        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 5.513        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 12.742                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.077        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.665        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.810                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.197        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.613        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.855                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.198        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 5.657        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.870                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.336        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.534        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.878                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.238        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.640        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 12.938                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.018        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 5.920        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.041                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.077        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 5.964        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup Summary                                           ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 1.392  ; 0.000         ;
+; CLOCK_50                                            ; 16.970 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold Summary                                           ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.170 ; 0.000         ;
+; CLOCK_50                                            ; 0.188 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery Summary                                        ;
++-----------------------------------------------------+--------+---------------+
+; Clock                                               ; Slack  ; End Point TNS ;
++-----------------------------------------------------+--------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.783  ; 0.000         ;
+; CLOCK_50                                            ; 16.478 ; 0.000         ;
++-----------------------------------------------------+--------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal Summary                                        ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; CLOCK_50                                            ; 0.851 ; 0.000         ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 2.398 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++-----------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary                            ;
++-----------------------------------------------------+-------+---------------+
+; Clock                                               ; Slack ; End Point TNS ;
++-----------------------------------------------------+-------+---------------+
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 3.746 ; 0.000         ;
+; CLOCK_50                                            ; 9.267 ; 0.000         ;
++-----------------------------------------------------+-------+---------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                   ; To Node                                           ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 1.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.299      ;
+; 1.392 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.299      ;
+; 1.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.264      ;
+; 1.427 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.316     ; 1.264      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.432 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.501     ; 1.074      ;
+; 1.468 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[20]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.322     ; 1.217      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.477 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.306     ; 1.224      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.498 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.204      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[21] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[12] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[8]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[9]  ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[10] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[11] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[14] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[13] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[16] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[15] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[17] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[19] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[18] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[20] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.578 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR2_ADDR[22] ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.317     ; 1.112      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[22]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[18]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[13]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[9]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.618 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[8]      ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.305     ; 1.084      ;
+; 1.632 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.312     ; 1.063      ;
+; 1.632 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.312     ; 1.063      ;
+; 1.632 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|WR_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.312     ; 1.063      ;
+; 1.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD           ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.298     ; 1.041      ;
+; 1.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.298     ; 1.041      ;
+; 1.668 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]    ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.298     ; 1.041      ;
+; 1.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.017      ;
+; 1.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[19]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.017      ;
+; 1.669 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[15]     ; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.321     ; 1.017      ;
+; 4.603 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.159      ; 3.563      ;
+; 4.605 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.158      ; 3.560      ;
+; 4.665 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.159      ; 3.501      ;
+; 4.669 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.138      ; 3.476      ;
+; 4.669 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.138      ; 3.476      ;
+; 4.685 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.159      ; 3.481      ;
+; 4.685 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.158      ; 3.480      ;
+; 4.686 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[10]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.159      ; 3.480      ;
+; 4.687 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[11]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.158      ; 3.478      ;
+; 4.691 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.057     ; 3.259      ;
+; 4.691 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; -0.057     ; 3.259      ;
+; 4.702 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.143      ; 3.448      ;
+; 4.704 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[14]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.138      ; 3.441      ;
+; 4.704 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[12]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.138      ; 3.441      ;
+; 4.704 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[21]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.142      ; 3.445      ;
+; 4.715 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.148      ; 3.440      ;
+; 4.715 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.148      ; 3.440      ;
+; 4.717 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[17]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.147      ; 3.437      ;
+; 4.717 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|mADDR[16]     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 8.000        ; 0.147      ; 3.437      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Setup: 'CLOCK_50'                                                                                                                                           ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                            ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.970 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.991      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 16.973 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.988      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.035 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.926      ;
+; 17.044 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.917      ;
+; 17.047 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.914      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.071 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.045     ; 2.891      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.100 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.871      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.108 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.853      ;
+; 17.109 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.046     ; 2.852      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
+; 17.110 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]         ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]               ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.036     ; 2.861      ;
++--------+----------------------------------------------+----------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                                                                                                                                                                 ; To Node                                                                                                                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.170 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.230      ; 0.484      ;
+; 0.178 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.502      ;
+; 0.179 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.220      ; 0.503      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a6                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a7                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a9                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a8                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a5                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a4                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.180 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.181 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.042      ; 0.307      ;
+; 0.183 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.216      ; 0.503      ;
+; 0.185 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.313      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.315      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.315      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|OUT_VALID                                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|ST[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Read                                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Write                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|mWR_DONE                                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_write                                                                                                             ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|ex_read                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.187 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.314      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|oe4                                                                                                                  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_flag                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|REF_ACK                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REF_REQ                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.315      ;
+; 0.188 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|init_timer[0]                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.317      ;
+; 0.190 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.230      ; 0.504      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.313      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[15]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[9]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[17]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[9]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|BA[0]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|BA[0]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_done                                                                                                              ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[0]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[2]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rp_shift[1]                                                                                                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_precharge                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.194 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_load_mode                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[4]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[4]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[6]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[6]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[7]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[7]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.315      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[10]                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[10]                                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.518      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[1]                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|SA[1]                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.315      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rRD1_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.044      ; 0.324      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|REFRESH                                                                                                    ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_refresh                                                                                                           ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.315      ;
+; 0.196 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|rw_shift[0]                                                                                                          ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|do_rw                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.315      ;
+; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|SADDR[16]                                                                                                  ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|SA[8]                                                                                                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.316      ;
+; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|RAS_N                                                                                                                ; DE0_D5M:inst|Sdram_Control_4Port:u7|RAS_N                                                                                                                                 ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.316      ;
+; 0.197 ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.324      ;
+; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.325      ;
+; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.043      ; 0.325      ;
+; 0.198 ; DE0_D5M:inst|Sdram_Control_4Port:u7|command:command1|CM_ACK                                                                                                               ; DE0_D5M:inst|Sdram_Control_4Port:u7|control_interface:control1|CMD_ACK                                                                                                    ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.317      ;
++-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Hold: 'CLOCK_50'                                                                                                                                                       ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.188 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.307      ;
+; 0.194 ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.314      ;
+; 0.195 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.314      ;
+; 0.195 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.314      ;
+; 0.196 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.315      ;
+; 0.201 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.307      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.324      ;
+; 0.205 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.325      ;
+; 0.208 ; DE0_D5M:inst|rClk[0]                                  ; DE0_D5M:inst|rClk[0]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.314      ;
+; 0.231 ; ps2:inst6|clk_div[8]                                  ; ps2:inst6|clk_div[8]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.022      ; 0.337      ;
+; 0.272 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.391      ;
+; 0.293 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.413      ;
+; 0.295 ; ps2:inst6|clk_div[4]                                  ; ps2:inst6|clk_div[4]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.414      ;
+; 0.296 ; ps2:inst6|clk_div[6]                                  ; ps2:inst6|clk_div[6]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; ps2:inst6|clk_div[3]                                  ; ps2:inst6|clk_div[3]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.415      ;
+; 0.296 ; ps2:inst6|clk_div[2]                                  ; ps2:inst6|clk_div[2]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.415      ;
+; 0.297 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.417      ;
+; 0.297 ; ps2:inst6|clk_div[7]                                  ; ps2:inst6|clk_div[7]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.416      ;
+; 0.297 ; ps2:inst6|clk_div[5]                                  ; ps2:inst6|clk_div[5]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.416      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.417      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.298 ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.299 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.418      ;
+; 0.299 ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.419      ;
+; 0.300 ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.420      ;
+; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.421      ;
+; 0.301 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.420      ;
+; 0.301 ; ps2:inst6|clk_div[1]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.420      ;
+; 0.302 ; ps2:inst6|clk_div[0]                                  ; ps2:inst6|clk_div[1]                                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.421      ;
+; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.424      ;
+; 0.304 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.424      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[8]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.305 ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.425      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.306 ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.426      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; DE0_D5M:inst|Reset_Delay:u2|Cont[9]                   ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.307 ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.427      ;
+; 0.308 ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.036      ; 0.428      ;
+; 0.312 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.431      ;
+; 0.316 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.435      ;
+; 0.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.436      ;
+; 0.317 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.436      ;
+; 0.318 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.437      ;
+; 0.319 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.438      ;
+; 0.319 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.438      ;
+; 0.369 ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.035      ; 0.488      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                 ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.783 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.828      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.790 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.825      ;
+; 0.819 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.364     ; 1.846      ;
+; 0.826 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.360     ; 1.843      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.856 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.499     ; 1.652      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.863 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.638      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.637      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.637      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.637      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.637      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.506     ; 1.637      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.864 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.640      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_brp|dffe12a[0]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[1]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[2]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[3]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[4]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[5]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[6]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[7]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.865 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[8]                               ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.503     ; 1.639      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a2                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a3                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[1]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.644      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.644      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|sub_parity10a[2]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.644      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a0                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|counter8a1                       ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[1]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[4]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.496     ; 1.644      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[7]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[2]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
+; 0.867 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[8]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 4.000        ; -1.497     ; 1.643      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Recovery: 'CLOCK_50'                                                                                                                                     ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack  ; From Node                                    ; To Node                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 16.478 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 3.031      ;
+; 16.481 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 3.028      ;
+; 16.543 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.966      ;
+; 16.579 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.931      ;
+; 16.616 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.893      ;
+; 16.660 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.850      ;
+; 16.662 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.848      ;
+; 16.663 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.847      ;
+; 16.723 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.787      ;
+; 16.725 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.785      ;
+; 16.797 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.713      ;
+; 16.798 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.712      ;
+; 16.799 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.711      ;
+; 16.800 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.710      ;
+; 16.863 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.647      ;
+; 16.934 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.497     ; 2.576      ;
+; 16.994 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.515      ;
+; 17.068 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.441      ;
+; 17.075 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.434      ;
+; 17.079 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.430      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.114 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.855      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.117 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.852      ;
+; 17.123 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.386      ;
+; 17.140 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.369      ;
+; 17.146 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.363      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.179 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.790      ;
+; 17.213 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK    ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.498     ; 2.296      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.215 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]  ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.037     ; 2.755      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11] ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
+; 17.252 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]  ; CLOCK_50     ; CLOCK_50    ; 20.000       ; -0.038     ; 2.717      ;
++--------+----------------------------------------------+-------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'CLOCK_50'                                                                                                                                                    ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; Slack ; From Node                                             ; To Node                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.851 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 0.969      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 0.996 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.114      ;
+; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.352      ;
+; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.352      ;
+; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.352      ;
+; 1.225 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.352      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.231 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.043      ; 1.358      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.267 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.044      ; 1.395      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.413 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.033      ; 1.530      ;
+; 1.454 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.417     ; 1.121      ;
+; 1.604 ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK          ; CLOCK_50     ; CLOCK_50    ; 0.000        ; -0.417     ; 1.271      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.684 ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.042      ; 1.810      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
+; 1.704 ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ; CLOCK_50     ; CLOCK_50    ; 0.000        ; 0.034      ; 1.822      ;
++-------+-------------------------------------------------------+-------------------------------------------------------+--------------+-------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Removal: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                  ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; Slack ; From Node                          ; To Node                                                                                                                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+; 2.398 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.475      ;
+; 2.398 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.007     ; 1.475      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.405 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.004     ; 1.485      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.476      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.409 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.477      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.410 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.009     ; 1.485      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.483      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.483      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.483      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.483      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.483      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.017     ; 1.478      ;
+; 2.411 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.012     ; 1.483      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.480      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.480      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.480      ;
+; 2.415 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.019     ; 1.480      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.417 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.010     ; 1.491      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_ojc:wrptr_g1p|parity9                          ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.485      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[5]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.485      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[3]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.485      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[9]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.485      ;
+; 2.419 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[6]                                                   ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.018     ; 1.485      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.422 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.490      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                           ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2]  ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
+; 2.423 ; DE0_D5M:inst|Reset_Delay:u2|oRST_0 ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ; CLOCK_50     ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; -1.016     ; 1.491      ;
++-------+------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                        ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                    ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_address_reg0    ;
+; 3.746 ; 3.976        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_we_reg          ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.748 ; 3.978        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~porta_datain_reg0     ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.749 ; 3.979        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[0]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[10]                            ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[11]                            ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[12]                            ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[13]                            ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[14]                            ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[15]                            ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[1]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[2]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[3]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[4]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[5]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[6]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[7]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[8]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|q_b[9]                             ;
+; 3.752 ; 3.982        ; 0.230          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|altsyncram_de51:fifo_ram|ram_block11a0~portb_address_reg0   ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[0]                                                                                                                            ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|RD_MASK[1]                                                                                                                            ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[0]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[1]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[2]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[3]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[4]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[5]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[6]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[8]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[0]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[1]                                ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mDATAOUT[9]                                                                                                                           ;
+; 3.779 ; 3.963        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|mRD                                                                                                                                   ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0]  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[10]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[11]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[12]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[13]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[14]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[15]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[16]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[17]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[18]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[19]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[20]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[21]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[22]                                                                                                                         ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[8]                                                                                                                          ;
+; 3.780 ; 3.964        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|rWR1_ADDR[9]                                                                                                                          ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9]  ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|wrptr_g[0]                                                   ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                           ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_brp|dffe12a[7]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[2]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[3]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[4]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[5]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[6]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[8]                                ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0                      ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6                         ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[0]                 ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; 3.781 ; 3.965        ; 0.184          ; Low Pulse Width ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
++-------+--------------+----------------+-----------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'                                                                                    ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; Slack ; Actual Width ; Required Width ; Type            ; Clock    ; Clock Edge ; Target                                                ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[0]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[10]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[11]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[12]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[13]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[14]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[15]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[16]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[17]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[18]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[19]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[1]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[20]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[21]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[22]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[23]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[24]          ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[2]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[3]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[4]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[5]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[6]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[7]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[8]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|combo_cnt[9]           ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[0] ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[1] ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[2] ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|iexposure_adj_delay[3] ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[0]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[10]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[11]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[12]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[13]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[14]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[15]       ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[1]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[2]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[3]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[4]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[5]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[6]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[7]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[8]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CLK_DIV[9]        ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[0]                   ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[16]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[17]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[18]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[19]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[20]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[21]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[22]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[23]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[24]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[25]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[26]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[27]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[28]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[29]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[30]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[31]                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_0                    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_1                    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|oRST_2                    ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[0]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[1]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[2]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[3]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[4]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[5]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[6]                                  ;
+; 9.267 ; 9.451        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; ps2:inst6|clk_div[7]                                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[0]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[10]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[11]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[12]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[13]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[14]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[15]    ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[3]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[4]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[5]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[6]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[7]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[8]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|I2C_CCD_Config:u8|sensor_exposure[9]     ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[10]                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[11]                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[12]                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[13]                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[14]                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[15]                  ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[1]                   ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[2]                   ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[3]                   ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[4]                   ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[5]                   ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[6]                   ;
+; 9.268 ; 9.452        ; 0.184          ; Low Pulse Width ; CLOCK_50 ; Rise       ; DE0_D5M:inst|Reset_Delay:u2|Cont[7]                   ;
++-------+--------------+----------------+-----------------+----------+------------+-------------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 2.291 ; 3.215 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 2.291 ; 3.215 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 2.282 ; 3.091 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.415 ; 3.254 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.288 ; 3.103 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.152 ; 2.950 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.201 ; 2.947 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.248 ; 3.046 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.415 ; 3.254 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.122 ; 2.871 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.297 ; 3.095 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.118 ; 2.868 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.143 ; 2.892 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.141 ; 2.938 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.144 ; 2.895 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.141 ; 2.894 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.229 ; 2.973 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.138 ; 2.888 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.249 ; 3.019 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.138 ; -1.987 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.174 ; -2.007 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.138 ; -1.987 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.725 ; -2.460 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -1.890 ; -2.688 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -1.745 ; -2.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -1.811 ; -2.549 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -1.842 ; -2.630 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -1.997 ; -2.818 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -1.730 ; -2.464 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -1.899 ; -2.681 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -1.725 ; -2.460 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.751 ; -2.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.733 ; -2.513 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -1.752 ; -2.489 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.748 ; -2.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.839 ; -2.575 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.746 ; -2.481 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.852 ; -2.606 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.775  ; 3.846  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.773  ; 3.846  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 3.775  ; 3.734  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.358  ; 3.454  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.358  ; 3.454  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.341  ; 3.261  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 2.064  ; 2.040  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 2.048  ; 2.025  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 2.064  ; 2.040  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 2.051  ; 2.023  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 2.045  ; 2.017  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.947  ; 1.917  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.928  ; 1.892  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.835  ; 1.793  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.846  ; 1.805  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.824  ; 1.783  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.835  ; 1.794  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.980  ; 1.954  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.826  ; 1.785  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.887  ; 1.861  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.977  ; 1.961  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.924  ; 1.896  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 2.148  ; 2.162  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 4.843  ; 4.633  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 3.565  ; 3.488  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 3.560  ; 3.597  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 3.378  ; 3.355  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 4.843  ; 4.633  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 3.442  ; 3.441  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 3.561  ; 3.567  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 3.557  ; 3.480  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 3.484  ; 3.501  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 3.496  ; 3.477  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 3.538  ; 3.529  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 3.603  ; 3.588  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 3.646  ; 3.586  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 3.640  ; 3.640  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 3.635  ; 3.633  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 3.562  ; 3.486  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 3.545  ; 3.522  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 2.063  ; 2.042  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 2.028  ; 2.008  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 2.031  ; 2.013  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.470  ; 3.239  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.313 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.366 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.685  ; 3.643  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.685  ; 3.753  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 3.686  ; 3.643  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.286  ; 3.374  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.286  ; 3.374  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.266  ; 3.193  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.574  ; 1.532  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.789  ; 1.764  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 1.806  ; 1.779  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.794  ; 1.763  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.787  ; 1.756  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.694  ; 1.661  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.674  ; 1.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.585  ; 1.542  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.595  ; 1.553  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.574  ; 1.532  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.584  ; 1.542  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.725  ; 1.696  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.575  ; 1.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.634  ; 1.607  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.720  ; 1.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.670  ; 1.640  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.883  ; 1.893  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.138  ; 2.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.138  ; 2.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.630  ; 2.712  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.422  ; 2.456  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.881  ; 3.708  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.479  ; 2.515  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.549  ; 2.620  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.472  ; 2.507  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.545  ; 2.606  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.366  ; 2.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.394  ; 2.422  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.457  ; 2.478  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.394  ; 2.427  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.622  ; 2.676  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.497  ; 2.535  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.304  ; 2.306  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.395  ; 2.416  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.803  ; 1.779  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.770  ; 1.747  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.772  ; 1.752  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.215  ; 2.983  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------+
+; Propagation Delay                                        ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 5.032 ; 5.020 ; 5.918 ; 5.899 ;
+; SW[4]      ; VGA_B[1]    ; 4.956 ; 4.945 ; 5.792 ; 5.781 ;
+; SW[4]      ; VGA_B[2]    ; 5.017 ; 5.003 ; 5.903 ; 5.882 ;
+; SW[4]      ; VGA_B[3]    ; 5.082 ; 5.107 ; 5.940 ; 5.981 ;
+; SW[4]      ; VGA_G[0]    ; 5.061 ; 5.043 ; 5.894 ; 5.883 ;
+; SW[4]      ; VGA_G[1]    ; 5.253 ; 5.269 ; 6.121 ; 6.137 ;
+; SW[4]      ; VGA_G[2]    ; 5.125 ; 5.123 ; 5.958 ; 5.963 ;
+; SW[4]      ; VGA_G[3]    ; 5.388 ; 5.380 ; 6.256 ; 6.248 ;
+; SW[4]      ; VGA_R[0]    ; 5.219 ; 5.219 ; 6.105 ; 6.098 ;
+; SW[4]      ; VGA_R[1]    ; 5.347 ; 5.431 ; 6.167 ; 6.244 ;
+; SW[4]      ; VGA_R[2]    ; 5.068 ; 5.067 ; 5.906 ; 5.905 ;
+; SW[4]      ; VGA_R[3]    ; 5.195 ; 5.209 ; 6.029 ; 6.043 ;
+; SW[5]      ; VGA_B[0]    ; 4.781 ; 4.762 ; 5.604 ; 5.585 ;
+; SW[5]      ; VGA_B[1]    ; 5.196 ; 5.185 ; 6.071 ; 6.060 ;
+; SW[5]      ; VGA_B[2]    ; 4.825 ; 4.811 ; 5.685 ; 5.664 ;
+; SW[5]      ; VGA_B[3]    ; 5.391 ; 5.416 ; 6.284 ; 6.325 ;
+; SW[5]      ; VGA_G[0]    ; 4.979 ; 4.961 ; 5.825 ; 5.807 ;
+; SW[5]      ; VGA_G[1]    ; 5.231 ; 5.247 ; 6.094 ; 6.110 ;
+; SW[5]      ; VGA_G[2]    ; 5.040 ; 5.038 ; 5.886 ; 5.884 ;
+; SW[5]      ; VGA_G[3]    ; 5.365 ; 5.357 ; 6.229 ; 6.221 ;
+; SW[5]      ; VGA_R[0]    ; 5.023 ; 5.023 ; 5.882 ; 5.875 ;
+; SW[5]      ; VGA_R[1]    ; 5.813 ; 5.897 ; 6.699 ; 6.785 ;
+; SW[5]      ; VGA_R[2]    ; 4.937 ; 4.936 ; 5.760 ; 5.759 ;
+; SW[5]      ; VGA_R[3]    ; 5.436 ; 5.450 ; 6.313 ; 6.327 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 4.871 ; 4.857 ; 5.715 ; 5.701 ;
+; SW[4]      ; VGA_B[1]    ; 4.662 ; 4.640 ; 5.472 ; 5.476 ;
+; SW[4]      ; VGA_B[2]    ; 4.854 ; 4.839 ; 5.699 ; 5.684 ;
+; SW[4]      ; VGA_B[3]    ; 4.588 ; 4.587 ; 5.391 ; 5.410 ;
+; SW[4]      ; VGA_G[0]    ; 4.860 ; 4.847 ; 5.716 ; 5.696 ;
+; SW[4]      ; VGA_G[1]    ; 4.861 ; 4.865 ; 5.688 ; 5.718 ;
+; SW[4]      ; VGA_G[2]    ; 4.920 ; 4.923 ; 5.775 ; 5.771 ;
+; SW[4]      ; VGA_G[3]    ; 4.699 ; 4.697 ; 5.557 ; 5.518 ;
+; SW[4]      ; VGA_R[0]    ; 5.048 ; 5.046 ; 5.894 ; 5.892 ;
+; SW[4]      ; VGA_R[1]    ; 4.994 ; 5.031 ; 5.796 ; 5.853 ;
+; SW[4]      ; VGA_R[2]    ; 4.913 ; 4.917 ; 5.749 ; 5.753 ;
+; SW[4]      ; VGA_R[3]    ; 4.889 ; 4.891 ; 5.702 ; 5.730 ;
+; SW[5]      ; VGA_B[0]    ; 4.558 ; 4.528 ; 5.361 ; 5.357 ;
+; SW[5]      ; VGA_B[1]    ; 5.040 ; 5.034 ; 5.885 ; 5.879 ;
+; SW[5]      ; VGA_B[2]    ; 4.472 ; 4.453 ; 5.269 ; 5.269 ;
+; SW[5]      ; VGA_B[3]    ; 5.178 ; 5.188 ; 6.044 ; 6.054 ;
+; SW[5]      ; VGA_G[0]    ; 4.645 ; 4.628 ; 5.463 ; 5.465 ;
+; SW[5]      ; VGA_G[1]    ; 5.033 ; 5.053 ; 5.895 ; 5.908 ;
+; SW[5]      ; VGA_G[2]    ; 4.702 ; 4.701 ; 5.519 ; 5.537 ;
+; SW[5]      ; VGA_G[3]    ; 5.120 ; 5.119 ; 5.985 ; 5.979 ;
+; SW[5]      ; VGA_R[0]    ; 4.670 ; 4.664 ; 5.465 ; 5.478 ;
+; SW[5]      ; VGA_R[1]    ; 5.583 ; 5.633 ; 6.472 ; 6.506 ;
+; SW[5]      ; VGA_R[2]    ; 4.707 ; 4.695 ; 5.510 ; 5.524 ;
+; SW[5]      ; VGA_R[3]    ; 5.271 ; 5.289 ; 6.117 ; 6.135 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Output Enable Times                                                                                          ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.856 ; 2.837 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.598 ; 2.579 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.677 ; 2.658 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.689 ; 2.670 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.588 ; 2.569 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.709 ; 2.690 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.688 ; 2.669 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.876 ; 2.857 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.876 ; 2.857 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.876 ; 2.857 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.866 ; 2.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.866 ; 2.847 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.876 ; 2.857 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.856 ; 2.837 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.689 ; 2.670 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Minimum Output Enable Times                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.467 ; 1.467 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.725 ; 1.725 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.467 ; 1.467 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.477 ; 1.477 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.553 ; 1.553 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.564 ; 1.564 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.467 ; 1.467 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.584 ; 1.584 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.563 ; 1.563 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.745 ; 1.745 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.745 ; 1.745 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.745 ; 1.745 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.735 ; 1.735 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.735 ; 1.735 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.745 ; 1.745 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.725 ; 1.725 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.564 ; 1.564 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Output Disable Times                                                                                                 ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 2.636     ; 2.636     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 2.937     ; 2.937     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 2.636     ; 2.636     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 2.646     ; 2.646     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 2.728     ; 2.728     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 2.752     ; 2.752     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 2.636     ; 2.636     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 2.772     ; 2.772     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 2.749     ; 2.749     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 2.963     ; 2.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 2.963     ; 2.963     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 2.957     ; 2.957     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 2.953     ; 2.953     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 2.947     ; 2.947     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 2.957     ; 2.957     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 2.937     ; 2.937     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 2.752     ; 2.752     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Minimum Output Disable Times                                                                                         ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+; DRAM_DQ[*]   ; CLOCK_50   ; 1.514     ; 1.646     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 1.802     ; 1.934     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 1.514     ; 1.646     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 1.524     ; 1.656     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 1.601     ; 1.733     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 1.625     ; 1.757     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 1.514     ; 1.646     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 1.645     ; 1.777     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 1.622     ; 1.754     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 1.828     ; 1.960     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 1.828     ; 1.960     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 1.822     ; 1.954     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 1.818     ; 1.950     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 1.812     ; 1.944     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 1.822     ; 1.954     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 1.802     ; 1.934     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15] ; CLOCK_50   ; 1.625     ; 1.757     ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-----------+-----------+------------+-----------------------------------------------------+
+
+
+----------------
+; MTBF Summary ;
+----------------
+Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+Number of Synchronizer Chains Found: 40
+Shortest Synchronizer Chain: 2 Registers
+Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+Worst Case Available Settling Time: 13.148 ns
+
+Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Synchronizer Summary                                                                                                                                                                                                                                                                                                                                                                      ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; Source Node                                                                                                                      ; Synchronization Node                                                                                                                                                      ; Worst-Case MTBF (Years) ; Typical MTBF (Years)   ; Included in Design MTBF ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1] ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
+; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]          ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1]  ; Greater than 1 Billion  ; Greater than 1 Billion ; Yes                     ;
++----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------+------------------------+-------------------------+
+
+
+Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.148                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.315        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 5.833        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #2: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.215                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 5.623        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #3: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.235                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.593        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 5.642        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #4: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.298                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.311        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 5.987        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #5: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.370                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 5.845        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #6: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.409                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.588        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 5.821        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #7: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.442                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.589        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 5.853        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #8: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.454                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 5.864        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #9: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.572                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 5.982        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #10: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.583                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.592        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 5.991        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #11: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.594                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.071        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #12: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.634                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.590        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.044        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #13: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.643                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.229        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.414        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #14: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.668                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.542        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.126        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #15: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.676                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.152        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #16: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.711                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[8]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ;                        ;              ;                  ; 6.186        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #17: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.718                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.127        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #18: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.731                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.600        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.131        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #19: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.752                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.226        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #20: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.761                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[2]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ;                        ;              ;                  ; 6.360        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #21: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.838                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[3]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ;                        ;              ;                  ; 7.453        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ;                        ;              ;                  ; 6.385        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #22: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.845                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[6]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ;                        ;              ;                  ; 7.402        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ;                        ;              ;                  ; 6.443        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #23: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.845                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[8]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[8] ;                        ;              ;                  ; 7.526        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[8] ;                        ;              ;                  ; 6.319        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #24: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.869                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[9]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ;                        ;              ;                  ; 7.510        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ;                        ;              ;                  ; 6.359        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #25: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.911                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[5]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[5] ;                        ;              ;                  ; 7.532        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[5] ;                        ;              ;                  ; 6.379        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #26: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.914                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[4]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ;                        ;              ;                  ; 7.401        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ;                        ;              ;                  ; 6.513        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #27: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.923                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[7]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ;                        ;              ;                  ; 7.456        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ;                        ;              ;                  ; 6.467        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #28: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.923                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[6]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[6] ;                        ;              ;                  ; 7.525        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[6] ;                        ;              ;                  ; 6.398        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #29: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.942                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[0]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ;                        ;              ;                  ; 7.444        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ;                        ;              ;                  ; 6.498        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #30: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.951                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[4]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[4] ;                        ;              ;                  ; 7.535        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[4] ;                        ;              ;                  ; 6.416        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #31: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.978                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[3]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[3] ;                        ;              ;                  ; 7.528        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[3] ;                        ;              ;                  ; 6.450        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #32: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 13.982                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[5]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ;                        ;              ;                  ; 7.442        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ;                        ;              ;                  ; 6.540        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #33: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 13.990                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.523        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.467        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #34: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.000                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[2]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[2] ;                        ;              ;                  ; 7.527        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[2] ;                        ;              ;                  ; 6.473        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #35: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.002                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[9]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[9] ;                        ;              ;                  ; 7.513        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[9] ;                        ;              ;                  ; 6.489        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #36: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.031                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.591        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.440        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #37: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.093                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[7]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[7] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[7] ;                        ;              ;                  ; 6.569        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #38: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.094                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[0]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0] ;                        ;              ;                  ; 7.524        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0] ;                        ;              ;                  ; 6.570        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #39: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                     ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                    ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                    ;
+; Included in Design MTBF ; Yes                                                                                                                                                                       ;
++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                           ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                   ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                      ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                    ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                       ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                               ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                               ; 14.146                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                  ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                               ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                   ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                      ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                       ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                        ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|delayed_wrptr_g[1]                                          ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                  ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[1] ;                        ;              ;                  ; 7.404        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[1] ;                        ;              ;                  ; 6.742        ;
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
+Synchronizer Chain #40: Worst-Case MTBF is Greater than 1 Billion Years
+===============================================================================
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Chain Summary                                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Property                ; Value                                                                                                                                                                    ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Source Node             ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;
+; Synchronization Node    ; DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;
+; Worst-Case MTBF (years) ; Greater than 1 Billion                                                                                                                                                   ;
+; Typical MTBF (years)    ; Greater than 1 Billion                                                                                                                                                   ;
+; Included in Design MTBF ; Yes                                                                                                                                                                      ;
++-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Statistics                                                                                                                                                                                                                                          ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Property                                                                                                                                                                  ; Value                  ; Clock Period ; Active Edge Rate ; Output Slack ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+; Method of Synchronizer Identification                                                                                                                                     ; User Specified         ;              ;                  ;              ;
+; Worst-Case MTBF (years)                                                                                                                                                   ; Greater than 1 Billion ;              ;                  ;              ;
+; Typical MTBF (years)                                                                                                                                                      ; Greater than 1 Billion ;              ;                  ;              ;
+; Number of Synchronization Registers in Chain                                                                                                                              ; 2                      ;              ;                  ;              ;
+; Available Settling Time (ns)                                                                                                                                              ; 14.159                 ;              ;                  ;              ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec)                                                                                                 ; 15.63                  ;              ;                  ;              ;
+; Source Clock                                                                                                                                                              ;                        ;              ;                  ;              ;
+;  Unknown                                                                                                                                                                  ;                        ;              ;                  ;              ;
+; Synchronization Clock                                                                                                                                                     ;                        ;              ;                  ;              ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0]                                                                                                                      ;                        ; 8.000        ; 125.0 MHz        ;              ;
+; Asynchronous Source                                                                                                                                                       ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|rdptr_g[1]                                                  ;                        ;              ;                  ;              ;
+; Synchronization Registers                                                                                                                                                 ;                        ;              ;                  ;              ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ;                        ;              ;                  ; 7.440        ;
+;  DE0_D5M:inst|Sdram_Control_4Port:u7|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_v5o1:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ;                        ;              ;                  ; 6.719        ;
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
+
+
+
++-------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary                                                                               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Clock                                                ; Setup   ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+; Worst-case Slack                                     ; -0.490  ; 0.170 ; -1.484   ; 0.851   ; 3.733               ;
+;  CLOCK_50                                            ; 14.792  ; 0.188 ; 14.000   ; 0.851   ; 9.267               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -0.490  ; 0.170 ; -1.484   ; 2.398   ; 3.733               ;
+; Design-wide TNS                                      ; -24.984 ; 0.0   ; -348.952 ; 0.0     ; 0.0                 ;
+;  CLOCK_50                                            ; 0.000   ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
+;  inst|u6|altpll_component|auto_generated|pll1|clk[0] ; -24.984 ; 0.000 ; -348.952 ; 0.000   ; 0.000               ;
++------------------------------------------------------+---------+-------+----------+---------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Setup Times                                                                                                  ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; 4.162 ; 4.886 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; 4.162 ; 4.886 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; 4.039 ; 4.609 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; 4.195 ; 4.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; 3.989 ; 4.558 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; 3.703 ; 4.276 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; 3.849 ; 4.364 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; 3.867 ; 4.442 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; 4.195 ; 4.756 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; 3.689 ; 4.201 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; 3.971 ; 4.530 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; 3.696 ; 4.203 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; 3.713 ; 4.224 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; 3.663 ; 4.241 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; 3.721 ; 4.230 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; 3.722 ; 4.233 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; 3.874 ; 4.393 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; 3.710 ; 4.224 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; 3.905 ; 4.446 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+-------+-------+------------+-----------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------+
+; Hold Times                                                                                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port    ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+; SW[*]        ; CLOCK_50   ; -1.138 ; -1.987 ; Rise       ; CLOCK_50                                            ;
+;  SW[0]       ; CLOCK_50   ; -1.174 ; -2.007 ; Rise       ; CLOCK_50                                            ;
+;  SW[1]       ; CLOCK_50   ; -1.138 ; -1.987 ; Rise       ; CLOCK_50                                            ;
+; DRAM_DQ[*]   ; CLOCK_50   ; -1.725 ; -2.460 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]  ; CLOCK_50   ; -1.890 ; -2.688 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]  ; CLOCK_50   ; -1.745 ; -2.526 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]  ; CLOCK_50   ; -1.811 ; -2.549 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]  ; CLOCK_50   ; -1.842 ; -2.630 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]  ; CLOCK_50   ; -1.997 ; -2.818 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]  ; CLOCK_50   ; -1.730 ; -2.464 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]  ; CLOCK_50   ; -1.899 ; -2.681 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]  ; CLOCK_50   ; -1.725 ; -2.460 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]  ; CLOCK_50   ; -1.751 ; -2.485 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]  ; CLOCK_50   ; -1.733 ; -2.513 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10] ; CLOCK_50   ; -1.752 ; -2.489 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11] ; CLOCK_50   ; -1.748 ; -2.486 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12] ; CLOCK_50   ; -1.839 ; -2.575 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13] ; CLOCK_50   ; -1.746 ; -2.481 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14] ; CLOCK_50   ; -1.852 ; -2.606 ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
++--------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Clock to Output Times                                                                                               ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 6.431  ; 6.267  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 6.284  ; 6.232  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 6.431  ; 6.267  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 5.650  ; 5.688  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 5.650  ; 5.688  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 5.538  ; 5.554  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 3.434  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 3.430  ; 3.281  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 3.434  ; 3.299  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 3.410  ; 3.272  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 3.410  ; 3.280  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 3.228  ; 3.089  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 3.207  ; 3.075  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 3.040  ; 2.920  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 3.050  ; 2.930  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 3.042  ; 2.918  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 3.035  ; 2.919  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 3.278  ; 3.155  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 3.026  ; 2.912  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 3.104  ; 3.009  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 3.264  ; 3.154  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 3.210  ; 3.078  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 3.582  ; 3.529  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 7.477  ; 7.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 5.872  ; 5.694  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 5.872  ; 5.846  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 5.578  ; 5.489  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 7.477  ; 7.147  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 5.679  ; 5.582  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 5.894  ; 5.773  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 5.858  ; 5.642  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 5.792  ; 5.739  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 5.729  ; 5.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 5.790  ; 5.709  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 5.922  ; 5.821  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 5.990  ; 5.797  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 6.015  ; 5.897  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 5.995  ; 5.873  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 5.870  ; 5.693  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 5.824  ; 5.740  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 3.456  ; 3.316  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 3.401  ; 3.282  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 3.348  ; 3.248  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 5.256  ; 4.904  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -0.448 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -0.595 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Minimum Clock to Output Times                                                                                       ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; Data Port         ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+; GPIO_1[*]         ; CLOCK_50   ; 3.685  ; 3.643  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[14]       ; CLOCK_50   ; 3.685  ; 3.753  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1[20]       ; CLOCK_50   ; 3.686  ; 3.643  ; Rise       ; CLOCK_50                                            ;
+; GPIO_1_CLKOUT[*]  ; CLOCK_50   ; 3.286  ; 3.374  ; Rise       ; CLOCK_50                                            ;
+;  GPIO_1_CLKOUT[0] ; CLOCK_50   ; 3.286  ; 3.374  ; Rise       ; CLOCK_50                                            ;
+; VGA_CLK           ; CLOCK_50   ; 3.266  ; 3.193  ; Rise       ; CLOCK_50                                            ;
+; DRAM_ADDR[*]      ; CLOCK_50   ; 1.574  ; 1.532  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[0]     ; CLOCK_50   ; 1.789  ; 1.764  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[1]     ; CLOCK_50   ; 1.806  ; 1.779  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[2]     ; CLOCK_50   ; 1.794  ; 1.763  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[3]     ; CLOCK_50   ; 1.787  ; 1.756  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[4]     ; CLOCK_50   ; 1.694  ; 1.661  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[5]     ; CLOCK_50   ; 1.674  ; 1.636  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[6]     ; CLOCK_50   ; 1.585  ; 1.542  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[7]     ; CLOCK_50   ; 1.595  ; 1.553  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[8]     ; CLOCK_50   ; 1.574  ; 1.532  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[9]     ; CLOCK_50   ; 1.584  ; 1.542  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[10]    ; CLOCK_50   ; 1.725  ; 1.696  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_ADDR[11]    ; CLOCK_50   ; 1.575  ; 1.533  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_0         ; CLOCK_50   ; 1.634  ; 1.607  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_BA_1         ; CLOCK_50   ; 1.720  ; 1.702  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CAS_N        ; CLOCK_50   ; 1.670  ; 1.640  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CS_N         ; CLOCK_50   ; 1.883  ; 1.893  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_DQ[*]        ; CLOCK_50   ; 2.138  ; 2.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[0]       ; CLOCK_50   ; 2.138  ; 2.126  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[1]       ; CLOCK_50   ; 2.630  ; 2.712  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[2]       ; CLOCK_50   ; 2.422  ; 2.456  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[3]       ; CLOCK_50   ; 3.881  ; 3.708  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[4]       ; CLOCK_50   ; 2.479  ; 2.515  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[5]       ; CLOCK_50   ; 2.549  ; 2.620  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[6]       ; CLOCK_50   ; 2.472  ; 2.507  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[7]       ; CLOCK_50   ; 2.545  ; 2.606  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[8]       ; CLOCK_50   ; 2.366  ; 2.385  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[9]       ; CLOCK_50   ; 2.394  ; 2.422  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[10]      ; CLOCK_50   ; 2.457  ; 2.478  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[11]      ; CLOCK_50   ; 2.394  ; 2.427  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[12]      ; CLOCK_50   ; 2.622  ; 2.676  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[13]      ; CLOCK_50   ; 2.497  ; 2.535  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[14]      ; CLOCK_50   ; 2.304  ; 2.306  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+;  DRAM_DQ[15]      ; CLOCK_50   ; 2.395  ; 2.416  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_LDQM         ; CLOCK_50   ; 1.803  ; 1.779  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_RAS_N        ; CLOCK_50   ; 1.770  ; 1.747  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_UDQM         ; CLOCK_50   ; 1.772  ; 1.752  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_WE_N         ; CLOCK_50   ; 3.215  ; 2.983  ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ;
+; DRAM_CLK          ; CLOCK_50   ; -1.537 ;        ; Rise       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
+; DRAM_CLK          ; CLOCK_50   ;        ; -1.591 ; Fall       ; inst|u6|altpll_component|auto_generated|pll1|clk[1] ;
++-------------------+------------+--------+--------+------------+-----------------------------------------------------+
+
+
++------------------------------------------------------------+
+; Propagation Delay                                          ;
++------------+-------------+-------+-------+--------+--------+
+; Input Port ; Output Port ; RR    ; RF    ; FR     ; FF     ;
++------------+-------------+-------+-------+--------+--------+
+; SW[4]      ; VGA_B[0]    ; 8.598 ; 8.436 ; 9.243  ; 9.072  ;
+; SW[4]      ; VGA_B[1]    ; 8.447 ; 8.325 ; 9.042  ; 8.914  ;
+; SW[4]      ; VGA_B[2]    ; 8.575 ; 8.414 ; 9.221  ; 9.051  ;
+; SW[4]      ; VGA_B[3]    ; 8.667 ; 8.584 ; 9.283  ; 9.242  ;
+; SW[4]      ; VGA_G[0]    ; 8.652 ; 8.475 ; 9.234  ; 9.066  ;
+; SW[4]      ; VGA_G[1]    ; 9.016 ; 8.875 ; 9.652  ; 9.511  ;
+; SW[4]      ; VGA_G[2]    ; 8.756 ; 8.632 ; 9.342  ; 9.227  ;
+; SW[4]      ; VGA_G[3]    ; 9.210 ; 9.093 ; 9.844  ; 9.730  ;
+; SW[4]      ; VGA_R[0]    ; 8.916 ; 8.791 ; 9.563  ; 9.429  ;
+; SW[4]      ; VGA_R[1]    ; 9.140 ; 9.076 ; 9.701  ; 9.628  ;
+; SW[4]      ; VGA_R[2]    ; 8.626 ; 8.470 ; 9.215  ; 9.063  ;
+; SW[4]      ; VGA_R[3]    ; 8.836 ; 8.685 ; 9.435  ; 9.279  ;
+; SW[5]      ; VGA_B[0]    ; 8.150 ; 7.979 ; 8.767  ; 8.596  ;
+; SW[5]      ; VGA_B[1]    ; 8.882 ; 8.754 ; 9.475  ; 9.347  ;
+; SW[5]      ; VGA_B[2]    ; 8.247 ; 8.086 ; 8.912  ; 8.742  ;
+; SW[5]      ; VGA_B[3]    ; 9.227 ; 9.142 ; 9.829  ; 9.788  ;
+; SW[5]      ; VGA_G[0]    ; 8.549 ; 8.372 ; 9.098  ; 8.924  ;
+; SW[5]      ; VGA_G[1]    ; 9.002 ; 8.861 ; 9.616  ; 9.475  ;
+; SW[5]      ; VGA_G[2]    ; 8.653 ; 8.529 ; 9.203  ; 9.084  ;
+; SW[5]      ; VGA_G[3]    ; 9.192 ; 9.078 ; 9.808  ; 9.694  ;
+; SW[5]      ; VGA_R[0]    ; 8.583 ; 8.458 ; 9.256  ; 9.122  ;
+; SW[5]      ; VGA_R[1]    ; 9.959 ; 9.909 ; 10.554 ; 10.517 ;
+; SW[5]      ; VGA_R[2]    ; 8.412 ; 8.256 ; 9.035  ; 8.879  ;
+; SW[5]      ; VGA_R[3]    ; 9.269 ; 9.113 ; 9.869  ; 9.713  ;
++------------+-------------+-------+-------+--------+--------+
+
+
++----------------------------------------------------------+
+; Minimum Propagation Delay                                ;
++------------+-------------+-------+-------+-------+-------+
+; Input Port ; Output Port ; RR    ; RF    ; FR    ; FF    ;
++------------+-------------+-------+-------+-------+-------+
+; SW[4]      ; VGA_B[0]    ; 4.871 ; 4.857 ; 5.715 ; 5.701 ;
+; SW[4]      ; VGA_B[1]    ; 4.662 ; 4.640 ; 5.472 ; 5.476 ;
+; SW[4]      ; VGA_B[2]    ; 4.854 ; 4.839 ; 5.699 ; 5.684 ;
+; SW[4]      ; VGA_B[3]    ; 4.588 ; 4.587 ; 5.391 ; 5.410 ;
+; SW[4]      ; VGA_G[0]    ; 4.860 ; 4.847 ; 5.716 ; 5.696 ;
+; SW[4]      ; VGA_G[1]    ; 4.861 ; 4.865 ; 5.688 ; 5.718 ;
+; SW[4]      ; VGA_G[2]    ; 4.920 ; 4.923 ; 5.775 ; 5.771 ;
+; SW[4]      ; VGA_G[3]    ; 4.699 ; 4.697 ; 5.557 ; 5.518 ;
+; SW[4]      ; VGA_R[0]    ; 5.048 ; 5.046 ; 5.894 ; 5.892 ;
+; SW[4]      ; VGA_R[1]    ; 4.994 ; 5.031 ; 5.796 ; 5.853 ;
+; SW[4]      ; VGA_R[2]    ; 4.913 ; 4.917 ; 5.749 ; 5.753 ;
+; SW[4]      ; VGA_R[3]    ; 4.889 ; 4.891 ; 5.702 ; 5.730 ;
+; SW[5]      ; VGA_B[0]    ; 4.558 ; 4.528 ; 5.361 ; 5.357 ;
+; SW[5]      ; VGA_B[1]    ; 5.040 ; 5.034 ; 5.885 ; 5.879 ;
+; SW[5]      ; VGA_B[2]    ; 4.472 ; 4.453 ; 5.269 ; 5.269 ;
+; SW[5]      ; VGA_B[3]    ; 5.178 ; 5.188 ; 6.044 ; 6.054 ;
+; SW[5]      ; VGA_G[0]    ; 4.645 ; 4.628 ; 5.463 ; 5.465 ;
+; SW[5]      ; VGA_G[1]    ; 5.033 ; 5.053 ; 5.895 ; 5.908 ;
+; SW[5]      ; VGA_G[2]    ; 4.702 ; 4.701 ; 5.519 ; 5.537 ;
+; SW[5]      ; VGA_G[3]    ; 5.120 ; 5.119 ; 5.985 ; 5.979 ;
+; SW[5]      ; VGA_R[0]    ; 4.670 ; 4.664 ; 5.465 ; 5.478 ;
+; SW[5]      ; VGA_R[1]    ; 5.583 ; 5.633 ; 6.472 ; 6.506 ;
+; SW[5]      ; VGA_R[2]    ; 4.707 ; 4.695 ; 5.510 ; 5.524 ;
+; SW[5]      ; VGA_R[3]    ; 5.271 ; 5.289 ; 6.117 ; 6.135 ;
++------------+-------------+-------+-------+-------+-------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                       ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin              ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times                                                     ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; GPIO_1_CLKIN[1]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[9]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[8]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[15]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[14]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[13]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[12]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[11]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[10]             ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[9]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[8]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[7]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[6]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[5]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[4]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[3]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[2]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[1]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; DRAM_DQ[0]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[31]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[30]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[29]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[28]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[27]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[26]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[25]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[24]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[23]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[22]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[21]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[20]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[19]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[18]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[17]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[16]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[15]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[14]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[13]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[12]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[11]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[10]              ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[9]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[8]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[7]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[6]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[5]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[4]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[3]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[2]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[1]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1[0]               ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_DAT                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; PS2_CLK                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[4]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[5]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; CLOCK_50                ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[0]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[7]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[6]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[3]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[2]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[1]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; SW[0]                   ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[1]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; GPIO_1_CLKIN[0]         ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; KEY[2]                  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.08 V              ; -0.00513 V          ; 0.274 V                              ; 0.267 V                              ; 5.67e-09 s                  ; 4.62e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.08 V             ; -0.00513 V         ; 0.274 V                             ; 0.267 V                             ; 5.67e-09 s                 ; 4.62e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.08 V              ; -0.00596 V          ; 0.305 V                              ; 0.266 V                              ; 5.3e-09 s                   ; 4.39e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.08e-06 V                  ; 3.08 V             ; -0.00596 V         ; 0.305 V                             ; 0.266 V                             ; 5.3e-09 s                  ; 4.39e-09 s                 ; Yes                       ; Yes                       ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.08e-06 V                   ; 3.13 V              ; -0.0523 V           ; 0.237 V                              ; 0.168 V                              ; 6.67e-10 s                  ; 6.11e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 3.08e-06 V                  ; 3.13 V             ; -0.0523 V          ; 0.237 V                             ; 0.168 V                             ; 6.67e-10 s                 ; 6.11e-10 s                 ; No                        ; No                        ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.06e-06 V                   ; 3.12 V              ; -0.0308 V           ; 0.224 V                              ; 0.218 V                              ; 1.32e-09 s                  ; 1.07e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 2.06e-06 V                  ; 3.12 V             ; -0.0308 V          ; 0.224 V                             ; 0.218 V                             ; 1.32e-09 s                 ; 1.07e-09 s                 ; No                        ; Yes                       ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.02e-06 V                   ; 3.14 V              ; -0.0402 V           ; 0.146 V                              ; 0.156 V                              ; 4.62e-10 s                  ; 4.36e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.02e-06 V                  ; 3.14 V             ; -0.0402 V          ; 0.146 V                             ; 0.156 V                             ; 4.62e-10 s                 ; 4.36e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin              ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; DRAM_LDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_UDQM        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_1        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_BA_0        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CKE         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_CS_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_RAS_N       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_WE_N        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_CLK         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; VGA_HS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_VS           ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_ADDR[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_ADDR[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1_CLKOUT[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX0[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX1[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX2[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; HEX3[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; LEDG[9]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[8]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[7]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[6]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[5]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[4]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[3]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[2]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
+; LEDG[1]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; LEDG[0]          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_B[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_G[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[3]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[2]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[1]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; VGA_R[0]         ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; DRAM_DQ[15]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[14]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[13]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[12]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[11]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[10]      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[9]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[8]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[7]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[6]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[5]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[4]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[3]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
+; DRAM_DQ[2]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[1]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; DRAM_DQ[0]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[31]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[30]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[29]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[28]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[27]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[26]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[25]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[24]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[23]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[22]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[21]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[20]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[19]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[18]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[17]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[16]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[15]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[14]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[13]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[12]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[11]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[10]       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[9]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[8]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[7]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[6]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[5]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[4]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[3]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[2]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[1]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; GPIO_1[0]        ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
+; PS2_DAT          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; PS2_CLK          ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+; ~ALTERA_DCLK~    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.52e-08 V                   ; 3.58 V              ; -0.064 V            ; 0.234 V                              ; 0.085 V                              ; 2.93e-10 s                  ; 3.07e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.52e-08 V                  ; 3.58 V             ; -0.064 V           ; 0.234 V                             ; 0.085 V                             ; 2.93e-10 s                 ; 3.07e-10 s                 ; Yes                       ; Yes                       ;
++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Setup Transfers                                                                                                                                       ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3231     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11699    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Hold Transfers                                                                                                                                        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock                                          ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50                                            ; CLOCK_50                                            ; 3231     ; 0        ; 0        ; 0        ;
+; CLOCK_50                                            ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 141      ; 0        ; 0        ; 0        ;
+; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 11699    ; 0        ; 0        ; 0        ;
++-----------------------------------------------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Recovery Transfers                                                                                           ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
++--------------------------------------------------------------------------------------------------------------+
+; Removal Transfers                                                                                            ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+; CLOCK_50   ; CLOCK_50                                            ; 519      ; 0        ; 0        ; 0        ;
+; CLOCK_50   ; inst|u6|altpll_component|auto_generated|pll1|clk[0] ; 302      ; 0        ; 0        ; 0        ;
++------------+-----------------------------------------------------+----------+----------+----------+----------+
+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths                            ;
++---------------------------------+-------+------+
+; Property                        ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks                  ; 0     ; 0    ;
+; Unconstrained Clocks            ; 5     ; 5    ;
+; Unconstrained Input Ports       ; 43    ; 43   ;
+; Unconstrained Input Port Paths  ; 428   ; 428  ;
+; Unconstrained Output Ports      ; 89    ; 89   ;
+; Unconstrained Output Port Paths ; 530   ; 530  ;
++---------------------------------+-------+------+
+
+
++------------------------------------+
+; TimeQuest Timing Analyzer Messages ;
++------------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
+    Info: Processing started: Mon Mar 17 11:17:27 2014
+Info: Command: quartus_sta DE0_D5M -c DE0_D5M
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (332164): Evaluating HDL-embedded SDC commands
+    Info (332165): Entity dcfifo_v5o1
+        Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a* 
+        Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a* 
+Info (332104): Reading SDC File: 'DE0_D5M.sdc'
+Info (332110): Deriving PLL clocks
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[0]} {inst|u6|altpll_component|auto_generated|pll1|clk[0]}
+    Info (332110): create_generated_clock -source {inst|u6|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 2 -multiply_by 5 -phase -117.00 -duty_cycle 50.00 -name {inst|u6|altpll_component|auto_generated|pll1|clk[1]} {inst|u6|altpll_component|auto_generated|pll1|clk[1]}
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case setup slack is -0.490
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.490             -24.984 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.792               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.332
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.332               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.358               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is -1.484
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -1.484            -348.952 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.000               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.548
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.548               0.000 CLOCK_50 
+    Info (332119):     4.100               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.733
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.733               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.580               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 10.993 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 0.022
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.022               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    15.359               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.298
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.298               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.312               0.000 CLOCK_50 
+Critical Warning (332148): Timing requirements not met
+    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
+Info (332146): Worst-case recovery slack is -0.828
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    -0.828            -158.364 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    14.667               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 1.412
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.412               0.000 CLOCK_50 
+    Info (332119):     3.602               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.739
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.739               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.562               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 11.499 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info: Analyzing Fast 1200mV 0C Model
+Warning (332060): Node: ps2:inst6|clk_div[8] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: ps2:inst6|ps2_clk_in was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|rClk[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: GPIO_1_CLKIN[0] was determined to be a clock but was found without an associated clock assignment.
+Warning (332060): Node: DE0_D5M:inst|I2C_CCD_Config:u8|mI2C_CTRL_CLK was determined to be a clock but was found without an associated clock assignment.
+Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
+    Critical Warning (332169): From CLOCK_50 (Rise) to CLOCK_50 (Rise) (setup and hold)
+    Critical Warning (332169): From CLOCK_50 (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+    Critical Warning (332169): From inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) to inst|u6|altpll_component|auto_generated|pll1|clk[0] (Rise) (setup and hold)
+Info (332146): Worst-case setup slack is 1.392
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     1.392               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    16.970               0.000 CLOCK_50 
+Info (332146): Worst-case hold slack is 0.170
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.170               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     0.188               0.000 CLOCK_50 
+Info (332146): Worst-case recovery slack is 0.783
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.783               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):    16.478               0.000 CLOCK_50 
+Info (332146): Worst-case removal slack is 0.851
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.851               0.000 CLOCK_50 
+    Info (332119):     2.398               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+Info (332146): Worst-case minimum pulse width slack is 3.746
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     3.746               0.000 inst|u6|altpll_component|auto_generated|pll1|clk[0] 
+    Info (332119):     9.267               0.000 CLOCK_50 
+Info (332114): Report Metastability: Found 40 synchronizer chains.
+    Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+    Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
+
+    Info (332114): Number of Synchronizer Chains Found: 40
+    Info (332114): Shortest Synchronizer Chain: 2 Registers
+    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
+    Info (332114): Worst Case Available Settling Time: 13.148 ns
+    Info (332114): 
+    Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
+    Info (332114):   - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 6.5
+    Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions.
+    Info (332114):   - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 9.9
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 29 warnings
+    Info: Peak virtual memory: 555 megabytes
+    Info: Processing ended: Mon Mar 17 11:17:31 2014
+    Info: Elapsed time: 00:00:04
+    Info: Total CPU time (on all processors): 00:00:04
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary
new file mode 100644
index 0000000..b8b9e43
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.sta.summary
@@ -0,0 +1,125 @@
+------------------------------------------------------------
+TimeQuest Timing Analyzer Summary
+------------------------------------------------------------
+
+Type  : Slow 1200mV 85C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.490
+TNS   : -24.984
+
+Type  : Slow 1200mV 85C Model Setup 'CLOCK_50'
+Slack : 14.792
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.332
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Hold 'CLOCK_50'
+Slack : 0.358
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -1.484
+TNS   : -348.952
+
+Type  : Slow 1200mV 85C Model Recovery 'CLOCK_50'
+Slack : 14.000
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'CLOCK_50'
+Slack : 1.548
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 4.100
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.733
+TNS   : 0.000
+
+Type  : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.580
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.022
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 15.359
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.298
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.312
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : -0.828
+TNS   : -158.364
+
+Type  : Slow 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 14.667
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 1.412
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.602
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.739
+TNS   : 0.000
+
+Type  : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.562
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 1.392
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Setup 'CLOCK_50'
+Slack : 16.970
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.170
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Hold 'CLOCK_50'
+Slack : 0.188
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 0.783
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Recovery 'CLOCK_50'
+Slack : 16.478
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'CLOCK_50'
+Slack : 0.851
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Removal 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 2.398
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'inst|u6|altpll_component|auto_generated|pll1|clk[0]'
+Slack : 3.746
+TNS   : 0.000
+
+Type  : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
+Slack : 9.267
+TNS   : 0.000
+
+------------------------------------------------------------
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb
new file mode 100644
index 0000000..8a35815
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.tis_db_list.ddb
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
new file mode 100644
index 0000000..278fabe
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v
@@ -0,0 +1,379 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		VGA_X,							//	VGA X scan coord
+		VGA_Y,							//	VGA Y scan coord
+		VGA_ACTIVE,						//	VGA ACTIVE
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+output	[11:0]		VGA_X;				//	VGA X scan coord
+output	[11:0]		VGA_Y;				//	VGA Y scan coord
+output         VGA_ACTIVE;          // VGA ACTIVE
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[9:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[9:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[9:0]		VGA_B;   				//	VGA Blue[9:0]
+wire	[11:0]		VGA_X;	 				//	VGA X scan 
+wire	[11:0]		VGA_Y;   				//	VGA Y scan
+wire				VGA_ACTIVE;
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:0];
+assign	VGA_G		=	oVGA_G[9:0];
+assign	VGA_B		=	oVGA_B[9:0];
+
+// vga scan coordinates
+wire	[11:0]	oVGA_X;
+wire	[11:0]	oVGA_Y;
+assign	VGA_X		=	oVGA_Y;
+assign	VGA_Y		=	oVGA_X;
+
+// vga output active
+wire 	oVGA_ACTIVE;
+assign VGA_ACTIVE = oVGA_ACTIVE;
+
+
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							// VGA Scan Coordinates
+							.oVGA_X(oVGA_X),
+							.oVGA_Y(oVGA_Y),
+							.oVGA_ACTIVE(oVGA_ACTIVE),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak
new file mode 100644
index 0000000..8059c4c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/DE0_D5M.v.bak
@@ -0,0 +1,369 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE0_D5M
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 12/03/14  :| DE0 support
+// --------------------------------------------------------------------
+
+module DE0_D5M
+	(
+		////////////////////	Clock Input	 	////////////////////	 
+		CLOCK_50,						//	50 MHz
+		////////////////////	Push Button		////////////////////
+		KEY,								//	Pushbutton[2:0]
+		////////////////////	DPDT Switch		////////////////////
+		SW,								//	Toggle Switch[9:0]
+		////////////////////////	LED		////////////////////////
+		LEDG,								//	LED Green[9:0]
+		////////////////////	7-SEG Dispaly	////////////////////
+		HEX0,								//	Seven Segment Digit 0
+		HEX1,								//	Seven Segment Digit 1
+		HEX2,								//	Seven Segment Digit 2
+		HEX3,								//	Seven Segment Digit 3
+		/////////////////////	SDRAM Interface		////////////////
+		DRAM_DQ,							//	SDRAM Data bus 16 Bits
+		DRAM_ADDR,						//	SDRAM Address bus 12 Bits
+		DRAM_LDQM,						//	SDRAM Low-byte Data Mask 
+		DRAM_UDQM,						//	SDRAM High-byte Data Mask
+		DRAM_WE_N,						//	SDRAM Write Enable
+		DRAM_CAS_N,						//	SDRAM Column Address Strobe
+		DRAM_RAS_N,						//	SDRAM Row Address Strobe
+		DRAM_CS_N,						//	SDRAM Chip Select
+		DRAM_BA_0,						//	SDRAM Bank Address 0
+		DRAM_BA_1,						//	SDRAM Bank Address 0
+		DRAM_CLK,						//	SDRAM Clock
+		DRAM_CKE,						//	SDRAM Clock Enable
+		////////////////////	VGA		////////////////////////////
+		VGA_HS,							//	VGA H_SYNC
+		VGA_VS,							//	VGA V_SYNC
+		VGA_R,   						//	VGA Red[3:0]
+		VGA_G,	 						//	VGA Green[3:0]
+		VGA_B,  							//	VGA Blue[3:0]
+		VGA_CLK,                   // VGA Clk
+		VGA_X,							//	VGA X scan coord
+		VGA_Y,							//	VGA Y scan coord
+		////////////////////	GPIO	////////////////////////////
+		//GPIO_0,							//	GPIO Connection 0
+		GPIO_1_CLKIN,              // GPIO Connection 1 CLK INPUTS
+		GPIO_1_CLKOUT,             // GPIO Connection 1 CLK OUTPUTS
+		GPIO_1							//	GPIO Connection 1
+	);
+
+////////////////////////	Clock Input	 	////////////////////////
+input			CLOCK_50;				//	50 MHz
+////////////////////////	Push Button		////////////////////////
+input	[2:0]	KEY;						//	Pushbutton[3:0]
+////////////////////////	DPDT Switch		////////////////////////
+input	[9:0]	SW;						//	Toggle Switch[9:0]
+////////////////////////////	LED		////////////////////////////
+output	[9:0]	LEDG;					//	LED Green[7:0]
+////////////////////////	7-SEG Dispaly	////////////////////////
+output	[6:0]	HEX0;					//	Seven Segment Digit 0
+output	[6:0]	HEX1;					//	Seven Segment Digit 1
+output	[6:0]	HEX2;					//	Seven Segment Digit 2
+output	[6:0]	HEX3;					//	Seven Segment Digit 3
+///////////////////////		SDRAM Interface	////////////////////////
+inout	[15:0]	DRAM_DQ;				//	SDRAM Data bus 16 Bits
+output[11:0]	DRAM_ADDR;			//	SDRAM Address bus 12 Bits
+output			DRAM_LDQM;			//	SDRAM Low-byte Data Mask 
+output			DRAM_UDQM;			//	SDRAM High-byte Data Mask
+output			DRAM_WE_N;			//	SDRAM Write Enable
+output			DRAM_CAS_N;			//	SDRAM Column Address Strobe
+output			DRAM_RAS_N;			//	SDRAM Row Address Strobe
+output			DRAM_CS_N;			//	SDRAM Chip Select
+output			DRAM_BA_0;			//	SDRAM Bank Address 0
+output			DRAM_BA_1;			//	SDRAM Bank Address 0
+output			DRAM_CLK;			//	SDRAM Clock
+output			DRAM_CKE;			//	SDRAM Clock Enable
+////////////////////////	VGA			////////////////////////////
+output			VGA_HS;				//	VGA H_SYNC
+output			VGA_VS;				//	VGA V_SYNC
+output	[3:0]	VGA_R;   			//	VGA Red[3:0]
+output	[3:0]	VGA_G;	 			//	VGA Green[3:0]
+output	[3:0]	VGA_B;   			//	VGA Blue[3:0]
+output         VGA_CLK;          // VGA Clk
+output	[11:0]		VGA_X;				//	VGA X scan coord
+output	[11:0]		VGA_Y;				//	VGA Y scan coord
+////////////////////////	GPIO	////////////////////////////////
+
+input	[1:0]	   GPIO_1_CLKIN;				//	GPIO Connection 1 - need stand alone inputs for external clock, pins on the board rewired
+output [1:0]	GPIO_1_CLKOUT;				//	GPIO Connection 1 - need stand alone outputs for external clock, pins on the board rewired
+inout	[31:0]	GPIO_1;				//	GPIO Connection 1
+///////////////////////////////////////////////////////////////////
+//=============================================================================
+// REG/WIRE declarations
+//=============================================================================
+
+//	CCD
+wire	[11:0]	CCD_DATA;
+wire				CCD_SDAT;
+wire				CCD_SCLK;
+wire				CCD_FLASH;
+wire				CCD_FVAL;
+wire				CCD_LVAL;
+wire				CCD_PIXCLK;
+wire				CCD_MCLK;				//	CCD Master Clock
+
+wire	[15:0]	Read_DATA1;
+wire	[15:0]	Read_DATA2;
+wire				VGA_CTRL_CLK;
+wire	[11:0]	mCCD_DATA;
+wire				mCCD_DVAL;
+wire				mCCD_DVAL_d;
+wire	[15:0]	X_Cont;
+wire	[15:0]	Y_Cont;
+wire	[9:0]		X_ADDR;
+wire	[31:0]	Frame_Cont;
+wire				DLY_RST_0;
+wire				DLY_RST_1;
+wire				DLY_RST_2;
+wire				Read;
+reg	[11:0]	rCCD_DATA;
+reg				rCCD_LVAL;
+reg				rCCD_FVAL;
+wire	[11:0]	sCCD_R;
+wire	[11:0]	sCCD_G;
+wire	[11:0]	sCCD_B;
+wire				sCCD_DVAL;
+wire	[9:0]		VGA_R;   				//	VGA Red[9:0]
+wire	[9:0]		VGA_G;	 				//	VGA Green[9:0]
+wire	[9:0]		VGA_B;   				//	VGA Blue[9:0]
+wire	[11:0]		VGA_X;	 				//	VGA X scan 
+wire	[11:0]		VGA_Y;   				//	VGA Y scan
+reg	[1:0]		rClk;
+wire				sdram_ctrl_clk;
+
+//=============================================================================
+// Structural coding
+//=============================================================================
+assign	CCD_DATA[0]	=	GPIO_1[11];
+assign	CCD_DATA[1]	=	GPIO_1[10];
+assign	CCD_DATA[2]	=	GPIO_1[9];
+assign	CCD_DATA[3]	=	GPIO_1[8];
+assign	CCD_DATA[4]	=	GPIO_1[7];
+assign	CCD_DATA[5]	=	GPIO_1[6];
+assign	CCD_DATA[6]	=	GPIO_1[5];
+assign	CCD_DATA[7]	=	GPIO_1[4];
+assign	CCD_DATA[8]	=	GPIO_1[3];
+assign	CCD_DATA[9]	=	GPIO_1[2];
+assign	CCD_DATA[10]=	GPIO_1[1];
+assign	CCD_DATA[11]=	GPIO_1[0];
+assign	GPIO_1_CLKOUT[0]	=	CCD_MCLK;
+assign	CCD_FVAL	   =	GPIO_1[18];
+assign	CCD_LVAL	   =	GPIO_1[17];
+assign	CCD_PIXCLK	=	GPIO_1_CLKIN[0]; 
+assign	GPIO_1[15]	=	1'b1;  // tRIGGER
+assign	GPIO_1[14]	=	DLY_RST_1;
+
+assign	LEDG		   =	Y_Cont;
+
+assign	VGA_CTRL_CLK=	rClk[0];
+assign	VGA_CLK		=	~rClk[0];
+
+always@(posedge CLOCK_50)	rClk	<=	rClk+1;
+
+wire	[9:0]	oVGA_R;
+wire	[9:0]	oVGA_G;
+wire	[9:0]	oVGA_B;
+assign	VGA_R		=	oVGA_R[9:0];
+assign	VGA_G		=	oVGA_G[9:0];
+assign	VGA_B		=	oVGA_B[9:0];
+
+
+wire	[11:0]	oVGA_X;
+wire	[11:0]	oVGA_Y;
+assign	VGA_X		=	oVGA_Y;
+assign	VGA_Y		=	oVGA_X;
+
+
+
+always@(posedge CCD_PIXCLK)
+begin
+	rCCD_DATA	<=	CCD_DATA;
+	rCCD_LVAL	<=	CCD_LVAL;
+	rCCD_FVAL	<=	CCD_FVAL;
+end
+
+VGA_Controller		u1	(	//	Host Side
+							.oRequest   (Read),
+//							.iRed       (10'b1111111111),
+//							.iGreen     (10'b0000000000),
+//							.iBlue      (10'b0000000000),
+							.iRed       (Read_DATA2[9:0]),
+							.iGreen     ({Read_DATA1[14:10],Read_DATA2[14:10]}),
+							.iBlue      (Read_DATA1[9:0]),
+							//	VGA Side
+							.oVGA_R     (oVGA_R),
+							.oVGA_G     (oVGA_G),
+							.oVGA_B     (oVGA_B),
+							.oVGA_H_SYNC(VGA_HS),
+							.oVGA_V_SYNC(VGA_VS),
+							// VGA Scan Coordinates
+							.oVGA_X(oVGA_X),
+							.oVGA_Y(oVGA_Y),
+							//	Control Signal
+							.iCLK       (VGA_CTRL_CLK),
+							.iRST_N     (DLY_RST_2)
+						);
+
+
+Reset_Delay			u2	(	
+							.iCLK  (CLOCK_50),
+							.iRST  (KEY[0]),
+							.oRST_0(DLY_RST_0),
+							.oRST_1(DLY_RST_1),
+							.oRST_2(DLY_RST_2)
+						);
+
+CCD_Capture			u3	(	
+							.oDATA      (mCCD_DATA),
+							.oDVAL      (mCCD_DVAL),
+							.oX_Cont    (X_Cont),
+							.oY_Cont    (Y_Cont),
+							.oFrame_Cont(Frame_Cont),
+							.iDATA      (rCCD_DATA),
+							.iFVAL      (rCCD_FVAL),
+							.iLVAL      (rCCD_LVAL),
+							.iSTART     (!KEY[1]),
+							.iEND       (!KEY[2]),
+							.iCLK       (CCD_PIXCLK),
+							.iRST       (DLY_RST_2)
+						);
+
+RAW2RGB				u4	(	
+						   .iCLK   (CCD_PIXCLK),
+							.iRST   (DLY_RST_1),
+							.iDATA  (mCCD_DATA),
+							.iDVAL  (mCCD_DVAL),
+							.oRed   (sCCD_R),
+							.oGreen (sCCD_G),
+							.oBlue  (sCCD_B),
+							.oDVAL  (sCCD_DVAL),
+							.iX_Cont(X_Cont),
+							.iY_Cont(Y_Cont)
+						);
+
+SEG7_LUT_8 			u5	(	
+							.oSEG0(HEX0),
+							.oSEG1(HEX1),
+							.oSEG2(HEX2),
+							.oSEG3(HEX3),
+							.oSEG4(),
+							.oSEG5(),
+							.oSEG6(),
+							.oSEG7(),
+							.iDIG (Frame_Cont[31:0])
+						);
+
+sdram_pll 			u6	(
+							.inclk0(CLOCK_50),
+							.c0    (sdram_ctrl_clk),
+							.c1    (DRAM_CLK)
+						);
+
+assign CCD_MCLK = rClk[0];
+
+Sdram_Control_4Port	u7	(	//	HOST Side						
+								 .REF_CLK     (CLOCK_50),
+						       .RESET_N     (1'b1),
+							    .CLK    	  (sdram_ctrl_clk),
+
+									//	FIFO Write Side 1
+							    .WR1_DATA	  ({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
+							    .WR1     	  (sCCD_DVAL),
+								 .WR1_ADDR	  (0),
+								 .WR1_MAX_ADDR(640*480),
+								 .WR1_LENGTH  (9'h100),
+								 .WR1_LOAD	  (!DLY_RST_0),
+								 .WR1_CLK	  (~CCD_PIXCLK),
+
+								  //	FIFO Write Side 2
+								 .WR2_DATA    ({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
+								 .WR2			  (sCCD_DVAL),
+								 .WR2_ADDR    (22'h100000),
+								 .WR2_MAX_ADDR(22'h100000+640*480),
+								 .WR2_LENGTH  (9'h100),
+								 .WR2_LOAD    (!DLY_RST_0),
+								 .WR2_CLK     (~CCD_PIXCLK),
+
+
+								  //	FIFO Read Side 1
+						       .RD1_DATA	  (Read_DATA1),
+								 .RD1			  (Read),
+				        	    .RD1_ADDR    (0),
+								 .RD1_MAX_ADDR(640*480),
+								 .RD1_LENGTH  (9'h100),
+								 .RD1_LOAD	  (!DLY_RST_0),
+								 .RD1_CLK	  (~VGA_CTRL_CLK),
+							
+								  //	FIFO Read Side 2
+						       .RD2_DATA	  (Read_DATA2),
+								 .RD2         (Read),
+								 .RD2_ADDR    (22'h100000),
+								 .RD2_MAX_ADDR(22'h100000+640*480),
+								 .RD2_LENGTH  (9'h100),
+								 .RD2_LOAD    (!DLY_RST_0),
+								 .RD2_CLK     (~VGA_CTRL_CLK),
+							
+								  //	SDRAM Side
+						       .SA			  (DRAM_ADDR),
+						       .BA			  ({DRAM_BA_1,DRAM_BA_0}),
+								 .CS_N		  (DRAM_CS_N),
+        					    .CKE			  (DRAM_CKE),
+								 .RAS_N		  (DRAM_RAS_N),
+								 .CAS_N		  (DRAM_CAS_N),
+								 .WE_N		  (DRAM_WE_N),
+								 .DQ			  (DRAM_DQ),
+								 .DQM			  ({DRAM_UDQM,DRAM_LDQM})
+						       );
+
+
+
+I2C_CCD_Config 		u8	(	//	Host Side
+								 .iCLK			  (CLOCK_50),
+								 .iRST_N         (DLY_RST_2),
+								 .iZOOM_MODE_SW  (SW[2]),
+								 .iEXPOSURE_ADJ  (SW[1]),
+								 .iEXPOSURE_DEC_p(SW[0]),
+								  //	I2C Side
+								 .I2C_SCLK		  (GPIO_1[20]),
+								 .I2C_SDAT		  (GPIO_1[19])
+							   );
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Line_Buffer.qip
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v
new file mode 100644
index 0000000..22e2411
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Control_4Port.v
@@ -0,0 +1,567 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Sdram_Control_4Port
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module Sdram_Control_4Port(
+		//	HOST Side
+        REF_CLK,
+        RESET_N,
+		CLK,
+		//	FIFO Write Side 1
+        WR1_DATA,
+		WR1,
+		WR1_ADDR,
+		WR1_MAX_ADDR,
+		WR1_LENGTH,
+		WR1_LOAD,
+		WR1_CLK,
+		//	FIFO Write Side 2
+        WR2_DATA,
+		WR2,
+		WR2_ADDR,
+		WR2_MAX_ADDR,
+		WR2_LENGTH,
+		WR2_LOAD,
+		WR2_CLK,
+		//	FIFO Read Side 1
+        RD1_DATA,
+		RD1,
+		RD1_ADDR,
+		RD1_MAX_ADDR,
+		RD1_LENGTH,
+		RD1_LOAD,	
+		RD1_CLK,
+		//	FIFO Read Side 2
+        RD2_DATA,
+		RD2,
+		RD2_ADDR,
+		RD2_MAX_ADDR,
+		RD2_LENGTH,
+		RD2_LOAD,
+		RD2_CLK,
+		//	SDRAM Side
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N,
+        DQ,
+        DQM,
+        );
+
+
+`include        "Sdram_Params.h"
+//	HOST Side
+input                           REF_CLK;                //System Clock
+input                           RESET_N;                //System Reset
+input 							CLK;
+//	FIFO Write Side 1
+input   [`DSIZE-1:0]            WR1_DATA;               //Data input
+input							WR1;					//Write Request
+input	[`ASIZE-1:0]			WR1_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR1_MAX_ADDR;			//Write max address
+input	[8:0]					WR1_LENGTH;				//Write length
+input							WR1_LOAD;				//Write register load & fifo clear
+input							WR1_CLK;				//Write fifo clock
+
+//	FIFO Write Side 2
+input   [`DSIZE-1:0]            WR2_DATA;               //Data input
+input							WR2;					//Write Request
+input	[`ASIZE-1:0]			WR2_ADDR;				//Write start address
+input	[`ASIZE-1:0]			WR2_MAX_ADDR;			//Write max address
+input	[8:0]					WR2_LENGTH;				//Write length
+input							WR2_LOAD;				//Write register load & fifo clear
+input							WR2_CLK;				//Write fifo clock
+
+//	FIFO Read Side 1
+output  [`DSIZE-1:0]            RD1_DATA;               //Data output
+input							RD1;					//Read Request
+input	[`ASIZE-1:0]			RD1_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD1_MAX_ADDR;			//Read max address
+input	[8:0]					RD1_LENGTH;				//Read length
+input							RD1_LOAD;				//Read register load & fifo clear
+input							RD1_CLK;				//Read fifo clock
+
+//	FIFO Read Side 2
+output  [`DSIZE-1:0]            RD2_DATA;               //Data output
+input							RD2;					//Read Request
+input	[`ASIZE-1:0]			RD2_ADDR;				//Read start address
+input	[`ASIZE-1:0]			RD2_MAX_ADDR;			//Read max address
+input	[8:0]					RD2_LENGTH;				//Read length
+input							RD2_LOAD;				//Read register load & fifo clear
+input							RD2_CLK;				//Read fifo clock
+
+//	SDRAM Side
+output  [11:0]                  SA;                     //SDRAM address output
+output  [1:0]                   BA;                     //SDRAM bank address
+output  [1:0]                   CS_N;                   //SDRAM Chip Selects
+output                          CKE;                    //SDRAM clock enable
+output                          RAS_N;                  //SDRAM Row address Strobe
+output                          CAS_N;                  //SDRAM Column address Strobe
+output                          WE_N;                   //SDRAM write enable
+inout   [`DSIZE-1:0]            DQ;                     //SDRAM data bus
+output  [`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+
+//	Internal Registers/Wires
+//	Controller
+reg		[`ASIZE-1:0]			mADDR;					//Internal address
+reg		[8:0]					mLENGTH;				//Internal length
+reg		[`ASIZE-1:0]			rWR1_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR1_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR1_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rWR2_ADDR;				//Register write address				
+reg		[`ASIZE-1:0]			rWR2_MAX_ADDR;			//Register max write address				
+reg		[8:0]					rWR2_LENGTH;			//Register write length
+reg		[`ASIZE-1:0]			rRD1_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD1_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD1_LENGTH;			//Register read length
+reg		[`ASIZE-1:0]			rRD2_ADDR;				//Register read address
+reg		[`ASIZE-1:0]			rRD2_MAX_ADDR;			//Register max read address
+reg		[8:0]					rRD2_LENGTH;			//Register read length
+reg		[1:0]					WR_MASK;				//Write port active mask
+reg		[1:0]					RD_MASK;				//Read port active mask
+reg								mWR_DONE;				//Flag write done, 1 pulse SDR_CLK
+reg								mRD_DONE;				//Flag read done, 1 pulse SDR_CLK
+reg								mWR,Pre_WR;				//Internal WR edge capture
+reg								mRD,Pre_RD;				//Internal RD edge capture
+reg 	[9:0] 					ST;						//Controller status
+reg		[1:0] 					CMD;					//Controller command
+reg								PM_STOP;				//Flag page mode stop
+reg								PM_DONE;				//Flag page mode done
+reg								Read;					//Flag read active
+reg								Write;					//Flag write active
+reg	    [`DSIZE-1:0]           	mDATAOUT;               //Controller Data output
+wire    [`DSIZE-1:0]           	mDATAIN;                //Controller Data input
+wire    [`DSIZE-1:0]           	mDATAIN1;                //Controller Data input 1
+wire    [`DSIZE-1:0]           	mDATAIN2;                //Controller Data input 2
+wire                          	CMDACK;                 //Controller command acknowledgement
+//	DRAM Control
+reg  	[`DSIZE/8-1:0]          DQM;                    //SDRAM data mask lines
+reg     [11:0]                  SA;                     //SDRAM address output
+reg     [1:0]                   BA;                     //SDRAM bank address
+reg     [1:0]                   CS_N;                   //SDRAM Chip Selects
+reg                             CKE;                    //SDRAM clock enable
+reg                             RAS_N;                  //SDRAM Row address Strobe
+reg                             CAS_N;                  //SDRAM Column address Strobe
+reg                             WE_N;                   //SDRAM write enable
+wire    [`DSIZE-1:0]            DQOUT;					//SDRAM data out link
+wire  	[`DSIZE/8-1:0]          IDQM;                   //SDRAM data mask lines
+wire    [11:0]                  ISA;                    //SDRAM address output
+wire    [1:0]                   IBA;                    //SDRAM bank address
+wire    [1:0]                   ICS_N;                  //SDRAM Chip Selects
+wire                            ICKE;                   //SDRAM clock enable
+wire                            IRAS_N;                 //SDRAM Row address Strobe
+wire                            ICAS_N;                 //SDRAM Column address Strobe
+wire                            IWE_N;                  //SDRAM write enable
+//	FIFO Control
+reg								OUT_VALID;				//Output data request to read side fifo
+reg								IN_REQ;					//Input	data request to write side fifo
+wire	[8:0]					write_side_fifo_rusedw1;
+wire	[8:0]					read_side_fifo_wusedw1;
+wire	[8:0]					write_side_fifo_rusedw2;
+wire	[8:0]					read_side_fifo_wusedw2;
+//	DRAM Internal Control
+wire    [`ASIZE-1:0]            saddr;
+wire                            load_mode;
+wire                            nop;
+wire                            reada;
+wire                            writea;
+wire                            refresh;
+wire                            precharge;
+wire                            oe;
+wire							ref_ack;
+wire							ref_req;
+wire							init_req;
+wire							cm_ack;
+wire							active;
+wire                            CLK;
+wire							CCD_CLK;
+
+control_interface control1 (
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .CMD(CMD),
+                .ADDR(mADDR),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+                .PRECHARGE(precharge),
+                .LOAD_MODE(load_mode),
+                .SADDR(saddr),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .CMD_ACK(CMDACK)
+                );
+
+command command1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .SADDR(saddr),
+                .NOP(nop),
+                .READA(reada),
+                .WRITEA(writea),
+                .REFRESH(refresh),
+				.LOAD_MODE(load_mode),
+                .PRECHARGE(precharge),
+                .REF_REQ(ref_req),
+				.INIT_REQ(init_req),
+                .REF_ACK(ref_ack),
+                .CM_ACK(cm_ack),
+                .OE(oe),
+				.PM_STOP(PM_STOP),
+				.PM_DONE(PM_DONE),
+                .SA(ISA),
+                .BA(IBA),
+                .CS_N(ICS_N),
+                .CKE(ICKE),
+                .RAS_N(IRAS_N),
+                .CAS_N(ICAS_N),
+                .WE_N(IWE_N)
+                );
+                
+sdr_data_path data_path1(
+                .CLK(CLK),
+                .RESET_N(RESET_N),
+                .DATAIN(mDATAIN),
+                .DM(2'b00),
+                .DQOUT(DQOUT),
+                .DQM(IDQM)
+                );
+
+Sdram_FIFO 	write_fifo1(
+				.data(WR1_DATA),
+				.wrreq(WR1),
+				.wrclk(WR1_CLK),
+				.aclr(WR1_LOAD),
+				.rdreq(IN_REQ&WR_MASK[0]),
+				.rdclk(CLK),
+				.q(mDATAIN1),
+				.rdusedw(write_side_fifo_rusedw1)
+				);
+
+Sdram_FIFO 	write_fifo2(
+				.data(WR2_DATA),
+				.wrreq(WR2),
+				.wrclk(WR2_CLK),
+				.aclr(WR2_LOAD),
+				.rdreq(IN_REQ&WR_MASK[1]),
+				.rdclk(CLK),
+				.q(mDATAIN2),
+				.rdusedw(write_side_fifo_rusedw2)
+				);
+				
+assign	mDATAIN	=	(WR_MASK[0])	?	mDATAIN1	:
+										mDATAIN2	;
+
+Sdram_FIFO 	read_fifo1(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[0]),
+				.wrclk(CLK),
+				.aclr(RD1_LOAD),
+				.rdreq(RD1),
+				.rdclk(RD1_CLK),
+				.q(RD1_DATA),
+				.wrusedw(read_side_fifo_wusedw1)
+				);
+				
+Sdram_FIFO 	read_fifo2(
+				.data(mDATAOUT),
+				.wrreq(OUT_VALID&RD_MASK[1]),
+				.wrclk(CLK),
+				.aclr(RD2_LOAD),
+				.rdreq(RD2),
+				.rdclk(RD2_CLK),
+				.q(RD2_DATA),
+				.wrusedw(read_side_fifo_wusedw2)
+				);
+
+always @(posedge CLK)
+begin
+	SA      <= (ST==SC_CL+mLENGTH)			?	12'h200	:	ISA;
+    BA      <= IBA;
+    CS_N    <= ICS_N;
+    CKE     <= ICKE;
+    RAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IRAS_N;
+    CAS_N   <= (ST==SC_CL+mLENGTH)			?	1'b1	:	ICAS_N;
+    WE_N    <= (ST==SC_CL+mLENGTH)			?	1'b0	:	IWE_N;
+	PM_STOP	<= (ST==SC_CL+mLENGTH)			?	1'b1	:	1'b0;
+	PM_DONE	<= (ST==SC_CL+SC_RCD+mLENGTH+2)	?	1'b1	:	1'b0;
+	DQM		<= ( active && (ST>=SC_CL) )	?	(	((ST==SC_CL+mLENGTH) && Write)?	2'b11	:	2'b00	)	:	2'b11	;
+	mDATAOUT<= DQ;
+end
+
+assign  DQ = oe ? DQOUT : `DSIZE'hzzzz;
+assign	active	=	Read | Write;
+
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(RESET_N==0)
+	begin
+		CMD			<=  0;
+		ST			<=  0;
+		Pre_RD		<=  0;
+		Pre_WR		<=  0;
+		Read		<=	0;
+		Write		<=	0;
+		OUT_VALID	<=	0;
+		IN_REQ		<=	0;
+		mWR_DONE	<=	0;
+		mRD_DONE	<=	0;
+	end
+	else
+	begin
+		Pre_RD	<=	mRD;
+		Pre_WR	<=	mWR;
+		case(ST)
+		0:	begin
+				if({Pre_RD,mRD}==2'b01)
+				begin
+					Read	<=	1;
+					Write	<=	0;
+					CMD		<=	2'b01;
+					ST		<=	1;
+				end
+				else if({Pre_WR,mWR}==2'b01)
+				begin
+					Read	<=	0;
+					Write	<=	1;
+					CMD		<=	2'b10;
+					ST		<=	1;
+				end
+			end
+		1:	begin
+				if(CMDACK==1)
+				begin
+					CMD<=2'b00;
+					ST<=2;
+				end
+			end
+		default:	
+			begin	
+				if(ST!=SC_CL+SC_RCD+mLENGTH+1)
+				ST<=ST+1;
+				else
+				ST<=0;
+			end
+		endcase
+	
+		if(Read)
+		begin
+			if(ST==SC_CL+SC_RCD+1)
+			OUT_VALID	<=	1;
+			else if(ST==SC_CL+SC_RCD+mLENGTH+1)
+			begin
+				OUT_VALID	<=	0;
+				Read		<=	0;
+				mRD_DONE	<=	1;
+			end
+		end
+		else
+		mRD_DONE	<=	0;
+		
+		if(Write)
+		begin
+			if(ST==SC_CL-1)
+			IN_REQ	<=	1;
+			else if(ST==SC_CL+mLENGTH-1)
+			IN_REQ	<=	0;
+			else if(ST==SC_CL+SC_RCD+mLENGTH)
+			begin
+				Write	<=	0;
+				mWR_DONE<=	1;
+			end
+		end
+		else
+		mWR_DONE<=	0;
+
+	end
+end
+//	Internal Address & Length Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		rWR1_ADDR		<=	0;
+		rWR2_ADDR		<=	22'h100000;
+		rRD1_ADDR		<=	0;
+		rRD2_ADDR		<=	22'h100000;
+		rWR1_MAX_ADDR	<=	640*480;
+		rWR2_MAX_ADDR	<=	22'h100000+640*480;
+		rRD1_MAX_ADDR	<=	640*480;
+		rRD2_MAX_ADDR	<=	22'h100000+640*480;
+		rWR1_LENGTH		<=	256;
+		rWR2_LENGTH		<=	256;
+		rRD1_LENGTH		<=	256;
+		rRD2_LENGTH		<=	256;
+	end
+	else
+	begin
+		//	Write Side 1
+		if(WR1_LOAD)
+		begin
+			rWR1_ADDR	<=	WR1_ADDR;
+			rWR1_LENGTH	<=	WR1_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[0])
+		begin
+			if(rWR1_ADDR<rWR1_MAX_ADDR-rWR1_LENGTH)
+				rWR1_ADDR	<=	rWR1_ADDR+rWR1_LENGTH;
+			else
+				rWR1_ADDR	<=	WR1_ADDR;
+		end
+		//	Write Side 2
+		if(WR2_LOAD)
+		begin
+			rWR2_ADDR	<=	WR2_ADDR;
+			rWR2_LENGTH	<=	WR2_LENGTH;
+		end
+		else if(mWR_DONE&WR_MASK[1])
+		begin
+			if(rWR2_ADDR<rWR2_MAX_ADDR-rWR2_LENGTH)
+				rWR2_ADDR	<=	rWR2_ADDR+rWR2_LENGTH;
+			else
+				rWR2_ADDR	<=	WR2_ADDR;
+		end
+		//	Read Side 1
+		if(RD1_LOAD)
+		begin
+			rRD1_ADDR	<=	RD1_ADDR;
+			rRD1_LENGTH	<=	RD1_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[0])
+		begin
+			if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
+				rRD1_ADDR	<=	rRD1_ADDR+rRD1_LENGTH;
+			else
+				rRD1_ADDR	<=	RD1_ADDR;
+		end
+		//	Read Side 2
+		if(RD2_LOAD)
+		begin
+			rRD2_ADDR	<=	RD2_ADDR;
+			rRD2_LENGTH	<=	RD2_LENGTH;
+		end
+		else if(mRD_DONE&RD_MASK[1])
+		begin
+			if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
+				rRD2_ADDR	<=	rRD2_ADDR+rRD2_LENGTH;
+			else
+				rRD2_ADDR	<=	RD2_ADDR;
+		end
+	end
+end
+//	Auto Read/Write Control
+always@(posedge CLK or negedge RESET_N)
+begin
+	if(!RESET_N)
+	begin
+		mWR		<=	0;
+		mRD		<=	0;
+		mADDR	<=	0;
+		mLENGTH	<=	0;
+	end
+	else
+	begin
+		if( (mWR==0) && (mRD==0) && (ST==0) &&
+			(WR_MASK==0)	&&	(RD_MASK==0) &&
+			(WR1_LOAD==0)	&&	(RD1_LOAD==0) &&
+			(WR2_LOAD==0)	&&	(RD2_LOAD==0) )
+		begin
+			//	Write Side 1
+			if( (write_side_fifo_rusedw1 >= rWR1_LENGTH) && (rWR1_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR1_ADDR;
+				mLENGTH	<=	rWR1_LENGTH;
+				WR_MASK	<=	2'b01;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Write Side 2
+			else if( (write_side_fifo_rusedw2 >= rWR2_LENGTH) && (rWR2_LENGTH!=0) )
+			begin
+				mADDR	<=	rWR2_ADDR;
+				mLENGTH	<=	rWR2_LENGTH;
+				WR_MASK	<=	2'b10;
+				RD_MASK	<=	2'b00;
+				mWR		<=	1;
+				mRD		<=	0;
+			end
+			//	Read Side 1
+			else if( (read_side_fifo_wusedw1 < rRD1_LENGTH) )
+			begin
+				mADDR	<=	rRD1_ADDR;
+				mLENGTH	<=	rRD1_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b01;
+				mWR		<=	0;
+				mRD		<=	1;				
+			end
+			//	Read Side 2
+			else if( (read_side_fifo_wusedw2 < rRD2_LENGTH) )
+			begin
+				mADDR	<=	rRD2_ADDR;
+				mLENGTH	<=	rRD2_LENGTH;
+				WR_MASK	<=	2'b00;
+				RD_MASK	<=	2'b10;
+				mWR		<=	0;
+				mRD		<=	1;
+			end
+		end
+		if(mWR_DONE)
+		begin
+			WR_MASK	<=	0;
+			mWR		<=	0;
+		end
+		if(mRD_DONE)
+		begin
+			RD_MASK	<=	0;
+			mRD		<=	0;
+		end
+	end
+end
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip
new file mode 100644
index 0000000..ceca5c0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "10.0"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Sdram_FIFO.v"]
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v
new file mode 100644
index 0000000..af2662b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_FIFO.v
@@ -0,0 +1,190 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: Sdram_FIFO.v
+// Megafunction Name(s):
+// 			dcfifo
+//
+// Simulation Library Files(s):
+// 			
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Sdram_FIFO (
+	aclr,
+	data,
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw);
+
+	input	  aclr;
+	input	[15:0]  data;
+	input	  rdclk;
+	input	  rdreq;
+	input	  wrclk;
+	input	  wrreq;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[8:0]  rdusedw;
+	output	  wrfull;
+	output	[8:0]  wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [15:0] sub_wire1;
+	wire  sub_wire2;
+	wire [8:0] sub_wire3;
+	wire [8:0] sub_wire4;
+	wire  wrfull = sub_wire0;
+	wire [15:0] q = sub_wire1[15:0];
+	wire  rdempty = sub_wire2;
+	wire [8:0] wrusedw = sub_wire3[8:0];
+	wire [8:0] rdusedw = sub_wire4[8:0];
+
+	dcfifo	dcfifo_component (
+				.rdclk (rdclk),
+				.wrclk (wrclk),
+				.wrreq (wrreq),
+				.aclr (aclr),
+				.data (data),
+				.rdreq (rdreq),
+				.wrfull (sub_wire0),
+				.q (sub_wire1),
+				.rdempty (sub_wire2),
+				.wrusedw (sub_wire3),
+				.rdusedw (sub_wire4),
+				.rdfull (),
+				.wrempty ());
+	defparam
+		dcfifo_component.add_ram_output_register = "OFF",
+		dcfifo_component.clocks_are_synchronized = "FALSE",
+		dcfifo_component.intended_device_family = "Cyclone",
+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+		dcfifo_component.lpm_numwords = 512,
+		dcfifo_component.lpm_showahead = "OFF",
+		dcfifo_component.lpm_type = "dcfifo",
+		dcfifo_component.lpm_width = 16,
+		dcfifo_component.lpm_widthu = 9,
+		dcfifo_component.overflow_checking = "ON",
+		dcfifo_component.underflow_checking = "ON",
+		dcfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Sdram_FIFO_wave*.jpg FALSE
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
new file mode 100644
index 0000000..59b473c
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/Sdram_Params.h
@@ -0,0 +1,60 @@
+// Address Space Parameters
+
+`define ROWSTART        8          
+`define ROWSIZE         12
+`define COLSTART        0
+`define COLSIZE         8
+`define BANKSTART       20
+`define BANKSIZE        2
+
+// Address and Data Bus Sizes
+
+`define  ASIZE           23      // total address width of the SDRAM
+`define  DSIZE           16      // Width of data bus to SDRAMS
+
+//parameter	INIT_PER	=	100;		//	For Simulation
+
+//	Controller Parameter
+////////////	133 MHz	///////////////
+/*
+parameter	INIT_PER	=	32000;
+parameter	REF_PER		=	1536;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+////////////	100 MHz	///////////////
+parameter	INIT_PER	=	24000;
+parameter	REF_PER		=	1024;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+///////////////////////////////////////
+////////////	50 MHz	///////////////
+/*
+parameter	INIT_PER	=	12000;
+parameter	REF_PER		=	512;
+parameter	SC_CL		=	3;
+parameter	SC_RCD		=	3;
+parameter	SC_RRD		=	7;
+parameter	SC_PM		=	1;
+parameter	SC_BL		=	1;
+*/
+///////////////////////////////////////
+
+//	SDRAM Parameter
+parameter	SDR_BL		=	(SC_PM == 1)?	3'b111	:
+							(SC_BL == 1)?	3'b000	:
+							(SC_BL == 2)?	3'b001	:
+							(SC_BL == 4)?	3'b010	:
+											3'b011	;
+parameter	SDR_BT		=	1'b0;	//	Sequential
+							//	1'b1:	//	Interteave
+parameter	SDR_CL		=	(SC_CL == 2)?	3'b10:
+											3'b11;
+ 	
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v
new file mode 100644
index 0000000..8b37dff
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/command.v
@@ -0,0 +1,482 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	command
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module command(
+        CLK,
+        RESET_N,
+        SADDR,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        REF_REQ,
+		INIT_REQ,
+		PM_STOP,
+		PM_DONE,
+        REF_ACK,
+        CM_ACK,
+        OE,
+        SA,
+        BA,
+        CS_N,
+        CKE,
+        RAS_N,
+        CAS_N,
+        WE_N
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`ASIZE-1:0]            SADDR;                  // Address
+input                           NOP;                    // Decoded NOP command
+input                           READA;                  // Decoded READA command
+input                           WRITEA;                 // Decoded WRITEA command
+input                           REFRESH;                // Decoded REFRESH command
+input                           PRECHARGE;              // Decoded PRECHARGE command
+input                           LOAD_MODE;              // Decoded LOAD_MODE command
+input                           REF_REQ;                // Hidden refresh request
+input							INIT_REQ;				// Hidden initial request
+input							PM_STOP;				// Page mode stop
+input							PM_DONE;				// Page mode done
+output                          REF_ACK;                // Refresh request acknowledge
+output                          CM_ACK;                 // Command acknowledge
+output                          OE;                     // OE signal for data path module
+output  [11:0]                  SA;                     // SDRAM address
+output  [1:0]                   BA;                     // SDRAM bank address
+output  [1:0]                   CS_N;                   // SDRAM chip selects
+output                          CKE;                    // SDRAM clock enable
+output                          RAS_N;                  // SDRAM RAS
+output                          CAS_N;                  // SDRAM CAS
+output                          WE_N;                   // SDRAM WE_N
+            
+reg                             CM_ACK;
+reg                             REF_ACK;
+reg                             OE;
+reg     [11:0]                  SA;
+reg     [1:0]                   BA;
+reg     [1:0]                   CS_N;
+reg                             CKE;
+reg                             RAS_N;
+reg                             CAS_N;
+reg                             WE_N;
+
+// Internal signals
+reg                             do_reada;
+reg                             do_writea;
+reg                             do_refresh;
+reg                             do_precharge;
+reg                             do_load_mode;
+reg								do_initial;
+reg                             command_done;
+reg     [7:0]                   command_delay;
+reg     [1:0]                   rw_shift;
+reg                             do_act;
+reg                             rw_flag;
+reg                             do_rw;
+reg     [6:0]                   oe_shift;
+reg                             oe1;
+reg                             oe2;
+reg                             oe3;
+reg                             oe4;
+reg     [3:0]                   rp_shift;
+reg                             rp_done;
+reg								ex_read;
+reg								ex_write;
+
+wire    [`ROWSIZE - 1:0]        rowaddr;
+wire    [`COLSIZE - 1:0]        coladdr;
+wire    [`BANKSIZE - 1:0]       bankaddr;
+
+assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR
+assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits
+assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits
+
+// This always block monitors the individual command lines and issues a command
+// to the next stage if there currently another command already running.
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 0;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+        end
+        
+        else
+        begin
+
+//  Issue the appropriate command if the sdram is not currently busy
+			if( INIT_REQ == 1 )
+			begin
+                do_reada        <= 0;
+                do_writea       <= 0;
+                do_refresh      <= 0;
+                do_precharge    <= 0;
+                do_load_mode    <= 0;
+				do_initial		<= 1;
+                command_done    <= 0;
+                command_delay   <= 0;
+                rw_flag         <= 0;
+                rp_shift        <= 0;
+                rp_done         <= 0;
+				ex_read			<= 0;
+				ex_write		<= 0;
+			end
+			else
+			begin
+				do_initial		<= 0;
+				
+                if ((REF_REQ == 1 | REFRESH == 1) & command_done == 0 & do_refresh == 0 & rp_done == 0         // Refresh
+                        & do_reada == 0 & do_writea == 0)
+                        do_refresh <= 1;         
+                else
+                        do_refresh <= 0;
+
+                if ((READA == 1) & (command_done == 0) & (do_reada == 0) & (rp_done == 0) & (REF_REQ == 0))    // READA
+                begin
+				        do_reada <= 1;
+						ex_read <= 1;
+				end
+                else
+                        do_reada <= 0;
+                    
+                if ((WRITEA == 1) & (command_done == 0) & (do_writea == 0) & (rp_done == 0) & (REF_REQ == 0))  // WRITEA
+                begin
+				        do_writea <= 1;
+						ex_write <= 1;
+				end
+                else
+                        do_writea <= 0;
+
+                if ((PRECHARGE == 1) & (command_done == 0) & (do_precharge == 0))	// PRECHARGE
+                        do_precharge <= 1;
+                else
+                        do_precharge <= 0;
+ 
+                if ((LOAD_MODE == 1) & (command_done == 0) & (do_load_mode == 0))	// LOADMODE
+                        do_load_mode <= 1;
+                else
+                        do_load_mode <= 0;
+                                               
+// set command_delay shift register and command_done flag
+// The command delay shift register is a timer that is used to ensure that
+// the SDRAM devices have had sufficient time to finish the last command.
+
+                if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)
+                     | (do_load_mode == 1))
+                begin
+                        command_delay <= 8'b11111111;
+                        command_done  <= 1;
+                        rw_flag <= do_reada;                                                  
+                end
+                
+                else
+                begin
+                        command_done        <= command_delay[0];                // the command_delay shift operation
+                        command_delay		<= (command_delay>>1);
+                end 
+                
+ 
+ // start additional timer that is used for the refresh, writea, reada commands               
+                if (command_delay[0] == 0 & command_done == 1)
+                begin
+                	rp_shift <= 4'b1111;
+                	rp_done <= 1;
+                end
+                else
+                begin						
+					if(SC_PM == 0)
+					begin
+						rp_shift	<= (rp_shift>>1);
+                    	rp_done		<= rp_shift[0];
+					end
+					else
+					begin
+						if( (ex_read == 0) && (ex_write == 0) )
+						begin
+							rp_shift	<= (rp_shift>>1);
+        	            	rp_done		<= rp_shift[0];
+						end
+						else
+						begin
+							if( PM_STOP==1 )
+							begin
+								rp_shift	<= (rp_shift>>1);
+        	      		      	rp_done     <= rp_shift[0];
+								ex_read		<= 1'b0;
+								ex_write	<= 1'b0;
+							end					
+						end
+					end
+                end
+			end
+        end
+end
+
+
+// logic that generates the OE signal for the data path module
+// For normal burst write he duration of OE is dependent on the configured burst length.
+// For page mode accesses(SC_PM=1) the OE signal is turned on at the start of the write command
+// and is left on until a PRECHARGE(page burst terminate) is detected.
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                oe_shift <= 0;
+                oe1      <= 0;
+                oe2      <= 0;
+                OE       <= 0;
+        end
+        else
+        begin
+                if (SC_PM == 0)
+                begin
+                        if (do_writea == 1)
+                        begin
+                                if (SC_BL == 1)				//  Set the shift register to the appropriate
+                                        oe_shift <= 0;		// value based on burst length.
+                                else if (SC_BL == 2)
+                                        oe_shift <= 1;
+                                else if (SC_BL == 4)
+                                        oe_shift <= 7;
+                                else if (SC_BL == 8)
+                                        oe_shift <= 127;
+                                oe1 <= 1;
+                        end
+                        else 
+                        begin
+                                oe_shift <= (oe_shift>>1);
+                                oe1  <= oe_shift[0];
+                                oe2  <= oe1;
+                                oe3  <= oe2;
+                                oe4  <= oe3;
+                                if (SC_RCD == 2)
+                                        OE <= oe3;
+                                else
+                                        OE <= oe4;
+                        end
+                end
+                else
+                begin
+                        if (do_writea == 1)					 // OE generation for page mode accesses
+                                oe4   <= 1;
+                        else if (do_precharge == 1 | do_reada == 1 | do_refresh==1 | do_initial == 1 | PM_STOP==1 )
+                                oe4   <= 0;
+                        OE <= oe4;
+                end
+                               
+        end
+end
+
+
+
+
+// This always block tracks the time between the activate command and the
+// subsequent WRITEA or READA command, RC.  The shift register is set using
+// the configuration register setting SC_RCD. The shift register is loaded with
+// a single '1' with the position within the register dependent on SC_RCD.
+// When the '1' is shifted out of the register it sets so_rw which triggers
+// a writea or reada command
+//
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+        begin
+                rw_shift <= 0;
+                do_rw    <= 0;
+        end
+        
+        else
+        begin
+                
+                if ((do_reada == 1) | (do_writea == 1))
+                begin
+                        if (SC_RCD == 1)                          // Set the shift register
+                                do_rw <= 1;
+                        else if (SC_RCD == 2)
+                                rw_shift <= 1;
+                        else if (SC_RCD == 3)
+                                rw_shift <= 2;
+                end
+                else
+                begin
+                        rw_shift <= (rw_shift>>1);
+                        do_rw    <= rw_shift[0];
+                end 
+        end
+end              
+
+// This always block generates the command acknowledge, CM_ACK, signal.
+// It also generates the acknowledge signal, REF_ACK, that acknowledges
+// a refresh request that was generated by the internal refresh timer circuit.
+always @(posedge CLK or negedge RESET_N) 
+begin
+
+        if (RESET_N == 0) 
+        begin
+                CM_ACK   <= 0;
+                REF_ACK  <= 0;
+        end
+        
+        else
+        begin
+                if (do_refresh == 1 & REF_REQ == 1)                   // Internal refresh timer refresh request
+                        REF_ACK <= 1;
+                else if ((do_refresh == 1) | (do_reada == 1) | (do_writea == 1) | (do_precharge == 1)   // externa  commands
+                         | (do_load_mode))
+                        CM_ACK <= 1;
+                else
+                begin
+                        REF_ACK <= 0;
+                        CM_ACK  <= 0;
+                end
+        end
+end 
+                    
+
+
+
+
+
+
+// This always block generates the address, cs, cke, and command signals(ras,cas,wen)
+// 
+always @(posedge CLK ) begin
+        if (RESET_N==0) begin
+                SA    <= 0;
+                BA    <= 0;
+                CS_N  <= 1;
+                RAS_N <= 1;
+                CAS_N <= 1;
+                WE_N  <= 1;
+                CKE   <= 0;
+        end
+        else begin
+                CKE <= 1;
+
+// Generate SA 	
+                if (do_writea == 1 | do_reada == 1)    // ACTIVATE command is being issued, so present the row address
+                        SA <= rowaddr;
+                else
+                        SA <= coladdr;                 // else alway present column address
+                if ((do_rw==1) | (do_precharge))
+                        SA[10] <= !SC_PM;              // set SA[10] for autoprecharge read/write or for a precharge all command
+                                                       // don't set it if the controller is in page mode.           
+                if (do_precharge==1 | do_load_mode==1)
+                        BA <= 0;                       // Set BA=0 if performing a precharge or load_mode command
+                else
+                        BA <= bankaddr[1:0];           // else set it with the appropriate address bits
+		
+                if (do_refresh==1 | do_precharge==1 | do_load_mode==1 | do_initial==1)
+                        CS_N <= 0;                                    // Select both chip selects if performing
+                else                                                  // refresh, precharge(all) or load_mode
+                begin
+                        CS_N[0] <= SADDR[`ASIZE-1];                   // else set the chip selects based off of the
+                        CS_N[1] <= ~SADDR[`ASIZE-1];                  // msb address bit
+                end
+				
+				if(do_load_mode==1)
+				SA	  <= {2'b00,SDR_CL,SDR_BT,SDR_BL};
+
+
+//Generate the appropriate logic levels on RAS_N, CAS_N, and WE_N
+//depending on the issued command.
+//		
+                if ( do_refresh==1 ) begin                        // Refresh: S=00, RAS=0, CAS=0, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 1;
+                end
+                else if ((do_precharge==1) & ((oe4 == 1) | (rw_flag == 1))) begin      // burst terminate if write is active
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_precharge==1) begin                 // Precharge All: S=00, RAS=0, CAS=1, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 0;
+                end
+                else if (do_load_mode==1) begin                 // Mode Write: S=00, RAS=0, CAS=0, WE=0
+                        RAS_N <= 0;
+                        CAS_N <= 0;
+                        WE_N  <= 0;
+                end
+                else if (do_reada == 1 | do_writea == 1) begin  // Activate: S=01 or 10, RAS=0, CAS=1, WE=1
+                        RAS_N <= 0;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+                else if (do_rw == 1) begin                      // Read/Write: S=01 or 10, RAS=1, CAS=0, WE=0 or 1
+                        RAS_N <= 1;
+                        CAS_N <= 0;
+                        WE_N  <= rw_flag;
+                end
+				else if (do_initial ==1) begin
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;				
+				end
+                else begin                                      // No Operation: RAS=1, CAS=1, WE=1
+                        RAS_N <= 1;
+                        CAS_N <= 1;
+                        WE_N  <= 1;
+                end
+        end 
+end
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v
new file mode 100644
index 0000000..d7930e2
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/control_interface.v
@@ -0,0 +1,240 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	control_interface
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module control_interface(
+        CLK,
+        RESET_N,
+        CMD,
+        ADDR,
+        REF_ACK,
+		INIT_ACK,
+        CM_ACK,
+        NOP,
+        READA,
+        WRITEA,
+        REFRESH,
+        PRECHARGE,
+        LOAD_MODE,
+        SADDR,
+        REF_REQ,
+		INIT_REQ,
+        CMD_ACK
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [2:0]                   CMD;                    // Command input
+input   [`ASIZE-1:0]            ADDR;                   // Address
+input                           REF_ACK;                // Refresh request acknowledge
+input							INIT_ACK;				// Initial request acknowledge
+input                           CM_ACK;                 // Command acknowledge
+output                          NOP;                    // Decoded NOP command
+output                          READA;                  // Decoded READA command
+output                          WRITEA;                 // Decoded WRITEA command
+output                          REFRESH;                // Decoded REFRESH command
+output                          PRECHARGE;              // Decoded PRECHARGE command
+output                          LOAD_MODE;              // Decoded LOAD_MODE command
+output  [`ASIZE-1:0]            SADDR;                  // Registered version of ADDR
+output                          REF_REQ;                // Hidden refresh request
+output                          INIT_REQ;               // Hidden initial request
+output                          CMD_ACK;                // Command acknowledge
+
+
+            
+reg                             NOP;
+reg                             READA;
+reg                             WRITEA;
+reg                             REFRESH;
+reg                             PRECHARGE;
+reg                             LOAD_MODE;
+reg     [`ASIZE-1:0]            SADDR;
+reg                             REF_REQ;
+reg                             INIT_REQ;
+reg                             CMD_ACK;
+
+// Internal signals
+reg     [15:0]                  timer;
+reg		[15:0]					init_timer;
+
+
+
+// Command decode and ADDR register
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+        begin
+                NOP             <= 0;
+                READA           <= 0;
+                WRITEA          <= 0;
+                SADDR           <= 0;
+        end
+        
+        else
+        begin
+        
+                SADDR <= ADDR;                                  // register the address to keep proper
+                                                                // alignment with the command
+                                                             
+                if (CMD == 3'b000)                              // NOP command
+                        NOP <= 1;
+                else
+                        NOP <= 0;
+                        
+                if (CMD == 3'b001)                              // READA command
+                        READA <= 1;
+                else
+                        READA <= 0;
+                 
+                if (CMD == 3'b010)                              // WRITEA command
+                        WRITEA <= 1;
+                else
+                        WRITEA <= 0;
+                        
+        end
+end
+
+
+//  Generate CMD_ACK
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0)
+                CMD_ACK <= 0;
+        else
+                if ((CM_ACK == 1) & (CMD_ACK == 0))
+                        CMD_ACK <= 1;
+                else
+                        CMD_ACK <= 0;
+end
+
+
+// refresh timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                timer           <= 0;
+                REF_REQ         <= 0;
+        end        
+        else 
+        begin
+                if (REF_ACK == 1)
+				begin
+                	timer <= REF_PER;
+					REF_REQ	<=0;
+				end
+				else if (INIT_REQ == 1)
+				begin
+                	timer <= REF_PER+200;
+					REF_REQ	<=0;					
+				end
+                else
+                	timer <= timer - 1'b1;
+
+                if (timer==0)
+                    REF_REQ    <= 1;
+
+        end
+end
+
+// initial timer
+always @(posedge CLK or negedge RESET_N) begin
+        if (RESET_N == 0) 
+        begin
+                init_timer      <= 0;
+				REFRESH         <= 0;
+                PRECHARGE      	<= 0; 
+				LOAD_MODE		<= 0;
+				INIT_REQ		<= 0;
+        end        
+        else 
+        begin
+                if (init_timer < (INIT_PER+201))
+					init_timer 	<= init_timer+1;
+					
+				if (init_timer < INIT_PER)
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=1;
+				end
+				else if(init_timer == (INIT_PER+20))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=1;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if( 	(init_timer == (INIT_PER+40))	||
+							(init_timer == (INIT_PER+60))	||
+							(init_timer == (INIT_PER+80))	||
+							(init_timer == (INIT_PER+100))	||
+							(init_timer == (INIT_PER+120))	||
+							(init_timer == (INIT_PER+140))	||
+							(init_timer == (INIT_PER+160))	||
+							(init_timer == (INIT_PER+180))	)
+				begin
+					REFRESH		<=1;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;
+				end
+				else if(init_timer == (INIT_PER+200))
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=1;
+					INIT_REQ	<=0;				
+				end
+				else
+				begin
+					REFRESH		<=0;
+					PRECHARGE	<=0;
+					LOAD_MODE	<=0;
+					INIT_REQ	<=0;									
+				end
+        end
+end
+
+endmodule
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v
new file mode 100644
index 0000000..b064bbe
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_Control_4Port/sdr_data_path.v
@@ -0,0 +1,76 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2008 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	sdr_data_path
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny Fan        :| 08/04/22  :| Initial Revision
+// --------------------------------------------------------------------
+
+module sdr_data_path(
+        CLK,
+        RESET_N,
+        DATAIN,
+        DM,
+        DQOUT,
+        DQM
+        );
+
+`include        "Sdram_Params.h"
+
+input                           CLK;                    // System Clock
+input                           RESET_N;                // System Reset
+input   [`DSIZE-1:0]            DATAIN;                 // Data input from the host
+input   [`DSIZE/8-1:0]          DM;                     // byte data masks
+output  [`DSIZE-1:0]            DQOUT;
+output  [`DSIZE/8-1:0]          DQM;                    // SDRAM data mask ouputs
+reg     [`DSIZE/8-1:0]          DQM;
+            
+
+
+// Allign the input and output data to the SDRAM control path
+always @(posedge CLK or negedge RESET_N)
+begin
+        if (RESET_N == 0) 
+		DQM		<= `DSIZE/8-1'hF;
+        else
+ 		DQM		<=	DM;                 
+end
+
+assign DQOUT = DATAIN;
+
+endmodule
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/Sdram_FIFO.qip
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v
new file mode 100644
index 0000000..338ae75
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/CCD_Capture.v
@@ -0,0 +1,186 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	D5M CCD_Capture
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module CCD_Capture(	oDATA,
+					oDVAL,
+					oX_Cont,
+					oY_Cont,
+					oFrame_Cont,
+					iDATA,
+					iFVAL,
+					iLVAL,
+					iSTART,
+					iEND,
+					iCLK,
+					iRST
+					);
+					
+input	[11:0]	iDATA;
+input			iFVAL;
+input			iLVAL;
+input			iSTART;
+input			iEND;
+input			iCLK;
+input			iRST;
+output	[11:0]	oDATA;
+output	[15:0]	oX_Cont;
+output	[15:0]	oY_Cont;
+output	[31:0]	oFrame_Cont;
+output			oDVAL;
+reg				Pre_FVAL;
+reg				mCCD_FVAL;
+reg				mCCD_LVAL;
+reg		[11:0]	mCCD_DATA;
+reg		[15:0]	X_Cont;
+reg		[15:0]	Y_Cont;
+reg		[31:0]	Frame_Cont;
+reg				mSTART;
+
+parameter COLUMN_WIDTH = 1280;
+
+assign	oX_Cont		=	X_Cont;
+assign	oY_Cont		=	Y_Cont;
+assign	oFrame_Cont	=	Frame_Cont;
+assign	oDATA		=	mCCD_DATA;
+assign	oDVAL		=	mCCD_FVAL&mCCD_LVAL;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	mSTART	<=	0;
+	else
+	begin
+		if(iSTART)
+		mSTART	<=	1;
+		if(iEND)
+		mSTART	<=	0;		
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Pre_FVAL	<=	0;
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	0;
+
+		X_Cont		<=	0;
+		Y_Cont		<=	0;
+	end
+	else
+	begin
+		Pre_FVAL	<=	iFVAL;
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		mCCD_FVAL	<=	1;
+		else if({Pre_FVAL,iFVAL}==2'b10)
+		mCCD_FVAL	<=	0;
+		mCCD_LVAL	<=	iLVAL;
+		if(mCCD_FVAL)
+		begin
+			if(mCCD_LVAL)
+			begin
+				if(X_Cont<(COLUMN_WIDTH-1))
+				X_Cont	<=	X_Cont+1;
+				else
+				begin
+					X_Cont	<=	0;
+					Y_Cont	<=	Y_Cont+1;
+				end
+			end
+		end
+		else
+		begin
+			X_Cont	<=	0;
+			Y_Cont	<=	0;
+		end
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	Frame_Cont	<=	0;
+	else
+	begin
+		if( ({Pre_FVAL,iFVAL}==2'b01) && mSTART )
+		Frame_Cont	<=	Frame_Cont+1;
+	end
+end
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		mCCD_DATA	<=	0;
+	else if (iLVAL)
+		mCCD_DATA	<=	iDATA;
+	else
+		mCCD_DATA	<=	0;	
+end			
+
+reg	ifval_dealy;
+
+wire ifval_fedge;	
+reg	[15:0]	y_cnt_d;
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		y_cnt_d	<=	0;
+	else
+		y_cnt_d	<=	Y_Cont;	
+end
+
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+		ifval_dealy	<=	0;
+	else
+		ifval_dealy	<=	iFVAL;	
+end
+
+assign ifval_fedge = ({ifval_dealy,iFVAL}==2'b10)?1:0;  
+
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v
new file mode 100644
index 0000000..11d3a70
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v
@@ -0,0 +1,287 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| CCD config, spelling
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+
+// `define 	ENABLE_TEST_PATTERN 1
+
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	sensor_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			sensor_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((sensor_exposure < exposure_change_value)||
+							(sensor_exposure == 16'h0))
+							sensor_exposure <= 0;
+						else	
+							sensor_exposure <= sensor_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -sensor_exposure) <exposure_change_value)||
+							(sensor_exposure == 16'hffff))
+							sensor_exposure <= 16'hffff;
+						else
+							sensor_exposure <= sensor_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,sensor_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak
new file mode 100644
index 0000000..81810a8
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_CCD_Config.v.bak
@@ -0,0 +1,282 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	I2C_CCD_Config
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module I2C_CCD_Config (	//	Host Side
+						iCLK,
+						iRST_N,
+						iUART_CTRL,
+						iZOOM_MODE_SW,
+						iEXPOSURE_ADJ,
+						iEXPOSURE_DEC_p,
+						//	I2C Side
+						I2C_SCLK,
+						I2C_SDAT
+						);
+						
+//	Host Side
+input			iCLK;
+input			iRST_N;
+input 			iUART_CTRL;
+input 			iZOOM_MODE_SW;
+
+//	I2C Side
+output		I2C_SCLK;
+inout		I2C_SDAT;
+
+//	Internal Registers/Wires
+reg	[15:0]	mI2C_CLK_DIV;
+reg	[31:0]	mI2C_DATA;
+reg			mI2C_CTRL_CLK;
+reg			mI2C_GO;
+wire		mI2C_END;
+wire		mI2C_ACK;
+reg	[23:0]	LUT_DATA;
+reg	[5:0]	LUT_INDEX;
+reg	[3:0]	mSetup_ST;
+
+//////////////   CMOS sensor registers setting //////////////////////
+
+input 		iEXPOSURE_ADJ;
+input		iEXPOSURE_DEC_p;	
+
+parameter 	default_exposure 			= 16'h07c0;
+parameter 	exposure_change_value	 	= 16'd200;
+
+reg	[24:0]	combo_cnt;
+wire		combo_pulse;
+
+reg	[1:0]	izoom_mode_sw_delay;
+
+reg	[3:0]	iexposure_adj_delay;
+wire		exposure_adj_set;	
+wire		exposure_adj_reset;
+reg	[15:0]	senosr_exposure;
+
+wire [23:0] sensor_start_row;
+wire [23:0] sensor_start_column;
+wire [23:0] sensor_row_size;
+wire [23:0] sensor_column_size; 
+wire [23:0] sensor_row_mode;
+wire [23:0] sensor_column_mode;
+
+assign sensor_start_row 		= iZOOM_MODE_SW ?  24'h010036 : 24'h010000;
+assign sensor_start_column 		= iZOOM_MODE_SW ?  24'h020010 : 24'h020000;
+assign sensor_row_size	 		= iZOOM_MODE_SW ?  24'h0303BF : 24'h03077F;
+assign sensor_column_size 		= iZOOM_MODE_SW ?  24'h0404FF : 24'h0409FF;
+assign sensor_row_mode 			= iZOOM_MODE_SW ?  24'h220000 : 24'h220011;
+assign sensor_column_mode		= iZOOM_MODE_SW ?  24'h230000 : 24'h230011;
+
+	
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			begin
+				iexposure_adj_delay <= 0;
+			end
+		else 
+			begin
+				iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};		
+			end	
+	end
+
+assign 	exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
+assign  exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;		
+
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			senosr_exposure <= default_exposure;
+		else if (exposure_adj_set|combo_pulse)
+			begin
+				if (iEXPOSURE_DEC_p)
+					begin
+						if ((senosr_exposure < exposure_change_value)||
+							(senosr_exposure == 16'h0))
+							senosr_exposure <= 0;
+						else	
+							senosr_exposure <= senosr_exposure - exposure_change_value;
+					end		
+				else
+					begin
+						if (((16'hffff -senosr_exposure) <exposure_change_value)||
+							(senosr_exposure == 16'hffff))
+							senosr_exposure <= 16'hffff;
+						else
+							senosr_exposure <= senosr_exposure + exposure_change_value;	
+					end		
+			end
+	end			
+				
+		
+always@(posedge iCLK or negedge iRST_N)
+	begin
+		if (!iRST_N)
+			combo_cnt <= 0;
+		else if (!iexposure_adj_delay[3])
+			combo_cnt <= combo_cnt + 1;
+		else
+			combo_cnt <= 0;	
+	end
+	
+assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;				
+		
+wire	i2c_reset;		
+
+assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
+
+/////////////////////////////////////////////////////////////////////
+
+//	Clock Setting
+parameter	CLK_Freq	=	50000000;	//	50	MHz
+parameter	I2C_Freq	=	20000;		//	20	KHz
+//	LUT Data Number
+parameter	LUT_SIZE	=	25;
+
+/////////////////////	I2C Control Clock	////////////////////////
+always@(posedge iCLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		mI2C_CTRL_CLK	<=	0;
+		mI2C_CLK_DIV	<=	0;
+	end
+	else
+	begin
+		if( mI2C_CLK_DIV	< (CLK_Freq/I2C_Freq) )
+		mI2C_CLK_DIV	<=	mI2C_CLK_DIV+1;
+		else
+		begin
+			mI2C_CLK_DIV	<=	0;
+			mI2C_CTRL_CLK	<=	~mI2C_CTRL_CLK;
+		end
+	end
+end
+////////////////////////////////////////////////////////////////////
+I2C_Controller 	u0	(	.CLOCK(mI2C_CTRL_CLK),		//	Controller Work Clock
+						.I2C_SCLK(I2C_SCLK),		//	I2C CLOCK
+ 	 	 	 	 	 	.I2C_SDAT(I2C_SDAT),		//	I2C DATA
+						.I2C_DATA(mI2C_DATA),		//	DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+						.GO(mI2C_GO),      			//	GO transfor
+						.END(mI2C_END),				//	END transfor 
+						.ACK(mI2C_ACK),				//	ACK
+						.RESET(i2c_reset)
+					);
+////////////////////////////////////////////////////////////////////
+//////////////////////	Config Control	////////////////////////////
+//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
+always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
+begin
+	if(!i2c_reset)
+	begin
+		LUT_INDEX	<=	0;
+		mSetup_ST	<=	0;
+		mI2C_GO		<=	0;
+
+	end
+
+	else if(LUT_INDEX<LUT_SIZE)
+		begin
+			case(mSetup_ST)
+			0:	begin
+					mI2C_DATA	<=	{8'hBA,LUT_DATA};
+					mI2C_GO		<=	1;
+					mSetup_ST	<=	1;
+				end
+			1:	begin
+					if(mI2C_END)
+					begin
+						if(!mI2C_ACK)
+						mSetup_ST	<=	2;
+						else
+						mSetup_ST	<=	0;							
+						mI2C_GO		<=	0;
+					end
+				end
+			2:	begin
+					LUT_INDEX	<=	LUT_INDEX+1;
+					mSetup_ST	<=	0;
+				end
+			endcase
+		end
+end
+////////////////////////////////////////////////////////////////////
+/////////////////////	Config Data LUT	  //////////////////////////		
+always
+begin
+	case(LUT_INDEX)
+	0	:	LUT_DATA	<=	24'h000000;
+	1	:	LUT_DATA	<=	24'h20c000;				//	Mirror Row and Columns
+	2	:	LUT_DATA	<=	{8'h09,senosr_exposure};//	Exposure
+	3	:	LUT_DATA	<=	24'h050000;				//	H_Blanking
+	4	:	LUT_DATA	<=	24'h060019;				//	V_Blanking	
+	5	:	LUT_DATA	<=	24'h0A8000;				//	change latch
+	6	:	LUT_DATA	<=	24'h2B000b;				//	Green 1 Gain
+	7	:	LUT_DATA	<=	24'h2C000f;				//	Blue Gain
+	8	:	LUT_DATA	<=	24'h2D000f;				//	Red Gain
+	9	:	LUT_DATA	<=	24'h2E000b;				//	Green 2 Gain
+	10	:	LUT_DATA	<=	24'h100051;				//	set up PLL power on
+	11	:	LUT_DATA	<=	24'h111807;				//	PLL_m_Factor<<8+PLL_n_Divider
+	12	:	LUT_DATA	<=	24'h120002;				//	PLL_p1_Divider
+	13	:	LUT_DATA	<=	24'h100053;				//	set USE PLL	 
+	14	:	LUT_DATA	<=	24'h980000;				//	disble calibration 	
+`ifdef ENABLE_TEST_PATTERN
+	15	:	LUT_DATA	<=	24'hA00001;				//	Test pattern control 	
+	16	:	LUT_DATA	<=	24'hA10123;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20456;				//	Test red pattern value
+`else
+	15	:	LUT_DATA	<=	24'hA00000;				//	Test pattern control 
+	16	:	LUT_DATA	<=	24'hA10000;				//	Test green pattern value
+	17	:	LUT_DATA	<=	24'hA20FFF;				//	Test red pattern value
+`endif
+	18	:	LUT_DATA	<=	sensor_start_row 	;	//	set start row	
+	19	:	LUT_DATA	<=	sensor_start_column ;	//	set start column 	
+
+	20	:	LUT_DATA	<=	sensor_row_size;		//	set row size	
+	21	:	LUT_DATA	<=	sensor_column_size;		//	set column size
+	22	:	LUT_DATA	<=	sensor_row_mode;		//	set row mode in bin mode
+	23	:	LUT_DATA	<=	sensor_column_mode;		//	set column mode	 in bin mode
+	24	:	LUT_DATA	<=	24'h4901A8;				//	row black target		
+	default:LUT_DATA	<=	24'h000000;
+	endcase
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v
new file mode 100644
index 0000000..3740541
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/I2C_Controller.v
@@ -0,0 +1,150 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2005 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altrea Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL or Verilog source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:i2c controller
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Joe Yang          :| 05/07/10  :|      Initial Revision
+// --------------------------------------------------------------------
+module I2C_Controller (
+	CLOCK,
+	I2C_SCLK,//I2C CLOCK
+ 	I2C_SDAT,//I2C DATA
+	I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
+	GO,      //GO transfor
+	END,     //END transfor 
+
+	ACK,      //ACK
+	RESET
+);
+	input  CLOCK;
+	input  [31:0]I2C_DATA;	
+	input  GO;
+	input  RESET;	
+ 	inout  I2C_SDAT;	
+	output I2C_SCLK;
+	output END;	
+	output ACK;
+
+
+reg SDO;
+reg SCLK;
+reg END;
+reg [31:0]SD;
+reg [6:0]SD_COUNTER;
+
+wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
+wire I2C_SDAT=SDO?1'bz:0 ;
+
+reg ACK1,ACK2,ACK3,ACK4;
+wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
+
+//--I2C COUNTER
+always @(negedge RESET or posedge CLOCK ) begin
+if (!RESET) SD_COUNTER=6'b111111;
+else begin
+if (GO==0) 
+	SD_COUNTER=0;
+	else 
+	if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;	
+end
+end
+//----
+
+always @(negedge RESET or  posedge CLOCK ) begin
+if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
+else
+case (SD_COUNTER)
+	6'd0  : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
+	//start
+	6'd1  : begin SD=I2C_DATA;SDO=0;end
+	6'd2  : SCLK=0;
+	//SLAVE ADDR
+	6'd3  : SDO=SD[31];
+	6'd4  : SDO=SD[30];
+	6'd5  : SDO=SD[29];
+	6'd6  : SDO=SD[28];
+	6'd7  : SDO=SD[27];
+	6'd8  : SDO=SD[26];
+	6'd9  : SDO=SD[25];
+	6'd10 : SDO=SD[24];	
+	6'd11 : SDO=1'b1;//ACK
+
+	//SUB ADDR
+	6'd12  : begin SDO=SD[23]; ACK1=I2C_SDAT; end
+	6'd13  : SDO=SD[22];
+	6'd14  : SDO=SD[21];
+	6'd15  : SDO=SD[20];
+	6'd16  : SDO=SD[19];
+	6'd17  : SDO=SD[18];
+	6'd18  : SDO=SD[17];
+	6'd19  : SDO=SD[16];
+	6'd20  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd21  : begin SDO=SD[15]; ACK2=I2C_SDAT; end
+	6'd22  : SDO=SD[14];
+	6'd23  : SDO=SD[13];
+	6'd24  : SDO=SD[12];
+	6'd25  : SDO=SD[11];
+	6'd26  : SDO=SD[10];
+	6'd27  : SDO=SD[9];
+	6'd28  : SDO=SD[8];
+	6'd29  : SDO=1'b1;//ACK
+
+	//DATA
+	6'd30  : begin SDO=SD[7]; ACK3=I2C_SDAT; end
+	6'd31  : SDO=SD[6];
+	6'd32  : SDO=SD[5];
+	6'd33  : SDO=SD[4];
+	6'd34  : SDO=SD[3];
+	6'd35  : SDO=SD[2];
+	6'd36  : SDO=SD[1];
+	6'd37  : SDO=SD[0];
+	6'd38  : SDO=1'b1;//ACK
+
+	
+	//stop
+    6'd39 : begin SDO=1'b0;	SCLK=1'b0; ACK4=I2C_SDAT; end	
+    6'd40 : SCLK=1'b1; 
+    6'd41 : begin SDO=1'b1; END=1; end 
+
+endcase
+end
+
+
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf
new file mode 100644
index 0000000..b7b5b56
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.bsf
@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 184 128)
+	(text "Line_Buffer" (rect 60 1 135 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "shiftin[11..0]" (rect 0 0 69 14)(font "Arial" (font_size 8)))
+		(text "shiftin[11..0]" (rect 20 34 78 47)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 50 43 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 184 40)
+		(output)
+		(text "shiftout[11..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "shiftout[11..0]" (rect 99 34 163 47)(font "Arial" (font_size 8)))
+		(line (pt 184 40)(pt 168 40)(line_width 3))
+	)
+	(port
+		(pt 184 56)
+		(output)
+		(text "taps1x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps1x[11..0]" (rect 102 50 162 63)(font "Arial" (font_size 8)))
+		(line (pt 184 56)(pt 168 56)(line_width 3))
+	)
+	(port
+		(pt 184 72)
+		(output)
+		(text "taps0x[11..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "taps0x[11..0]" (rect 102 66 162 79)(font "Arial" (font_size 8)))
+		(line (pt 184 72)(pt 168 72)(line_width 3))
+	)
+	(drawing
+		(text "altshift_taps" (rect 63 18 119 31)(font "Arial" (font_size 8)))
+		(text "Number of taps 2" (rect 19 90 93 102)(font "Arial" ))
+		(text "Tap distance 1280" (rect 19 100 95 112)(font "Arial" ))
+		(line (pt 16 16)(pt 168 16)(line_width 1))
+		(line (pt 168 16)(pt 168 112)(line_width 1))
+		(line (pt 168 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v
new file mode 100644
index 0000000..09482ce
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Line_Buffer.v
@@ -0,0 +1,111 @@
+// megafunction wizard: %Shift register (RAM-based)%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altshift_taps 
+
+// ============================================================
+// File Name: Line_Buffer.v
+// Megafunction Name(s):
+// 			altshift_taps
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2007 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module Line_Buffer (
+	clken,
+	clock,
+	shiftin,
+	shiftout,
+	taps0x,
+	taps1x);
+
+	input	  clken;
+	input	  clock;
+	input	[11:0]  shiftin;
+	output	[11:0]  shiftout;
+	output	[11:0]  taps0x;
+	output	[11:0]  taps1x;
+
+	wire [23:0] sub_wire0;
+	wire [11:0] sub_wire3;
+	wire [23:12] sub_wire1 = sub_wire0[23:12];
+	wire [11:0] sub_wire2 = sub_wire0[11:0];
+	wire [11:0] taps1x = sub_wire1[23:12];
+	wire [11:0] taps0x = sub_wire2[11:0];
+	wire [11:0] shiftout = sub_wire3[11:0];
+
+	altshift_taps	altshift_taps_component (
+				.clken (clken),
+				.clock (clock),
+				.shiftin (shiftin),
+				.taps (sub_wire0),
+				.shiftout (sub_wire3));
+	defparam
+		altshift_taps_component.lpm_type = "altshift_taps",
+		altshift_taps_component.number_of_taps = 2,
+		altshift_taps_component.tap_distance = 1280,
+		altshift_taps_component.width = 12;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
+// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
+// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
+// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
+// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
+// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
+// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
+// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
+// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
+// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
+// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
+// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v
new file mode 100644
index 0000000..16493c7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/RAW2RGB.v
@@ -0,0 +1,128 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	RAW2RGB
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module RAW2RGB(	oRed,
+				oGreen,
+				oBlue,
+				oDVAL,
+				iX_Cont,
+				iY_Cont,
+				iDATA,
+				iDVAL,
+				iCLK,
+				iRST
+				);
+
+input	[10:0]	iX_Cont;
+input	[10:0]	iY_Cont;
+input	[11:0]	iDATA;
+input			iDVAL;
+input			iCLK;
+input			iRST;
+output	[11:0]	oRed;
+output	[11:0]	oGreen;
+output	[11:0]	oBlue;
+output			oDVAL;
+wire	[11:0]	mDATA_0;
+wire	[11:0]	mDATA_1;
+reg		[11:0]	mDATAd_0;
+reg		[11:0]	mDATAd_1;
+reg		[11:0]	mCCD_R;
+reg		[12:0]	mCCD_G;
+reg		[11:0]	mCCD_B;
+reg				mDVAL;
+
+assign	oRed	=	mCCD_R[11:0];
+assign	oGreen	=	mCCD_G[12:1];
+assign	oBlue	=	mCCD_B[11:0];
+assign	oDVAL	=	mDVAL;
+
+Line_Buffer 	u0	(	.clken(iDVAL),
+						.clock(iCLK),
+						.shiftin(iDATA),
+						.taps0x(mDATA_1),
+						.taps1x(mDATA_0)	);
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		mCCD_R	<=	0;
+		mCCD_G	<=	0;
+		mCCD_B	<=	0;
+		mDATAd_0<=	0;
+		mDATAd_1<=	0;
+		mDVAL	<=	0;
+	end
+	else
+	begin
+		mDATAd_0	<=	mDATA_0;
+		mDATAd_1	<=	mDATA_1;
+		mDVAL		<=	{iY_Cont[0]|iX_Cont[0]}	?	1'b0	:	iDVAL;
+		if({iY_Cont[0],iX_Cont[0]}==2'b10)
+		begin
+			mCCD_R	<=	mDATA_0;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATAd_1;
+		end	
+		else if({iY_Cont[0],iX_Cont[0]}==2'b11)
+		begin
+			mCCD_R	<=	mDATAd_0;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATA_1;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b00)
+		begin
+			mCCD_R	<=	mDATA_1;
+			mCCD_G	<=	mDATA_0+mDATAd_1;
+			mCCD_B	<=	mDATAd_0;
+		end
+		else if({iY_Cont[0],iX_Cont[0]}==2'b01)
+		begin
+			mCCD_R	<=	mDATAd_1;
+			mCCD_G	<=	mDATAd_0+mDATA_1;
+			mCCD_B	<=	mDATA_0;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v
new file mode 100644
index 0000000..578a964
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/Reset_Delay.v
@@ -0,0 +1,74 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	Reset_Delay
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module	Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
+input		iCLK;
+input		iRST;
+output reg	oRST_0;
+output reg	oRST_1;
+output reg	oRST_2;
+
+reg	[31:0]	Cont;
+
+always@(posedge iCLK or negedge iRST)
+begin
+	if(!iRST)
+	begin
+		Cont	<=	0;
+		oRST_0	<=	0;
+		oRST_1	<=	0;
+		oRST_2	<=	0;
+	end
+	else
+	begin
+		if(Cont!=32'h11FFFFF)
+		Cont	<=	Cont+1;
+		if(Cont>=32'h1FFFFF)
+		oRST_0	<=	1;
+		if(Cont>=32'h2FFFFF)
+		oRST_1	<=	1;
+		if(Cont>=32'h11FFFFF)
+		oRST_2	<=	1;
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v
new file mode 100644
index 0000000..2756db0
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT.v
@@ -0,0 +1,70 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT	(	oSEG,iDIG	);
+input	[3:0]	iDIG;
+output	[6:0]	oSEG;
+reg		[6:0]	oSEG;
+
+always @(iDIG)
+begin
+		case(iDIG)
+		4'h1: oSEG = 7'b1111001;	// ---t----
+		4'h2: oSEG = 7'b0100100; 	// |	  |
+		4'h3: oSEG = 7'b0110000; 	// lt	 rt
+		4'h4: oSEG = 7'b0011001; 	// |	  |
+		4'h5: oSEG = 7'b0010010; 	// ---m----
+		4'h6: oSEG = 7'b0000010; 	// |	  |
+		4'h7: oSEG = 7'b1111000; 	// lb	 rb
+		4'h8: oSEG = 7'b0000000; 	// |	  |
+		4'h9: oSEG = 7'b0011000; 	// ---b----
+		4'ha: oSEG = 7'b0001000;
+		4'hb: oSEG = 7'b0000011;
+		4'hc: oSEG = 7'b1000110;
+		4'hd: oSEG = 7'b0100001;
+		4'he: oSEG = 7'b0000110;
+		4'hf: oSEG = 7'b0001110;
+		4'h0: oSEG = 7'b1000000;
+		endcase
+end
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v
new file mode 100644
index 0000000..e84af4e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/SEG7_LUT_8.v
@@ -0,0 +1,56 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2007 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	SEG7_LUT_8
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN        :| 07/07/09  :| Initial Revision
+// --------------------------------------------------------------------
+
+module SEG7_LUT_8 (	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input	[31:0]	iDIG;
+output	[6:0]	oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT	u0	(	oSEG0,iDIG[3:0]		);
+SEG7_LUT	u1	(	oSEG1,iDIG[7:4]		);
+SEG7_LUT	u2	(	oSEG2,iDIG[11:8]	);
+SEG7_LUT	u3	(	oSEG3,iDIG[15:12]	);
+SEG7_LUT	u4	(	oSEG4,iDIG[19:16]	);
+SEG7_LUT	u5	(	oSEG5,iDIG[23:20]	);
+SEG7_LUT	u6	(	oSEG6,iDIG[27:24]	);
+SEG7_LUT	u7	(	oSEG7,iDIG[31:28]	);
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf
new file mode 100644
index 0000000..aa3e75d
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/TOP_DE0_CAMERA_MOUSE.bdf
@@ -0,0 +1,1746 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 424 88 592 104)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "CLOCK_50" (rect 5 0 60 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 288 232 352 248))
+)
+(pin
+	(input)
+	(rect 512 120 680 136)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "SW[9..0]" (rect 5 0 48 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 448 136 504 152))
+)
+(pin
+	(input)
+	(rect 480 136 704 152)
+	(text "INPUT" (rect 180 6 208 16)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKIN[1..0]" (rect 6 4 109 16)(font "Arial" ))
+	(pt 224 8)
+	(drawing
+		(line (pt 139 4)(pt 164 4))
+		(line (pt 139 12)(pt 164 12))
+		(line (pt 168 8)(pt 223 8))
+		(line (pt 139 4)(pt 139 12))
+		(line (pt 164 12)(pt 168 8))
+		(line (pt 164 4)(pt 168 8))
+	)
+	(flipx)
+	(text "VCC" (rect 183 -1 203 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 664 192 720 208))
+)
+(pin
+	(input)
+	(rect 424 104 592 120)
+	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
+	(text "KEY[2..0]" (rect 5 0 53 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 336 344 392 360))
+)
+(pin
+	(output)
+	(rect 504 24 680 40)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "LEDG[9..0]" (rect 5 0 60 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 96 168 160 184))
+)
+(pin
+	(output)
+	(rect 1144 200 1320 216)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_LDQM" (rect 103 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1008 296 1072 312))
+)
+(pin
+	(output)
+	(rect 1144 216 1320 232)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_UDQM" (rect 101 0 171 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 192 1416 208))
+)
+(pin
+	(output)
+	(rect 1144 312 1320 328)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_1" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 288 1416 304))
+)
+(pin
+	(output)
+	(rect 1144 296 1320 312)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_BA_0" (rect 107 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1008 264 1072 280))
+)
+(pin
+	(output)
+	(rect 1144 248 1320 264)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 224 1424 240))
+)
+(pin
+	(output)
+	(rect 1144 344 1320 360)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CKE" (rect 110 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 320 1424 336))
+)
+(pin
+	(output)
+	(rect 1144 280 1320 296)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CS_N" (rect 103 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 256 1416 272))
+)
+(pin
+	(output)
+	(rect 1144 264 1320 280)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_RAS_N" (rect 96 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 240 1416 256))
+)
+(pin
+	(output)
+	(rect 1144 232 1320 248)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_WE_N" (rect 101 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1360 208 1416 224))
+)
+(pin
+	(output)
+	(rect 1144 328 1320 344)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_CLK" (rect 111 0 170 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 96 688 160 704))
+)
+(pin
+	(output)
+	(rect 736 1272 912 1288)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_CLK" (rect 37 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 912 1288 968 1304))
+)
+(pin
+	(output)
+	(rect 736 1224 912 1240)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_HS" (rect 43 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 616 1240 672 1256))
+)
+(pin
+	(output)
+	(rect 736 1240 912 1256)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_VS" (rect 44 0 86 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 624 1256 680 1272))
+)
+(pin
+	(output)
+	(rect 736 1176 912 1192)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_R[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 648 1152 704 1168))
+)
+(pin
+	(output)
+	(rect 736 1192 912 1208)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_G[3..0]" (rect 5 0 67 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 624 1200 680 1216))
+)
+(pin
+	(output)
+	(rect 736 1208 912 1224)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "VGA_B[3..0]" (rect 5 0 66 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 624 1216 680 1232))
+)
+(pin
+	(output)
+	(rect 1144 184 1353 200)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DRAM_ADDR[11..0] " (rect 98 0 203 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1296 144 1360 160))
+)
+(pin
+	(output)
+	(rect 504 -64 680 -48)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX3[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 360 -72 424 -56))
+)
+(pin
+	(output)
+	(rect 504 -48 680 -32)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX2[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 416 32 480 48))
+)
+(pin
+	(output)
+	(rect 504 -32 680 -16)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX1[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 208 56 272 72))
+)
+(pin
+	(output)
+	(rect 504 -16 680 0)
+	(text "OUTPUT" (rect 137 0 175 10)(font "Arial" (font_size 6)))
+	(text "HEX0[6..0]" (rect 5 0 58 12)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 124 4)(pt 98 4))
+		(line (pt 124 12)(pt 98 12))
+		(line (pt 124 12)(pt 124 4))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 94 8)(pt 98 12))
+		(line (pt 98 12)(pt 94 8))
+	)
+	(flipy)
+	(annotation_block (location)(rect 552 32 616 48))
+)
+(pin
+	(output)
+	(rect 1144 504 1354 520)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1_CLKOUT[1..0]" (rect 90 0 204 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1416 504 1472 520))
+)
+(pin
+	(bidir)
+	(rect 1144 168 1328 184)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "DRAM_DQ[15..0] " (rect 90 0 179 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1448 96 1512 112))
+)
+(pin
+	(bidir)
+	(rect 376 576 552 592)
+	(text "BIDIR" (rect 151 6 175 16)(font "Arial" (font_size 6)))
+	(text "PS2_DAT" (rect 5 4 52 16)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 120 12)(pt 98 12))
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 120 4)(pt 98 4))
+		(line (pt 98 12)(pt 94 8))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 120 12)(pt 124 8))
+		(line (pt 124 8)(pt 120 4))
+	)
+	(rotate180)
+	(text "VCC" (rect 152 -1 172 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 120 504 176 520))
+)
+(pin
+	(bidir)
+	(rect 376 600 552 616)
+	(text "BIDIR" (rect 151 6 175 16)(font "Arial" (font_size 6)))
+	(text "PS2_CLK" (rect 5 4 52 16)(font "Arial" ))
+	(pt 176 8)
+	(drawing
+		(line (pt 120 12)(pt 98 12))
+		(line (pt 176 8)(pt 124 8))
+		(line (pt 120 4)(pt 98 4))
+		(line (pt 98 12)(pt 94 8))
+		(line (pt 98 4)(pt 94 8))
+		(line (pt 120 12)(pt 124 8))
+		(line (pt 124 8)(pt 120 4))
+	)
+	(rotate180)
+	(text "VCC" (rect 152 -1 172 9)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 504 632 560 648))
+)
+(pin
+	(bidir)
+	(rect 1144 520 1320 536)
+	(text "BIDIR" (rect 1 0 25 10)(font "Arial" (font_size 6)))
+	(text "GPIO_1[31..0]" (rect 90 0 160 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 56 4)(pt 78 4))
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 56 12)(pt 78 12))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 78 12)(pt 82 8))
+		(line (pt 56 4)(pt 52 8))
+		(line (pt 52 8)(pt 56 12))
+	)
+	(text "VCC" (rect 4 7 24 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 1368 584 1424 600))
+)
+(symbol
+	(rect 992 952 1024 984)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst5" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 1496 944 1528 960)
+	(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
+	(text "inst4" (rect 3 5 26 17)(font "Arial" )(invisible))
+	(port
+		(pt 16 16)
+		(output)
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(line (pt 16 16)(pt 16 8))
+	)
+	(drawing
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 760 704 968 944)
+	(text "ps2" (rect 5 0 22 12)(font "Arial" ))
+	(text "inst6" (rect 8 224 31 236)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "iSTART" (rect 0 0 36 12)(font "Arial" ))
+		(text "iSTART" (rect 21 27 57 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "iRST_n" (rect 0 0 35 12)(font "Arial" ))
+		(text "iRST_n" (rect 21 43 56 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "iCLK_50" (rect 0 0 41 12)(font "Arial" ))
+		(text "iCLK_50" (rect 21 59 62 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "oLEFBUT" (rect 0 0 47 12)(font "Arial" ))
+		(text "oLEFBUT" (rect 148 59 195 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "oRIGBUT" (rect 0 0 47 12)(font "Arial" ))
+		(text "oRIGBUT" (rect 148 75 195 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "oMIDBUT" (rect 0 0 47 12)(font "Arial" ))
+		(text "oMIDBUT" (rect 148 91 195 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "oX[7..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "oX[7..0]" (rect 156 107 193 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112)(line_width 3))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "oY[7..0]" (rect 0 0 40 12)(font "Arial" ))
+		(text "oY[7..0]" (rect 154 123 194 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128)(line_width 3))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "oX_MOV1[6..0]" (rect 0 0 73 12)(font "Arial" ))
+		(text "oX_MOV1[6..0]" (rect 126 139 199 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144)(line_width 3))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "oX_MOV2[6..0]" (rect 0 0 73 12)(font "Arial" ))
+		(text "oX_MOV2[6..0]" (rect 126 155 199 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160)(line_width 3))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "oY_MOV1[6..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "oY_MOV1[6..0]" (rect 124 171 199 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "oY_MOV2[6..0]" (rect 0 0 75 12)(font "Arial" ))
+		(text "oY_MOV2[6..0]" (rect 124 187 199 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 32)
+		(bidir)
+		(text "PS2_CLK" (rect 0 0 47 12)(font "Arial" ))
+		(text "PS2_CLK" (rect 145 27 192 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32))
+	)
+	(port
+		(pt 208 48)
+		(bidir)
+		(text "PS2_DAT" (rect 0 0 47 12)(font "Arial" ))
+		(text "PS2_DAT" (rect 144 43 191 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48))
+	)
+	(parameter
+		"enable_byte"
+		"011110100"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"listen"
+		"00"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pullclk"
+		"01"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pulldat"
+		"10"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"trans"
+		"11"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(drawing
+		(rectangle (rect 16 16 192 224))
+	)
+	(annotation_block (parameter)(rect 736 616 960 704))
+)
+(symbol
+	(rect 2304 1056 2448 1168)
+	(text "vga_mux" (rect 48 0 108 16)(font "Arial" (font_size 10)))
+	(text "inst10" (rect 8 96 37 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[29..0]" (rect 4 26 78 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[29..0]" (rect 4 42 78 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[29..0]" (rect 4 58 78 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[29..0]" (rect 4 74 78 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 72 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 65 59 79 103)(font "Arial" (font_size 8))(vertical))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
+	)
+	(port
+		(pt 144 64)
+		(output)
+		(text "result[29..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[29..0]" (rect 84 50 151 64)(font "Arial" (font_size 8)))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 104))
+		(line (pt 64 24)(pt 80 32))
+		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 32)(pt 80 96))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
+(symbol
+	(rect 760 64 1048 560)
+	(text "DE0_D5M" (rect 5 0 54 12)(font "Arial" ))
+	(text "inst" (rect 8 480 25 492)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "CLOCK_50" (rect 0 0 55 12)(font "Arial" ))
+		(text "CLOCK_50" (rect 21 27 76 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "KEY[2..0]" (rect 0 0 48 12)(font "Arial" ))
+		(text "KEY[2..0]" (rect 21 43 69 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "SW[9..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "SW[9..0]" (rect 21 59 64 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "GPIO_1_CLKIN[1..0]" (rect 0 0 103 12)(font "Arial" ))
+		(text "GPIO_1_CLKIN[1..0]" (rect 21 75 124 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "LEDG[9..0]" (rect 0 0 55 12)(font "Arial" ))
+		(text "LEDG[9..0]" (rect 221 27 276 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(port
+		(pt 288 48)
+		(output)
+		(text "HEX0[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX0[6..0]" (rect 223 43 276 55)(font "Arial" ))
+		(line (pt 288 48)(pt 272 48)(line_width 3))
+	)
+	(port
+		(pt 288 64)
+		(output)
+		(text "HEX1[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX1[6..0]" (rect 223 59 276 71)(font "Arial" ))
+		(line (pt 288 64)(pt 272 64)(line_width 3))
+	)
+	(port
+		(pt 288 80)
+		(output)
+		(text "HEX2[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX2[6..0]" (rect 223 75 276 87)(font "Arial" ))
+		(line (pt 288 80)(pt 272 80)(line_width 3))
+	)
+	(port
+		(pt 288 96)
+		(output)
+		(text "HEX3[6..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "HEX3[6..0]" (rect 223 91 276 103)(font "Arial" ))
+		(line (pt 288 96)(pt 272 96)(line_width 3))
+	)
+	(port
+		(pt 288 128)
+		(output)
+		(text "DRAM_ADDR[11..0]" (rect 0 0 101 12)(font "Arial" ))
+		(text "DRAM_ADDR[11..0]" (rect 182 123 283 135)(font "Arial" ))
+		(line (pt 288 128)(pt 272 128)(line_width 3))
+	)
+	(port
+		(pt 288 144)
+		(output)
+		(text "DRAM_LDQM" (rect 0 0 68 12)(font "Arial" ))
+		(text "DRAM_LDQM" (rect 210 139 278 151)(font "Arial" ))
+		(line (pt 288 144)(pt 272 144))
+	)
+	(port
+		(pt 288 160)
+		(output)
+		(text "DRAM_UDQM" (rect 0 0 70 12)(font "Arial" ))
+		(text "DRAM_UDQM" (rect 208 155 278 167)(font "Arial" ))
+		(line (pt 288 160)(pt 272 160))
+	)
+	(port
+		(pt 288 176)
+		(output)
+		(text "DRAM_WE_N" (rect 0 0 69 12)(font "Arial" ))
+		(text "DRAM_WE_N" (rect 209 171 278 183)(font "Arial" ))
+		(line (pt 288 176)(pt 272 176))
+	)
+	(port
+		(pt 288 192)
+		(output)
+		(text "DRAM_CAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_CAS_N" (rect 205 187 279 199)(font "Arial" ))
+		(line (pt 288 192)(pt 272 192))
+	)
+	(port
+		(pt 288 208)
+		(output)
+		(text "DRAM_RAS_N" (rect 0 0 74 12)(font "Arial" ))
+		(text "DRAM_RAS_N" (rect 205 203 279 215)(font "Arial" ))
+		(line (pt 288 208)(pt 272 208))
+	)
+	(port
+		(pt 288 224)
+		(output)
+		(text "DRAM_CS_N" (rect 0 0 67 12)(font "Arial" ))
+		(text "DRAM_CS_N" (rect 211 219 278 231)(font "Arial" ))
+		(line (pt 288 224)(pt 272 224))
+	)
+	(port
+		(pt 288 240)
+		(output)
+		(text "DRAM_BA_0" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_0" (rect 214 235 277 247)(font "Arial" ))
+		(line (pt 288 240)(pt 272 240))
+	)
+	(port
+		(pt 288 256)
+		(output)
+		(text "DRAM_BA_1" (rect 0 0 63 12)(font "Arial" ))
+		(text "DRAM_BA_1" (rect 214 251 277 263)(font "Arial" ))
+		(line (pt 288 256)(pt 272 256))
+	)
+	(port
+		(pt 288 272)
+		(output)
+		(text "DRAM_CLK" (rect 0 0 59 12)(font "Arial" ))
+		(text "DRAM_CLK" (rect 218 267 277 279)(font "Arial" ))
+		(line (pt 288 272)(pt 272 272))
+	)
+	(port
+		(pt 288 288)
+		(output)
+		(text "DRAM_CKE" (rect 0 0 60 12)(font "Arial" ))
+		(text "DRAM_CKE" (rect 217 283 277 295)(font "Arial" ))
+		(line (pt 288 288)(pt 272 288))
+	)
+	(port
+		(pt 288 304)
+		(output)
+		(text "VGA_HS" (rect 0 0 43 12)(font "Arial" ))
+		(text "VGA_HS" (rect 231 299 274 311)(font "Arial" ))
+		(line (pt 288 304)(pt 272 304))
+	)
+	(port
+		(pt 288 320)
+		(output)
+		(text "VGA_VS" (rect 0 0 42 12)(font "Arial" ))
+		(text "VGA_VS" (rect 232 315 274 327)(font "Arial" ))
+		(line (pt 288 320)(pt 272 320))
+	)
+	(port
+		(pt 288 336)
+		(output)
+		(text "VGA_R[9..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_R[9..0]" (rect 215 331 277 343)(font "Arial" ))
+		(line (pt 288 336)(pt 272 336)(line_width 3))
+	)
+	(port
+		(pt 288 352)
+		(output)
+		(text "VGA_G[9..0]" (rect 0 0 62 12)(font "Arial" ))
+		(text "VGA_G[9..0]" (rect 215 347 277 359)(font "Arial" ))
+		(line (pt 288 352)(pt 272 352)(line_width 3))
+	)
+	(port
+		(pt 288 368)
+		(output)
+		(text "VGA_B[9..0]" (rect 0 0 61 12)(font "Arial" ))
+		(text "VGA_B[9..0]" (rect 216 363 277 375)(font "Arial" ))
+		(line (pt 288 368)(pt 272 368)(line_width 3))
+	)
+	(port
+		(pt 288 384)
+		(output)
+		(text "VGA_CLK" (rect 0 0 49 12)(font "Arial" ))
+		(text "VGA_CLK" (rect 226 379 275 391)(font "Arial" ))
+		(line (pt 288 384)(pt 272 384))
+	)
+	(port
+		(pt 288 400)
+		(output)
+		(text "VGA_X[11..0]" (rect 0 0 66 12)(font "Arial" ))
+		(text "VGA_X[11..0]" (rect 212 395 278 407)(font "Arial" ))
+		(line (pt 288 400)(pt 272 400)(line_width 3))
+	)
+	(port
+		(pt 288 416)
+		(output)
+		(text "VGA_Y[11..0]" (rect 0 0 68 12)(font "Arial" ))
+		(text "VGA_Y[11..0]" (rect 210 411 278 423)(font "Arial" ))
+		(line (pt 288 416)(pt 272 416)(line_width 3))
+	)
+	(port
+		(pt 288 432)
+		(output)
+		(text "VGA_ACTIVE" (rect 0 0 67 12)(font "Arial" ))
+		(text "VGA_ACTIVE" (rect 211 427 278 439)(font "Arial" ))
+		(line (pt 288 432)(pt 272 432))
+	)
+	(port
+		(pt 288 448)
+		(output)
+		(text "GPIO_1_CLKOUT[1..0]" (rect 0 0 114 12)(font "Arial" ))
+		(text "GPIO_1_CLKOUT[1..0]" (rect 171 443 285 455)(font "Arial" ))
+		(line (pt 288 448)(pt 272 448)(line_width 3))
+	)
+	(port
+		(pt 288 112)
+		(bidir)
+		(text "DRAM_DQ[15..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "DRAM_DQ[15..0]" (rect 192 107 278 119)(font "Arial" ))
+		(line (pt 288 112)(pt 272 112)(line_width 3))
+	)
+	(port
+		(pt 288 464)
+		(bidir)
+		(text "GPIO_1[31..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "GPIO_1[31..0]" (rect 212 459 282 471)(font "Arial" ))
+		(line (pt 288 464)(pt 272 464)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 480))
+	)
+)
+(symbol
+	(rect 1800 536 1832 568)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst7" (rect 3 21 26 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(symbol
+	(rect 1896 456 2040 560)
+	(text "ALTSHIFT_TAPS" (rect 23 1 141 17)(font "Arial" (font_size 10)))
+	(text "fifo_inst2" (rect 8 88 55 100)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "shiftin[WIDTH-1..0]" (rect 0 0 96 12)(font "Arial" ))
+		(text "shiftin[]" (rect 21 25 62 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "clken" (rect 0 0 25 12)(font "Arial" ))
+		(text "clken" (rect 21 57 50 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 25 12)(font "Arial" ))
+		(text "clock" (rect 21 41 50 55)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "aclr" (rect 24 72 45 86)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 24 72 45 86)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "shiftout[WIDTH-1..0]" (rect -208 0 -105 12)(font "Arial" ))
+		(text "shiftout[]" (rect 82 25 131 39)(font "Arial" (font_size 8)))
+		(line (pt 144 32)(pt 128 32)(line_width 3))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "taps[(WIDTH*NUMBER_OF_TAPS) -1..0]" (rect -208 0 -4 12)(font "Arial" ))
+		(text "taps[]" (rect 97 41 128 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(parameter
+		"NUMBER_OF_TAPS"
+		"5"
+		"Number of output taps, each separated by TAP_DISTANCE clock cycles"
+	)
+	(parameter
+		"TAP_DISTANCE"
+		"800"
+		"Number of shift positions between output taps"
+	)
+	(parameter
+		"WIDTH"
+		"30"
+		"Number of bits for the shiftin input"
+	)
+	(drawing
+		(line (pt 16 56)(pt 24 48))
+		(line (pt 16 40)(pt 24 48))
+		(rectangle (rect 16 16 128 88))
+	)
+	(annotation_block (parameter)(rect 1880 400 2049 456))
+)
+(symbol
+	(rect 1672 848 1960 1024)
+	(text "vga_mouse_square" (rect 5 0 101 12)(font "Arial" ))
+	(text "vga_mouse_catapult_inst" (rect 8 160 134 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vga_xy_rsc_z[19..0]" (rect 0 0 101 12)(font "Arial" ))
+		(text "vga_xy_rsc_z[19..0]" (rect 21 27 122 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "mouse_xy_rsc_z[19..0]" (rect 0 0 115 12)(font "Arial" ))
+		(text "mouse_xy_rsc_z[19..0]" (rect 21 43 136 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "cursor_size_rsc_z[7..0]" (rect 0 0 113 12)(font "Arial" ))
+		(text "cursor_size_rsc_z[7..0]" (rect 21 59 134 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "video_in_rsc_z[29..0]" (rect 0 0 105 12)(font "Arial" ))
+		(text "video_in_rsc_z[29..0]" (rect 21 75 126 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 91 35 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "en" (rect 0 0 11 12)(font "Arial" ))
+		(text "en" (rect 21 107 32 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "arst_n" (rect 0 0 30 12)(font "Arial" ))
+		(text "arst_n" (rect 21 123 51 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "video_out_rsc_z[29..0]" (rect 0 0 112 12)(font "Arial" ))
+		(text "video_out_rsc_z[29..0]" (rect 173 27 285 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 160))
+	)
+)
+(symbol
+	(rect 1704 1080 1944 1192)
+	(text "mean_vga" (rect 5 0 56 12)(font "Arial" ))
+	(text "vga_blur_catapult_inst" (rect 8 96 118 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vin_rsc_z[89..0]" (rect 0 0 79 12)(font "Arial" ))
+		(text "vin_rsc_z[89..0]" (rect 21 27 100 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 14 12)(font "Arial" ))
+		(text "clk" (rect 21 43 35 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 11 12)(font "Arial" ))
+		(text "en" (rect 21 59 32 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "arst_n" (rect 0 0 30 12)(font "Arial" ))
+		(text "arst_n" (rect 21 75 51 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 240 32)
+		(output)
+		(text "vout_rsc_z[29..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "vout_rsc_z[29..0]" (rect 147 27 233 39)(font "Arial" ))
+		(line (pt 240 32)(pt 224 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 224 96))
+	)
+)
+(symbol
+	(rect 1528 1128 1560 1144)
+	(text "VCC" (rect 7 0 27 10)(font "Arial" (font_size 6)))
+	(text "inst8" (rect 3 5 26 17)(font "Arial" )(invisible))
+	(port
+		(pt 16 16)
+		(output)
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 19 7 24 19)(font "Courier New" (bold))(invisible))
+		(line (pt 16 16)(pt 16 8))
+	)
+	(drawing
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(connector
+	(pt 1048 96)
+	(pt 1080 96)
+	(bus)
+)
+(connector
+	(pt 1048 112)
+	(pt 1096 112)
+	(bus)
+)
+(connector
+	(pt 1112 128)
+	(pt 1048 128)
+	(bus)
+)
+(connector
+	(pt 1128 144)
+	(pt 1048 144)
+	(bus)
+)
+(connector
+	(pt 1144 160)
+	(pt 1048 160)
+	(bus)
+)
+(connector
+	(pt 1048 176)
+	(pt 1144 176)
+	(bus)
+)
+(connector
+	(pt 1048 192)
+	(pt 1144 192)
+	(bus)
+)
+(connector
+	(pt 1048 208)
+	(pt 1144 208)
+)
+(connector
+	(pt 1048 224)
+	(pt 1144 224)
+)
+(connector
+	(pt 1048 240)
+	(pt 1144 240)
+)
+(connector
+	(pt 1048 256)
+	(pt 1144 256)
+)
+(connector
+	(pt 1048 272)
+	(pt 1144 272)
+)
+(connector
+	(pt 1048 288)
+	(pt 1144 288)
+)
+(connector
+	(pt 1048 304)
+	(pt 1144 304)
+)
+(connector
+	(pt 1048 320)
+	(pt 1144 320)
+)
+(connector
+	(pt 1048 336)
+	(pt 1144 336)
+)
+(connector
+	(pt 1048 352)
+	(pt 1144 352)
+)
+(connector
+	(pt 1080 96)
+	(pt 1080 32)
+	(bus)
+)
+(connector
+	(pt 1096 112)
+	(pt 1096 -8)
+	(bus)
+)
+(connector
+	(pt 1112 128)
+	(pt 1112 -24)
+	(bus)
+)
+(connector
+	(pt 1128 144)
+	(pt 1128 -40)
+	(bus)
+)
+(connector
+	(pt 1144 160)
+	(pt 1144 -56)
+	(bus)
+)
+(connector
+	(pt 656 736)
+	(pt 656 728)
+)
+(connector
+	(text "HEX1[6..0]" (rect 978 848 1031 860)(font "Arial" ))
+	(pt 968 864)
+	(pt 1096 864)
+	(bus)
+)
+(connector
+	(text "HEX2[6..0]" (rect 978 864 1031 876)(font "Arial" ))
+	(pt 968 880)
+	(pt 1096 880)
+	(bus)
+)
+(connector
+	(text "HEX3[6..0]" (rect 978 880 1031 892)(font "Arial" ))
+	(pt 968 896)
+	(pt 1096 896)
+	(bus)
+)
+(connector
+	(text "MOUSE_X[1..0]" (rect 1018 912 1094 924)(font "Arial" ))
+	(pt 1008 928)
+	(pt 1120 928)
+	(bus)
+)
+(connector
+	(text "MOUSE_Y[1..0]" (rect 1018 928 1097 940)(font "Arial" ))
+	(pt 1008 944)
+	(pt 1120 944)
+	(bus)
+)
+(connector
+	(text "KEY[1]" (rect 666 720 701 732)(font "Arial" ))
+	(pt 656 736)
+	(pt 760 736)
+)
+(connector
+	(text "KEY[0]" (rect 666 736 701 748)(font "Arial" ))
+	(pt 656 752)
+	(pt 760 752)
+)
+(connector
+	(pt 1008 928)
+	(pt 1008 944)
+	(bus)
+)
+(connector
+	(pt 1008 944)
+	(pt 1008 952)
+	(bus)
+)
+(connector
+	(text "PS2_CLK" (rect 986 720 1033 732)(font "Arial" ))
+	(pt 968 736)
+	(pt 1072 736)
+)
+(connector
+	(text "PS2_DAT" (rect 978 736 1025 748)(font "Arial" ))
+	(pt 968 752)
+	(pt 1072 752)
+)
+(connector
+	(text "HEX0[6..0]" (rect 978 832 1031 844)(font "Arial" ))
+	(pt 968 848)
+	(pt 1096 848)
+	(bus)
+)
+(connector
+	(text "LEDG[2]" (rect 978 752 1020 764)(font "Arial" ))
+	(pt 968 768)
+	(pt 1096 768)
+)
+(connector
+	(text "VGA_CLK" (rect 1058 432 1107 444)(font "Arial" ))
+	(pt 1048 448)
+	(pt 1232 448)
+)
+(connector
+	(pt 760 144)
+	(pt 704 144)
+	(bus)
+)
+(connector
+	(text "oLEDG[9..0]" (rect 978 16 1039 28)(font "Arial" ))
+	(pt 1080 32)
+	(pt 968 32)
+	(bus)
+)
+(connector
+	(text "X[11..0]" (rect 1056 448 1093 460)(font "Arial" ))
+	(pt 1048 464)
+	(pt 1256 464)
+	(bus)
+)
+(connector
+	(text "Y[11..0]" (rect 1056 464 1096 476)(font "Arial" ))
+	(pt 1048 480)
+	(pt 1256 480)
+	(bus)
+)
+(connector
+	(pt 760 128)
+	(pt 680 128)
+	(bus)
+)
+(connector
+	(text "CLOCK_50" (rect 666 752 721 764)(font "Arial" ))
+	(pt 656 768)
+	(pt 760 768)
+)
+(connector
+	(pt 552 608)
+	(pt 640 608)
+)
+(connector
+	(pt 640 608)
+	(pt 640 616)
+)
+(connector
+	(pt 552 584)
+	(pt 640 584)
+)
+(connector
+	(text "CLOCK_50" (rect 602 80 657 92)(font "Arial" ))
+	(pt 592 96)
+	(pt 760 96)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -24 1037 -12)(font "Arial" ))
+	(pt 1096 -8)
+	(pt 968 -8)
+	(bus)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -40 1037 -28)(font "Arial" ))
+	(pt 1112 -24)
+	(pt 968 -24)
+	(bus)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -56 1037 -44)(font "Arial" ))
+	(pt 1128 -40)
+	(pt 968 -40)
+	(bus)
+)
+(connector
+	(text "oHEX0[6..0]" (rect 978 -72 1037 -60)(font "Arial" ))
+	(pt 1144 -56)
+	(pt 968 -56)
+	(bus)
+)
+(connector
+	(text "KEY[2..0]" (rect 602 96 650 108)(font "Arial" ))
+	(pt 592 112)
+	(pt 760 112)
+	(bus)
+)
+(connector
+	(pt 2376 1168)
+	(pt 2376 1216)
+	(bus)
+)
+(connector
+	(text "SW[5..4]" (rect 2306 1200 2349 1212)(font "Arial" ))
+	(pt 2376 1216)
+	(pt 2296 1216)
+	(bus)
+)
+(connector
+	(pt 1048 512)
+	(pt 1144 512)
+	(bus)
+)
+(connector
+	(pt 1048 528)
+	(pt 1144 528)
+	(bus)
+)
+(connector
+	(text "VGA_HS" (rect 1058 352 1101 364)(font "Arial" ))
+	(pt 1048 368)
+	(pt 1128 368)
+)
+(connector
+	(text "VGA_VS" (rect 1058 368 1100 380)(font "Arial" ))
+	(pt 1048 384)
+	(pt 1128 384)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 2122 1128 2230 1140)(font "Arial" ))
+	(pt 2304 1144)
+	(pt 2112 1144)
+	(bus)
+)
+(connector
+	(text "VGA_MOUSE_OUT[29..0]" (rect 2130 1112 2257 1124)(font "Arial" ))
+	(pt 2120 1128)
+	(pt 2304 1128)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[29..0]" (rect 2458 1104 2568 1116)(font "Arial" ))
+	(pt 2448 1120)
+	(pt 2600 1120)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[29..26]" (rect 922 1168 1038 1180)(font "Arial" ))
+	(pt 912 1184)
+	(pt 1120 1184)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[19..16]" (rect 922 1184 1038 1196)(font "Arial" ))
+	(pt 912 1200)
+	(pt 1120 1200)
+	(bus)
+)
+(connector
+	(text "VGA_MUX_OUT[9..6]" (rect 922 1200 1027 1212)(font "Arial" ))
+	(pt 912 1216)
+	(pt 1120 1216)
+	(bus)
+)
+(connector
+	(text "R[9..0]" (rect 1058 384 1092 396)(font "Arial" ))
+	(pt 1048 400)
+	(pt 1256 400)
+	(bus)
+)
+(connector
+	(text "G[9..0]" (rect 1058 400 1092 412)(font "Arial" ))
+	(pt 1048 416)
+	(pt 1256 416)
+	(bus)
+)
+(connector
+	(text "B[9..0]" (rect 1058 416 1091 428)(font "Arial" ))
+	(pt 1048 432)
+	(pt 1256 432)
+	(bus)
+)
+(connector
+	(text "LEDG[0]" (rect 978 768 1020 780)(font "Arial" ))
+	(pt 968 784)
+	(pt 1096 784)
+)
+(connector
+	(text "LEDG[1]" (rect 978 784 1020 796)(font "Arial" ))
+	(pt 968 800)
+	(pt 1096 800)
+)
+(connector
+	(text "MOUSE_Y[9..2]" (rect 978 800 1057 812)(font "Arial" ))
+	(pt 968 816)
+	(pt 1096 816)
+	(bus)
+)
+(connector
+	(text "MOUSE_X[9..2]" (rect 978 816 1054 828)(font "Arial" ))
+	(pt 968 832)
+	(pt 1096 832)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1842 488 1891 500)(font "Arial" ))
+	(pt 1840 504)
+	(pt 1896 504)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 1706 472 1814 484)(font "Arial" ))
+	(pt 1896 488)
+	(pt 1696 488)
+	(bus)
+)
+(connector
+	(pt 1816 536)
+	(pt 1896 536)
+)
+(connector
+	(text "RGB_TAP[149..0]" (rect 2050 488 2137 500)(font "Arial" ))
+	(pt 2040 504)
+	(pt 2152 504)
+	(bus)
+)
+(connector
+	(pt 2152 504)
+	(pt 2104 528)
+	(bus)
+)
+(connector
+	(text "VGA_ACTIVE" (rect 1634 504 1701 516)(font "Arial" ))
+	(pt 1624 520)
+	(pt 1896 520)
+)
+(connector
+	(text "VGA_ACTIVE" (rect 1058 480 1125 492)(font "Arial" ))
+	(pt 1048 496)
+	(pt 1192 496)
+)
+(connector
+	(text "RGB_TAP[59..30]" (rect 2202 1080 2289 1092)(font "Arial" ))
+	(pt 2304 1096)
+	(pt 2192 1096)
+	(bus)
+)
+(connector
+	(text "X[9..0],Y[9..0]" (rect 1474 864 1543 876)(font "Arial" ))
+	(pt 1464 880)
+	(pt 1672 880)
+	(bus)
+)
+(connector
+	(text "SW[7..0]" (rect 1474 896 1517 908)(font "Arial" ))
+	(pt 1464 912)
+	(pt 1672 912)
+	(bus)
+)
+(connector
+	(text "R[9..0],G[9..0],B[9..0]" (rect 1474 912 1582 924)(font "Arial" ))
+	(pt 1464 928)
+	(pt 1672 928)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1594 928 1643 940)(font "Arial" ))
+	(pt 1584 944)
+	(pt 1672 944)
+)
+(connector
+	(text "MOUSE_X[9..0],MOUSE_Y[9..0]" (rect 1472 880 1631 892)(font "Arial" ))
+	(pt 1464 896)
+	(pt 1672 896)
+	(bus)
+)
+(connector
+	(pt 1512 960)
+	(pt 1672 960)
+)
+(connector
+	(text "KEY[0]" (rect 1618 960 1653 972)(font "Arial" ))
+	(pt 1608 976)
+	(pt 1672 976)
+)
+(connector
+	(text "VGA_MOUSE_OUT[29..0]" (rect 2002 864 2129 876)(font "Arial" ))
+	(pt 1960 880)
+	(pt 2192 880)
+	(bus)
+)
+(connector
+	(text "<<__$DEF_ALIAS133>>" (rect 1954 1096 2072 1108)(font "Arial" )(invisible))
+	(pt 2304 1112)
+	(pt 1944 1112)
+	(bus)
+)
+(connector
+	(text "VGA_CLK" (rect 1626 1112 1675 1124)(font "Arial" ))
+	(pt 1616 1128)
+	(pt 1704 1128)
+)
+(connector
+	(pt 1544 1144)
+	(pt 1704 1144)
+)
+(connector
+	(text "KEY[0]" (rect 1650 1144 1685 1156)(font "Arial" ))
+	(pt 1640 1160)
+	(pt 1704 1160)
+)
+(connector
+	(text "RGB_TAP[89..0]" (rect 1602 1096 1683 1108)(font "Arial" ))
+	(pt 1704 1112)
+	(pt 1592 1112)
+	(bus)
+)
+(junction (pt 1008 944))
+(text "MEMORY" (rect 1464 192 1517 206)(font "Arial" (font_size 8)))
+(text "PS/2 MOUSE CONTROLLER" (rect 760 992 1058 1014)(font "Arial" (font_size 14)))
+(text "PS/2 Interface" (rect 1088 736 1168 750)(font "Arial" (font_size 8)))
+(text "Mouse Buttons" (rect 1112 768 1196 782)(font "Arial" (font_size 8)))
+(text "Mouse XY Coordinates" (rect 1112 816 1242 830)(font "Arial" (font_size 8)))
+(text "7-Segments Mouse XY Coordinates" (rect 1112 864 1314 878)(font "Arial" (font_size 8)))
+(text "DIGITAL CAMERA" (rect 1416 488 1517 502)(font "Arial" (font_size 8)))
+(text "Hardware Block generated by the High-Level Synthesis Tool" (rect 1568 816 2222 838)(font "Arial" (font_size 14)(bold)))
+(text "Line Buffer" (rect 1912 376 2021 398)(font "Arial" (font_size 14)))
+(text "RED     GREEN    BLUE" (rect 2368 392 2566 410)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 584 2566 602)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 536 2566 554)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 488 2566 506)(font "Arial" (font_size 12)))
+(text "RED     GREEN    BLUE" (rect 2368 440 2566 458)(font "Arial" (font_size 12)))
+(text "149..120" (rect 2288 392 2347 408)(font "Arial" (font_size 10)(bold)))
+(text "119..90" (rect 2296 440 2346 456)(font "Arial" (font_size 10)(bold)))
+(text "89..60" (rect 2304 488 2346 504)(font "Arial" (font_size 10)(bold)))
+(text "59..30" (rect 2304 536 2346 552)(font "Arial" (font_size 10)(bold)))
+(text "29..0" (rect 2312 584 2346 600)(font "Arial" (font_size 10)(bold)))
+(text "RGB_TAP: 10 bits/colour x 3 colours x 5 rows" (rect 2296 352 2670 370)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 4" (rect 2560 584 2690 602)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 3" (rect 2560 536 2690 554)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 2" (rect 2560 488 2690 506)(font "Arial" (font_size 11)(bold)))
+(text "Current Row - 1" (rect 2560 440 2690 458)(font "Arial" (font_size 11)(bold)))
+(text "Current Row" (rect 2560 392 2666 410)(font "Arial" (font_size 11)(bold)))
+(text "29..20            19..10             9..0" (rect 2368 616 2548 630)(font "Arial" (font_size 8)))
+(line (pt 2416 616)(pt 2416 376))
+(line (pt 2480 616)(pt 2480 376))
+(line (pt 2352 616)(pt 2352 376)(color 0 0 0)(line_width 2))
+(line (pt 2544 616)(pt 2544 376)(color 0 0 0)(line_width 2))
+(line (pt 2352 376)(pt 2544 376)(color 0 0 0)(line_width 2))
+(line (pt 2352 616)(pt 2544 616)(color 0 0 0)(line_width 2))
+(line (pt 2352 568)(pt 2544 568)(color 0 0 0)(line_width 2))
+(line (pt 2352 520)(pt 2544 520)(color 0 0 0)(line_width 2))
+(line (pt 2352 472)(pt 2544 472)(color 0 0 0)(line_width 2))
+(line (pt 2352 424)(pt 2544 424)(color 0 0 0)(line_width 2))
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v
new file mode 100644
index 0000000..f7904df
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v
@@ -0,0 +1,158 @@
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author            :| Mod. Date :| Changes Made:
+//   V1.0 :| ??????????        :| ??/??/??  :| Initial Revision
+//   V2.0 :| Rui Duarte        :| 16/03/14  :| X-Y coords
+// --------------------------------------------------------------------
+ 
+
+
+
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						oVGA_X,
+						oVGA_Y,
+						oVGA_ACTIVE,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+output  		[11:0]		oVGA_X;
+output  		[11:0]		oVGA_Y;
+output         	oVGA_ACTIVE;
+
+
+
+
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+reg 				active;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+						
+assign oVGA_X = 		H_Cont;				
+assign oVGA_Y = 		V_Cont;				
+assign oVGA_ACTIVE = active;
+	
+						
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+		active		<= 0;	
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		begin
+			H_Cont	<=	H_Cont+1;
+			active <= 1'b1;
+			end
+		else
+		begin
+			H_Cont	<=	0;
+			active <= 1'b0;			
+			end
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+			oVGA_H_SYNC	<=	0;
+		else
+			oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak
new file mode 100644
index 0000000..c9c3537
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Controller.v.bak
@@ -0,0 +1,122 @@
+module	VGA_Controller(	//	Host Side
+						iRed,
+						iGreen,
+						iBlue,
+						oRequest,
+						//	VGA Side
+						oVGA_R,
+						oVGA_G,
+						oVGA_B,
+						oVGA_H_SYNC,
+						oVGA_V_SYNC,
+						oVGA_SYNC,
+						oVGA_BLANK,
+						oVGA_CLOCK,
+						//	Control Signal
+						iCLK,
+						iRST_N	);
+
+`include "VGA_Param.h"
+
+//	Host Side
+input		[9:0]	iRed;
+input		[9:0]	iGreen;
+input		[9:0]	iBlue;
+output	reg			oRequest;
+//	VGA Side
+output		[9:0]	oVGA_R;
+output		[9:0]	oVGA_G;
+output		[9:0]	oVGA_B;
+output	reg			oVGA_H_SYNC;
+output	reg			oVGA_V_SYNC;
+output				oVGA_SYNC;
+output				oVGA_BLANK;
+output				oVGA_CLOCK;
+//	Control Signal
+input				iCLK;
+input				iRST_N;
+
+//	Internal Registers and Wires
+reg		[11:0]		H_Cont;
+reg		[11:0]		V_Cont;
+
+assign	oVGA_BLANK	=	oVGA_H_SYNC & oVGA_V_SYNC;
+assign	oVGA_SYNC	=	1'b0;
+assign	oVGA_CLOCK	=	iCLK;
+
+assign	oVGA_R	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iRed	:	0;
+assign	oVGA_G	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iGreen	:	0;
+assign	oVGA_B	=	(	H_Cont>=X_START 	&& H_Cont<X_START+H_SYNC_ACT &&
+						V_Cont>=Y_START 	&& V_Cont<Y_START+V_SYNC_ACT )
+						?	iBlue	:	0;
+
+//	Pixel LUT Address Generator
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	oRequest	<=	0;
+	else
+	begin
+		if(	H_Cont>=X_START-2 && H_Cont<X_START+H_SYNC_ACT-2 &&
+			V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
+		oRequest	<=	1;
+		else
+		oRequest	<=	0;
+	end
+end
+
+//	H_Sync Generator, Ref. 25.175 MHz Clock
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		H_Cont		<=	0;
+		oVGA_H_SYNC	<=	0;
+	end
+	else
+	begin
+		//	H_Sync Counter
+		if( H_Cont < H_SYNC_TOTAL )
+		H_Cont	<=	H_Cont+1;
+		else
+		H_Cont	<=	0;
+		//	H_Sync Generator
+		if( H_Cont < H_SYNC_CYC )
+		oVGA_H_SYNC	<=	0;
+		else
+		oVGA_H_SYNC	<=	1;
+	end
+end
+
+//	V_Sync Generator, Ref. H_Sync
+always@(posedge iCLK or negedge iRST_N)
+begin
+	if(!iRST_N)
+	begin
+		V_Cont		<=	0;
+		oVGA_V_SYNC	<=	0;
+	end
+	else
+	begin
+		//	When H_Sync Re-start
+		if(H_Cont==0)
+		begin
+			//	V_Sync Counter
+			if( V_Cont < V_SYNC_TOTAL )
+			V_Cont	<=	V_Cont+1;
+			else
+			V_Cont	<=	0;
+			//	V_Sync Generator
+			if(	V_Cont < V_SYNC_CYC )
+			oVGA_V_SYNC	<=	0;
+			else
+			oVGA_V_SYNC	<=	1;
+		end
+	end
+end
+
+endmodule
\ No newline at end of file
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h
new file mode 100644
index 0000000..9d0fd32
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/VGA_Param.h
@@ -0,0 +1,16 @@
+//	Horizontal Parameter	( Pixel )
+parameter	H_SYNC_CYC	=	96;
+parameter	H_SYNC_BACK	=	48;
+parameter	H_SYNC_ACT	=	640;	
+parameter	H_SYNC_FRONT=	16;
+parameter	H_SYNC_TOTAL=	800;
+
+//	Virtical Parameter		( Line )
+parameter	V_SYNC_CYC	=	2;
+parameter	V_SYNC_BACK	=	33;
+parameter	V_SYNC_ACT	=	480;	
+parameter	V_SYNC_FRONT=	10;
+parameter	V_SYNC_TOTAL=	525;
+//	Start Offset
+parameter	X_START		=	H_SYNC_CYC+H_SYNC_BACK;
+parameter	Y_START		=	V_SYNC_CYC+V_SYNC_BACK;
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v
new file mode 100644
index 0000000..6063417
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/ps2.v
@@ -0,0 +1,271 @@
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+//
+// Major Functions:	DE2_115_PS2 Mouse Controller 
+//
+// --------------------------------------------------------------------
+//
+// Revision History :
+// --------------------------------------------------------------------
+//   Ver  :| Author                    :| Mod. Date :| Changes Made:
+//   V1.0 :| Johnny FAN,HdHuang        :| 05/16/10  :| Initial Revision
+//   V1.1 :| Rui Duarte
+// --------------------------------------------------------------------
+module ps2(
+           iSTART,   //press the button for transmitting instrucions to device;
+           iRST_n,   //FSM reset signal;
+           iCLK_50,  //clock source;
+           PS2_CLK,  //ps2_clock signal inout;
+           PS2_DAT,  //ps2_data  signal inout;
+           oLEFBUT,  //left button press display;
+           oRIGBUT,  //right button press display;
+           oMIDBUT,  //middle button press display;
+			  oX,		   // 8-bit X coordinate value
+			  oY, 	   // 8-bit Y coordinate value
+           oX_MOV1,  //lower SEG of mouse displacement display for X axis.
+           oX_MOV2,  //higher SEG of mouse displacement display for X axis.
+           oY_MOV1,  //lower SEG of mouse displacement display for Y axis.
+           oY_MOV2   //higher SEG of mouse displacement display for Y axis.
+           ); 
+           //interface;
+//=======================================================
+//  PORT declarations
+//=======================================================
+
+input iSTART;
+input iRST_n;
+input iCLK_50;
+
+inout PS2_CLK;
+inout PS2_DAT;
+
+output oLEFBUT;
+output oRIGBUT;
+output oMIDBUT;
+output [7:0] oX;
+output [7:0] oY;
+output [6:0] oX_MOV1;
+output [6:0] oX_MOV2;
+output [6:0] oY_MOV1;
+output [6:0] oY_MOV2;
+
+//instantiation
+SEG7_LUT U1(.oSEG(oX_MOV1),.iDIG(x_latch[3:0]));
+SEG7_LUT U2(.oSEG(oX_MOV2),.iDIG(x_latch[7:4]));
+SEG7_LUT U3(.oSEG(oY_MOV1),.iDIG(y_latch[3:0]));
+SEG7_LUT U4(.oSEG(oY_MOV2),.iDIG(y_latch[7:4]));
+//instruction define, users can charge the instruction byte here for other purpose according to ps/2 mouse datasheet.
+//the MSB is of parity check bit, that's when there are odd number of 1's with data bits, it's value is '0',otherwise it's '1' instead.
+
+parameter enable_byte =9'b011110100;
+
+
+//=======================================================
+//  REG/WIRE declarations
+//=======================================================
+reg [1:0] cur_state,nex_state;
+reg ce,de;
+reg [3:0] byte_cnt,delay;
+reg [5:0] ct;
+reg [7:0] x_latch,y_latch,cnt;
+reg [8:0] clk_div;
+reg [9:0] dout_reg;
+reg [32:0] shift_reg;
+reg       leflatch,riglatch,midlatch;
+reg       ps2_clk_in,ps2_clk_syn1,ps2_dat_in,ps2_dat_syn1;
+wire      clk,ps2_dat_syn0,ps2_clk_syn0,ps2_dat_out,ps2_clk_out,flag;
+
+//=======================================================
+//  PARAMETER declarations
+//=======================================================
+//state define
+parameter listen =2'b00,
+          pullclk=2'b01,
+          pulldat=2'b10,
+          trans  =2'b11;
+          
+//=======================================================
+//  Structural coding
+//=======================================================          
+//clk division, derive a 97.65625KHz clock from the 50MHz source;
+
+always@(posedge iCLK_50)
+	begin
+		clk_div <= clk_div+1;
+	end
+	
+assign clk = clk_div[8];
+//tristate output control for PS2_DAT and PS2_CLK;
+assign PS2_CLK = ce?ps2_clk_out:1'bZ;
+assign PS2_DAT = de?ps2_dat_out:1'bZ;
+assign ps2_clk_out = 1'b0;
+assign ps2_dat_out = dout_reg[0];
+assign ps2_clk_syn0 = ce?1'b1:PS2_CLK;
+assign ps2_dat_syn0 = de?1'b1:PS2_DAT;
+//
+assign oLEFBUT = leflatch;
+assign oRIGBUT = riglatch;
+assign oMIDBUT = midlatch;
+//
+assign oX = x_latch;
+assign oY = y_latch;
+//
+//multi-clock region simple synchronization
+always@(posedge clk)
+	begin
+		ps2_clk_syn1 <= ps2_clk_syn0;
+		ps2_clk_in   <= ps2_clk_syn1;
+		ps2_dat_syn1 <= ps2_dat_syn0;
+		ps2_dat_in   <= ps2_dat_syn1;
+	end
+//FSM shift
+always@(*)
+begin
+   case(cur_state)
+     listen  :begin
+              if ((!iSTART) && (cnt == 8'b11111111))
+                  nex_state = pullclk;
+              else
+                  nex_state = listen;
+                         ce = 1'b0;
+                         de = 1'b0;
+              end
+     pullclk :begin
+              if (delay == 4'b1100)
+                  nex_state = pulldat;
+              else
+                  nex_state = pullclk;
+                         ce = 1'b1;
+                         de = 1'b0;
+              end
+     pulldat :begin
+                  nex_state = trans;
+                         ce = 1'b1;
+                         de = 1'b1;
+              end
+     trans   :begin
+              if  (byte_cnt == 4'b1010)
+                  nex_state = listen;
+              else    
+                  nex_state = trans;
+                         ce = 1'b0;
+                         de = 1'b1;
+              end
+     default :    nex_state = listen;
+   endcase
+end
+//idle counter
+always@(posedge clk)
+begin
+  if ({ps2_clk_in,ps2_dat_in} == 2'b11)
+	begin
+		cnt <= cnt+1;
+    end
+  else begin
+		cnt <= 8'd0;
+       end
+end
+//periodically reset ct; ct counts the received data length;
+assign flag = (cnt == 8'hff)?1:0;
+always@(posedge ps2_clk_in,posedge flag)
+begin
+  if (flag)
+     ct <= 6'b000000;
+  else
+     ct <= ct+1;
+end
+//latch data from shift_reg;outputs is of 2's complement;
+//Please treat the cnt value here with caution, otherwise wrong data will be latched.
+always@(posedge clk,negedge iRST_n)
+begin
+   if (!iRST_n) 
+   begin
+      leflatch <= 1'b0;
+      riglatch <= 1'b0;
+      midlatch <= 1'b0;
+      x_latch  <= 8'd0;
+      y_latch  <= 8'd0;
+   end
+   else if (cnt == 8'b00011110 && (ct[5] == 1'b1 || ct[4] == 1'b1))
+   begin
+      leflatch <= shift_reg[1];
+      riglatch <= shift_reg[2];
+      midlatch <= shift_reg[3];
+      x_latch  <= x_latch+shift_reg[19 : 12];
+      y_latch  <= y_latch+shift_reg[30 : 23];
+   end
+end
+
+//pull ps2_clk low for 100us before transmit starts;
+always@(posedge clk)
+begin
+  if (cur_state == pullclk)
+     delay <= delay+1;
+  else
+     delay <= 4'b0000;
+end
+//transmit data to ps2 device;eg. 0xF4
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == trans)
+     dout_reg <= {1'b0,dout_reg[9:1]};
+  else
+     dout_reg <= {enable_byte,1'b0};
+end
+//transmit byte length counter
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == trans)
+     byte_cnt <= byte_cnt+1;
+  else
+     byte_cnt <= 4'b0000;
+end
+//receive data from ps2 device;
+always@(negedge ps2_clk_in)
+begin
+  if (cur_state == listen)
+     shift_reg <= {ps2_dat_in,shift_reg[32:1]};
+end
+//FSM movement
+always@(posedge clk,negedge iRST_n)
+begin
+  if (!iRST_n)
+     cur_state <= listen;
+  else
+     cur_state <= nex_state;
+end
+endmodule
+
+
+     
+
+
+     
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf
new file mode 100644
index 0000000..a895305
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.bsf
@@ -0,0 +1,81 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 240 168)
+	(text "sdram_pll" (rect 92 0 158 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 240 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 240 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 178 152 401 315)(font "Arial" ))
+		(text "inclk0 frequency: 50.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "5/2" (rect 77 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "5/2" (rect 77 121 165 253)(font "Arial" ))
+		(text "-117.00" (rect 98 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(line (pt 0 0)(pt 241 0))
+		(line (pt 241 0)(pt 241 169))
+		(line (pt 0 169)(pt 241 169))
+		(line (pt 0 0)(pt 0 169))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 91)(pt 48 132))
+		(line (pt 69 91)(pt 69 132)(line_width 3))
+		(line (pt 95 91)(pt 95 132)(line_width 3))
+		(line (pt 129 91)(pt 129 132)(line_width 3))
+		(line (pt 163 91)(pt 163 132))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 151))
+		(line (pt 40 151)(pt 207 151))
+		(line (pt 40 48)(pt 40 151))
+		(line (pt 239 64)(pt 207 64))
+		(line (pt 239 80)(pt 207 80))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf
new file mode 100644
index 0000000..a4a0f2e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="sdram_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip
new file mode 100644
index 0000000..7440d58
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sdram_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sdram_pll.ppf"]
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v
new file mode 100644
index 0000000..6b4189b
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v
@@ -0,0 +1,329 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-2600",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2.60000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2600"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak
new file mode 100644
index 0000000..7fd74a1
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll.v.bak
@@ -0,0 +1,326 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: sdram_pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 10.0 Build 218 06/27/2010 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2010 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sdram_pll (
+	inclk0,
+	c0,
+	c1);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+
+	wire [5:0] sub_wire0;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [1:1] sub_wire2 = sub_wire0[1:1];
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  c1 = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.clk0_divide_by = 2,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 5,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 2,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 5,
+		altpll_component.clk1_phase_shift = "-3000",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "Cyclone II",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "120.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3000"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg
new file mode 100644
index 0000000..a48389a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_wave0.jpg
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html
new file mode 100644
index 0000000..2d27f12
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/V/sdram_pll_waveforms.html
@@ -0,0 +1,13 @@
+<html>
+<head>
+<title>Sample Waveforms for sdram_pll.v </title>
+</head>
+<body>
+<h2><CENTER>Sample behavioral waveforms for design file sdram_pll.v </CENTER></h2>
+<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design sdram_pll.v. The design sdram_pll.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps. </P>
+<CENTER><img src=sdram_pll_wave0.jpg> </CENTER>
+<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
+<P><FONT size=3></P>
+<P></P>
+</body>
+</html>
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
new file mode 100644
index 0000000..6168631
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl.v
@@ -0,0 +1,429 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 21:47:19 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga_core
+// ------------------------------------------------------------------
+
+
+module mean_vga_core (
+  clk, en, arst_n, vin_rsc_mgc_in_wire_d, vout_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [89:0] vin_rsc_mgc_in_wire_d;
+  output [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] slc_regs_regs_2_1_itm;
+  reg [9:0] slc_regs_regs_2_2_itm;
+  reg [9:0] slc_regs_regs_2_itm;
+  reg [9:0] slc_regs_regs_2_4_itm;
+  reg [9:0] slc_regs_regs_2_5_itm;
+  reg [9:0] slc_regs_regs_2_3_itm;
+  reg [9:0] slc_regs_regs_2_7_itm;
+  reg [9:0] slc_regs_regs_2_8_itm;
+  reg [9:0] slc_regs_regs_2_6_itm;
+  reg [89:0] reg_regs_regs_0_sva_cse;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  wire [11:0] nl_reg_vout_rsc_mgc_out_stdreg_d_tmp;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [4:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_2;
+  reg [9:0] reg_vout_rsc_mgc_out_stdreg_d_tmp_3;
+  wire [13:0] ACC_acc_psp_sva;
+  wire [14:0] nl_ACC_acc_psp_sva;
+  wire [5:0] acc_imod_sva;
+  wire [6:0] nl_acc_imod_sva;
+  wire [11:0] acc_9_psp_sva;
+  wire [12:0] nl_acc_9_psp_sva;
+  wire [11:0] acc_14_psp_sva;
+  wire [12:0] nl_acc_14_psp_sva;
+  wire [13:0] ACC_acc_21_psp_sva;
+  wire [14:0] nl_ACC_acc_21_psp_sva;
+  wire [5:0] acc_imod_4_sva;
+  wire [6:0] nl_acc_imod_4_sva;
+  wire [3:0] acc_29_sdt;
+  wire [4:0] nl_acc_29_sdt;
+  wire [13:0] ACC_acc_20_psp_sva;
+  wire [14:0] nl_ACC_acc_20_psp_sva;
+  wire [5:0] acc_imod_2_sva;
+  wire [6:0] nl_acc_imod_2_sva;
+  wire [3:0] acc_19_sdt;
+  wire [4:0] nl_acc_19_sdt;
+  wire [3:0] acc_15_sdt;
+  wire [4:0] nl_acc_15_sdt;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign vout_rsc_mgc_out_stdreg_d = {reg_vout_rsc_mgc_out_stdreg_d_tmp , reg_vout_rsc_mgc_out_stdreg_d_tmp_1
+      , reg_vout_rsc_mgc_out_stdreg_d_tmp_2 , reg_vout_rsc_mgc_out_stdreg_d_tmp_3};
+  assign nl_ACC_acc_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_1_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_2_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[29:20]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[59:50]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[89:80])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[29:20])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[59:50])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[89:80])
+      + conv_u2u_10_11(slc_regs_regs_2_itm)));
+  assign ACC_acc_psp_sva = nl_ACC_acc_psp_sva[13:0];
+  assign nl_acc_imod_sva = conv_s2s_5_6({(({1'b1 , (acc_15_sdt[3:1])}) + 4'b1) ,
+      (acc_15_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_psp_sva[2:0]));
+  assign acc_imod_sva = nl_acc_imod_sva[5:0];
+  assign nl_acc_9_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_20_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_20_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_2_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_2_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_2_sva[5:3])) , (~ (acc_imod_2_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_2_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_20_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_2_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_20_psp_sva[13:12])
+      * 10'b111000111));
+  assign acc_9_psp_sva = nl_acc_9_psp_sva[11:0];
+  assign nl_acc_14_psp_sva = conv_s2s_10_12(conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_21_psp_sva[11:9])
+      * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_21_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+      (acc_imod_4_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_4_sva[2:0])
+      , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_4_sva[5:3])) , (~ (acc_imod_4_sva[5]))})))))})
+      + conv_u2u_2_4(acc_imod_4_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_21_psp_sva[8:6])))
+      + ({4'b1001 , (acc_imod_4_sva[5])})))) + conv_u2s_10_13(conv_u2s_20_11(conv_u2u_2_10(ACC_acc_21_psp_sva[13:12])
+      * 10'b111000111));
+  assign acc_14_psp_sva = nl_acc_14_psp_sva[11:0];
+  assign nl_ACC_acc_21_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_7_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_8_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[19:10]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[49:40]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[79:70])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[19:10])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[49:40])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[79:70])
+      + conv_u2u_10_11(slc_regs_regs_2_6_itm)));
+  assign ACC_acc_21_psp_sva = nl_ACC_acc_21_psp_sva[13:0];
+  assign nl_acc_imod_4_sva = conv_s2s_5_6({(({1'b1 , (acc_29_sdt[3:1])}) + 4'b1)
+      , (acc_29_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_21_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_21_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_21_psp_sva[2:0]));
+  assign acc_imod_4_sva = nl_acc_imod_4_sva[5:0];
+  assign nl_acc_29_sdt = conv_u2u_3_4(~ (ACC_acc_21_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_21_psp_sva[8:6]);
+  assign acc_29_sdt = nl_acc_29_sdt[3:0];
+  assign nl_ACC_acc_20_psp_sva = conv_u2u_13_14(conv_u2u_12_13(conv_u2u_11_12(conv_u2u_10_11(slc_regs_regs_2_4_itm)
+      + conv_u2u_10_11(slc_regs_regs_2_5_itm)) + conv_u2u_10_12(vin_rsc_mgc_in_wire_d[9:0]))
+      + conv_u2u_11_13(conv_u2u_10_11(vin_rsc_mgc_in_wire_d[39:30]) + conv_u2u_10_11(vin_rsc_mgc_in_wire_d[69:60])))
+      + conv_u2u_12_14(conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[9:0])
+      + conv_u2u_10_11(reg_regs_regs_0_sva_cse[39:30])) + conv_u2u_11_12(conv_u2u_10_11(reg_regs_regs_0_sva_cse[69:60])
+      + conv_u2u_10_11(slc_regs_regs_2_3_itm)));
+  assign ACC_acc_20_psp_sva = nl_ACC_acc_20_psp_sva[13:0];
+  assign nl_acc_imod_2_sva = conv_s2s_5_6({(({1'b1 , (acc_19_sdt[3:1])}) + 4'b1)
+      , (acc_19_sdt[0])}) + conv_u2s_5_6(conv_u2u_4_5(conv_u2u_3_4(~ (ACC_acc_20_psp_sva[11:9]))
+      + conv_u2u_2_4(ACC_acc_20_psp_sva[13:12])) + conv_u2u_3_5(ACC_acc_20_psp_sva[2:0]));
+  assign acc_imod_2_sva = nl_acc_imod_2_sva[5:0];
+  assign nl_acc_19_sdt = conv_u2u_3_4(~ (ACC_acc_20_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_20_psp_sva[8:6]);
+  assign acc_19_sdt = nl_acc_19_sdt[3:0];
+  assign nl_acc_15_sdt = conv_u2u_3_4(~ (ACC_acc_psp_sva[5:3])) + conv_u2u_3_4(ACC_acc_psp_sva[8:6]);
+  assign acc_15_sdt = nl_acc_15_sdt[3:0];
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      slc_regs_regs_2_7_itm <= 10'b0;
+      slc_regs_regs_2_8_itm <= 10'b0;
+      reg_regs_regs_0_sva_cse <= 90'b0;
+      slc_regs_regs_2_6_itm <= 10'b0;
+      slc_regs_regs_2_4_itm <= 10'b0;
+      slc_regs_regs_2_5_itm <= 10'b0;
+      slc_regs_regs_2_3_itm <= 10'b0;
+      slc_regs_regs_2_1_itm <= 10'b0;
+      slc_regs_regs_2_2_itm <= 10'b0;
+      slc_regs_regs_2_itm <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= 5'b0;
+      reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        slc_regs_regs_2_7_itm <= reg_regs_regs_0_sva_cse[49:40];
+        slc_regs_regs_2_8_itm <= reg_regs_regs_0_sva_cse[79:70];
+        reg_regs_regs_0_sva_cse <= vin_rsc_mgc_in_wire_d;
+        slc_regs_regs_2_6_itm <= reg_regs_regs_0_sva_cse[19:10];
+        slc_regs_regs_2_4_itm <= reg_regs_regs_0_sva_cse[39:30];
+        slc_regs_regs_2_5_itm <= reg_regs_regs_0_sva_cse[69:60];
+        slc_regs_regs_2_3_itm <= reg_regs_regs_0_sva_cse[9:0];
+        slc_regs_regs_2_1_itm <= reg_regs_regs_0_sva_cse[59:50];
+        slc_regs_regs_2_2_itm <= reg_regs_regs_0_sva_cse[89:80];
+        slc_regs_regs_2_itm <= reg_regs_regs_0_sva_cse[29:20];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp <= ((conv_u2s_9_11(conv_u2s_18_10(conv_u2u_3_9(ACC_acc_psp_sva[11:9])
+            * 9'b111001)) + conv_s2s_8_10(conv_u2s_6_8(ACC_acc_psp_sva[8:3]) + conv_s2s_5_8((conv_u2u_4_5(conv_u2u_3_4({(~
+            (acc_imod_sva[5])) , 1'b1 , (~ (readslicef_5_1_4((({1'b1 , (acc_imod_sva[2:0])
+            , 1'b1}) + conv_u2s_4_5({(~ (acc_imod_sva[5:3])) , (~ (acc_imod_sva[5]))})))))})
+            + conv_u2u_2_4(acc_imod_sva[4:3])) + conv_u2u_3_5(~ (ACC_acc_psp_sva[8:6])))
+            + ({4'b1001 , (acc_imod_sva[5])})))) + conv_u2u_20_10(conv_u2u_2_10(ACC_acc_psp_sva[13:12])
+            * 10'b111000111)) | ({5'b0 , (signext_5_2(acc_9_psp_sva[11:10]))});
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_1 <= acc_9_psp_sva[9:5];
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_2 <= (acc_9_psp_sva[4:0]) | (signext_5_2(acc_14_psp_sva[11:10]));
+        reg_vout_rsc_mgc_out_stdreg_d_tmp_3 <= acc_14_psp_sva[9:0];
+      end
+    end
+  end
+
+  function [0:0] readslicef_5_1_4;
+    input [4:0] vector;
+    reg [4:0] tmp;
+  begin
+    tmp = vector >> 4;
+    readslicef_5_1_4 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [4:0] signext_5_2;
+    input [1:0] vector;
+  begin
+    signext_5_2= {{3{vector[1]}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_13_14 ;
+    input [12:0]  vector ;
+  begin
+    conv_u2u_13_14 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_12_13 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_13 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [10:0] conv_u2u_10_11 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_11 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_10_12 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2u_10_12 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [12:0] conv_u2u_11_13 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_13 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [13:0] conv_u2u_12_14 ;
+    input [11:0]  vector ;
+  begin
+    conv_u2u_12_14 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_s2s_5_6 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_6 = {vector[4], vector};
+  end
+  endfunction
+
+
+  function signed [5:0] conv_u2s_5_6 ;
+    input [4:0]  vector ;
+  begin
+    conv_u2s_5_6 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2u_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_3_4 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_4 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [3:0] conv_u2u_2_4 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_4 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [4:0] conv_u2u_3_5 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_5 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [11:0] conv_s2s_10_12 ;
+    input signed [9:0]  vector ;
+  begin
+    conv_s2s_10_12 = {{2{vector[9]}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_9_11 ;
+    input [8:0]  vector ;
+  begin
+    conv_u2s_9_11 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_u2s_18_10 ;
+    input [17:0]  vector ;
+  begin
+    conv_u2s_18_10 = vector[9:0];
+  end
+  endfunction
+
+
+  function  [8:0] conv_u2u_3_9 ;
+    input [2:0]  vector ;
+  begin
+    conv_u2u_3_9 = {{6{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [9:0] conv_s2s_8_10 ;
+    input signed [7:0]  vector ;
+  begin
+    conv_s2s_8_10 = {{2{vector[7]}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_u2s_6_8 ;
+    input [5:0]  vector ;
+  begin
+    conv_u2s_6_8 = {{2{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [7:0] conv_s2s_5_8 ;
+    input signed [4:0]  vector ;
+  begin
+    conv_s2s_5_8 = {{3{vector[4]}}, vector};
+  end
+  endfunction
+
+
+  function signed [4:0] conv_u2s_4_5 ;
+    input [3:0]  vector ;
+  begin
+    conv_u2s_4_5 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function signed [12:0] conv_u2s_10_13 ;
+    input [9:0]  vector ;
+  begin
+    conv_u2s_10_13 = {{3{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function signed [10:0] conv_u2s_20_11 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2s_20_11 = vector[10:0];
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_2_10 ;
+    input [1:0]  vector ;
+  begin
+    conv_u2u_2_10 = {{8{1'b0}}, vector};
+  end
+  endfunction
+
+
+  function  [9:0] conv_u2u_20_10 ;
+    input [19:0]  vector ;
+  begin
+    conv_u2u_20_10 = vector[9:0];
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    mean_vga
+//  Generated from file(s):
+//    5) $PROJECT_HOME/vga_mouse_filter/blur.c
+// ------------------------------------------------------------------
+
+
+module mean_vga (
+  vin_rsc_z, vout_rsc_z, clk, en, arst_n
+);
+  input [89:0] vin_rsc_z;
+  output [29:0] vout_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [89:0] vin_rsc_mgc_in_wire_d;
+  wire [29:0] vout_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(90)) vin_rsc_mgc_in_wire (
+      .d(vin_rsc_mgc_in_wire_d),
+      .z(vin_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(2),
+  .width(30)) vout_rsc_mgc_out_stdreg (
+      .d(vout_rsc_mgc_out_stdreg_d),
+      .z(vout_rsc_z)
+    );
+  mean_vga_core mean_vga_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
+      .vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/blur3x3/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
new file mode 100644
index 0000000..dda909a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl.v
@@ -0,0 +1,171 @@
+// ----------------------------------------------------------------------
+//  HLS HDL:        Verilog Netlister
+//  HLS Version:    2011a.126 Production Release
+//  HLS Date:       Wed Aug  8 00:52:07 PDT 2012
+// 
+//  Generated by:   rad09@EE-RAD09-02
+//  Generated date: Wed Mar 06 11:57:58 2013
+// ----------------------------------------------------------------------
+
+// 
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square_core
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square_core (
+  clk, en, arst_n, vga_xy_rsc_mgc_in_wire_d, mouse_xy_rsc_mgc_in_wire_d, cursor_size_rsc_mgc_in_wire_d,
+      video_in_rsc_mgc_in_wire_d, video_out_rsc_mgc_out_stdreg_d
+);
+  input clk;
+  input en;
+  input arst_n;
+  input [19:0] vga_xy_rsc_mgc_in_wire_d;
+  input [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  input [7:0] cursor_size_rsc_mgc_in_wire_d;
+  input [29:0] video_in_rsc_mgc_in_wire_d;
+  output [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_1;
+  reg [9:0] reg_video_out_rsc_mgc_out_stdreg_d_tmp_2;
+  wire or_itm;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  assign video_out_rsc_mgc_out_stdreg_d = {reg_video_out_rsc_mgc_out_stdreg_d_tmp
+      , reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 , reg_video_out_rsc_mgc_out_stdreg_d_tmp_2};
+  assign or_itm = (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[19:10])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[19:10])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(mouse_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (vga_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d})))) | (readslicef_12_1_11((conv_u2u_11_12(readslicef_12_11_1((conv_u2u_11_12({(vga_xy_rsc_mgc_in_wire_d[9:0])
+      , 1'b1}) + conv_u2u_11_12({(~ (mouse_xy_rsc_mgc_in_wire_d[9:0])) , 1'b1}))))
+      + conv_s2u_11_12({3'b100 , cursor_size_rsc_mgc_in_wire_d}))));
+  always @(posedge clk or negedge arst_n) begin
+    if ( ~ arst_n ) begin
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= 10'b0;
+      reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= 10'b0;
+    end
+    else begin
+      if ( en ) begin
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp <= (video_in_rsc_mgc_in_wire_d[29:20])
+            & ({{9{or_itm}}, or_itm});
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_1 <= video_in_rsc_mgc_in_wire_d[19:10];
+        reg_video_out_rsc_mgc_out_stdreg_d_tmp_2 <= (video_in_rsc_mgc_in_wire_d[9:0])
+            & ({{9{or_itm}}, or_itm});
+      end
+    end
+  end
+
+  function [0:0] readslicef_12_1_11;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 11;
+    readslicef_12_1_11 = tmp[0:0];
+  end
+  endfunction
+
+
+  function [10:0] readslicef_12_11_1;
+    input [11:0] vector;
+    reg [11:0] tmp;
+  begin
+    tmp = vector >> 1;
+    readslicef_12_11_1 = tmp[10:0];
+  end
+  endfunction
+
+
+  function  [11:0] conv_u2u_11_12 ;
+    input [10:0]  vector ;
+  begin
+    conv_u2u_11_12 = {1'b0, vector};
+  end
+  endfunction
+
+
+  function  [11:0] conv_s2u_11_12 ;
+    input signed [10:0]  vector ;
+  begin
+    conv_s2u_11_12 = {vector[10], vector};
+  end
+  endfunction
+
+endmodule
+
+// ------------------------------------------------------------------
+//  Design Unit:    vga_mouse_square
+//  Generated from file(s):
+//   12) $PROJECT_HOME/vga_mouse_square__old/vga_mouse_square_working_demo_sw.c
+// ------------------------------------------------------------------
+
+
+module vga_mouse_square (
+  vga_xy_rsc_z, mouse_xy_rsc_z, cursor_size_rsc_z, video_in_rsc_z, video_out_rsc_z,
+      clk, en, arst_n
+);
+  input [19:0] vga_xy_rsc_z;
+  input [19:0] mouse_xy_rsc_z;
+  input [7:0] cursor_size_rsc_z;
+  input [29:0] video_in_rsc_z;
+  output [29:0] video_out_rsc_z;
+  input clk;
+  input en;
+  input arst_n;
+
+
+  // Interconnect Declarations
+  wire [19:0] vga_xy_rsc_mgc_in_wire_d;
+  wire [19:0] mouse_xy_rsc_mgc_in_wire_d;
+  wire [7:0] cursor_size_rsc_mgc_in_wire_d;
+  wire [29:0] video_in_rsc_mgc_in_wire_d;
+  wire [29:0] video_out_rsc_mgc_out_stdreg_d;
+
+
+  // Interconnect Declarations for Component Instantiations 
+  mgc_in_wire #(.rscid(1),
+  .width(20)) vga_xy_rsc_mgc_in_wire (
+      .d(vga_xy_rsc_mgc_in_wire_d),
+      .z(vga_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(2),
+  .width(20)) mouse_xy_rsc_mgc_in_wire (
+      .d(mouse_xy_rsc_mgc_in_wire_d),
+      .z(mouse_xy_rsc_z)
+    );
+  mgc_in_wire #(.rscid(3),
+  .width(8)) cursor_size_rsc_mgc_in_wire (
+      .d(cursor_size_rsc_mgc_in_wire_d),
+      .z(cursor_size_rsc_z)
+    );
+  mgc_in_wire #(.rscid(4),
+  .width(30)) video_in_rsc_mgc_in_wire (
+      .d(video_in_rsc_mgc_in_wire_d),
+      .z(video_in_rsc_z)
+    );
+  mgc_out_stdreg #(.rscid(5),
+  .width(30)) video_out_rsc_mgc_out_stdreg (
+      .d(video_out_rsc_mgc_out_stdreg_d),
+      .z(video_out_rsc_z)
+    );
+  vga_mouse_square_core vga_mouse_square_core_inst (
+      .clk(clk),
+      .en(en),
+      .arst_n(arst_n),
+      .vga_xy_rsc_mgc_in_wire_d(vga_xy_rsc_mgc_in_wire_d),
+      .mouse_xy_rsc_mgc_in_wire_d(mouse_xy_rsc_mgc_in_wire_d),
+      .cursor_size_rsc_mgc_in_wire_d(cursor_size_rsc_mgc_in_wire_d),
+      .video_in_rsc_mgc_in_wire_d(video_in_rsc_mgc_in_wire_d),
+      .video_out_rsc_mgc_out_stdreg_d(video_out_rsc_mgc_out_stdreg_d)
+    );
+endmodule
+
+
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v
new file mode 100644
index 0000000..2f584b7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport.v
@@ -0,0 +1,542 @@
+//------------------------------------------------------------------
+//                M G C _ I O P O R T _ C O M P S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//                       M O D U L E S
+//------------------------------------------------------------------
+
+//------------------------------------------------------------------
+//-- INPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_in_wire (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output [width-1:0] d;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+
+  assign d = z;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output [width-1:0] d;
+  output             lz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_in_wire_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+  parameter integer sz_width = 8;
+
+  input              ld;
+  output             vd;
+  output [width-1:0] d;
+  output             lz;
+  input              vz;
+  input  [width-1:0] z;
+  output [sz_width-1:0] size;
+  input              req_size;
+  input  [sz_width-1:0] sizez;
+  output             sizelz;
+
+
+  wire               vd;
+  wire   [width-1:0] d;
+  wire               lz;
+  wire   [sz_width-1:0] size;
+  wire               sizelz;
+
+  assign d = z;
+  assign lz = ld;
+  assign vd = vz;
+  assign size = sizez;
+  assign sizelz = req_size;
+
+endmodule
+
+
+//------------------------------------------------------------------
+//-- OUTPUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_out_stdreg (d, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input    [width-1:0] d;
+  output   [width-1:0] z;
+
+  wire     [width-1:0] z;
+
+  assign z = d;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_en (ld, d, lz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  input  [width-1:0] d;
+  output             lz;
+  output [width-1:0] z;
+
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  input              ld;
+  output             vd;
+  input  [width-1:0] d;
+  output             lz;
+  input              vz;
+  output [width-1:0] z;
+
+  wire               vd;
+  wire               lz;
+  wire   [width-1:0] z;
+
+  assign z = d;
+  assign lz = ld;
+  assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_prereg_en (ld, d, lz, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    wire               lz;
+    wire   [width-1:0] z;
+
+    assign z = d;
+    assign lz = ld;
+
+endmodule
+
+//------------------------------------------------------------------
+//-- INOUT ENTITIES
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output [width-1:0] din;
+    input              ldout;
+    input  [width-1:0] dout;
+    output             lzin;
+    output             lzout;
+    inout  [width-1:0] z;
+
+    wire   [width-1:0] din;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign z = ldout ? dout : {width{1'bz}};
+
+endmodule
+
+//------------------------------------------------------------------
+module hid_tribuf( I_SIG, ENABLE, O_SIG);
+  parameter integer width = 8;
+
+  input [width-1:0] I_SIG;
+  input ENABLE;
+  inout [width-1:0] O_SIG;
+
+  assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}};
+
+endmodule
+//------------------------------------------------------------------
+
+module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid = 1;
+    parameter integer width = 8;
+
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+    wire   ldout_and_vzout;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = ldout;
+    assign vdout = vzout ;
+    assign ldout_and_vzout = ldout && vzout ;
+
+    hid_tribuf #(width) tb( .I_SIG(dout),
+                            .ENABLE(ldout_and_vzout),
+                            .O_SIG(z) );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    hid_tribuf #(width) tb( .I_SIG(z_buf),
+                            .ENABLE((lzout_buf && (!ldin) && vzout) ),
+                            .O_SIG(z)  );
+
+    mgc_out_buf_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFF
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+
+endmodule
+
+module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer ph_log2 = 3;     // log2(fifo_sz)
+    parameter integer pwropt  = 0;     // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output             lzin;
+    input              vzin;
+    output             lzout;
+    input              vzout;
+    inout  [width-1:0] z;
+
+    wire               lzout_buf;
+    wire               vzout_buf;
+    wire   [width-1:0] z_buf;
+    wire               comb;
+    wire               vdin;
+    wire   [width-1:0] din;
+    wire               vdout;
+    wire               lzin;
+    wire               lzout;
+    wire   [width-1:0] z;
+
+    assign lzin = ldin;
+    assign vdin = vzin;
+    assign din = ldin ? z : {width{1'bz}};
+    assign lzout = lzout_buf & ~ldin;
+    assign vzout_buf = vzout & ~ldin;
+    assign comb = (lzout_buf && (!ldin) && vzout);
+
+    hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z)  );
+
+    mgc_out_fifo_wait
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+    )
+    FIFO
+    (
+        .clk   (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (lzout_buf),
+        .vz      (vzout_buf),
+        .z       (z_buf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+//-- I/O SYNCHRONIZATION ENTITIES
+//------------------------------------------------------------------
+
+module mgc_io_sync (ld, lz);
+
+    input  ld;
+    output lz;
+
+    assign lz = ld;
+
+endmodule
+
+module mgc_bsync_rdy (rd, rz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 0;
+
+    input  rd;
+    output rz;
+
+    wire   rz;
+
+    assign rz = rd;
+
+endmodule
+
+module mgc_bsync_vld (vd, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 0;
+    parameter valid = 1;
+
+    output vd;
+    input  vz;
+
+    wire   vd;
+
+    assign vd = vz;
+
+endmodule
+
+module mgc_bsync_rv (rd, vd, rz, vz);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter ready = 1;
+    parameter valid = 1;
+
+    input  rd;
+    output vd;
+    output rz;
+    input  vz;
+
+    wire   vd;
+    wire   rz;
+
+    assign rz = rd;
+    assign vd = vz;
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_sync (ldin, vdin, ldout, vdout);
+
+  input  ldin;
+  output vdin;
+  input  ldout;
+  output vdout;
+
+  wire   vdin;
+  wire   vdout;
+
+  assign vdin = ldout;
+  assign vdout = ldin;
+
+endmodule
+
+///////////////////////////////////////////////////////////////////////////////
+// dummy function used to preserve funccalls for modulario
+// it looks like a memory read to the caller
+///////////////////////////////////////////////////////////////////////////////
+module funccall_inout (d, ad, bd, z, az, bz);
+
+  parameter integer ram_id = 1;
+  parameter integer width = 8;
+  parameter integer addr_width = 8;
+
+  output [width-1:0]       d;
+  input  [addr_width-1:0]  ad;
+  input                    bd;
+  input  [width-1:0]       z;
+  output [addr_width-1:0]  az;
+  output                   bz;
+
+  wire   [width-1:0]       d;
+  wire   [addr_width-1:0]  az;
+  wire                     bz;
+
+  assign d  = z;
+  assign az = ad;
+  assign bz = bd;
+
+endmodule
+
+
+///////////////////////////////////////////////////////////////////////////////
+// inlinable modular io not otherwise found in mgc_ioport
+///////////////////////////////////////////////////////////////////////////////
+
+module modulario_en_in (vd, d, vz, z);
+
+  parameter integer rscid = 1;
+  parameter integer width = 8;
+
+  output             vd;
+  output [width-1:0] d;
+  input              vz;
+  input  [width-1:0] z;
+
+  wire   [width-1:0] d;
+  wire               vd;
+
+  assign d = z;
+  assign vd = vz;
+
+endmodule
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v
new file mode 100644
index 0000000..6642af7
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/catapult_ip/mouse/rtl_mgc_ioport_v2001.v
@@ -0,0 +1,700 @@
+//------------------------------------------------------------------
+
+module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(posedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(posedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z);
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+    reg                lz;
+    reg    [width-1:0] z;
+
+    generate
+    if (ph_arst == 1'b0)
+    begin: NEG_ARST
+        always @(negedge clk or negedge arst)
+        if (arst == 1'b0)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    else
+    begin: POS_ARST
+        always @(negedge clk or posedge arst)
+        if (arst == 1'b1)
+        begin: B1
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (srst == ph_srst)
+        begin: B2
+            lz <= 1'b0;
+            z  <= {width{1'b0}};
+        end
+        else if (en == ph_en)
+        begin: B3
+            lz <= ld;
+            z  <= (ld) ? d : z;
+        end
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    input  [width-1:0] d;
+    output             lz;
+    output [width-1:0] z;
+
+
+    generate
+    if (ph_clk == 1'b0)
+    begin: NEG_EDGE
+
+        mgc_out_reg_neg
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_neg_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    else
+    begin: POS_EDGE
+
+        mgc_out_reg_pos
+        #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        mgc_out_reg_pos_inst
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (ld),
+            .d       (d),
+            .lz      (lz),
+            .z       (z)
+        );
+
+    end
+    endgenerate
+
+endmodule
+
+
+
+
+//------------------------------------------------------------------
+
+module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported
+
+    parameter integer rscid   = 1;
+    parameter integer width   = 8;
+    parameter         ph_clk  =  1'b1;
+    parameter         ph_en   =  1'b1;
+    parameter         ph_arst =  1'b1;
+    parameter         ph_srst =  1'b1;
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ld;
+    output             vd;
+    input  [width-1:0] d;
+    output             lz;
+    input              vz;
+    output [width-1:0] z;
+
+    wire               filled;
+    wire               filled_next;
+    wire   [width-1:0] abuf;
+    wire               lbuf;
+
+
+    assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz));
+
+    assign lbuf = ld & ~(filled ^ vz);
+
+    assign vd = vz | ~filled;
+
+    assign lz = ld | filled;
+
+    assign z = (filled) ? abuf : d;
+
+    wire dummy;
+    wire dummy_bufreg_lz;
+
+    // Output registers:
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (1'b1),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    STATREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (filled_next),
+        .d       (1'b0),       // input d is unused
+        .lz      (filled),
+        .z       (dummy)            // output z is unused
+    );
+
+    mgc_out_reg
+    #(
+        .rscid   (rscid),
+        .width   (width),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst)
+    )
+    BUFREG
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (lbuf),
+        .d       (d),
+        .lz      (dummy_bufreg_lz),
+        .z       (abuf)
+    );
+
+endmodule
+
+//------------------------------------------------------------------
+
+module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz,  z);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  = 1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1; // clock enable polarity
+    parameter         ph_arst = 1'b1; // async reset polarity
+    parameter         ph_srst = 1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+
+    wire    [31:0]      size;
+
+
+      // Output registers:
+ mgc_out_fifo_wait_core#(
+        .rscid   (rscid),
+        .width   (width),
+        .sz_width (32),
+        .fifo_sz (fifo_sz),
+        .ph_clk  (ph_clk),
+        .ph_en   (ph_en),
+        .ph_arst (ph_arst),
+        .ph_srst (ph_srst),
+        .ph_log2 (ph_log2),
+        .pwropt  (pwropt)
+        ) CORE (
+        .clk (clk),
+        .en (en),
+        .arst (arst),
+        .srst (srst),
+        .ld (ld),
+        .vd (vd),
+        .d (d),
+        .lz (lz),
+        .vz (vz),
+        .z (z),
+        .size (size)
+        );
+
+endmodule
+
+
+
+module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz,  z, size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // size of port for elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter         ph_clk  =  1'b1; // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   =  1'b1; // clock enable polarity
+    parameter         ph_arst =  1'b1; // async reset polarity
+    parameter         ph_srst =  1'b1; // sync reset polarity
+    parameter integer ph_log2 = 3; // log2(fifo_sz)
+    parameter integer pwropt  = 0; // pwropt
+
+   localparam integer  fifo_b = width * fifo_sz;
+
+    input                 clk;
+    input                 en;
+    input                 arst;
+    input                 srst;
+    input                 ld;    // load data
+    output                vd;    // fifo full active low
+    input     [width-1:0] d;
+    output                lz;    // fifo ready to send
+    input                 vz;    // dest ready for data
+    output    [width-1:0] z;
+    output    [sz_width-1:0]      size;
+
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre;
+    wire     [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat;
+    reg      [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre;
+    wire     [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff;
+    reg      [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l;
+    reg      [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s;
+
+    reg       [width-1:0] buff_nxt;
+
+    reg                   stat_nxt;
+    reg                   stat_before;
+    reg                   stat_after;
+    reg                   en_l_var;
+
+    integer               i;
+    genvar                eni;
+
+    wire [32:0]           size_t;
+    reg [31:0]            count;
+    reg [31:0]            count_t;
+    reg [32:0]            n_elem;
+// pragma translate_off
+    reg [31:0]            peak;
+// pragma translate_on
+
+    wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz;
+    wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz;
+
+    generate
+    if ( fifo_sz > 0 )
+    begin: FIFO_REG
+      assign vd = vz | ~stat[0];
+      assign lz = ld | stat[fifo_sz-1];
+      assign size_t = (count - (vz && stat[fifo_sz-1])) + ld;
+      assign size = size_t[sz_width-1:0];
+      assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d;
+
+      always @(*)
+      begin: FIFOPROC
+        n_elem = 33'b0;
+        for (i = fifo_sz-1; i >= 0; i = i - 1)
+        begin
+          if (i != 0)
+            stat_before = stat[i-1];
+          else
+            stat_before = 1'b0;
+
+          if (i != (fifo_sz-1))
+            stat_after = stat[i+1];
+          else
+            stat_after = 1'b1;
+
+          stat_nxt = stat_after &
+                    (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz)));
+
+          stat_pre[i] = stat_nxt;
+          en_l_var = 1'b1;
+          if (!stat_nxt)
+            begin
+              buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+          else if (vz && stat_before)
+            buff_nxt[0+:width] = buff[width*(i-1)+:width];
+          else if (ld && !((vz && stat_before) || ((!vz) && stat[i])))
+            buff_nxt = d;
+          else
+            begin
+              if (pwropt == 0)
+                buff_nxt[0+:width] = buff[width*i+:width];
+              else
+                buff_nxt = {width{1'b0}};
+              en_l_var = 1'b0;
+            end
+
+          if (ph_en != 0)
+            en_l[i] = en & en_l_var;
+          else
+            en_l[i] = en | ~en_l_var;
+
+          buff_pre[width*i+:width] = buff_nxt[0+:width];
+
+          if ((stat_after == 1'b1) && (stat[i] == 1'b0))
+            n_elem = ($unsigned(fifo_sz) - 1) - i;
+        end
+
+        if (ph_en != 0)
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1;
+        else
+          en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0;
+
+        for (i = fifo_sz-1; i >= 7; i = i - 1)
+        begin
+          if ((i%'d2) == 0)
+          begin
+            if (ph_en != 0)
+              en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]);
+            else
+              en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]);
+          end
+        end
+
+        if ( stat[fifo_sz-1] == 1'b0 )
+          count_t = 32'b0;
+        else if ( stat[0] == 1'b1 )
+          count_t = { {(32-ph_log2){1'b0}}, fifo_sz};
+        else
+          count_t = n_elem[31:0];
+        count = count_t;
+// pragma translate_off
+        if ( peak < count )
+          peak = count;
+// pragma translate_on
+      end
+
+      if (pwropt == 0)
+      begin: NOCGFIFO
+        // Output registers:
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        STATREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+        );
+        mgc_out_reg
+        #(
+            .rscid   (rscid),
+            .width   (fifo_b),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+        )
+        BUFREG
+        (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre),
+            .lz      (dummy_bufreg_lz[0]),
+            .z       (buff)
+        );
+      end
+      else
+      begin: CGFIFO
+        // Output registers:
+        if ( pwropt > 1)
+        begin: CGSTATFIFO2
+          for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+          begin: pwroptGEN1
+            mgc_out_reg
+            #(
+              .rscid   (rscid),
+              .width   (1),
+              .ph_clk  (ph_clk),
+              .ph_en   (ph_en),
+              .ph_arst (ph_arst),
+              .ph_srst (ph_srst)
+            )
+            STATREG
+            (
+              .clk     (clk),
+              .en      (en_l_s[eni/8]),
+              .arst    (arst),
+              .srst    (srst),
+              .ld      (1'b1),
+              .d       (stat_pre[eni]),
+              .lz      (dummy_statreg_lz[eni]),
+              .z       (stat[eni])
+            );
+          end
+        end
+        else
+        begin: CGSTATFIFO
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (fifo_sz),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          STATREG
+          (
+            .clk     (clk),
+            .en      (en),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (stat_pre),
+            .lz      (dummy_statreg_lz[0]),
+            .z       (stat)
+          );
+        end
+        for (eni = fifo_sz-1; eni >= 0; eni = eni - 1)
+        begin: pwroptGEN2
+          mgc_out_reg
+          #(
+            .rscid   (rscid),
+            .width   (width),
+            .ph_clk  (ph_clk),
+            .ph_en   (ph_en),
+            .ph_arst (ph_arst),
+            .ph_srst (ph_srst)
+          )
+          BUFREG
+          (
+            .clk     (clk),
+            .en      (en_l[eni]),
+            .arst    (arst),
+            .srst    (srst),
+            .ld      (1'b1),
+            .d       (buff_pre[width*eni+:width]),
+            .lz      (dummy_bufreg_lz[eni]),
+            .z       (buff[width*eni+:width])
+          );
+        end
+      end
+    end
+    else
+    begin: FEED_THRU
+      assign vd = vz;
+      assign lz = ld;
+      assign z = d;
+      assign size = ld && !vz;
+    end
+    endgenerate
+
+endmodule
+
+//------------------------------------------------------------------
+//-- PIPE ENTITIES
+//------------------------------------------------------------------
+/*
+ *
+ *             _______________________________________________
+ * WRITER    |                                               |          READER
+ *           |           MGC_PIPE                            |
+ *           |           __________________________          |
+ *        --<| vdout  --<| vd ---------------  vz<|-----ldin<|---
+ *           |           |      FIFO              |          |
+ *        ---|>ldout  ---|>ld ---------------- lz |> ---vdin |>--
+ *        ---|>dout -----|>d  ---------------- dz |> ----din |>--
+ *           |           |________________________|          |
+ *           |_______________________________________________|
+ */
+// two clock pipe
+module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);
+
+    parameter integer rscid   = 0; // resource ID
+    parameter integer width   = 8; // fifo width
+    parameter integer sz_width = 8; // width of size of elements in fifo
+    parameter integer fifo_sz = 8; // fifo depth
+    parameter integer log2_sz = 3; // log2(fifo_sz)
+    parameter         ph_clk  = 1'b1;  // clock polarity 1=rising edge, 0=falling edge
+    parameter         ph_en   = 1'b1;  // clock enable polarity
+    parameter         ph_arst = 1'b1;  // async reset polarity
+    parameter         ph_srst = 1'b1;  // sync reset polarity
+    parameter integer pwropt  = 0; // pwropt
+
+    input              clk;
+    input              en;
+    input              arst;
+    input              srst;
+    input              ldin;
+    output             vdin;
+    output [width-1:0] din;
+    input              ldout;
+    output             vdout;
+    input  [width-1:0] dout;
+    output [sz_width-1:0]      size;
+    input              req_size;
+
+
+    mgc_out_fifo_wait_core
+    #(
+        .rscid    (rscid),
+        .width    (width),
+        .sz_width (sz_width),
+        .fifo_sz  (fifo_sz),
+        .ph_clk   (ph_clk),
+        .ph_en    (ph_en),
+        .ph_arst  (ph_arst),
+        .ph_srst  (ph_srst),
+        .ph_log2  (log2_sz),
+        .pwropt   (pwropt)
+    )
+    FIFO
+    (
+        .clk     (clk),
+        .en      (en),
+        .arst    (arst),
+        .srst    (srst),
+        .ld      (ldout),
+        .vd      (vdout),
+        .d       (dout),
+        .lz      (vdin),
+        .vz      (ldin),
+        .z       (din),
+        .size    (size)
+    );
+
+endmodule
+
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt
new file mode 100644
index 0000000..a13a74e
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/greybox_tmp/cbx_args.txt
@@ -0,0 +1,11 @@
+LPM_SIZE=4
+LPM_TYPE=LPM_MUX
+LPM_WIDTH=30
+LPM_WIDTHS=2
+DEVICE_FAMILY="Cyclone III"
+data
+data
+data
+data
+sel
+result
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf
new file mode 100644
index 0000000..ad72508
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 256 128)
+	(text "mean_vga" (rect 5 0 48 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vin_rsc_z[89..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "vin_rsc_z[89..0]" (rect 21 27 85 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 43 31 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 59 30 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 75 46 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 240 32)
+		(output)
+		(text "vout_rsc_z[29..0]" (rect 0 0 70 12)(font "Arial" ))
+		(text "vout_rsc_z[29..0]" (rect 149 27 219 39)(font "Arial" ))
+		(line (pt 240 32)(pt 224 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 224 96)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf
new file mode 100644
index 0000000..782bad9
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/mean_vga_core.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 384 128)
+	(text "mean_vga_core" (rect 5 0 72 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 0 0 122 12)(font "Arial" ))
+		(text "vin_rsc_mgc_in_wire_d[89..0]" (rect 21 75 143 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 368 32)
+		(output)
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "vout_rsc_mgc_out_stdreg_d[29..0]" (rect 204 27 347 39)(font "Arial" ))
+		(line (pt 368 32)(pt 352 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 352 96)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf
new file mode 100644
index 0000000..bf9fac3
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/ps2.bsf
@@ -0,0 +1,153 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 224 256)
+	(text "ps2" (rect 5 0 19 12)(font "Arial" ))
+	(text "inst" (rect 8 224 20 236)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "iSTART" (rect 0 0 35 12)(font "Arial" ))
+		(text "iSTART" (rect 21 27 56 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "iRST_n" (rect 0 0 31 12)(font "Arial" ))
+		(text "iRST_n" (rect 21 43 52 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "iCLK_50" (rect 0 0 36 12)(font "Arial" ))
+		(text "iCLK_50" (rect 21 59 57 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "oLEFBUT" (rect 0 0 42 12)(font "Arial" ))
+		(text "oLEFBUT" (rect 145 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64)(line_width 1))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "oRIGBUT" (rect 0 0 41 12)(font "Arial" ))
+		(text "oRIGBUT" (rect 146 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80)(line_width 1))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "oMIDBUT" (rect 0 0 41 12)(font "Arial" ))
+		(text "oMIDBUT" (rect 146 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96)(line_width 1))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "oX[7..0]" (rect 0 0 30 12)(font "Arial" ))
+		(text "oX[7..0]" (rect 157 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112)(line_width 3))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "oY[7..0]" (rect 0 0 31 12)(font "Arial" ))
+		(text "oY[7..0]" (rect 156 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128)(line_width 3))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "oX_MOV1[6..0]" (rect 0 0 63 12)(font "Arial" ))
+		(text "oX_MOV1[6..0]" (rect 124 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144)(line_width 3))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "oX_MOV2[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "oX_MOV2[6..0]" (rect 123 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160)(line_width 3))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "oY_MOV1[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "oY_MOV1[6..0]" (rect 123 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "oY_MOV2[6..0]" (rect 0 0 66 12)(font "Arial" ))
+		(text "oY_MOV2[6..0]" (rect 121 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 32)
+		(bidir)
+		(text "PS2_CLK" (rect 0 0 42 12)(font "Arial" ))
+		(text "PS2_CLK" (rect 145 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 1))
+	)
+	(port
+		(pt 208 48)
+		(bidir)
+		(text "PS2_DAT" (rect 0 0 43 12)(font "Arial" ))
+		(text "PS2_DAT" (rect 144 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48)(line_width 1))
+	)
+	(parameter
+		"enable_byte"
+		"011110100"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"listen"
+		"00"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pullclk"
+		"01"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"pulldat"
+		"10"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(parameter
+		"trans"
+		"11"
+		""
+		(type "PARAMETER_UNSIGNED_BIN")	)
+	(drawing
+		(rectangle (rect 16 16 192 224)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 224 -64 324 16))
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/sdram_pll.qip
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf
new file mode 100644
index 0000000..ce4ccaf
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 304 192)
+	(text "vga_mouse_square" (rect 5 0 86 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "vga_xy_rsc_z[19..0]" (rect 0 0 83 12)(font "Arial" ))
+		(text "vga_xy_rsc_z[19..0]" (rect 21 27 104 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "mouse_xy_rsc_z[19..0]" (rect 0 0 95 12)(font "Arial" ))
+		(text "mouse_xy_rsc_z[19..0]" (rect 21 43 116 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "cursor_size_rsc_z[7..0]" (rect 0 0 94 12)(font "Arial" ))
+		(text "cursor_size_rsc_z[7..0]" (rect 21 59 115 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "video_in_rsc_z[29..0]" (rect 0 0 86 12)(font "Arial" ))
+		(text "video_in_rsc_z[29..0]" (rect 21 75 107 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 91 31 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 107 30 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 123 46 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 288 32)
+		(output)
+		(text "video_out_rsc_z[29..0]" (rect 0 0 92 12)(font "Arial" ))
+		(text "video_out_rsc_z[29..0]" (rect 175 27 267 39)(font "Arial" ))
+		(line (pt 288 32)(pt 272 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 272 160)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf
new file mode 100644
index 0000000..f468b93
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mouse_square_core.bsf
@@ -0,0 +1,85 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 440 192)
+	(text "vga_mouse_square_core" (rect 5 0 110 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "en" (rect 0 0 9 12)(font "Arial" ))
+		(text "en" (rect 21 43 30 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "arst_n" (rect 0 0 25 12)(font "Arial" ))
+		(text "arst_n" (rect 21 59 46 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "vga_xy_rsc_mgc_in_wire_d[19..0]" (rect 0 0 141 12)(font "Arial" ))
+		(text "vga_xy_rsc_mgc_in_wire_d[19..0]" (rect 21 75 162 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "mouse_xy_rsc_mgc_in_wire_d[19..0]" (rect 0 0 153 12)(font "Arial" ))
+		(text "mouse_xy_rsc_mgc_in_wire_d[19..0]" (rect 21 91 174 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "cursor_size_rsc_mgc_in_wire_d[7..0]" (rect 0 0 152 12)(font "Arial" ))
+		(text "cursor_size_rsc_mgc_in_wire_d[7..0]" (rect 21 107 173 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "video_in_rsc_mgc_in_wire_d[29..0]" (rect 0 0 143 12)(font "Arial" ))
+		(text "video_in_rsc_mgc_in_wire_d[29..0]" (rect 21 123 164 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 424 32)
+		(output)
+		(text "video_out_rsc_mgc_out_stdreg_d[29..0]" (rect 0 0 165 12)(font "Arial" ))
+		(text "video_out_rsc_mgc_out_stdreg_d[29..0]" (rect 238 27 403 39)(font "Arial" ))
+		(line (pt 424 32)(pt 408 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 408 160)(line_width 1))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf
new file mode 100644
index 0000000..5130f75
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.bsf
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 144 112)
+	(text "vga_mux" (rect 48 0 108 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[29..0]" (rect 4 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[29..0]" (rect 4 42 65 55)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[29..0]" (rect 4 58 65 71)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[29..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[29..0]" (rect 4 74 65 87)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 64 88)(line_width 3))
+	)
+	(port
+		(pt 72 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical))
+		(text "sel[1..0]" (rect 65 59 78 95)(font "Arial" (font_size 8))(vertical))
+		(line (pt 72 112)(pt 72 100)(line_width 3))
+	)
+	(port
+		(pt 144 64)
+		(output)
+		(text "result[29..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[29..0]" (rect 84 50 139 63)(font "Arial" (font_size 8)))
+		(line (pt 144 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 104))
+		(line (pt 64 24)(pt 80 32))
+		(line (pt 64 104)(pt 80 96))
+		(line (pt 80 32)(pt 80 96))
+		(line (pt 0 0)(pt 146 0))
+		(line (pt 146 0)(pt 146 114))
+		(line (pt 0 114)(pt 146 114))
+		(line (pt 0 0)(pt 0 114))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp
new file mode 100644
index 0000000..38915ab
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.cmp
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component vga_mux
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
+	);
+end component;
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip
new file mode 100644
index 0000000..363283f
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "vga_mux.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vga_mux.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "vga_mux.cmp"]
diff --git a/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd
new file mode 100644
index 0000000..1df4d5a
--- /dev/null
+++ b/student_files_2015[2]/student_files_2015/prj2/quartus_proj/DE0_CAMERA_MOUSE/vga_mux.vhd
@@ -0,0 +1,238 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_MUX 
+
+-- ============================================================
+-- File Name: vga_mux.vhd
+-- Megafunction Name(s):
+-- 			LPM_MUX
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY vga_mux IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (29 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
+	);
+END vga_mux;
+
+
+ARCHITECTURE SYN OF vga_mux IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 29 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (29 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(29 DOWNTO 0);
+	sub_wire4    <= data1x(29 DOWNTO 0);
+	sub_wire3    <= data2x(29 DOWNTO 0);
+	result    <= sub_wire0(29 DOWNTO 0);
+	sub_wire1    <= data3x(29 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+
+	LPM_MUX_component : LPM_MUX
+	GENERIC MAP (
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 30,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		data => sub_wire2,
+		sel => sel,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: data0x 0 0 30 0 INPUT NODEFVAL "data0x[29..0]"
+-- Retrieval info: USED_PORT: data1x 0 0 30 0 INPUT NODEFVAL "data1x[29..0]"
+-- Retrieval info: USED_PORT: data2x 0 0 30 0 INPUT NODEFVAL "data2x[29..0]"
+-- Retrieval info: USED_PORT: data3x 0 0 30 0 INPUT NODEFVAL "data3x[29..0]"
+-- Retrieval info: USED_PORT: result 0 0 30 0 OUTPUT NODEFVAL "result[29..0]"
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
+-- Retrieval info: CONNECT: @data 1 0 30 0 data0x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 1 30 0 data1x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 2 30 0 data2x 0 0 30 0
+-- Retrieval info: CONNECT: @data 1 3 30 0 data3x 0 0 30 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: CONNECT: result 0 0 30 0 @result 0 0 30 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL vga_mux_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm